projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Add new files.
[deliverable/binutils-gdb.git] / sim / d10v / interp.c
CommitLineData
d70b4d42 1#include <signal.h>
2934d1c9 2#include "sysdep.h"
2934d1c9 3#include "remote-sim.h"
2934d1c9
MH		 4
5#include "d10v_sim.h"
6
7#define IMEM_SIZE 18 /* D10V instruction memory size is 18 bits */
c422ecc7
MH		 8#define DMEM_SIZE 16 /* Data memory is 64K (but only 32K internal RAM) */
9#define UMEM_SIZE 17 /* each unified memory region is 17 bits */
2934d1c9 10
87178dbd
MM		 11enum _leftright { LEFT_FIRST, RIGHT_FIRST };
12
7eebfc62 13int d10v_debug;
87178dbd 14host_callback *d10v_callback;
aeb1f26b 15unsigned long ins_type_counters[ (int)INS_MAX ];
87178dbd 16
2934d1c9
MH		 17uint16 OP[4];
18
b30cdd35
MM		 19static int init_text_p = 0;
20asection *text;
21bfd_vma text_start;
22bfd_vma text_end;
23
aeb1f26b 24static long hash PARAMS ((long insn, int format));
2934d1c9 25static struct hash_entry *lookup_hash PARAMS ((uint32 ins, int size));
aeb1f26b
MM		 26static void get_operands PARAMS ((struct simops *s, uint32 ins));
27static void do_long PARAMS ((uint32 ins));
28static void do_2_short PARAMS ((uint16 ins1, uint16 ins2, enum _leftright leftright));
29static void do_parallel PARAMS ((uint16 ins1, uint16 ins2));
30static char *add_commas PARAMS ((char *buf, int sizeof_buf, unsigned long value));
31extern void sim_size PARAMS ((int power));
32static void init_system PARAMS ((void));
33extern int sim_write PARAMS ((SIM_ADDR addr, unsigned char *buffer, int size));
34extern void sim_open PARAMS ((char *args));
35extern void sim_close PARAMS ((int quitting));
36extern void sim_set_profile PARAMS ((int n));
37extern void sim_set_profile_size PARAMS ((int n));
38extern void sim_resume PARAMS ((int step, int siggnal));
39extern void sim_info PARAMS ((int verbose));
40extern void sim_create_inferior PARAMS ((SIM_ADDR start_address, char **argv, char **env));
41extern void sim_kill PARAMS ((void));
42extern void sim_set_callbacks PARAMS ((host_callback *p));
43extern void sim_stop_reason PARAMS ((enum sim_stop *reason, int *sigrc));
44extern void sim_fetch_register PARAMS ((int rn, unsigned char *memory));
45extern void sim_store_register PARAMS ((int rn, unsigned char *memory));
46extern int sim_read PARAMS ((SIM_ADDR addr, unsigned char *buffer, int size));
47extern void sim_do_command PARAMS ((char *cmd));
48
49#ifndef INLINE
50#if defined(__GNUC__) && defined(__OPTIMIZE__)
51#define INLINE __inline__
52#else
53#define INLINE
54#endif
55#endif
2934d1c9
MH		 56
57#define MAX_HASH 63
58struct hash_entry
59{
60 struct hash_entry *next;
61 long opcode;
62 long mask;
63 struct simops *ops;
64};
65
66struct hash_entry hash_table[MAX_HASH+1];
67
aeb1f26b 68INLINE static long
2934d1c9
MH		 69hash(insn, format)
70 long insn;
71 int format;
72{
73 if (format & LONG_OPCODE)
74 return ((insn & 0x3F000000) >> 24);
75 else
76 return((insn & 0x7E00) >> 9);
77}
78
aeb1f26b 79INLINE static struct hash_entry *
2934d1c9
MH		 80lookup_hash (ins, size)
81 uint32 ins;
82 int size;
83{
84 struct hash_entry *h;
85
86 if (size)
87 h = &hash_table[(ins & 0x3F000000) >> 24];
88 else
89 h = &hash_table[(ins & 0x7E00) >> 9];
90
aeb1f26b 91 while ((ins & h->mask) != h->opcode)
2934d1c9
MH		 92 {
93 if (h->next == NULL)
94 {
7eebfc62 95 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR looking up hash for %x at PC %x\n",ins, PC);
aeb1f26b 96 exit (1);
2934d1c9
MH		 97 }
98 h = h->next;
99 }
100 return (h);
101}
102
aeb1f26b 103INLINE static void
2934d1c9
MH		 104get_operands (struct simops *s, uint32 ins)
105{
106 int i, shift, bits, flags;
107 uint32 mask;
108 for (i=0; i < s->numops; i++)
109 {
110 shift = s->operands[3*i];
111 bits = s->operands[3*i+1];
112 flags = s->operands[3*i+2];
113 mask = 0x7FFFFFFF >> (31 - bits);
114 OP[i] = (ins >> shift) & mask;
115 }
116}
117
b30cdd35
MM		 118bfd_vma
119decode_pc ()
120{
121 asection *s;
122 if (!init_text_p)
123 {
124 init_text_p = 1;
125 for (s = exec_bfd->sections; s; s = s->next)
126 if (strcmp (bfd_get_section_name (exec_bfd, s), ".text") == 0)
127 {
128 text = s;
129 text_start = bfd_get_section_vma (exec_bfd, s);
130 text_end = text_start + bfd_section_size (exec_bfd, s);
131 break;
132 }
133 }
134
135 return (PC << 2) + text_start;
136}
137
2934d1c9
MH		 138static void
139do_long (ins)
140 uint32 ins;
141{
142 struct hash_entry *h;
7eebfc62
MM		 143#ifdef DEBUG
144 if ((d10v_debug & DEBUG_INSTRUCTION) != 0)
145 (*d10v_callback->printf_filtered) (d10v_callback, "do_long 0x%x\n", ins);
146#endif
2934d1c9
MH		 147 h = lookup_hash (ins, 1);
148 get_operands (h->ops, ins);
87178dbd 149 State.ins_type = INS_LONG;
7eebfc62 150 ins_type_counters[ (int)State.ins_type ]++;
2934d1c9
MH		 151 (h->ops->func)();
152}
215ac953 153
2934d1c9 154static void
87178dbd 155do_2_short (ins1, ins2, leftright)
2934d1c9 156 uint16 ins1, ins2;
87178dbd 157 enum _leftright leftright;
2934d1c9
MH		 158{
159 struct hash_entry *h;
215ac953 160 reg_t orig_pc = PC;
c422ecc7 161 enum _ins_type first, second;
215ac953 162
7eebfc62
MM		 163#ifdef DEBUG
164 if ((d10v_debug & DEBUG_INSTRUCTION) != 0)
165 (*d10v_callback->printf_filtered) (d10v_callback, "do_2_short 0x%x (%s) -> 0x%x\n",
166 ins1, (leftright) ? "left" : "right", ins2);
167#endif
c422ecc7
MH		 168
169 if (leftright == LEFT_FIRST)
170 {
171 first = INS_LEFT;
172 second = INS_RIGHT;
173 ins_type_counters[ (int)INS_LEFTRIGHT ]++;
174 }
175 else
176 {
177 first = INS_RIGHT;
178 second = INS_LEFT;
179 ins_type_counters[ (int)INS_RIGHTLEFT ]++;
180 }
181
2934d1c9
MH		 182 h = lookup_hash (ins1, 0);
183 get_operands (h->ops, ins1);
c422ecc7 184 State.ins_type = first;
7eebfc62 185 ins_type_counters[ (int)State.ins_type ]++;
2934d1c9 186 (h->ops->func)();
215ac953
MM		 187
188 /* If the PC has changed (ie, a jump), don't do the second instruction */
57bc1a72 189 if (orig_pc == PC && !State.exception)
215ac953
MM		 190 {
191 h = lookup_hash (ins2, 0);
192 get_operands (h->ops, ins2);
c422ecc7 193 State.ins_type = second;
215ac953 194 ins_type_counters[ (int)State.ins_type ]++;
c422ecc7 195 ins_type_counters[ (int)INS_CYCLES ]++;
215ac953
MM		 196 (h->ops->func)();
197 }
c422ecc7
MH		 198 else if (orig_pc != PC && !State.exception)
199 ins_type_counters[ (int)INS_COND_JUMP ]++;
2934d1c9 200}
215ac953 201
2934d1c9
MH		 202static void
203do_parallel (ins1, ins2)
204 uint16 ins1, ins2;
205{
206 struct hash_entry *h1, *h2;
7eebfc62
MM		 207#ifdef DEBUG
208 if ((d10v_debug & DEBUG_INSTRUCTION) != 0)
209 (*d10v_callback->printf_filtered) (d10v_callback, "do_parallel 0x%x || 0x%x\n", ins1, ins2);
210#endif
c422ecc7 211 ins_type_counters[ (int)INS_PARALLEL ]++;
2934d1c9 212 h1 = lookup_hash (ins1, 0);
2934d1c9 213 h2 = lookup_hash (ins2, 0);
d70b4d42 214
2934d1c9
MH		 215 if (h1->ops->exec_type == PARONLY)
216 {
d70b4d42 217 get_operands (h1->ops, ins1);
aeb1f26b 218 State.ins_type = INS_LEFT_COND_TEST;
7eebfc62 219 ins_type_counters[ (int)State.ins_type ]++;
2934d1c9
MH		 220 (h1->ops->func)();
221 if (State.exe)
d70b4d42 222 {
aeb1f26b 223 ins_type_counters[ (int)INS_COND_TRUE ]++;
d70b4d42 224 get_operands (h2->ops, ins2);
aeb1f26b
MM		 225 State.ins_type = INS_RIGHT_COND_EXE;
226 ins_type_counters[ (int)State.ins_type ]++;
d70b4d42
MH		 227 (h2->ops->func)();
228 }
aeb1f26b
MM		 229 else
230 ins_type_counters[ (int)INS_COND_FALSE ]++;
2934d1c9
MH		 231 }
232 else if (h2->ops->exec_type == PARONLY)
233 {
d70b4d42 234 get_operands (h2->ops, ins2);
aeb1f26b 235 State.ins_type = INS_RIGHT_COND_TEST;
7eebfc62 236 ins_type_counters[ (int)State.ins_type ]++;
2934d1c9
MH		 237 (h2->ops->func)();
238 if (State.exe)
d70b4d42 239 {
aeb1f26b 240 ins_type_counters[ (int)INS_COND_TRUE ]++;
d70b4d42 241 get_operands (h1->ops, ins1);
aeb1f26b
MM		 242 State.ins_type = INS_LEFT_COND_EXE;
243 ins_type_counters[ (int)State.ins_type ]++;
d70b4d42
MH		 244 (h1->ops->func)();
245 }
aeb1f26b
MM		 246 else
247 ins_type_counters[ (int)INS_COND_FALSE ]++;
2934d1c9
MH		 248 }
249 else
250 {
d70b4d42 251 get_operands (h1->ops, ins1);
87178dbd 252 State.ins_type = INS_LEFT_PARALLEL;
7eebfc62 253 ins_type_counters[ (int)State.ins_type ]++;
2934d1c9 254 (h1->ops->func)();
57bc1a72
MM		 255 if (!State.exception)
256 {
257 get_operands (h2->ops, ins2);
258 State.ins_type = INS_RIGHT_PARALLEL;
259 ins_type_counters[ (int)State.ins_type ]++;
260 (h2->ops->func)();
261 }
2934d1c9
MH		 262 }
263}
264
aeb1f26b
MM		 265static char *
266add_commas(buf, sizeof_buf, value)
267 char *buf;
268 int sizeof_buf;
269 unsigned long value;
270{
271 int comma = 3;
272 char *endbuf = buf + sizeof_buf - 1;
273
274 *--endbuf = '\0';
275 do {
276 if (comma-- == 0)
277 {
278 *--endbuf = ',';
279 comma = 2;
280 }
281
282 *--endbuf = (value % 10) + '0';
283 } while ((value /= 10) != 0);
284
285 return endbuf;
286}
2934d1c9
MH		 287
288void
289sim_size (power)
290 int power;
291
292{
c422ecc7
MH		 293 int i;
294
2934d1c9
MH		 295 if (State.imem)
296 {
c422ecc7
MH		 297 for (i=0;i<128;i++)
298 {
299 if (State.umem[i])
300 {
301 free (State.umem[i]);
302 State.umem[i] = NULL;
303 }
304 }
2934d1c9
MH		 305 free (State.imem);
306 free (State.dmem);
307 }
308
309 State.imem = (uint8 *)calloc(1,1<<IMEM_SIZE);
310 State.dmem = (uint8 *)calloc(1,1<<DMEM_SIZE);
c422ecc7
MH		 311 for (i=1;i<127;i++)
312 State.umem[i] = NULL;
313 State.umem[0] = (uint8 *)calloc(1,1<<UMEM_SIZE);
314 State.umem[1] = (uint8 *)calloc(1,1<<UMEM_SIZE);
315 State.umem[2] = (uint8 *)calloc(1,1<<UMEM_SIZE);
316 State.umem[127] = (uint8 *)calloc(1,1<<UMEM_SIZE);
317 if (!State.imem || !State.dmem || !State.umem[0] || !State.umem[1] || !State.umem[2] || !State.umem[127] )
2934d1c9 318 {
7eebfc62 319 (*d10v_callback->printf_filtered) (d10v_callback, "Memory allocation failed.\n");
2934d1c9
MH		 320 exit(1);
321 }
c422ecc7
MH		 322
323 SET_IMAP0(0x1000);
324 SET_IMAP1(0x1000);
325 SET_DMAP(0);
57bc1a72 326
7eebfc62
MM		 327#ifdef DEBUG
328 if ((d10v_debug & DEBUG_MEMSIZE) != 0)
329 {
aeb1f26b
MM		 330 char buffer[20];
331 (*d10v_callback->printf_filtered) (d10v_callback,
332 "Allocated %s bytes instruction memory and\n",
333 add_commas (buffer, sizeof (buffer), (1UL<<IMEM_SIZE)));
334
335 (*d10v_callback->printf_filtered) (d10v_callback, " %s bytes data memory.\n",
336 add_commas (buffer, sizeof (buffer), (1UL<<IMEM_SIZE)));
7eebfc62 337 }
87178dbd 338#endif
2934d1c9
MH		 339}
340
341static void
342init_system ()
343{
344 if (!State.imem)
345 sim_size(1);
346}
347
c422ecc7
MH		 348static int
349xfer_mem (addr, buffer, size, write)
2934d1c9
MH		 350 SIM_ADDR addr;
351 unsigned char *buffer;
352 int size;
c422ecc7 353 int write;
2934d1c9 354{
c422ecc7
MH		 355 if (!State.imem)
356 init_system ();
2934d1c9 357
57bc1a72
MM		 358#ifdef DEBUG
359 if ((d10v_debug & DEBUG_INSTRUCTION) != 0)
c422ecc7
MH		 360 {
361 if (write)
362 (*d10v_callback->printf_filtered) (d10v_callback, "sim_write %d bytes to 0x%x\n", size, addr);
363 else
364 (*d10v_callback->printf_filtered) (d10v_callback, "sim_read %d bytes from 0x%x\n", size, addr);
365 }
57bc1a72
MM		 366#endif
367
c422ecc7
MH		 368 /* to access data, we use the following mapping */
369 /* 0x01000000 - 0x0103ffff : instruction memory */
370 /* 0x02000000 - 0x0200ffff : data memory */
371 /* 0x03000000 - 0x03ffffff : unified memory */
57bc1a72 372
c422ecc7
MH		 373 if ( (addr & 0x03000000) == 0x03000000)
374 {
375 /* UNIFIED MEMORY */
376 int segment;
377 addr &= ~0x03000000;
378 segment = addr >> UMEM_SIZE;
379 addr &= 0x1ffff;
380 if (!State.umem[segment])
381 State.umem[segment] = (uint8 *)calloc(1,1<<UMEM_SIZE);
382 if (!State.umem[segment])
383 {
384 (*d10v_callback->printf_filtered) (d10v_callback, "Memory allocation failed.\n");
385 exit(1);
386 }
387#ifdef DEBUG
388 (*d10v_callback->printf_filtered) (d10v_callback,"Allocated %s bytes unified memory to region %d\n",
389 add_commas (buffer, sizeof (buffer), (1UL<<IMEM_SIZE)), segment);
390#endif
391 /* FIXME: need to check size and read/write multiple segments if necessary */
392 if (write)
393 memcpy (State.umem[segment]+addr, buffer, size);
394 else
395 memcpy (buffer, State.umem[segment]+addr, size);
396 }
397 else if ( (addr & 0x03000000) == 0x02000000)
398 {
399 /* DATA MEMORY */
400 addr &= ~0x02000000;
401 if (size > (1<<(DMEM_SIZE-1)))
402 {
403 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: data section is only %d bytes.\n",1<<(DMEM_SIZE-1));
404 exit(1);
405 }
406 if (write)
407 memcpy (State.dmem+addr, buffer, size);
408 else
409 memcpy (buffer, State.dmem+addr, size);
410 }
411 else if ( (addr & 0x03000000) == 0x01000000)
412 {
413 /* INSTRUCTION MEMORY */
414 addr &= ~0x01000000;
415 if (size > (1<<IMEM_SIZE))
416 {
417 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: inst section is only %d bytes.\n",1<<IMEM_SIZE);
418 exit(1);
419 }
420 if (write)
421 memcpy (State.imem+addr, buffer, size);
422 else
423 memcpy (buffer, State.imem+addr, size);
424 }
425 else if (write)
426 {
427 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: address 0x%x is not in valid range\n",addr);
428 (*d10v_callback->printf_filtered) (d10v_callback, "Instruction addresses start at 0x01000000\n");
429 (*d10v_callback->printf_filtered) (d10v_callback, "Data addresses start at 0x02000000\n");
430 (*d10v_callback->printf_filtered) (d10v_callback, "Unified addresses start at 0x03000000\n");
431 exit(1);
432 }
433 else
434 return 0;
57bc1a72 435
2934d1c9
MH		 436 return size;
437}
438
c422ecc7
MH		 439
440int
441sim_write (addr, buffer, size)
442 SIM_ADDR addr;
443 unsigned char *buffer;
444 int size;
445{
446 return xfer_mem( addr, buffer, size, 1);
447}
448
449int
450sim_read (addr, buffer, size)
451 SIM_ADDR addr;
452 unsigned char *buffer;
453 int size;
454{
455 return xfer_mem( addr, buffer, size, 0);
456}
457
458
2934d1c9
MH		 459void
460sim_open (args)
461 char *args;
462{
463 struct simops *s;
aeb1f26b 464 struct hash_entry *h;
1eaaf305
MM		 465 static int init_p = 0;
466
2934d1c9 467 if (args != NULL)
1eaaf305
MM		 468 {
469#ifdef DEBUG
470 if (strcmp (args, "-t") == 0)
471 d10v_debug = DEBUG;
472 else
473#endif
474 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: unsupported option(s): %s\n",args);
475 }
c422ecc7 476
2934d1c9 477 /* put all the opcodes in the hash table */
1eaaf305 478 if (!init_p++)
2934d1c9 479 {
1eaaf305 480 for (s = Simops; s->func; s++)
2934d1c9 481 {
1eaaf305
MM		 482 h = &hash_table[hash(s->opcode,s->format)];
483
484 /* go to the last entry in the chain */
485 while (h->next)
486 h = h->next;
487
488 if (h->ops)
489 {
490 h->next = calloc(1,sizeof(struct hash_entry));
491 h = h->next;
492 }
493 h->ops = s;
494 h->mask = s->mask;
495 h->opcode = s->opcode;
2934d1c9 496 }
2934d1c9
MH		 497 }
498}
499
500
501void
502sim_close (quitting)
503 int quitting;
504{
505 /* nothing to do */
506}
507
508void
509sim_set_profile (n)
510 int n;
511{
7eebfc62 512 (*d10v_callback->printf_filtered) (d10v_callback, "sim_set_profile %d\n",n);
2934d1c9
MH		 513}
514
515void
516sim_set_profile_size (n)
517 int n;
518{
7eebfc62 519 (*d10v_callback->printf_filtered) (d10v_callback, "sim_set_profile_size %d\n",n);
2934d1c9
MH		 520}
521
c422ecc7
MH		 522
523uint8 *
524dmem_addr( addr )
525 uint32 addr;
526{
527 int seg;
528
529 addr &= 0xffff;
530
531 if (addr > 0xbfff)
532 {
533 if ( (addr & 0xfff0) != 0xff00)
b30cdd35
MM		 534 (*d10v_callback->printf_filtered) (d10v_callback, "Data address 0x%lx is in I/O space, pc = 0x%lx.\n",
535 (long)addr, (long)decode_pc ());
c422ecc7
MH		 536 return State.dmem + addr;
537 }
538
539 if (addr > 0x7fff)
540 {
541 if (DMAP & 0x1000)
542 {
543 /* instruction memory */
544 return (DMAP & 0xf) * 0x4000 + State.imem;
545 }
546 /* unified memory */
547 /* this is ugly because we allocate unified memory in 128K segments and */
548 /* dmap addresses 16k segments */
549 seg = (DMAP & 0x3ff) >> 2;
550 if (State.umem[seg] == NULL)
551 {
b30cdd35
MM		 552 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: unified memory region %d unmapped, pc = 0x%lx\n",
553 seg, (long)decode_pc ());
c422ecc7
MH		 554 exit(1);
555 }
556 return State.umem[seg] + (DMAP & 3) * 0x4000;
557 }
558
559 return State.dmem + addr;
560}
561
562
563static uint8 *
564pc_addr()
565{
566 uint32 pc = ((uint32)PC) << 2;
567 uint16 imap;
568
569 if (pc & 0x20000)
570 imap = IMAP1;
571 else
572 imap = IMAP0;
573
574 if (imap & 0x1000)
575 return State.imem + pc;
576
577 if (State.umem[imap & 0xff] == NULL)
578 {
b30cdd35
MM		 579 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: unified memory region %d unmapped, pc = 0x%lx\n",
580 imap & 0xff, (long)PC);
c422ecc7
MH		 581 State.exception = SIGILL;
582 return 0;
583 }
584
585 return State.umem[imap & 0xff] + pc;
586}
587
588
2934d1c9
MH		 589void
590sim_resume (step, siggnal)
591 int step, siggnal;
592{
593 uint32 inst;
aeb1f26b 594 reg_t oldpc = 0;
2934d1c9 595
7eebfc62 596/* (*d10v_callback->printf_filtered) (d10v_callback, "sim_resume (%d,%d) PC=0x%x\n",step,siggnal,PC); */
2934d1c9 597
eca43eb1 598 State.exception = 0;
aeb1f26b
MM		 599 do
600 {
c422ecc7
MH		 601 inst = get_longword( pc_addr() );
602 oldpc = PC;
603 ins_type_counters[ (int)INS_CYCLES ]++;
604 switch (inst & 0xC0000000)
aeb1f26b 605 {
c422ecc7
MH		 606 case 0xC0000000:
607 /* long instruction */
608 do_long (inst & 0x3FFFFFFF);
609 break;
610 case 0x80000000:
611 /* R -> L */
612 do_2_short ( inst & 0x7FFF, (inst & 0x3FFF8000) >> 15, 0);
613 break;
614 case 0x40000000:
615 /* L -> R */
616 do_2_short ((inst & 0x3FFF8000) >> 15, inst & 0x7FFF, 1);
617 break;
618 case 0:
619 do_parallel ((inst & 0x3FFF8000) >> 15, inst & 0x7FFF);
620 break;
aeb1f26b 621 }
c422ecc7
MH		 622
623 if (State.RP && PC == RPT_E)
aeb1f26b 624 {
c422ecc7
MH		 625 RPT_C -= 1;
626 if (RPT_C == 0)
627 State.RP = 0;
628 else
629 PC = RPT_S;
aeb1f26b 630 }
c422ecc7
MH		 631
632 /* FIXME */
633 if (PC == oldpc)
634 PC++;
635
aeb1f26b
MM		 636 }
637 while ( !State.exception && !step);
c422ecc7 638
aeb1f26b
MM		 639 if (step && !State.exception)
640 State.exception = SIGTRAP;
2934d1c9
MH		 641}
642
643int
644sim_trace ()
645{
7eebfc62
MM		 646#ifdef DEBUG
647 d10v_debug = DEBUG;
648#endif
649 sim_resume (0, 0);
650 return 1;
2934d1c9
MH		 651}
652
653void
654sim_info (verbose)
655 int verbose;
656{
aeb1f26b
MM		 657 char buf1[40];
658 char buf2[40];
659 char buf3[40];
660 char buf4[40];
661 char buf5[40];
662 unsigned long left = ins_type_counters[ (int)INS_LEFT ] + ins_type_counters[ (int)INS_LEFT_COND_EXE ];
663 unsigned long left_nops = ins_type_counters[ (int)INS_LEFT_NOPS ];
664 unsigned long left_parallel = ins_type_counters[ (int)INS_LEFT_PARALLEL ];
665 unsigned long left_cond = ins_type_counters[ (int)INS_LEFT_COND_TEST ];
666 unsigned long left_total = left + left_parallel + left_cond + left_nops;
667
668 unsigned long right = ins_type_counters[ (int)INS_RIGHT ] + ins_type_counters[ (int)INS_RIGHT_COND_EXE ];
669 unsigned long right_nops = ins_type_counters[ (int)INS_RIGHT_NOPS ];
670 unsigned long right_parallel = ins_type_counters[ (int)INS_RIGHT_PARALLEL ];
671 unsigned long right_cond = ins_type_counters[ (int)INS_RIGHT_COND_TEST ];
672 unsigned long right_total = right + right_parallel + right_cond + right_nops;
673
674 unsigned long unknown = ins_type_counters[ (int)INS_UNKNOWN ];
675 unsigned long ins_long = ins_type_counters[ (int)INS_LONG ];
c422ecc7
MH		 676 unsigned long parallel = ins_type_counters[ (int)INS_PARALLEL ];
677 unsigned long leftright = ins_type_counters[ (int)INS_LEFTRIGHT ];
678 unsigned long rightleft = ins_type_counters[ (int)INS_RIGHTLEFT ];
aeb1f26b
MM		 679 unsigned long cond_true = ins_type_counters[ (int)INS_COND_TRUE ];
680 unsigned long cond_false = ins_type_counters[ (int)INS_COND_FALSE ];
c422ecc7 681 unsigned long cond_jump = ins_type_counters[ (int)INS_COND_JUMP ];
aeb1f26b
MM		 682 unsigned long cycles = ins_type_counters[ (int)INS_CYCLES ];
683 unsigned long total = (unknown + left_total + right_total + ins_long);
684
685 int size = strlen (add_commas (buf1, sizeof (buf1), total));
686 int parallel_size = strlen (add_commas (buf1, sizeof (buf1),
687 (left_parallel > right_parallel) ? left_parallel : right_parallel));
688 int cond_size = strlen (add_commas (buf1, sizeof (buf1), (left_cond > right_cond) ? left_cond : right_cond));
689 int nop_size = strlen (add_commas (buf1, sizeof (buf1), (left_nops > right_nops) ? left_nops : right_nops));
690 int normal_size = strlen (add_commas (buf1, sizeof (buf1), (left > right) ? left : right));
691
692 (*d10v_callback->printf_filtered) (d10v_callback,
c422ecc7 693 "executed %*s left instruction(s), %*s normal, %*s parallel, %*s EXExxx, %*s nops\n",
aeb1f26b
MM		 694 size, add_commas (buf1, sizeof (buf1), left_total),
695 normal_size, add_commas (buf2, sizeof (buf2), left),
696 parallel_size, add_commas (buf3, sizeof (buf3), left_parallel),
697 cond_size, add_commas (buf4, sizeof (buf4), left_cond),
698 nop_size, add_commas (buf5, sizeof (buf5), left_nops));
699
700 (*d10v_callback->printf_filtered) (d10v_callback,
c422ecc7 701 "executed %*s right instruction(s), %*s normal, %*s parallel, %*s EXExxx, %*s nops\n",
aeb1f26b
MM		 702 size, add_commas (buf1, sizeof (buf1), right_total),
703 normal_size, add_commas (buf2, sizeof (buf2), right),
704 parallel_size, add_commas (buf3, sizeof (buf3), right_parallel),
705 cond_size, add_commas (buf4, sizeof (buf4), right_cond),
706 nop_size, add_commas (buf5, sizeof (buf5), right_nops));
707
c422ecc7
MH		 708 if (ins_long)
709 (*d10v_callback->printf_filtered) (d10v_callback,
710 "executed %*s long instruction(s)\n",
711 size, add_commas (buf1, sizeof (buf1), ins_long));
712
713 if (parallel)
714 (*d10v_callback->printf_filtered) (d10v_callback,
715 "executed %*s parallel instruction(s)\n",
716 size, add_commas (buf1, sizeof (buf1), parallel));
717
718 if (leftright)
719 (*d10v_callback->printf_filtered) (d10v_callback,
720 "executed %*s instruction(s) encoded L->R\n",
721 size, add_commas (buf1, sizeof (buf1), leftright));
722
723 if (rightleft)
724 (*d10v_callback->printf_filtered) (d10v_callback,
725 "executed %*s instruction(s) encoded R->L\n",
726 size, add_commas (buf1, sizeof (buf1), rightleft));
7eebfc62 727
aeb1f26b
MM		 728 if (unknown)
729 (*d10v_callback->printf_filtered) (d10v_callback,
c422ecc7 730 "executed %*s unknown instruction(s)\n",
aeb1f26b 731 size, add_commas (buf1, sizeof (buf1), unknown));
7eebfc62 732
c422ecc7
MH		 733 if (cond_true)
734 (*d10v_callback->printf_filtered) (d10v_callback,
735 "executed %*s instruction(s) due to EXExxx condition being true\n",
736 size, add_commas (buf1, sizeof (buf1), cond_true));
7eebfc62 737
c422ecc7
MH		 738 if (cond_false)
739 (*d10v_callback->printf_filtered) (d10v_callback,
740 "skipped %*s instruction(s) due to EXExxx condition being false\n",
741 size, add_commas (buf1, sizeof (buf1), cond_false));
742
743 if (cond_jump)
744 (*d10v_callback->printf_filtered) (d10v_callback,
745 "skipped %*s instruction(s) due to conditional branch succeeding\n",
746 size, add_commas (buf1, sizeof (buf1), cond_jump));
7eebfc62
MM		 747
748 (*d10v_callback->printf_filtered) (d10v_callback,
c422ecc7 749 "executed %*s cycle(s)\n",
aeb1f26b 750 size, add_commas (buf1, sizeof (buf1), cycles));
7eebfc62
MM		 751
752 (*d10v_callback->printf_filtered) (d10v_callback,
aeb1f26b
MM		 753 "executed %*s total instructions\n",
754 size, add_commas (buf1, sizeof (buf1), total));
2934d1c9
MH		 755}
756
757void
758sim_create_inferior (start_address, argv, env)
759 SIM_ADDR start_address;
760 char **argv;
761 char **env;
762{
7eebfc62
MM		 763#ifdef DEBUG
764 if (d10v_debug)
765 (*d10v_callback->printf_filtered) (d10v_callback, "sim_create_inferior: PC=0x%x\n", start_address);
766#endif
c422ecc7 767
57bc1a72 768 /* reset all state information */
c422ecc7
MH		 769 memset (&State.regs, 0, (int)&State.imem - (int)&State.regs[0]);
770
57bc1a72 771 /* set PC */
2934d1c9 772 PC = start_address >> 2;
c422ecc7
MH		 773
774 /* cpu resets imap0 to 0 and imap1 to 0x7f, but D10V-EVA board */
775 /* resets imap0 and imap1 to 0x1000. */
776
777 SET_IMAP0(0x1000);
778 SET_IMAP1(0x1000);
779 SET_DMAP(0);
2934d1c9
MH		 780}
781
782
783void
784sim_kill ()
785{
786 /* nothing to do */
787}
788
789void
790sim_set_callbacks(p)
791 host_callback *p;
792{
87178dbd
MM		 793/* printf ("sim_set_callbacks\n"); */
794 d10v_callback = p;
2934d1c9
MH		 795}
796
797void
798sim_stop_reason (reason, sigrc)
799 enum sim_stop *reason;
800 int *sigrc;
801{
7eebfc62 802/* (*d10v_callback->printf_filtered) (d10v_callback, "sim_stop_reason: PC=0x%x\n",PC<<2); */
d70b4d42 803
a49a15ad 804 switch (State.exception)
d70b4d42 805 {
a49a15ad 806 case SIG_D10V_STOP: /* stop instruction */
d70b4d42 807 *reason = sim_exited;
a49a15ad
MM		 808 *sigrc = 0;
809 break;
810
811 case SIG_D10V_EXIT: /* exit trap */
812 *reason = sim_exited;
813 *sigrc = State.regs[2];
814 break;
815
816 default: /* some signal */
d70b4d42
MH		 817 *reason = sim_stopped;
818 *sigrc = State.exception;
a49a15ad 819 break;
d70b4d42
MH		 820 }
821}
822
823void
824sim_fetch_register (rn, memory)
825 int rn;
826 unsigned char *memory;
827{
c422ecc7
MH		 828 if (!State.imem)
829 init_system();
830
831 if (rn > 34)
5c839c67 832 WRITE_64 (memory, State.a[rn-35]);
c422ecc7
MH		 833 else if (rn == 32)
834 WRITE_16 (memory, IMAP0);
835 else if (rn == 33)
836 WRITE_16 (memory, IMAP1);
837 else if (rn == 34)
838 WRITE_16 (memory, DMAP);
d70b4d42 839 else
c422ecc7 840 WRITE_16 (memory, State.regs[rn]);
d70b4d42
MH		 841}
842
843void
844sim_store_register (rn, memory)
845 int rn;
846 unsigned char *memory;
847{
c422ecc7
MH		 848 if (!State.imem)
849 init_system();
850
851 if (rn > 34)
5c839c67 852 State.a[rn-35] = READ_64 (memory) & MASK40;
c422ecc7
MH		 853 else if (rn == 34)
854 SET_DMAP( READ_16(memory) );
855 else if (rn == 33)
856 SET_IMAP1( READ_16(memory) );
857 else if (rn == 32)
858 SET_IMAP0( READ_16(memory) );
d70b4d42 859 else
c422ecc7 860 State.regs[rn]= READ_16 (memory);
2934d1c9 861}
d70b4d42 862
d70b4d42
MH		 863
864void
865sim_do_command (cmd)
866 char *cmd;
867{
7eebfc62 868 (*d10v_callback->printf_filtered) (d10v_callback, "sim_do_command: %s\n",cmd);
d70b4d42
MH		 869}
870
871int
872sim_load (prog, from_tty)
873 char *prog;
874 int from_tty;
875{
876 /* Return nonzero so GDB will handle it. */
877 return 1;
878}
GDB Binutils - Deliverables
This page took 0.069355 seconds and 4 git commands to generate.