Commit | Line | Data |
---|---|---|
d0a5a356 | 1 | #include "config.h" |
11558abc | 2 | #include <inttypes.h> |
c906108c | 3 | #include <signal.h> |
c906108c | 4 | #include "bfd.h" |
3c25f8c7 AC |
5 | #include "gdb/callback.h" |
6 | #include "gdb/remote-sim.h" | |
c906108c | 7 | |
541ebcee MF |
8 | #include "sim-main.h" |
9 | #include "sim-options.h" | |
10 | ||
b91b96f4 | 11 | #include "gdb/sim-d10v.h" |
aba6488e | 12 | #include "gdb/signals.h" |
c906108c | 13 | |
d0a5a356 JB |
14 | #ifdef HAVE_STRING_H |
15 | #include <string.h> | |
16 | #else | |
17 | #ifdef HAVE_STRINGS_H | |
18 | #include <strings.h> | |
19 | #endif /* HAVE_STRING_H */ | |
20 | #endif /* HAVE_STRINGS_H */ | |
21 | ||
22 | #ifdef HAVE_STDLIB_H | |
23 | #include <stdlib.h> | |
24 | #endif | |
25 | ||
c906108c SS |
26 | enum _leftright { LEFT_FIRST, RIGHT_FIRST }; |
27 | ||
c906108c | 28 | int d10v_debug; |
cff3e48b JM |
29 | |
30 | /* Set this to true to get the previous segment layout. */ | |
31 | ||
32 | int old_segment_mapping; | |
33 | ||
c906108c SS |
34 | unsigned long ins_type_counters[ (int)INS_MAX ]; |
35 | ||
36 | uint16 OP[4]; | |
37 | ||
bdca5ee4 | 38 | static long hash (long insn, int format); |
67954606 | 39 | static struct hash_entry *lookup_hash (SIM_DESC, SIM_CPU *, uint32 ins, int size); |
bdca5ee4 | 40 | static void get_operands (struct simops *s, uint32 ins); |
67954606 MF |
41 | static void do_long (SIM_DESC, SIM_CPU *, uint32 ins); |
42 | static void do_2_short (SIM_DESC, SIM_CPU *, uint16 ins1, uint16 ins2, enum _leftright leftright); | |
43 | static void do_parallel (SIM_DESC, SIM_CPU *, uint16 ins1, uint16 ins2); | |
bdca5ee4 | 44 | static char *add_commas (char *buf, int sizeof_buf, unsigned long value); |
67954606 | 45 | static INLINE uint8 *map_memory (SIM_DESC, SIM_CPU *, unsigned phys_addr); |
c906108c | 46 | |
c906108c SS |
47 | #define MAX_HASH 63 |
48 | struct hash_entry | |
49 | { | |
50 | struct hash_entry *next; | |
51 | uint32 opcode; | |
52 | uint32 mask; | |
53 | int size; | |
54 | struct simops *ops; | |
55 | }; | |
56 | ||
57 | struct hash_entry hash_table[MAX_HASH+1]; | |
58 | ||
59 | INLINE static long | |
11558abc | 60 | hash (long insn, int format) |
c906108c SS |
61 | { |
62 | if (format & LONG_OPCODE) | |
63 | return ((insn & 0x3F000000) >> 24); | |
64 | else | |
65 | return((insn & 0x7E00) >> 9); | |
66 | } | |
67 | ||
68 | INLINE static struct hash_entry * | |
67954606 | 69 | lookup_hash (SIM_DESC sd, SIM_CPU *cpu, uint32 ins, int size) |
c906108c SS |
70 | { |
71 | struct hash_entry *h; | |
72 | ||
73 | if (size) | |
74 | h = &hash_table[(ins & 0x3F000000) >> 24]; | |
75 | else | |
76 | h = &hash_table[(ins & 0x7E00) >> 9]; | |
77 | ||
78 | while ((ins & h->mask) != h->opcode || h->size != size) | |
79 | { | |
80 | if (h->next == NULL) | |
aadc1740 | 81 | sim_engine_halt (sd, cpu, NULL, PC, sim_stopped, SIM_SIGILL); |
c906108c SS |
82 | h = h->next; |
83 | } | |
84 | return (h); | |
85 | } | |
86 | ||
87 | INLINE static void | |
88 | get_operands (struct simops *s, uint32 ins) | |
89 | { | |
90 | int i, shift, bits, flags; | |
91 | uint32 mask; | |
92 | for (i=0; i < s->numops; i++) | |
93 | { | |
94 | shift = s->operands[3*i]; | |
95 | bits = s->operands[3*i+1]; | |
96 | flags = s->operands[3*i+2]; | |
97 | mask = 0x7FFFFFFF >> (31 - bits); | |
98 | OP[i] = (ins >> shift) & mask; | |
99 | } | |
100 | /* FIXME: for tracing, update values that need to be updated each | |
101 | instruction decode cycle */ | |
102 | State.trace.psw = PSW; | |
103 | } | |
104 | ||
c906108c | 105 | static void |
67954606 | 106 | do_long (SIM_DESC sd, SIM_CPU *cpu, uint32 ins) |
c906108c SS |
107 | { |
108 | struct hash_entry *h; | |
109 | #ifdef DEBUG | |
110 | if ((d10v_debug & DEBUG_INSTRUCTION) != 0) | |
e9b0081f | 111 | sim_io_printf (sd, "do_long 0x%x\n", ins); |
c906108c | 112 | #endif |
67954606 | 113 | h = lookup_hash (sd, cpu, ins, 1); |
4ce44c66 JM |
114 | if (h == NULL) |
115 | return; | |
c906108c SS |
116 | get_operands (h->ops, ins); |
117 | State.ins_type = INS_LONG; | |
118 | ins_type_counters[ (int)State.ins_type ]++; | |
67954606 | 119 | (h->ops->func) (sd, cpu); |
c906108c SS |
120 | } |
121 | ||
122 | static void | |
67954606 | 123 | do_2_short (SIM_DESC sd, SIM_CPU *cpu, uint16 ins1, uint16 ins2, enum _leftright leftright) |
c906108c SS |
124 | { |
125 | struct hash_entry *h; | |
126 | enum _ins_type first, second; | |
127 | ||
128 | #ifdef DEBUG | |
129 | if ((d10v_debug & DEBUG_INSTRUCTION) != 0) | |
e9b0081f MF |
130 | sim_io_printf (sd, "do_2_short 0x%x (%s) -> 0x%x\n", ins1, |
131 | leftright ? "left" : "right", ins2); | |
c906108c SS |
132 | #endif |
133 | ||
134 | if (leftright == LEFT_FIRST) | |
135 | { | |
136 | first = INS_LEFT; | |
137 | second = INS_RIGHT; | |
138 | ins_type_counters[ (int)INS_LEFTRIGHT ]++; | |
139 | } | |
140 | else | |
141 | { | |
142 | first = INS_RIGHT; | |
143 | second = INS_LEFT; | |
144 | ins_type_counters[ (int)INS_RIGHTLEFT ]++; | |
145 | } | |
146 | ||
147 | /* Issue the first instruction */ | |
67954606 | 148 | h = lookup_hash (sd, cpu, ins1, 0); |
4ce44c66 JM |
149 | if (h == NULL) |
150 | return; | |
c906108c SS |
151 | get_operands (h->ops, ins1); |
152 | State.ins_type = first; | |
153 | ins_type_counters[ (int)State.ins_type ]++; | |
67954606 | 154 | (h->ops->func) (sd, cpu); |
c906108c SS |
155 | |
156 | /* Issue the second instruction (if the PC hasn't changed) */ | |
aadc1740 | 157 | if (!State.pc_changed) |
c906108c SS |
158 | { |
159 | /* finish any existing instructions */ | |
160 | SLOT_FLUSH (); | |
67954606 | 161 | h = lookup_hash (sd, cpu, ins2, 0); |
4ce44c66 JM |
162 | if (h == NULL) |
163 | return; | |
c906108c SS |
164 | get_operands (h->ops, ins2); |
165 | State.ins_type = second; | |
166 | ins_type_counters[ (int)State.ins_type ]++; | |
167 | ins_type_counters[ (int)INS_CYCLES ]++; | |
67954606 | 168 | (h->ops->func) (sd, cpu); |
c906108c | 169 | } |
aadc1740 | 170 | else |
c906108c SS |
171 | ins_type_counters[ (int)INS_COND_JUMP ]++; |
172 | } | |
173 | ||
174 | static void | |
67954606 | 175 | do_parallel (SIM_DESC sd, SIM_CPU *cpu, uint16 ins1, uint16 ins2) |
c906108c SS |
176 | { |
177 | struct hash_entry *h1, *h2; | |
178 | #ifdef DEBUG | |
179 | if ((d10v_debug & DEBUG_INSTRUCTION) != 0) | |
e9b0081f | 180 | sim_io_printf (sd, "do_parallel 0x%x || 0x%x\n", ins1, ins2); |
c906108c SS |
181 | #endif |
182 | ins_type_counters[ (int)INS_PARALLEL ]++; | |
67954606 | 183 | h1 = lookup_hash (sd, cpu, ins1, 0); |
4ce44c66 JM |
184 | if (h1 == NULL) |
185 | return; | |
67954606 | 186 | h2 = lookup_hash (sd, cpu, ins2, 0); |
4ce44c66 JM |
187 | if (h2 == NULL) |
188 | return; | |
c906108c SS |
189 | |
190 | if (h1->ops->exec_type == PARONLY) | |
191 | { | |
192 | get_operands (h1->ops, ins1); | |
193 | State.ins_type = INS_LEFT_COND_TEST; | |
194 | ins_type_counters[ (int)State.ins_type ]++; | |
67954606 | 195 | (h1->ops->func) (sd, cpu); |
c906108c SS |
196 | if (State.exe) |
197 | { | |
198 | ins_type_counters[ (int)INS_COND_TRUE ]++; | |
199 | get_operands (h2->ops, ins2); | |
200 | State.ins_type = INS_RIGHT_COND_EXE; | |
201 | ins_type_counters[ (int)State.ins_type ]++; | |
67954606 | 202 | (h2->ops->func) (sd, cpu); |
c906108c SS |
203 | } |
204 | else | |
205 | ins_type_counters[ (int)INS_COND_FALSE ]++; | |
206 | } | |
207 | else if (h2->ops->exec_type == PARONLY) | |
208 | { | |
209 | get_operands (h2->ops, ins2); | |
210 | State.ins_type = INS_RIGHT_COND_TEST; | |
211 | ins_type_counters[ (int)State.ins_type ]++; | |
67954606 | 212 | (h2->ops->func) (sd, cpu); |
c906108c SS |
213 | if (State.exe) |
214 | { | |
215 | ins_type_counters[ (int)INS_COND_TRUE ]++; | |
216 | get_operands (h1->ops, ins1); | |
217 | State.ins_type = INS_LEFT_COND_EXE; | |
218 | ins_type_counters[ (int)State.ins_type ]++; | |
67954606 | 219 | (h1->ops->func) (sd, cpu); |
c906108c SS |
220 | } |
221 | else | |
222 | ins_type_counters[ (int)INS_COND_FALSE ]++; | |
223 | } | |
224 | else | |
225 | { | |
226 | get_operands (h1->ops, ins1); | |
227 | State.ins_type = INS_LEFT_PARALLEL; | |
228 | ins_type_counters[ (int)State.ins_type ]++; | |
67954606 | 229 | (h1->ops->func) (sd, cpu); |
aadc1740 MF |
230 | get_operands (h2->ops, ins2); |
231 | State.ins_type = INS_RIGHT_PARALLEL; | |
232 | ins_type_counters[ (int)State.ins_type ]++; | |
233 | (h2->ops->func) (sd, cpu); | |
c906108c SS |
234 | } |
235 | } | |
236 | ||
237 | static char * | |
11558abc | 238 | add_commas (char *buf, int sizeof_buf, unsigned long value) |
c906108c SS |
239 | { |
240 | int comma = 3; | |
241 | char *endbuf = buf + sizeof_buf - 1; | |
242 | ||
243 | *--endbuf = '\0'; | |
244 | do { | |
245 | if (comma-- == 0) | |
246 | { | |
247 | *--endbuf = ','; | |
248 | comma = 2; | |
249 | } | |
250 | ||
251 | *--endbuf = (value % 10) + '0'; | |
252 | } while ((value /= 10) != 0); | |
253 | ||
254 | return endbuf; | |
255 | } | |
256 | ||
aadc1740 | 257 | static void |
11558abc | 258 | sim_size (int power) |
c906108c SS |
259 | { |
260 | int i; | |
4ce44c66 | 261 | for (i = 0; i < IMEM_SEGMENTS; i++) |
c906108c | 262 | { |
4ce44c66 JM |
263 | if (State.mem.insn[i]) |
264 | free (State.mem.insn[i]); | |
c906108c | 265 | } |
4ce44c66 | 266 | for (i = 0; i < DMEM_SEGMENTS; i++) |
c906108c | 267 | { |
4ce44c66 JM |
268 | if (State.mem.data[i]) |
269 | free (State.mem.data[i]); | |
c906108c | 270 | } |
4ce44c66 JM |
271 | for (i = 0; i < UMEM_SEGMENTS; i++) |
272 | { | |
273 | if (State.mem.unif[i]) | |
274 | free (State.mem.unif[i]); | |
275 | } | |
276 | /* Always allocate dmem segment 0. This contains the IMAP and DMAP | |
277 | registers. */ | |
278 | State.mem.data[0] = calloc (1, SEGMENT_SIZE); | |
279 | } | |
280 | ||
281 | /* For tracing - leave info on last access around. */ | |
282 | static char *last_segname = "invalid"; | |
283 | static char *last_from = "invalid"; | |
284 | static char *last_to = "invalid"; | |
285 | ||
286 | enum | |
287 | { | |
288 | IMAP0_OFFSET = 0xff00, | |
289 | DMAP0_OFFSET = 0xff08, | |
290 | DMAP2_SHADDOW = 0xff04, | |
291 | DMAP2_OFFSET = 0xff0c | |
292 | }; | |
293 | ||
294 | static void | |
67954606 | 295 | set_dmap_register (SIM_DESC sd, int reg_nr, unsigned long value) |
4ce44c66 | 296 | { |
67954606 | 297 | uint8 *raw = map_memory (sd, NULL, SIM_D10V_MEMORY_DATA |
4ce44c66 JM |
298 | + DMAP0_OFFSET + 2 * reg_nr); |
299 | WRITE_16 (raw, value); | |
c906108c | 300 | #ifdef DEBUG |
4ce44c66 | 301 | if ((d10v_debug & DEBUG_MEMORY)) |
c906108c | 302 | { |
e9b0081f | 303 | sim_io_printf (sd, "mem: dmap%d=0x%04lx\n", reg_nr, value); |
4ce44c66 JM |
304 | } |
305 | #endif | |
306 | } | |
c906108c | 307 | |
4ce44c66 | 308 | static unsigned long |
67954606 | 309 | dmap_register (SIM_DESC sd, SIM_CPU *cpu, void *regcache, int reg_nr) |
4ce44c66 | 310 | { |
67954606 | 311 | uint8 *raw = map_memory (sd, cpu, SIM_D10V_MEMORY_DATA |
4ce44c66 JM |
312 | + DMAP0_OFFSET + 2 * reg_nr); |
313 | return READ_16 (raw); | |
314 | } | |
315 | ||
316 | static void | |
67954606 | 317 | set_imap_register (SIM_DESC sd, int reg_nr, unsigned long value) |
4ce44c66 | 318 | { |
67954606 | 319 | uint8 *raw = map_memory (sd, NULL, SIM_D10V_MEMORY_DATA |
4ce44c66 JM |
320 | + IMAP0_OFFSET + 2 * reg_nr); |
321 | WRITE_16 (raw, value); | |
322 | #ifdef DEBUG | |
323 | if ((d10v_debug & DEBUG_MEMORY)) | |
324 | { | |
e9b0081f | 325 | sim_io_printf (sd, "mem: imap%d=0x%04lx\n", reg_nr, value); |
c906108c SS |
326 | } |
327 | #endif | |
328 | } | |
329 | ||
4ce44c66 | 330 | static unsigned long |
67954606 | 331 | imap_register (SIM_DESC sd, SIM_CPU *cpu, void *regcache, int reg_nr) |
4ce44c66 | 332 | { |
67954606 | 333 | uint8 *raw = map_memory (sd, cpu, SIM_D10V_MEMORY_DATA |
4ce44c66 JM |
334 | + IMAP0_OFFSET + 2 * reg_nr); |
335 | return READ_16 (raw); | |
336 | } | |
c906108c | 337 | |
4ce44c66 JM |
338 | enum |
339 | { | |
340 | HELD_SPI_IDX = 0, | |
341 | HELD_SPU_IDX = 1 | |
342 | }; | |
343 | ||
344 | static unsigned long | |
345 | spu_register (void) | |
c906108c | 346 | { |
4ce44c66 JM |
347 | if (PSW_SM) |
348 | return GPR (SP_IDX); | |
349 | else | |
350 | return HELD_SP (HELD_SPU_IDX); | |
351 | } | |
c906108c | 352 | |
4ce44c66 JM |
353 | static unsigned long |
354 | spi_register (void) | |
355 | { | |
356 | if (!PSW_SM) | |
357 | return GPR (SP_IDX); | |
358 | else | |
359 | return HELD_SP (HELD_SPI_IDX); | |
360 | } | |
361 | ||
362 | static void | |
363 | set_spi_register (unsigned long value) | |
364 | { | |
365 | if (!PSW_SM) | |
366 | SET_GPR (SP_IDX, value); | |
367 | SET_HELD_SP (HELD_SPI_IDX, value); | |
368 | } | |
369 | ||
370 | static void | |
371 | set_spu_register (unsigned long value) | |
372 | { | |
373 | if (PSW_SM) | |
374 | SET_GPR (SP_IDX, value); | |
375 | SET_HELD_SP (HELD_SPU_IDX, value); | |
376 | } | |
377 | ||
378 | /* Given a virtual address in the DMAP address space, translate it | |
379 | into a physical address. */ | |
380 | ||
6637a426 | 381 | static unsigned long |
67954606 MF |
382 | sim_d10v_translate_dmap_addr (SIM_DESC sd, |
383 | SIM_CPU *cpu, | |
384 | unsigned long offset, | |
4ce44c66 JM |
385 | int nr_bytes, |
386 | unsigned long *phys, | |
f6684c31 | 387 | void *regcache, |
67954606 MF |
388 | unsigned long (*dmap_register) (SIM_DESC, |
389 | SIM_CPU *, | |
390 | void *regcache, | |
f6684c31 | 391 | int reg_nr)) |
4ce44c66 JM |
392 | { |
393 | short map; | |
394 | int regno; | |
395 | last_from = "logical-data"; | |
396 | if (offset >= DMAP_BLOCK_SIZE * SIM_D10V_NR_DMAP_REGS) | |
c906108c | 397 | { |
4ce44c66 JM |
398 | /* Logical address out side of data segments, not supported */ |
399 | return 0; | |
400 | } | |
401 | regno = (offset / DMAP_BLOCK_SIZE); | |
402 | offset = (offset % DMAP_BLOCK_SIZE); | |
403 | if ((offset % DMAP_BLOCK_SIZE) + nr_bytes > DMAP_BLOCK_SIZE) | |
404 | { | |
405 | /* Don't cross a BLOCK boundary */ | |
406 | nr_bytes = DMAP_BLOCK_SIZE - (offset % DMAP_BLOCK_SIZE); | |
407 | } | |
67954606 | 408 | map = dmap_register (sd, cpu, regcache, regno); |
4ce44c66 JM |
409 | if (regno == 3) |
410 | { | |
411 | /* Always maps to data memory */ | |
412 | int iospi = (offset / 0x1000) % 4; | |
413 | int iosp = (map >> (4 * (3 - iospi))) % 0x10; | |
414 | last_to = "io-space"; | |
415 | *phys = (SIM_D10V_MEMORY_DATA + (iosp * 0x10000) + 0xc000 + offset); | |
416 | } | |
417 | else | |
418 | { | |
419 | int sp = ((map & 0x3000) >> 12); | |
420 | int segno = (map & 0x3ff); | |
421 | switch (sp) | |
c906108c | 422 | { |
4ce44c66 JM |
423 | case 0: /* 00: Unified memory */ |
424 | *phys = SIM_D10V_MEMORY_UNIFIED + (segno * DMAP_BLOCK_SIZE) + offset; | |
425 | last_to = "unified"; | |
426 | break; | |
427 | case 1: /* 01: Instruction Memory */ | |
428 | *phys = SIM_D10V_MEMORY_INSN + (segno * DMAP_BLOCK_SIZE) + offset; | |
429 | last_to = "chip-insn"; | |
430 | break; | |
431 | case 2: /* 10: Internal data memory */ | |
432 | *phys = SIM_D10V_MEMORY_DATA + (segno << 16) + (regno * DMAP_BLOCK_SIZE) + offset; | |
433 | last_to = "chip-data"; | |
434 | break; | |
435 | case 3: /* 11: Reserved */ | |
436 | return 0; | |
c906108c SS |
437 | } |
438 | } | |
4ce44c66 JM |
439 | return nr_bytes; |
440 | } | |
c906108c | 441 | |
4ce44c66 JM |
442 | /* Given a virtual address in the IMAP address space, translate it |
443 | into a physical address. */ | |
cff3e48b | 444 | |
6637a426 | 445 | static unsigned long |
67954606 MF |
446 | sim_d10v_translate_imap_addr (SIM_DESC sd, |
447 | SIM_CPU *cpu, | |
448 | unsigned long offset, | |
4ce44c66 JM |
449 | int nr_bytes, |
450 | unsigned long *phys, | |
f6684c31 | 451 | void *regcache, |
67954606 MF |
452 | unsigned long (*imap_register) (SIM_DESC, |
453 | SIM_CPU *, | |
454 | void *regcache, | |
f6684c31 | 455 | int reg_nr)) |
4ce44c66 JM |
456 | { |
457 | short map; | |
458 | int regno; | |
459 | int sp; | |
460 | int segno; | |
461 | last_from = "logical-insn"; | |
462 | if (offset >= (IMAP_BLOCK_SIZE * SIM_D10V_NR_IMAP_REGS)) | |
463 | { | |
464 | /* Logical address outside of IMAP segments, not supported */ | |
465 | return 0; | |
466 | } | |
467 | regno = (offset / IMAP_BLOCK_SIZE); | |
468 | offset = (offset % IMAP_BLOCK_SIZE); | |
469 | if (offset + nr_bytes > IMAP_BLOCK_SIZE) | |
470 | { | |
471 | /* Don't cross a BLOCK boundary */ | |
472 | nr_bytes = IMAP_BLOCK_SIZE - offset; | |
473 | } | |
67954606 | 474 | map = imap_register (sd, cpu, regcache, regno); |
4ce44c66 JM |
475 | sp = (map & 0x3000) >> 12; |
476 | segno = (map & 0x007f); | |
477 | switch (sp) | |
478 | { | |
479 | case 0: /* 00: unified memory */ | |
480 | *phys = SIM_D10V_MEMORY_UNIFIED + (segno << 17) + offset; | |
481 | last_to = "unified"; | |
482 | break; | |
483 | case 1: /* 01: instruction memory */ | |
484 | *phys = SIM_D10V_MEMORY_INSN + (IMAP_BLOCK_SIZE * regno) + offset; | |
485 | last_to = "chip-insn"; | |
486 | break; | |
487 | case 2: /*10*/ | |
488 | /* Reserved. */ | |
489 | return 0; | |
490 | case 3: /* 11: for testing - instruction memory */ | |
491 | offset = (offset % 0x800); | |
492 | *phys = SIM_D10V_MEMORY_INSN + offset; | |
493 | if (offset + nr_bytes > 0x800) | |
494 | /* don't cross VM boundary */ | |
495 | nr_bytes = 0x800 - offset; | |
496 | last_to = "test-insn"; | |
497 | break; | |
498 | } | |
499 | return nr_bytes; | |
500 | } | |
cff3e48b | 501 | |
6637a426 | 502 | static unsigned long |
67954606 MF |
503 | sim_d10v_translate_addr (SIM_DESC sd, |
504 | SIM_CPU *cpu, | |
505 | unsigned long memaddr, | |
4ce44c66 JM |
506 | int nr_bytes, |
507 | unsigned long *targ_addr, | |
f6684c31 | 508 | void *regcache, |
67954606 MF |
509 | unsigned long (*dmap_register) (SIM_DESC, |
510 | SIM_CPU *, | |
511 | void *regcache, | |
f6684c31 | 512 | int reg_nr), |
67954606 MF |
513 | unsigned long (*imap_register) (SIM_DESC, |
514 | SIM_CPU *, | |
515 | void *regcache, | |
f6684c31 | 516 | int reg_nr)) |
4ce44c66 JM |
517 | { |
518 | unsigned long phys; | |
519 | unsigned long seg; | |
520 | unsigned long off; | |
cff3e48b | 521 | |
4ce44c66 JM |
522 | last_from = "unknown"; |
523 | last_to = "unknown"; | |
cff3e48b | 524 | |
4ce44c66 JM |
525 | seg = (memaddr >> 24); |
526 | off = (memaddr & 0xffffffL); | |
c906108c | 527 | |
cff3e48b JM |
528 | /* However, if we've asked to use the previous generation of segment |
529 | mapping, rearrange the segments as follows. */ | |
530 | ||
531 | if (old_segment_mapping) | |
532 | { | |
4ce44c66 | 533 | switch (seg) |
cff3e48b JM |
534 | { |
535 | case 0x00: /* DMAP translated memory */ | |
4ce44c66 | 536 | seg = 0x10; |
cff3e48b JM |
537 | break; |
538 | case 0x01: /* IMAP translated memory */ | |
4ce44c66 | 539 | seg = 0x11; |
cff3e48b JM |
540 | break; |
541 | case 0x10: /* On-chip data memory */ | |
4ce44c66 | 542 | seg = 0x02; |
cff3e48b JM |
543 | break; |
544 | case 0x11: /* On-chip insn memory */ | |
4ce44c66 | 545 | seg = 0x01; |
cff3e48b JM |
546 | break; |
547 | case 0x12: /* Unified memory */ | |
4ce44c66 | 548 | seg = 0x00; |
cff3e48b JM |
549 | break; |
550 | } | |
551 | } | |
552 | ||
4ce44c66 | 553 | switch (seg) |
c906108c | 554 | { |
4ce44c66 JM |
555 | case 0x00: /* Physical unified memory */ |
556 | last_from = "phys-unified"; | |
557 | last_to = "unified"; | |
558 | phys = SIM_D10V_MEMORY_UNIFIED + off; | |
559 | if ((off % SEGMENT_SIZE) + nr_bytes > SEGMENT_SIZE) | |
560 | nr_bytes = SEGMENT_SIZE - (off % SEGMENT_SIZE); | |
561 | break; | |
c906108c | 562 | |
4ce44c66 JM |
563 | case 0x01: /* Physical instruction memory */ |
564 | last_from = "phys-insn"; | |
565 | last_to = "chip-insn"; | |
566 | phys = SIM_D10V_MEMORY_INSN + off; | |
567 | if ((off % SEGMENT_SIZE) + nr_bytes > SEGMENT_SIZE) | |
568 | nr_bytes = SEGMENT_SIZE - (off % SEGMENT_SIZE); | |
569 | break; | |
c906108c | 570 | |
4ce44c66 JM |
571 | case 0x02: /* Physical data memory segment */ |
572 | last_from = "phys-data"; | |
573 | last_to = "chip-data"; | |
574 | phys = SIM_D10V_MEMORY_DATA + off; | |
575 | if ((off % SEGMENT_SIZE) + nr_bytes > SEGMENT_SIZE) | |
576 | nr_bytes = SEGMENT_SIZE - (off % SEGMENT_SIZE); | |
577 | break; | |
578 | ||
579 | case 0x10: /* in logical data address segment */ | |
67954606 MF |
580 | nr_bytes = sim_d10v_translate_dmap_addr (sd, cpu, off, nr_bytes, &phys, |
581 | regcache, dmap_register); | |
4ce44c66 JM |
582 | break; |
583 | ||
584 | case 0x11: /* in logical instruction address segment */ | |
67954606 MF |
585 | nr_bytes = sim_d10v_translate_imap_addr (sd, cpu, off, nr_bytes, &phys, |
586 | regcache, imap_register); | |
4ce44c66 JM |
587 | break; |
588 | ||
589 | default: | |
590 | return 0; | |
591 | } | |
592 | ||
593 | *targ_addr = phys; | |
594 | return nr_bytes; | |
595 | } | |
596 | ||
597 | /* Return a pointer into the raw buffer designated by phys_addr. It | |
598 | is assumed that the client has already ensured that the access | |
599 | isn't going to cross a segment boundary. */ | |
600 | ||
601 | uint8 * | |
67954606 | 602 | map_memory (SIM_DESC sd, SIM_CPU *cpu, unsigned phys_addr) |
4ce44c66 JM |
603 | { |
604 | uint8 **memory; | |
605 | uint8 *raw; | |
606 | unsigned offset; | |
607 | int segment = ((phys_addr >> 24) & 0xff); | |
608 | ||
609 | switch (segment) | |
610 | { | |
611 | ||
612 | case 0x00: /* Unified memory */ | |
c906108c | 613 | { |
4ce44c66 JM |
614 | memory = &State.mem.unif[(phys_addr / SEGMENT_SIZE) % UMEM_SEGMENTS]; |
615 | last_segname = "umem"; | |
c906108c SS |
616 | break; |
617 | } | |
4ce44c66 | 618 | |
cff3e48b | 619 | case 0x01: /* On-chip insn memory */ |
c906108c | 620 | { |
4ce44c66 JM |
621 | memory = &State.mem.insn[(phys_addr / SEGMENT_SIZE) % IMEM_SEGMENTS]; |
622 | last_segname = "imem"; | |
c906108c SS |
623 | break; |
624 | } | |
4ce44c66 JM |
625 | |
626 | case 0x02: /* On-chip data memory */ | |
c906108c | 627 | { |
4ce44c66 | 628 | if ((phys_addr & 0xff00) == 0xff00) |
c906108c | 629 | { |
4ce44c66 JM |
630 | phys_addr = (phys_addr & 0xffff); |
631 | if (phys_addr == DMAP2_SHADDOW) | |
c906108c | 632 | { |
4ce44c66 JM |
633 | phys_addr = DMAP2_OFFSET; |
634 | last_segname = "dmap"; | |
c906108c | 635 | } |
4ce44c66 JM |
636 | else |
637 | last_segname = "reg"; | |
c906108c | 638 | } |
4ce44c66 JM |
639 | else |
640 | last_segname = "dmem"; | |
641 | memory = &State.mem.data[(phys_addr / SEGMENT_SIZE) % DMEM_SEGMENTS]; | |
c906108c SS |
642 | break; |
643 | } | |
4ce44c66 | 644 | |
c906108c | 645 | default: |
4ce44c66 JM |
646 | /* OOPS! */ |
647 | last_segname = "scrap"; | |
aadc1740 | 648 | sim_engine_halt (sd, cpu, NULL, PC, sim_stopped, SIM_SIGBUS); |
c906108c | 649 | } |
4ce44c66 JM |
650 | |
651 | if (*memory == NULL) | |
aadc1740 | 652 | *memory = xcalloc (1, SEGMENT_SIZE); |
4ce44c66 JM |
653 | |
654 | offset = (phys_addr % SEGMENT_SIZE); | |
655 | raw = *memory + offset; | |
656 | return raw; | |
657 | } | |
658 | ||
659 | /* Transfer data to/from simulated memory. Since a bug in either the | |
660 | simulated program or in gdb or the simulator itself may cause a | |
661 | bogus address to be passed in, we need to do some sanity checking | |
662 | on addresses to make sure they are within bounds. When an address | |
663 | fails the bounds check, treat it as a zero length read/write rather | |
664 | than aborting the entire run. */ | |
665 | ||
666 | static int | |
67954606 MF |
667 | xfer_mem (SIM_DESC sd, |
668 | SIM_ADDR virt, | |
4ce44c66 JM |
669 | unsigned char *buffer, |
670 | int size, | |
671 | int write_p) | |
672 | { | |
ea086965 AC |
673 | uint8 *memory; |
674 | unsigned long phys; | |
675 | int phys_size; | |
67954606 | 676 | phys_size = sim_d10v_translate_addr (sd, NULL, virt, size, &phys, NULL, |
ea086965 AC |
677 | dmap_register, imap_register); |
678 | if (phys_size == 0) | |
679 | return 0; | |
4ce44c66 | 680 | |
67954606 | 681 | memory = map_memory (sd, NULL, phys); |
4ce44c66 JM |
682 | |
683 | #ifdef DEBUG | |
ea086965 AC |
684 | if ((d10v_debug & DEBUG_INSTRUCTION) != 0) |
685 | { | |
e9b0081f MF |
686 | sim_io_printf |
687 | (sd, | |
ea086965 | 688 | "sim_%s %d bytes: 0x%08lx (%s) -> 0x%08lx (%s) -> 0x%08lx (%s)\n", |
e9b0081f | 689 | write_p ? "write" : "read", |
ea086965 AC |
690 | phys_size, virt, last_from, |
691 | phys, last_to, | |
692 | (long) memory, last_segname); | |
693 | } | |
4ce44c66 JM |
694 | #endif |
695 | ||
ea086965 AC |
696 | if (write_p) |
697 | { | |
698 | memcpy (memory, buffer, phys_size); | |
c906108c | 699 | } |
ea086965 AC |
700 | else |
701 | { | |
702 | memcpy (buffer, memory, phys_size); | |
703 | } | |
704 | ||
705 | return phys_size; | |
c906108c SS |
706 | } |
707 | ||
708 | ||
709 | int | |
11558abc | 710 | sim_write (SIM_DESC sd, SIM_ADDR addr, const unsigned char *buffer, int size) |
c906108c SS |
711 | { |
712 | /* FIXME: this should be performing a virtual transfer */ | |
67954606 | 713 | return xfer_mem (sd, addr, buffer, size, 1); |
c906108c SS |
714 | } |
715 | ||
716 | int | |
11558abc | 717 | sim_read (SIM_DESC sd, SIM_ADDR addr, unsigned char *buffer, int size) |
c906108c SS |
718 | { |
719 | /* FIXME: this should be performing a virtual transfer */ | |
67954606 | 720 | return xfer_mem (sd, addr, buffer, size, 0); |
c906108c SS |
721 | } |
722 | ||
27b97b40 MF |
723 | static sim_cia |
724 | d10v_pc_get (sim_cpu *cpu) | |
725 | { | |
726 | return PC; | |
727 | } | |
728 | ||
729 | static void | |
730 | d10v_pc_set (sim_cpu *cpu, sim_cia pc) | |
731 | { | |
67954606 | 732 | SIM_DESC sd = CPU_STATE (cpu); |
27b97b40 MF |
733 | SET_PC (pc); |
734 | } | |
735 | ||
541ebcee MF |
736 | static void |
737 | free_state (SIM_DESC sd) | |
738 | { | |
739 | if (STATE_MODULES (sd) != NULL) | |
740 | sim_module_uninstall (sd); | |
741 | sim_cpu_free_all (sd); | |
742 | sim_state_free (sd); | |
743 | } | |
744 | ||
c906108c | 745 | SIM_DESC |
541ebcee | 746 | sim_open (SIM_OPEN_KIND kind, host_callback *cb, struct bfd *abfd, char **argv) |
c906108c SS |
747 | { |
748 | struct simops *s; | |
749 | struct hash_entry *h; | |
750 | static int init_p = 0; | |
751 | char **p; | |
27b97b40 | 752 | int i; |
541ebcee MF |
753 | SIM_DESC sd = sim_state_alloc (kind, cb); |
754 | SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER); | |
c906108c | 755 | |
541ebcee MF |
756 | /* The cpu data is kept in a separately allocated chunk of memory. */ |
757 | if (sim_cpu_alloc_all (sd, 1, /*cgen_cpu_max_extra_bytes ()*/0) != SIM_RC_OK) | |
758 | { | |
759 | free_state (sd); | |
760 | return 0; | |
761 | } | |
762 | ||
763 | if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK) | |
764 | { | |
765 | free_state (sd); | |
766 | return 0; | |
767 | } | |
768 | ||
769 | /* getopt will print the error message so we just have to exit if this fails. | |
770 | FIXME: Hmmm... in the case of gdb we need getopt to call | |
771 | print_filtered. */ | |
772 | if (sim_parse_args (sd, argv) != SIM_RC_OK) | |
773 | { | |
774 | free_state (sd); | |
775 | return 0; | |
776 | } | |
777 | ||
778 | /* Check for/establish the a reference program image. */ | |
779 | if (sim_analyze_program (sd, | |
780 | (STATE_PROG_ARGV (sd) != NULL | |
781 | ? *STATE_PROG_ARGV (sd) | |
782 | : NULL), abfd) != SIM_RC_OK) | |
783 | { | |
784 | free_state (sd); | |
785 | return 0; | |
786 | } | |
787 | ||
788 | /* Configure/verify the target byte order and other runtime | |
789 | configuration options. */ | |
790 | if (sim_config (sd) != SIM_RC_OK) | |
791 | { | |
792 | sim_module_uninstall (sd); | |
793 | return 0; | |
794 | } | |
795 | ||
796 | if (sim_post_argv_init (sd) != SIM_RC_OK) | |
797 | { | |
798 | /* Uninstall the modules to avoid memory leaks, | |
799 | file descriptor leaks, etc. */ | |
800 | sim_module_uninstall (sd); | |
801 | return 0; | |
802 | } | |
803 | ||
27b97b40 MF |
804 | /* CPU specific initialization. */ |
805 | for (i = 0; i < MAX_NR_PROCESSORS; ++i) | |
806 | { | |
807 | SIM_CPU *cpu = STATE_CPU (sd, i); | |
808 | ||
809 | CPU_PC_FETCH (cpu) = d10v_pc_get; | |
810 | CPU_PC_STORE (cpu) = d10v_pc_set; | |
811 | } | |
812 | ||
cff3e48b | 813 | old_segment_mapping = 0; |
c906108c | 814 | |
4ce44c66 JM |
815 | /* NOTE: This argument parsing is only effective when this function |
816 | is called by GDB. Standalone argument parsing is handled by | |
817 | sim/common/run.c. */ | |
c906108c SS |
818 | for (p = argv + 1; *p; ++p) |
819 | { | |
cff3e48b JM |
820 | if (strcmp (*p, "-oldseg") == 0) |
821 | old_segment_mapping = 1; | |
c906108c | 822 | #ifdef DEBUG |
cff3e48b | 823 | else if (strcmp (*p, "-t") == 0) |
c906108c | 824 | d10v_debug = DEBUG; |
4ce44c66 JM |
825 | else if (strncmp (*p, "-t", 2) == 0) |
826 | d10v_debug = atoi (*p + 2); | |
c906108c | 827 | #endif |
c906108c SS |
828 | } |
829 | ||
830 | /* put all the opcodes in the hash table */ | |
831 | if (!init_p++) | |
832 | { | |
833 | for (s = Simops; s->func; s++) | |
834 | { | |
835 | h = &hash_table[hash(s->opcode,s->format)]; | |
836 | ||
837 | /* go to the last entry in the chain */ | |
838 | while (h->next) | |
839 | h = h->next; | |
840 | ||
841 | if (h->ops) | |
842 | { | |
843 | h->next = (struct hash_entry *) calloc(1,sizeof(struct hash_entry)); | |
844 | if (!h->next) | |
845 | perror ("malloc failure"); | |
846 | ||
847 | h = h->next; | |
848 | } | |
849 | h->ops = s; | |
850 | h->mask = s->mask; | |
851 | h->opcode = s->opcode; | |
852 | h->size = s->is_long; | |
853 | } | |
854 | } | |
855 | ||
856 | /* reset the processor state */ | |
4ce44c66 JM |
857 | if (!State.mem.data[0]) |
858 | sim_size (1); | |
c906108c SS |
859 | sim_create_inferior ((SIM_DESC) 1, NULL, NULL, NULL); |
860 | ||
541ebcee | 861 | return sd; |
c906108c SS |
862 | } |
863 | ||
c906108c | 864 | uint8 * |
67954606 | 865 | dmem_addr (SIM_DESC sd, SIM_CPU *cpu, uint16 offset) |
c906108c | 866 | { |
4ce44c66 JM |
867 | unsigned long phys; |
868 | uint8 *mem; | |
869 | int phys_size; | |
c906108c | 870 | |
4ce44c66 JM |
871 | /* Note: DMEM address range is 0..0x10000. Calling code can compute |
872 | things like ``0xfffe + 0x0e60 == 0x10e5d''. Since offset's type | |
873 | is uint16 this is modulo'ed onto 0x0e5d. */ | |
c906108c | 874 | |
67954606 | 875 | phys_size = sim_d10v_translate_dmap_addr (sd, cpu, offset, 1, &phys, NULL, |
4ce44c66 JM |
876 | dmap_register); |
877 | if (phys_size == 0) | |
aadc1740 MF |
878 | sim_engine_halt (sd, cpu, NULL, PC, sim_stopped, SIM_SIGBUS); |
879 | mem = map_memory (sd, cpu, phys); | |
c906108c | 880 | #ifdef DEBUG |
4ce44c66 JM |
881 | if ((d10v_debug & DEBUG_MEMORY)) |
882 | { | |
e9b0081f MF |
883 | sim_io_printf |
884 | (sd, | |
4ce44c66 JM |
885 | "mem: 0x%08x (%s) -> 0x%08lx %d (%s) -> 0x%08lx (%s)\n", |
886 | offset, last_from, | |
887 | phys, phys_size, last_to, | |
888 | (long) mem, last_segname); | |
c906108c | 889 | } |
4ce44c66 JM |
890 | #endif |
891 | return mem; | |
c906108c SS |
892 | } |
893 | ||
c906108c | 894 | uint8 * |
67954606 | 895 | imem_addr (SIM_DESC sd, SIM_CPU *cpu, uint32 offset) |
c906108c | 896 | { |
4ce44c66 JM |
897 | unsigned long phys; |
898 | uint8 *mem; | |
67954606 | 899 | int phys_size = sim_d10v_translate_imap_addr (sd, cpu, offset, 1, &phys, NULL, |
f6684c31 | 900 | imap_register); |
4ce44c66 | 901 | if (phys_size == 0) |
aadc1740 | 902 | sim_engine_halt (sd, cpu, NULL, PC, sim_stopped, SIM_SIGBUS); |
67954606 | 903 | mem = map_memory (sd, cpu, phys); |
4ce44c66 JM |
904 | #ifdef DEBUG |
905 | if ((d10v_debug & DEBUG_MEMORY)) | |
906 | { | |
e9b0081f MF |
907 | sim_io_printf |
908 | (sd, | |
4ce44c66 JM |
909 | "mem: 0x%08x (%s) -> 0x%08lx %d (%s) -> 0x%08lx (%s)\n", |
910 | offset, last_from, | |
911 | phys, phys_size, last_to, | |
912 | (long) mem, last_segname); | |
913 | } | |
914 | #endif | |
915 | return mem; | |
c906108c SS |
916 | } |
917 | ||
aadc1740 MF |
918 | static void |
919 | step_once (SIM_DESC sd, SIM_CPU *cpu) | |
c906108c SS |
920 | { |
921 | uint32 inst; | |
922 | uint8 *iaddr; | |
923 | ||
aadc1740 | 924 | /* TODO: Unindent this block. */ |
c906108c | 925 | { |
67954606 | 926 | iaddr = imem_addr (sd, cpu, (uint32)PC << 2); |
c906108c SS |
927 | |
928 | inst = get_longword( iaddr ); | |
929 | ||
930 | State.pc_changed = 0; | |
931 | ins_type_counters[ (int)INS_CYCLES ]++; | |
932 | ||
933 | switch (inst & 0xC0000000) | |
934 | { | |
935 | case 0xC0000000: | |
936 | /* long instruction */ | |
67954606 | 937 | do_long (sd, cpu, inst & 0x3FFFFFFF); |
c906108c SS |
938 | break; |
939 | case 0x80000000: | |
940 | /* R -> L */ | |
67954606 | 941 | do_2_short (sd, cpu, inst & 0x7FFF, (inst & 0x3FFF8000) >> 15, RIGHT_FIRST); |
c906108c SS |
942 | break; |
943 | case 0x40000000: | |
944 | /* L -> R */ | |
67954606 | 945 | do_2_short (sd, cpu, (inst & 0x3FFF8000) >> 15, inst & 0x7FFF, LEFT_FIRST); |
c906108c SS |
946 | break; |
947 | case 0: | |
67954606 | 948 | do_parallel (sd, cpu, (inst & 0x3FFF8000) >> 15, inst & 0x7FFF); |
c906108c SS |
949 | break; |
950 | } | |
951 | ||
952 | /* If the PC of the current instruction matches RPT_E then | |
953 | schedule a branch to the loop start. If one of those | |
954 | instructions happens to be a branch, than that instruction | |
955 | will be ignored */ | |
956 | if (!State.pc_changed) | |
957 | { | |
958 | if (PSW_RP && PC == RPT_E) | |
959 | { | |
960 | /* Note: The behavour of a branch instruction at RPT_E | |
961 | is implementation dependant, this simulator takes the | |
962 | branch. Branching to RPT_E is valid, the instruction | |
963 | must be executed before the loop is taken. */ | |
964 | if (RPT_C == 1) | |
965 | { | |
966 | SET_PSW_RP (0); | |
967 | SET_RPT_C (0); | |
968 | SET_PC (PC + 1); | |
969 | } | |
970 | else | |
971 | { | |
972 | SET_RPT_C (RPT_C - 1); | |
973 | SET_PC (RPT_S); | |
974 | } | |
975 | } | |
976 | else | |
977 | SET_PC (PC + 1); | |
978 | } | |
979 | ||
980 | /* Check for a breakpoint trap on this instruction. This | |
981 | overrides any pending branches or loops */ | |
982 | if (PSW_DB && PC == IBA) | |
983 | { | |
984 | SET_BPC (PC); | |
985 | SET_BPSW (PSW); | |
986 | SET_PSW (PSW & PSW_SM_BIT); | |
987 | SET_PC (SDBT_VECTOR_START); | |
988 | } | |
989 | ||
990 | /* Writeback all the DATA / PC changes */ | |
991 | SLOT_FLUSH (); | |
c906108c | 992 | } |
aadc1740 MF |
993 | } |
994 | ||
995 | void | |
996 | sim_engine_run (SIM_DESC sd, | |
997 | int next_cpu_nr, /* ignore */ | |
998 | int nr_cpus, /* ignore */ | |
999 | int siggnal) | |
1000 | { | |
1001 | sim_cpu *cpu; | |
1002 | ||
1003 | SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER); | |
1004 | ||
1005 | cpu = STATE_CPU (sd, 0); | |
1006 | ||
1007 | switch (siggnal) | |
1008 | { | |
1009 | case 0: | |
1010 | break; | |
1011 | case GDB_SIGNAL_BUS: | |
1012 | SET_BPC (PC); | |
1013 | SET_BPSW (PSW); | |
1014 | SET_HW_PSW ((PSW & (PSW_F0_BIT | PSW_F1_BIT | PSW_C_BIT))); | |
1015 | JMP (AE_VECTOR_START); | |
1016 | SLOT_FLUSH (); | |
1017 | break; | |
1018 | case GDB_SIGNAL_ILL: | |
1019 | SET_BPC (PC); | |
1020 | SET_BPSW (PSW); | |
1021 | SET_HW_PSW ((PSW & (PSW_F0_BIT | PSW_F1_BIT | PSW_C_BIT))); | |
1022 | JMP (RIE_VECTOR_START); | |
1023 | SLOT_FLUSH (); | |
1024 | break; | |
1025 | default: | |
1026 | /* just ignore it */ | |
1027 | break; | |
1028 | } | |
1029 | ||
1030 | while (1) | |
1031 | { | |
1032 | step_once (sd, cpu); | |
1033 | if (sim_events_tick (sd)) | |
1034 | sim_events_process (sd); | |
1035 | } | |
c906108c SS |
1036 | } |
1037 | ||
c906108c | 1038 | void |
11558abc | 1039 | sim_info (SIM_DESC sd, int verbose) |
c906108c SS |
1040 | { |
1041 | char buf1[40]; | |
1042 | char buf2[40]; | |
1043 | char buf3[40]; | |
1044 | char buf4[40]; | |
1045 | char buf5[40]; | |
1046 | unsigned long left = ins_type_counters[ (int)INS_LEFT ] + ins_type_counters[ (int)INS_LEFT_COND_EXE ]; | |
1047 | unsigned long left_nops = ins_type_counters[ (int)INS_LEFT_NOPS ]; | |
1048 | unsigned long left_parallel = ins_type_counters[ (int)INS_LEFT_PARALLEL ]; | |
1049 | unsigned long left_cond = ins_type_counters[ (int)INS_LEFT_COND_TEST ]; | |
1050 | unsigned long left_total = left + left_parallel + left_cond + left_nops; | |
1051 | ||
1052 | unsigned long right = ins_type_counters[ (int)INS_RIGHT ] + ins_type_counters[ (int)INS_RIGHT_COND_EXE ]; | |
1053 | unsigned long right_nops = ins_type_counters[ (int)INS_RIGHT_NOPS ]; | |
1054 | unsigned long right_parallel = ins_type_counters[ (int)INS_RIGHT_PARALLEL ]; | |
1055 | unsigned long right_cond = ins_type_counters[ (int)INS_RIGHT_COND_TEST ]; | |
1056 | unsigned long right_total = right + right_parallel + right_cond + right_nops; | |
1057 | ||
1058 | unsigned long unknown = ins_type_counters[ (int)INS_UNKNOWN ]; | |
1059 | unsigned long ins_long = ins_type_counters[ (int)INS_LONG ]; | |
1060 | unsigned long parallel = ins_type_counters[ (int)INS_PARALLEL ]; | |
1061 | unsigned long leftright = ins_type_counters[ (int)INS_LEFTRIGHT ]; | |
1062 | unsigned long rightleft = ins_type_counters[ (int)INS_RIGHTLEFT ]; | |
1063 | unsigned long cond_true = ins_type_counters[ (int)INS_COND_TRUE ]; | |
1064 | unsigned long cond_false = ins_type_counters[ (int)INS_COND_FALSE ]; | |
1065 | unsigned long cond_jump = ins_type_counters[ (int)INS_COND_JUMP ]; | |
1066 | unsigned long cycles = ins_type_counters[ (int)INS_CYCLES ]; | |
1067 | unsigned long total = (unknown + left_total + right_total + ins_long); | |
1068 | ||
1069 | int size = strlen (add_commas (buf1, sizeof (buf1), total)); | |
1070 | int parallel_size = strlen (add_commas (buf1, sizeof (buf1), | |
1071 | (left_parallel > right_parallel) ? left_parallel : right_parallel)); | |
1072 | int cond_size = strlen (add_commas (buf1, sizeof (buf1), (left_cond > right_cond) ? left_cond : right_cond)); | |
1073 | int nop_size = strlen (add_commas (buf1, sizeof (buf1), (left_nops > right_nops) ? left_nops : right_nops)); | |
1074 | int normal_size = strlen (add_commas (buf1, sizeof (buf1), (left > right) ? left : right)); | |
1075 | ||
e9b0081f MF |
1076 | sim_io_printf (sd, |
1077 | "executed %*s left instruction(s), %*s normal, %*s parallel, %*s EXExxx, %*s nops\n", | |
1078 | size, add_commas (buf1, sizeof (buf1), left_total), | |
1079 | normal_size, add_commas (buf2, sizeof (buf2), left), | |
1080 | parallel_size, add_commas (buf3, sizeof (buf3), left_parallel), | |
1081 | cond_size, add_commas (buf4, sizeof (buf4), left_cond), | |
1082 | nop_size, add_commas (buf5, sizeof (buf5), left_nops)); | |
1083 | ||
1084 | sim_io_printf (sd, | |
1085 | "executed %*s right instruction(s), %*s normal, %*s parallel, %*s EXExxx, %*s nops\n", | |
1086 | size, add_commas (buf1, sizeof (buf1), right_total), | |
1087 | normal_size, add_commas (buf2, sizeof (buf2), right), | |
1088 | parallel_size, add_commas (buf3, sizeof (buf3), right_parallel), | |
1089 | cond_size, add_commas (buf4, sizeof (buf4), right_cond), | |
1090 | nop_size, add_commas (buf5, sizeof (buf5), right_nops)); | |
c906108c SS |
1091 | |
1092 | if (ins_long) | |
e9b0081f MF |
1093 | sim_io_printf (sd, |
1094 | "executed %*s long instruction(s)\n", | |
1095 | size, add_commas (buf1, sizeof (buf1), ins_long)); | |
c906108c SS |
1096 | |
1097 | if (parallel) | |
e9b0081f MF |
1098 | sim_io_printf (sd, |
1099 | "executed %*s parallel instruction(s)\n", | |
1100 | size, add_commas (buf1, sizeof (buf1), parallel)); | |
c906108c SS |
1101 | |
1102 | if (leftright) | |
e9b0081f MF |
1103 | sim_io_printf (sd, |
1104 | "executed %*s instruction(s) encoded L->R\n", | |
1105 | size, add_commas (buf1, sizeof (buf1), leftright)); | |
c906108c SS |
1106 | |
1107 | if (rightleft) | |
e9b0081f MF |
1108 | sim_io_printf (sd, |
1109 | "executed %*s instruction(s) encoded R->L\n", | |
1110 | size, add_commas (buf1, sizeof (buf1), rightleft)); | |
c906108c SS |
1111 | |
1112 | if (unknown) | |
e9b0081f MF |
1113 | sim_io_printf (sd, |
1114 | "executed %*s unknown instruction(s)\n", | |
1115 | size, add_commas (buf1, sizeof (buf1), unknown)); | |
c906108c SS |
1116 | |
1117 | if (cond_true) | |
e9b0081f MF |
1118 | sim_io_printf (sd, |
1119 | "executed %*s instruction(s) due to EXExxx condition being true\n", | |
1120 | size, add_commas (buf1, sizeof (buf1), cond_true)); | |
c906108c SS |
1121 | |
1122 | if (cond_false) | |
e9b0081f MF |
1123 | sim_io_printf (sd, |
1124 | "skipped %*s instruction(s) due to EXExxx condition being false\n", | |
1125 | size, add_commas (buf1, sizeof (buf1), cond_false)); | |
c906108c SS |
1126 | |
1127 | if (cond_jump) | |
e9b0081f MF |
1128 | sim_io_printf (sd, |
1129 | "skipped %*s instruction(s) due to conditional branch succeeding\n", | |
1130 | size, add_commas (buf1, sizeof (buf1), cond_jump)); | |
c906108c | 1131 | |
e9b0081f MF |
1132 | sim_io_printf (sd, |
1133 | "executed %*s cycle(s)\n", | |
1134 | size, add_commas (buf1, sizeof (buf1), cycles)); | |
c906108c | 1135 | |
e9b0081f MF |
1136 | sim_io_printf (sd, |
1137 | "executed %*s total instructions\n", | |
1138 | size, add_commas (buf1, sizeof (buf1), total)); | |
c906108c SS |
1139 | } |
1140 | ||
1141 | SIM_RC | |
11558abc | 1142 | sim_create_inferior (SIM_DESC sd, struct bfd *abfd, char **argv, char **env) |
c906108c SS |
1143 | { |
1144 | bfd_vma start_address; | |
1145 | ||
1146 | /* reset all state information */ | |
11558abc | 1147 | memset (&State.regs, 0, (uintptr_t)&State.mem - (uintptr_t)&State.regs); |
c906108c | 1148 | |
1aa5e64f EZ |
1149 | /* There was a hack here to copy the values of argc and argv into r0 |
1150 | and r1. The values were also saved into some high memory that | |
1151 | won't be overwritten by the stack (0x7C00). The reason for doing | |
1152 | this was to allow the 'run' program to accept arguments. Without | |
1153 | the hack, this is not possible anymore. If the simulator is run | |
1154 | from the debugger, arguments cannot be passed in, so this makes | |
1155 | no difference. */ | |
1156 | ||
c906108c SS |
1157 | /* set PC */ |
1158 | if (abfd != NULL) | |
1159 | start_address = bfd_get_start_address (abfd); | |
1160 | else | |
1161 | start_address = 0xffc0 << 2; | |
1162 | #ifdef DEBUG | |
1163 | if (d10v_debug) | |
e9b0081f | 1164 | sim_io_printf (sd, "sim_create_inferior: PC=0x%lx\n", (long) start_address); |
c906108c | 1165 | #endif |
67954606 MF |
1166 | { |
1167 | SIM_CPU *cpu = STATE_CPU (sd, 0); | |
1168 | SET_CREG (PC_CR, start_address >> 2); | |
1169 | } | |
c906108c | 1170 | |
4ce44c66 JM |
1171 | /* cpu resets imap0 to 0 and imap1 to 0x7f, but D10V-EVA board |
1172 | initializes imap0 and imap1 to 0x1000 as part of its ROM | |
1173 | initialization. */ | |
cff3e48b | 1174 | if (old_segment_mapping) |
c906108c | 1175 | { |
4ce44c66 | 1176 | /* External memory startup. This is the HARD reset state. */ |
67954606 MF |
1177 | set_imap_register (sd, 0, 0x0000); |
1178 | set_imap_register (sd, 1, 0x007f); | |
1179 | set_dmap_register (sd, 0, 0x2000); | |
1180 | set_dmap_register (sd, 1, 0x2000); | |
1181 | set_dmap_register (sd, 2, 0x0000); /* Old DMAP */ | |
1182 | set_dmap_register (sd, 3, 0x0000); | |
c906108c SS |
1183 | } |
1184 | else | |
1185 | { | |
4ce44c66 | 1186 | /* Internal memory startup. This is the ROM intialized state. */ |
67954606 MF |
1187 | set_imap_register (sd, 0, 0x1000); |
1188 | set_imap_register (sd, 1, 0x1000); | |
1189 | set_dmap_register (sd, 0, 0x2000); | |
1190 | set_dmap_register (sd, 1, 0x2000); | |
1191 | set_dmap_register (sd, 2, 0x2000); /* DMAP2 initial internal value is | |
1192 | 0x2000 on the new board. */ | |
1193 | set_dmap_register (sd, 3, 0x0000); | |
c906108c SS |
1194 | } |
1195 | ||
1196 | SLOT_FLUSH (); | |
1197 | return SIM_RC_OK; | |
1198 | } | |
1199 | ||
c906108c | 1200 | int |
11558abc | 1201 | sim_fetch_register (SIM_DESC sd, int rn, unsigned char *memory, int length) |
c906108c | 1202 | { |
67954606 | 1203 | SIM_CPU *cpu = STATE_CPU (sd, 0); |
4ce44c66 | 1204 | int size; |
983b727e | 1205 | switch ((enum sim_d10v_regs) rn) |
4ce44c66 | 1206 | { |
18c0df9e AC |
1207 | case SIM_D10V_R0_REGNUM: |
1208 | case SIM_D10V_R1_REGNUM: | |
1209 | case SIM_D10V_R2_REGNUM: | |
1210 | case SIM_D10V_R3_REGNUM: | |
1211 | case SIM_D10V_R4_REGNUM: | |
1212 | case SIM_D10V_R5_REGNUM: | |
1213 | case SIM_D10V_R6_REGNUM: | |
1214 | case SIM_D10V_R7_REGNUM: | |
1215 | case SIM_D10V_R8_REGNUM: | |
1216 | case SIM_D10V_R9_REGNUM: | |
1217 | case SIM_D10V_R10_REGNUM: | |
1218 | case SIM_D10V_R11_REGNUM: | |
1219 | case SIM_D10V_R12_REGNUM: | |
1220 | case SIM_D10V_R13_REGNUM: | |
1221 | case SIM_D10V_R14_REGNUM: | |
1222 | case SIM_D10V_R15_REGNUM: | |
4ce44c66 JM |
1223 | WRITE_16 (memory, GPR (rn - SIM_D10V_R0_REGNUM)); |
1224 | size = 2; | |
18c0df9e AC |
1225 | break; |
1226 | case SIM_D10V_CR0_REGNUM: | |
1227 | case SIM_D10V_CR1_REGNUM: | |
1228 | case SIM_D10V_CR2_REGNUM: | |
1229 | case SIM_D10V_CR3_REGNUM: | |
1230 | case SIM_D10V_CR4_REGNUM: | |
1231 | case SIM_D10V_CR5_REGNUM: | |
1232 | case SIM_D10V_CR6_REGNUM: | |
1233 | case SIM_D10V_CR7_REGNUM: | |
1234 | case SIM_D10V_CR8_REGNUM: | |
1235 | case SIM_D10V_CR9_REGNUM: | |
1236 | case SIM_D10V_CR10_REGNUM: | |
1237 | case SIM_D10V_CR11_REGNUM: | |
1238 | case SIM_D10V_CR12_REGNUM: | |
1239 | case SIM_D10V_CR13_REGNUM: | |
1240 | case SIM_D10V_CR14_REGNUM: | |
1241 | case SIM_D10V_CR15_REGNUM: | |
4ce44c66 JM |
1242 | WRITE_16 (memory, CREG (rn - SIM_D10V_CR0_REGNUM)); |
1243 | size = 2; | |
18c0df9e AC |
1244 | break; |
1245 | case SIM_D10V_A0_REGNUM: | |
1246 | case SIM_D10V_A1_REGNUM: | |
4ce44c66 JM |
1247 | WRITE_64 (memory, ACC (rn - SIM_D10V_A0_REGNUM)); |
1248 | size = 8; | |
18c0df9e AC |
1249 | break; |
1250 | case SIM_D10V_SPI_REGNUM: | |
4ce44c66 JM |
1251 | /* PSW_SM indicates that the current SP is the USER |
1252 | stack-pointer. */ | |
1253 | WRITE_16 (memory, spi_register ()); | |
1254 | size = 2; | |
18c0df9e AC |
1255 | break; |
1256 | case SIM_D10V_SPU_REGNUM: | |
4ce44c66 JM |
1257 | /* PSW_SM indicates that the current SP is the USER |
1258 | stack-pointer. */ | |
1259 | WRITE_16 (memory, spu_register ()); | |
1260 | size = 2; | |
18c0df9e AC |
1261 | break; |
1262 | case SIM_D10V_IMAP0_REGNUM: | |
1263 | case SIM_D10V_IMAP1_REGNUM: | |
67954606 | 1264 | WRITE_16 (memory, imap_register (sd, cpu, NULL, rn - SIM_D10V_IMAP0_REGNUM)); |
4ce44c66 | 1265 | size = 2; |
18c0df9e AC |
1266 | break; |
1267 | case SIM_D10V_DMAP0_REGNUM: | |
1268 | case SIM_D10V_DMAP1_REGNUM: | |
1269 | case SIM_D10V_DMAP2_REGNUM: | |
1270 | case SIM_D10V_DMAP3_REGNUM: | |
67954606 | 1271 | WRITE_16 (memory, dmap_register (sd, cpu, NULL, rn - SIM_D10V_DMAP0_REGNUM)); |
4ce44c66 | 1272 | size = 2; |
18c0df9e AC |
1273 | break; |
1274 | case SIM_D10V_TS2_DMAP_REGNUM: | |
1275 | size = 0; | |
1276 | break; | |
1277 | default: | |
1278 | size = 0; | |
1279 | break; | |
4ce44c66 | 1280 | } |
4ce44c66 | 1281 | return size; |
c906108c SS |
1282 | } |
1283 | ||
1284 | int | |
11558abc | 1285 | sim_store_register (SIM_DESC sd, int rn, unsigned char *memory, int length) |
c906108c | 1286 | { |
67954606 | 1287 | SIM_CPU *cpu = STATE_CPU (sd, 0); |
4ce44c66 | 1288 | int size; |
983b727e | 1289 | switch ((enum sim_d10v_regs) rn) |
4ce44c66 | 1290 | { |
18c0df9e AC |
1291 | case SIM_D10V_R0_REGNUM: |
1292 | case SIM_D10V_R1_REGNUM: | |
1293 | case SIM_D10V_R2_REGNUM: | |
1294 | case SIM_D10V_R3_REGNUM: | |
1295 | case SIM_D10V_R4_REGNUM: | |
1296 | case SIM_D10V_R5_REGNUM: | |
1297 | case SIM_D10V_R6_REGNUM: | |
1298 | case SIM_D10V_R7_REGNUM: | |
1299 | case SIM_D10V_R8_REGNUM: | |
1300 | case SIM_D10V_R9_REGNUM: | |
1301 | case SIM_D10V_R10_REGNUM: | |
1302 | case SIM_D10V_R11_REGNUM: | |
1303 | case SIM_D10V_R12_REGNUM: | |
1304 | case SIM_D10V_R13_REGNUM: | |
1305 | case SIM_D10V_R14_REGNUM: | |
1306 | case SIM_D10V_R15_REGNUM: | |
4ce44c66 JM |
1307 | SET_GPR (rn - SIM_D10V_R0_REGNUM, READ_16 (memory)); |
1308 | size = 2; | |
18c0df9e AC |
1309 | break; |
1310 | case SIM_D10V_CR0_REGNUM: | |
1311 | case SIM_D10V_CR1_REGNUM: | |
1312 | case SIM_D10V_CR2_REGNUM: | |
1313 | case SIM_D10V_CR3_REGNUM: | |
1314 | case SIM_D10V_CR4_REGNUM: | |
1315 | case SIM_D10V_CR5_REGNUM: | |
1316 | case SIM_D10V_CR6_REGNUM: | |
1317 | case SIM_D10V_CR7_REGNUM: | |
1318 | case SIM_D10V_CR8_REGNUM: | |
1319 | case SIM_D10V_CR9_REGNUM: | |
1320 | case SIM_D10V_CR10_REGNUM: | |
1321 | case SIM_D10V_CR11_REGNUM: | |
1322 | case SIM_D10V_CR12_REGNUM: | |
1323 | case SIM_D10V_CR13_REGNUM: | |
1324 | case SIM_D10V_CR14_REGNUM: | |
1325 | case SIM_D10V_CR15_REGNUM: | |
4ce44c66 JM |
1326 | SET_CREG (rn - SIM_D10V_CR0_REGNUM, READ_16 (memory)); |
1327 | size = 2; | |
18c0df9e AC |
1328 | break; |
1329 | case SIM_D10V_A0_REGNUM: | |
1330 | case SIM_D10V_A1_REGNUM: | |
4ce44c66 JM |
1331 | SET_ACC (rn - SIM_D10V_A0_REGNUM, READ_64 (memory) & MASK40); |
1332 | size = 8; | |
18c0df9e AC |
1333 | break; |
1334 | case SIM_D10V_SPI_REGNUM: | |
4ce44c66 JM |
1335 | /* PSW_SM indicates that the current SP is the USER |
1336 | stack-pointer. */ | |
1337 | set_spi_register (READ_16 (memory)); | |
1338 | size = 2; | |
18c0df9e AC |
1339 | break; |
1340 | case SIM_D10V_SPU_REGNUM: | |
4ce44c66 JM |
1341 | set_spu_register (READ_16 (memory)); |
1342 | size = 2; | |
18c0df9e AC |
1343 | break; |
1344 | case SIM_D10V_IMAP0_REGNUM: | |
1345 | case SIM_D10V_IMAP1_REGNUM: | |
67954606 | 1346 | set_imap_register (sd, rn - SIM_D10V_IMAP0_REGNUM, READ_16(memory)); |
4ce44c66 | 1347 | size = 2; |
18c0df9e AC |
1348 | break; |
1349 | case SIM_D10V_DMAP0_REGNUM: | |
1350 | case SIM_D10V_DMAP1_REGNUM: | |
1351 | case SIM_D10V_DMAP2_REGNUM: | |
1352 | case SIM_D10V_DMAP3_REGNUM: | |
67954606 | 1353 | set_dmap_register (sd, rn - SIM_D10V_DMAP0_REGNUM, READ_16(memory)); |
4ce44c66 | 1354 | size = 2; |
18c0df9e AC |
1355 | break; |
1356 | case SIM_D10V_TS2_DMAP_REGNUM: | |
1357 | size = 0; | |
1358 | break; | |
1359 | default: | |
1360 | size = 0; | |
1361 | break; | |
4ce44c66 | 1362 | } |
c906108c | 1363 | SLOT_FLUSH (); |
4ce44c66 | 1364 | return size; |
c906108c | 1365 | } |