Commit | Line | Data |
---|---|---|
fd435e9f MM |
1 | #include "config.h" |
2 | ||
4f425a32 | 3 | #include <signal.h> |
63a91cfb MM |
4 | #include <errno.h> |
5 | #include <sys/types.h> | |
6 | #include <sys/stat.h> | |
fd435e9f | 7 | #ifdef HAVE_UNISTD_H |
63a91cfb | 8 | #include <unistd.h> |
fd435e9f | 9 | #endif |
63a91cfb | 10 | |
2934d1c9 MH |
11 | #include "d10v_sim.h" |
12 | #include "simops.h" | |
8719be26 | 13 | #include "sys/syscall.h" |
2934d1c9 | 14 | |
c422ecc7 MH |
15 | extern char *strrchr (); |
16 | ||
87178dbd MM |
17 | enum op_types { |
18 | OP_VOID, | |
19 | OP_REG, | |
20 | OP_REG_OUTPUT, | |
21 | OP_DREG, | |
22 | OP_DREG_OUTPUT, | |
23 | OP_ACCUM, | |
24 | OP_ACCUM_OUTPUT, | |
25 | OP_ACCUM_REVERSE, | |
26 | OP_CR, | |
27 | OP_CR_OUTPUT, | |
28 | OP_CR_REVERSE, | |
29 | OP_FLAG, | |
60fc5b72 | 30 | OP_FLAG_OUTPUT, |
87178dbd | 31 | OP_CONSTANT16, |
a18cb100 | 32 | OP_CONSTANT8, |
87178dbd MM |
33 | OP_CONSTANT3, |
34 | OP_CONSTANT4, | |
35 | OP_MEMREF, | |
36 | OP_MEMREF2, | |
37 | OP_POSTDEC, | |
38 | OP_POSTINC, | |
a18cb100 MM |
39 | OP_PREDEC, |
40 | OP_R2, | |
8918b3a7 MM |
41 | OP_R3, |
42 | OP_R4, | |
43 | OP_R2R3 | |
87178dbd MM |
44 | }; |
45 | ||
7eebfc62 | 46 | #ifdef DEBUG |
a49a15ad MM |
47 | static void trace_input_func PARAMS ((char *name, |
48 | enum op_types in1, | |
49 | enum op_types in2, | |
50 | enum op_types in3)); | |
87178dbd | 51 | |
a49a15ad MM |
52 | #define trace_input(name, in1, in2, in3) do { if (d10v_debug) trace_input_func (name, in1, in2, in3); } while (0) |
53 | ||
54 | static void trace_output_func PARAMS ((enum op_types result)); | |
55 | ||
56 | #define trace_output(result) do { if (d10v_debug) trace_output_func (result); } while (0) | |
57 | ||
87178dbd | 58 | #ifndef SIZE_INSTRUCTION |
a49a15ad | 59 | #define SIZE_INSTRUCTION 8 |
87178dbd MM |
60 | #endif |
61 | ||
62 | #ifndef SIZE_OPERANDS | |
a49a15ad | 63 | #define SIZE_OPERANDS 18 |
87178dbd MM |
64 | #endif |
65 | ||
66 | #ifndef SIZE_VALUES | |
67 | #define SIZE_VALUES 13 | |
68 | #endif | |
69 | ||
a49a15ad MM |
70 | #ifndef SIZE_LOCATION |
71 | #define SIZE_LOCATION 20 | |
72 | #endif | |
73 | ||
891513ee MM |
74 | #ifndef SIZE_PC |
75 | #define SIZE_PC 6 | |
76 | #endif | |
77 | ||
78 | #ifndef SIZE_LINE_NUMBER | |
79 | #define SIZE_LINE_NUMBER 4 | |
80 | #endif | |
81 | ||
87178dbd | 82 | static void |
a49a15ad | 83 | trace_input_func (name, in1, in2, in3) |
87178dbd MM |
84 | char *name; |
85 | enum op_types in1; | |
86 | enum op_types in2; | |
87 | enum op_types in3; | |
88 | { | |
89 | char *comma; | |
90 | enum op_types in[3]; | |
91 | int i; | |
a49a15ad | 92 | char buf[1024]; |
87178dbd MM |
93 | char *p; |
94 | long tmp; | |
95 | char *type; | |
a49a15ad MM |
96 | const char *filename; |
97 | const char *functionname; | |
98 | unsigned int linenumber; | |
99 | bfd_vma byte_pc; | |
87178dbd | 100 | |
7eebfc62 MM |
101 | if ((d10v_debug & DEBUG_TRACE) == 0) |
102 | return; | |
103 | ||
87178dbd MM |
104 | switch (State.ins_type) |
105 | { | |
106 | default: | |
107 | case INS_UNKNOWN: type = " ?"; break; | |
108 | case INS_LEFT: type = " L"; break; | |
109 | case INS_RIGHT: type = " R"; break; | |
110 | case INS_LEFT_PARALLEL: type = "*L"; break; | |
111 | case INS_RIGHT_PARALLEL: type = "*R"; break; | |
c422ecc7 MH |
112 | case INS_LEFT_COND_TEST: type = "?L"; break; |
113 | case INS_RIGHT_COND_TEST: type = "?R"; break; | |
114 | case INS_LEFT_COND_EXE: type = "&L"; break; | |
115 | case INS_RIGHT_COND_EXE: type = "&R"; break; | |
87178dbd MM |
116 | case INS_LONG: type = " B"; break; |
117 | } | |
118 | ||
a49a15ad MM |
119 | if ((d10v_debug & DEBUG_LINE_NUMBER) == 0) |
120 | (*d10v_callback->printf_filtered) (d10v_callback, | |
f061ddf6 | 121 | "0x%.*x %s: %-*s ", |
891513ee MM |
122 | SIZE_PC, (unsigned)PC, |
123 | type, | |
a49a15ad MM |
124 | SIZE_INSTRUCTION, name); |
125 | ||
126 | else | |
127 | { | |
891513ee | 128 | buf[0] = '\0'; |
b30cdd35 | 129 | byte_pc = decode_pc (); |
a49a15ad MM |
130 | if (text && byte_pc >= text_start && byte_pc < text_end) |
131 | { | |
132 | filename = (const char *)0; | |
133 | functionname = (const char *)0; | |
134 | linenumber = 0; | |
0535fa1a | 135 | if (bfd_find_nearest_line (exec_bfd, text, (struct symbol_cache_entry **)0, byte_pc - text_start, |
a49a15ad MM |
136 | &filename, &functionname, &linenumber)) |
137 | { | |
138 | p = buf; | |
139 | if (linenumber) | |
140 | { | |
891513ee | 141 | sprintf (p, "#%-*d ", SIZE_LINE_NUMBER, linenumber); |
a49a15ad MM |
142 | p += strlen (p); |
143 | } | |
891513ee MM |
144 | else |
145 | { | |
146 | sprintf (p, "%-*s ", SIZE_LINE_NUMBER+1, "---"); | |
147 | p += SIZE_LINE_NUMBER+2; | |
148 | } | |
a49a15ad MM |
149 | |
150 | if (functionname) | |
151 | { | |
152 | sprintf (p, "%s ", functionname); | |
153 | p += strlen (p); | |
154 | } | |
155 | else if (filename) | |
156 | { | |
c422ecc7 | 157 | char *q = strrchr (filename, '/'); |
a49a15ad MM |
158 | sprintf (p, "%s ", (q) ? q+1 : filename); |
159 | p += strlen (p); | |
160 | } | |
161 | ||
162 | if (*p == ' ') | |
163 | *p = '\0'; | |
164 | } | |
165 | } | |
166 | ||
167 | (*d10v_callback->printf_filtered) (d10v_callback, | |
f061ddf6 | 168 | "0x%.*x %s: %-*.*s %-*s ", |
891513ee MM |
169 | SIZE_PC, (unsigned)PC, |
170 | type, | |
a49a15ad MM |
171 | SIZE_LOCATION, SIZE_LOCATION, buf, |
172 | SIZE_INSTRUCTION, name); | |
173 | } | |
87178dbd MM |
174 | |
175 | in[0] = in1; | |
176 | in[1] = in2; | |
177 | in[2] = in3; | |
178 | comma = ""; | |
179 | p = buf; | |
180 | for (i = 0; i < 3; i++) | |
181 | { | |
182 | switch (in[i]) | |
183 | { | |
184 | case OP_VOID: | |
a18cb100 MM |
185 | case OP_R2: |
186 | case OP_R3: | |
8918b3a7 | 187 | case OP_R4: |
c422ecc7 | 188 | case OP_R2R3: |
87178dbd MM |
189 | break; |
190 | ||
191 | case OP_REG: | |
192 | case OP_REG_OUTPUT: | |
193 | case OP_DREG: | |
194 | case OP_DREG_OUTPUT: | |
195 | sprintf (p, "%sr%d", comma, OP[i]); | |
196 | p += strlen (p); | |
197 | comma = ","; | |
198 | break; | |
199 | ||
200 | case OP_CR: | |
201 | case OP_CR_OUTPUT: | |
202 | case OP_CR_REVERSE: | |
203 | sprintf (p, "%scr%d", comma, OP[i]); | |
204 | p += strlen (p); | |
205 | comma = ","; | |
206 | break; | |
207 | ||
208 | case OP_ACCUM: | |
209 | case OP_ACCUM_OUTPUT: | |
210 | case OP_ACCUM_REVERSE: | |
211 | sprintf (p, "%sa%d", comma, OP[i]); | |
212 | p += strlen (p); | |
213 | comma = ","; | |
214 | break; | |
215 | ||
216 | case OP_CONSTANT16: | |
217 | sprintf (p, "%s%d", comma, OP[i]); | |
218 | p += strlen (p); | |
219 | comma = ","; | |
220 | break; | |
221 | ||
a18cb100 MM |
222 | case OP_CONSTANT8: |
223 | sprintf (p, "%s%d", comma, SEXT8(OP[i])); | |
224 | p += strlen (p); | |
225 | comma = ","; | |
226 | break; | |
227 | ||
87178dbd MM |
228 | case OP_CONSTANT4: |
229 | sprintf (p, "%s%d", comma, SEXT4(OP[i])); | |
230 | p += strlen (p); | |
231 | comma = ","; | |
232 | break; | |
233 | ||
234 | case OP_CONSTANT3: | |
235 | sprintf (p, "%s%d", comma, SEXT3(OP[i])); | |
236 | p += strlen (p); | |
237 | comma = ","; | |
238 | break; | |
239 | ||
240 | case OP_MEMREF: | |
241 | sprintf (p, "%s@r%d", comma, OP[i]); | |
242 | p += strlen (p); | |
243 | comma = ","; | |
244 | break; | |
245 | ||
246 | case OP_MEMREF2: | |
247 | sprintf (p, "%s@(%d,r%d)", comma, (int16)OP[i], OP[i+1]); | |
248 | p += strlen (p); | |
249 | comma = ","; | |
250 | break; | |
251 | ||
252 | case OP_POSTINC: | |
253 | sprintf (p, "%s@r%d+", comma, OP[i]); | |
254 | p += strlen (p); | |
255 | comma = ","; | |
256 | break; | |
257 | ||
258 | case OP_POSTDEC: | |
259 | sprintf (p, "%s@r%d-", comma, OP[i]); | |
260 | p += strlen (p); | |
261 | comma = ","; | |
262 | break; | |
263 | ||
264 | case OP_PREDEC: | |
265 | sprintf (p, "%s@-r%d", comma, OP[i]); | |
266 | p += strlen (p); | |
267 | comma = ","; | |
268 | break; | |
269 | ||
270 | case OP_FLAG: | |
60fc5b72 | 271 | case OP_FLAG_OUTPUT: |
87178dbd MM |
272 | if (OP[i] == 0) |
273 | sprintf (p, "%sf0", comma); | |
274 | ||
275 | else if (OP[i] == 1) | |
276 | sprintf (p, "%sf1", comma); | |
277 | ||
278 | else | |
60fc5b72 | 279 | sprintf (p, "%sc", comma); |
87178dbd MM |
280 | |
281 | p += strlen (p); | |
282 | comma = ","; | |
283 | break; | |
284 | } | |
285 | } | |
286 | ||
7eebfc62 MM |
287 | if ((d10v_debug & DEBUG_VALUES) == 0) |
288 | { | |
289 | *p++ = '\n'; | |
290 | *p = '\0'; | |
291 | (*d10v_callback->printf_filtered) (d10v_callback, "%s", buf); | |
292 | } | |
293 | else | |
294 | { | |
295 | *p = '\0'; | |
296 | (*d10v_callback->printf_filtered) (d10v_callback, "%-*s", SIZE_OPERANDS, buf); | |
87178dbd | 297 | |
7eebfc62 MM |
298 | p = buf; |
299 | for (i = 0; i < 3; i++) | |
300 | { | |
301 | buf[0] = '\0'; | |
302 | switch (in[i]) | |
303 | { | |
304 | case OP_VOID: | |
305 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, ""); | |
306 | break; | |
307 | ||
308 | case OP_REG_OUTPUT: | |
309 | case OP_DREG_OUTPUT: | |
310 | case OP_CR_OUTPUT: | |
311 | case OP_ACCUM_OUTPUT: | |
60fc5b72 | 312 | case OP_FLAG_OUTPUT: |
7eebfc62 MM |
313 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "---"); |
314 | break; | |
315 | ||
316 | case OP_REG: | |
317 | case OP_MEMREF: | |
318 | case OP_POSTDEC: | |
319 | case OP_POSTINC: | |
320 | case OP_PREDEC: | |
321 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", | |
322 | (uint16)State.regs[OP[i]]); | |
323 | break; | |
324 | ||
325 | case OP_DREG: | |
326 | tmp = (long)((((uint32) State.regs[OP[i]]) << 16) | ((uint32) State.regs[OP[i]+1])); | |
327 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.8lx", SIZE_VALUES-10, "", tmp); | |
328 | break; | |
329 | ||
330 | case OP_CR: | |
331 | case OP_CR_REVERSE: | |
332 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", | |
333 | (uint16)State.cregs[OP[i]]); | |
334 | break; | |
335 | ||
336 | case OP_ACCUM: | |
337 | case OP_ACCUM_REVERSE: | |
338 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.2x%.8lx", SIZE_VALUES-12, "", | |
339 | ((int)(State.a[OP[i]] >> 32) & 0xff), | |
340 | ((unsigned long)State.a[OP[i]]) & 0xffffffff); | |
341 | break; | |
342 | ||
343 | case OP_CONSTANT16: | |
344 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", | |
345 | (uint16)OP[i]); | |
346 | break; | |
347 | ||
348 | case OP_CONSTANT4: | |
349 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", | |
350 | (uint16)SEXT4(OP[i])); | |
351 | break; | |
352 | ||
a18cb100 MM |
353 | case OP_CONSTANT8: |
354 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", | |
355 | (uint16)SEXT8(OP[i])); | |
356 | break; | |
357 | ||
7eebfc62 MM |
358 | case OP_CONSTANT3: |
359 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", | |
360 | (uint16)SEXT3(OP[i])); | |
361 | break; | |
362 | ||
363 | case OP_FLAG: | |
364 | if (OP[i] == 0) | |
365 | (*d10v_callback->printf_filtered) (d10v_callback, "%*sF0 = %d", SIZE_VALUES-6, "", | |
366 | State.F0 != 0); | |
367 | ||
368 | else if (OP[i] == 1) | |
369 | (*d10v_callback->printf_filtered) (d10v_callback, "%*sF1 = %d", SIZE_VALUES-6, "", | |
370 | State.F1 != 0); | |
371 | ||
372 | else | |
373 | (*d10v_callback->printf_filtered) (d10v_callback, "%*sC = %d", SIZE_VALUES-5, "", | |
374 | State.C != 0); | |
375 | ||
376 | break; | |
377 | ||
378 | case OP_MEMREF2: | |
379 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", | |
380 | (uint16)OP[i]); | |
381 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", | |
382 | (uint16)State.regs[OP[++i]]); | |
383 | break; | |
a18cb100 MM |
384 | |
385 | case OP_R2: | |
386 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", | |
387 | (uint16)State.regs[2]); | |
388 | break; | |
389 | ||
390 | case OP_R3: | |
391 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", | |
392 | (uint16)State.regs[3]); | |
393 | break; | |
8918b3a7 MM |
394 | |
395 | case OP_R4: | |
396 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", | |
397 | (uint16)State.regs[4]); | |
398 | break; | |
c422ecc7 MH |
399 | |
400 | case OP_R2R3: | |
401 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", | |
402 | (uint16)State.regs[2]); | |
403 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", | |
404 | (uint16)State.regs[3]); | |
405 | i++; | |
406 | break; | |
7eebfc62 MM |
407 | } |
408 | } | |
409 | } | |
fd435e9f MM |
410 | |
411 | (*d10v_callback->flush_stdout) (d10v_callback); | |
7eebfc62 | 412 | } |
87178dbd | 413 | |
7eebfc62 | 414 | static void |
a49a15ad | 415 | trace_output_func (result) |
7eebfc62 MM |
416 | enum op_types result; |
417 | { | |
418 | if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES)) | |
87178dbd | 419 | { |
7eebfc62 | 420 | long tmp; |
87178dbd | 421 | |
7eebfc62 MM |
422 | switch (result) |
423 | { | |
424 | default: | |
425 | putchar ('\n'); | |
87178dbd MM |
426 | break; |
427 | ||
428 | case OP_REG: | |
7eebfc62 MM |
429 | case OP_REG_OUTPUT: |
430 | (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "", | |
431 | (uint16)State.regs[OP[0]], | |
432 | State.F0 != 0, State.F1 != 0, State.C != 0); | |
87178dbd MM |
433 | break; |
434 | ||
435 | case OP_DREG: | |
7eebfc62 MM |
436 | case OP_DREG_OUTPUT: |
437 | tmp = (long)((((uint32) State.regs[OP[0]]) << 16) | ((uint32) State.regs[OP[0]+1])); | |
438 | (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-10, "", tmp, | |
439 | State.F0 != 0, State.F1 != 0, State.C != 0); | |
87178dbd MM |
440 | break; |
441 | ||
442 | case OP_CR: | |
7eebfc62 MM |
443 | case OP_CR_OUTPUT: |
444 | (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "", | |
445 | (uint16)State.cregs[OP[0]], | |
446 | State.F0 != 0, State.F1 != 0, State.C != 0); | |
87178dbd MM |
447 | break; |
448 | ||
7eebfc62 MM |
449 | case OP_CR_REVERSE: |
450 | (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "", | |
451 | (uint16)State.cregs[OP[1]], | |
452 | State.F0 != 0, State.F1 != 0, State.C != 0); | |
87178dbd MM |
453 | break; |
454 | ||
7eebfc62 MM |
455 | case OP_ACCUM: |
456 | case OP_ACCUM_OUTPUT: | |
069398aa | 457 | (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-12, "", |
7eebfc62 MM |
458 | ((int)(State.a[OP[0]] >> 32) & 0xff), |
459 | ((unsigned long)State.a[OP[0]]) & 0xffffffff, | |
460 | State.F0 != 0, State.F1 != 0, State.C != 0); | |
87178dbd MM |
461 | break; |
462 | ||
7eebfc62 | 463 | case OP_ACCUM_REVERSE: |
069398aa | 464 | (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-12, "", |
7eebfc62 MM |
465 | ((int)(State.a[OP[1]] >> 32) & 0xff), |
466 | ((unsigned long)State.a[OP[1]]) & 0xffffffff, | |
467 | State.F0 != 0, State.F1 != 0, State.C != 0); | |
87178dbd MM |
468 | break; |
469 | ||
470 | case OP_FLAG: | |
60fc5b72 | 471 | case OP_FLAG_OUTPUT: |
7eebfc62 MM |
472 | (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s F0=%d F1=%d C=%d\n", SIZE_VALUES, "", |
473 | State.F0 != 0, State.F1 != 0, State.C != 0); | |
87178dbd | 474 | break; |
8918b3a7 MM |
475 | |
476 | case OP_R2: | |
477 | (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "", | |
478 | (uint16)State.regs[2], | |
479 | State.F0 != 0, State.F1 != 0, State.C != 0); | |
480 | break; | |
481 | ||
482 | case OP_R2R3: | |
483 | (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-10, "", | |
484 | (uint16)State.regs[2], (uint16)State.regs[3], | |
485 | State.F0 != 0, State.F1 != 0, State.C != 0); | |
486 | break; | |
87178dbd MM |
487 | } |
488 | } | |
fd435e9f MM |
489 | |
490 | (*d10v_callback->flush_stdout) (d10v_callback); | |
87178dbd MM |
491 | } |
492 | ||
493 | #else | |
494 | #define trace_input(NAME, IN1, IN2, IN3) | |
495 | #define trace_output(RESULT) | |
496 | #endif | |
2934d1c9 MH |
497 | |
498 | /* abs */ | |
499 | void | |
500 | OP_4607 () | |
501 | { | |
87178dbd | 502 | trace_input ("abs", OP_REG, OP_VOID, OP_VOID); |
2934d1c9 MH |
503 | State.F1 = State.F0; |
504 | if ((int16)(State.regs[OP[0]]) < 0) | |
505 | { | |
506 | State.regs[OP[0]] = -(int16)(State.regs[OP[0]]); | |
507 | State.F0 = 1; | |
508 | } | |
509 | else | |
510 | State.F0 = 0; | |
87178dbd | 511 | trace_output (OP_REG); |
2934d1c9 MH |
512 | } |
513 | ||
514 | /* abs */ | |
515 | void | |
516 | OP_5607 () | |
517 | { | |
518 | int64 tmp; | |
519 | ||
87178dbd | 520 | trace_input ("abs", OP_ACCUM, OP_VOID, OP_VOID); |
4f425a32 MH |
521 | State.F1 = State.F0; |
522 | State.a[OP[0]] = SEXT40(State.a[OP[0]]); | |
523 | ||
4c38885c | 524 | if (State.a[OP[0]] < 0 ) |
2934d1c9 | 525 | { |
4c38885c | 526 | tmp = -State.a[OP[0]]; |
2934d1c9 MH |
527 | if (State.ST) |
528 | { | |
4c38885c | 529 | if (tmp > MAX32) |
2934d1c9 | 530 | State.a[OP[0]] = MAX32; |
4c38885c | 531 | else if (tmp < MIN32) |
2934d1c9 MH |
532 | State.a[OP[0]] = MIN32; |
533 | else | |
4f425a32 | 534 | State.a[OP[0]] = tmp & MASK40; |
2934d1c9 MH |
535 | } |
536 | else | |
4f425a32 | 537 | State.a[OP[0]] = tmp & MASK40; |
2934d1c9 MH |
538 | State.F0 = 1; |
539 | } | |
540 | else | |
541 | State.F0 = 0; | |
87178dbd | 542 | trace_output (OP_ACCUM); |
2934d1c9 MH |
543 | } |
544 | ||
545 | /* add */ | |
546 | void | |
547 | OP_200 () | |
548 | { | |
549 | uint16 tmp = State.regs[OP[0]]; | |
87178dbd | 550 | trace_input ("add", OP_REG, OP_REG, OP_VOID); |
2934d1c9 MH |
551 | State.regs[OP[0]] += State.regs[OP[1]]; |
552 | if ( tmp > State.regs[OP[0]]) | |
553 | State.C = 1; | |
554 | else | |
555 | State.C = 0; | |
87178dbd | 556 | trace_output (OP_REG); |
2934d1c9 MH |
557 | } |
558 | ||
559 | /* add */ | |
560 | void | |
561 | OP_1201 () | |
562 | { | |
4c38885c | 563 | int64 tmp; |
4f425a32 | 564 | tmp = SEXT40(State.a[OP[0]]) + (SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]); |
87178dbd MM |
565 | |
566 | trace_input ("add", OP_ACCUM, OP_REG, OP_VOID); | |
4c38885c MH |
567 | if (State.ST) |
568 | { | |
569 | if ( tmp > MAX32) | |
570 | State.a[OP[0]] = MAX32; | |
571 | else if ( tmp < MIN32) | |
572 | State.a[OP[0]] = MIN32; | |
573 | else | |
4f425a32 | 574 | State.a[OP[0]] = tmp & MASK40; |
4c38885c MH |
575 | } |
576 | else | |
4f425a32 | 577 | State.a[OP[0]] = tmp & MASK40; |
87178dbd | 578 | trace_output (OP_ACCUM); |
2934d1c9 MH |
579 | } |
580 | ||
581 | /* add */ | |
582 | void | |
583 | OP_1203 () | |
584 | { | |
4c38885c | 585 | int64 tmp; |
4f425a32 | 586 | tmp = SEXT40(State.a[OP[0]]) + SEXT40(State.a[OP[1]]); |
87178dbd MM |
587 | |
588 | trace_input ("add", OP_ACCUM, OP_ACCUM, OP_VOID); | |
4c38885c MH |
589 | if (State.ST) |
590 | { | |
591 | if (tmp > MAX32) | |
592 | State.a[OP[0]] = MAX32; | |
593 | else if ( tmp < MIN32) | |
594 | State.a[OP[0]] = MIN32; | |
595 | else | |
4f425a32 | 596 | State.a[OP[0]] = tmp & MASK40; |
4c38885c MH |
597 | } |
598 | else | |
4f425a32 | 599 | State.a[OP[0]] = tmp & MASK40; |
87178dbd | 600 | trace_output (OP_ACCUM); |
2934d1c9 MH |
601 | } |
602 | ||
603 | /* add2w */ | |
604 | void | |
605 | OP_1200 () | |
606 | { | |
607 | uint32 tmp; | |
608 | uint32 tmp1 = (State.regs[OP[0]]) << 16 | State.regs[OP[0]+1]; | |
609 | uint32 tmp2 = (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]; | |
87178dbd MM |
610 | |
611 | trace_input ("add2w", OP_DREG, OP_DREG, OP_VOID); | |
2934d1c9 MH |
612 | tmp = tmp1 + tmp2; |
613 | if ( (tmp < tmp1) || (tmp < tmp2) ) | |
614 | State.C = 1; | |
615 | else | |
616 | State.C = 0; | |
617 | State.regs[OP[0]] = tmp >> 16; | |
618 | State.regs[OP[0]+1] = tmp & 0xFFFF; | |
87178dbd | 619 | trace_output (OP_DREG); |
2934d1c9 MH |
620 | } |
621 | ||
622 | /* add3 */ | |
623 | void | |
624 | OP_1000000 () | |
625 | { | |
626 | uint16 tmp = State.regs[OP[0]]; | |
2934d1c9 | 627 | State.regs[OP[0]] = State.regs[OP[1]] + OP[2]; |
87178dbd MM |
628 | |
629 | trace_input ("add3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16); | |
2934d1c9 MH |
630 | if ( tmp > State.regs[OP[0]]) |
631 | State.C = 1; | |
632 | else | |
633 | State.C = 0; | |
87178dbd | 634 | trace_output (OP_REG); |
2934d1c9 MH |
635 | } |
636 | ||
637 | /* addac3 */ | |
638 | void | |
639 | OP_17000200 () | |
640 | { | |
4c38885c | 641 | int64 tmp; |
4f425a32 | 642 | tmp = SEXT40(State.a[OP[2]]) + SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]); |
87178dbd MM |
643 | |
644 | trace_input ("addac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM); | |
4c38885c MH |
645 | State.regs[OP[0]] = (tmp >> 16) & 0xffff; |
646 | State.regs[OP[0]+1] = tmp & 0xffff; | |
87178dbd | 647 | trace_output (OP_DREG); |
2934d1c9 MH |
648 | } |
649 | ||
650 | /* addac3 */ | |
651 | void | |
652 | OP_17000202 () | |
653 | { | |
4c38885c | 654 | int64 tmp; |
4f425a32 | 655 | tmp = SEXT40(State.a[OP[1]]) + SEXT40(State.a[OP[2]]); |
87178dbd MM |
656 | |
657 | trace_input ("addac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM); | |
4c38885c MH |
658 | State.regs[OP[0]] = (tmp >> 16) & 0xffff; |
659 | State.regs[OP[0]+1] = tmp & 0xffff; | |
87178dbd | 660 | trace_output (OP_DREG); |
2934d1c9 MH |
661 | } |
662 | ||
663 | /* addac3s */ | |
664 | void | |
665 | OP_17001200 () | |
666 | { | |
4c38885c | 667 | int64 tmp; |
4c38885c | 668 | State.F1 = State.F0; |
87178dbd MM |
669 | |
670 | trace_input ("addac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM); | |
4f425a32 | 671 | tmp = SEXT40(State.a[OP[2]]) + SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]); |
4c38885c MH |
672 | if ( tmp > MAX32) |
673 | { | |
674 | State.regs[OP[0]] = 0x7fff; | |
675 | State.regs[OP[0]+1] = 0xffff; | |
676 | State.F0 = 1; | |
677 | } | |
678 | else if (tmp < MIN32) | |
679 | { | |
680 | State.regs[OP[0]] = 0x8000; | |
681 | State.regs[OP[0]+1] = 0; | |
682 | State.F0 = 1; | |
683 | } | |
684 | else | |
685 | { | |
686 | State.regs[OP[0]] = (tmp >> 16) & 0xffff; | |
687 | State.regs[OP[0]+1] = tmp & 0xffff; | |
688 | State.F0 = 0; | |
689 | } | |
87178dbd | 690 | trace_output (OP_DREG); |
2934d1c9 MH |
691 | } |
692 | ||
693 | /* addac3s */ | |
694 | void | |
695 | OP_17001202 () | |
696 | { | |
4c38885c | 697 | int64 tmp; |
4c38885c | 698 | State.F1 = State.F0; |
87178dbd MM |
699 | |
700 | trace_input ("addac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM); | |
4f425a32 | 701 | tmp = SEXT40(State.a[OP[1]]) + SEXT40(State.a[OP[2]]); |
4c38885c MH |
702 | if ( tmp > MAX32) |
703 | { | |
704 | State.regs[OP[0]] = 0x7fff; | |
705 | State.regs[OP[0]+1] = 0xffff; | |
706 | State.F0 = 1; | |
707 | } | |
708 | else if (tmp < MIN32) | |
709 | { | |
710 | State.regs[OP[0]] = 0x8000; | |
711 | State.regs[OP[0]+1] = 0; | |
712 | State.F0 = 1; | |
713 | } | |
714 | else | |
715 | { | |
716 | State.regs[OP[0]] = (tmp >> 16) & 0xffff; | |
717 | State.regs[OP[0]+1] = tmp & 0xffff; | |
718 | State.F0 = 0; | |
719 | } | |
87178dbd | 720 | trace_output (OP_DREG); |
2934d1c9 MH |
721 | } |
722 | ||
723 | /* addi */ | |
724 | void | |
725 | OP_201 () | |
726 | { | |
2254cd90 | 727 | uint tmp = State.regs[OP[0]]; |
4f425a32 MH |
728 | if (OP[1] == 0) |
729 | OP[1] = 16; | |
87178dbd | 730 | trace_input ("addi", OP_REG, OP_CONSTANT16, OP_VOID); |
2934d1c9 | 731 | State.regs[OP[0]] += OP[1]; |
2254cd90 MM |
732 | if (tmp > State.regs[OP[0]]) |
733 | State.C = 1; | |
734 | else | |
735 | State.C = 0; | |
87178dbd | 736 | trace_output (OP_REG); |
2934d1c9 MH |
737 | } |
738 | ||
739 | /* and */ | |
740 | void | |
741 | OP_C00 () | |
742 | { | |
87178dbd | 743 | trace_input ("and", OP_REG, OP_REG, OP_VOID); |
2934d1c9 | 744 | State.regs[OP[0]] &= State.regs[OP[1]]; |
87178dbd | 745 | trace_output (OP_REG); |
2934d1c9 MH |
746 | } |
747 | ||
748 | /* and3 */ | |
749 | void | |
750 | OP_6000000 () | |
751 | { | |
87178dbd | 752 | trace_input ("and3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16); |
2934d1c9 | 753 | State.regs[OP[0]] = State.regs[OP[1]] & OP[2]; |
87178dbd | 754 | trace_output (OP_REG); |
2934d1c9 MH |
755 | } |
756 | ||
757 | /* bclri */ | |
758 | void | |
759 | OP_C01 () | |
760 | { | |
87178dbd | 761 | trace_input ("bclri", OP_REG, OP_CONSTANT16, OP_VOID); |
2934d1c9 | 762 | State.regs[OP[0]] &= ~(0x8000 >> OP[1]); |
87178dbd | 763 | trace_output (OP_REG); |
2934d1c9 MH |
764 | } |
765 | ||
766 | /* bl.s */ | |
767 | void | |
768 | OP_4900 () | |
769 | { | |
a18cb100 | 770 | trace_input ("bl.s", OP_CONSTANT8, OP_R2, OP_R3); |
2934d1c9 | 771 | State.regs[13] = PC+1; |
fd435e9f | 772 | JMP( PC + SEXT8 (OP[0])); |
87178dbd | 773 | trace_output (OP_VOID); |
2934d1c9 MH |
774 | } |
775 | ||
776 | /* bl.l */ | |
777 | void | |
778 | OP_24800000 () | |
779 | { | |
a18cb100 | 780 | trace_input ("bl.l", OP_CONSTANT16, OP_R2, OP_R3); |
2934d1c9 | 781 | State.regs[13] = PC+1; |
fd435e9f | 782 | JMP (PC + OP[0]); |
87178dbd | 783 | trace_output (OP_VOID); |
2934d1c9 MH |
784 | } |
785 | ||
786 | /* bnoti */ | |
787 | void | |
788 | OP_A01 () | |
789 | { | |
87178dbd | 790 | trace_input ("bnoti", OP_REG, OP_CONSTANT16, OP_VOID); |
2934d1c9 | 791 | State.regs[OP[0]] ^= 0x8000 >> OP[1]; |
87178dbd | 792 | trace_output (OP_REG); |
2934d1c9 MH |
793 | } |
794 | ||
795 | /* bra.s */ | |
796 | void | |
797 | OP_4800 () | |
798 | { | |
a18cb100 | 799 | trace_input ("bra.s", OP_CONSTANT8, OP_VOID, OP_VOID); |
fd435e9f | 800 | JMP (PC + SEXT8 (OP[0])); |
87178dbd | 801 | trace_output (OP_VOID); |
2934d1c9 MH |
802 | } |
803 | ||
804 | /* bra.l */ | |
805 | void | |
806 | OP_24000000 () | |
807 | { | |
87178dbd | 808 | trace_input ("bra.l", OP_CONSTANT16, OP_VOID, OP_VOID); |
fd435e9f | 809 | JMP (PC + OP[0]); |
87178dbd | 810 | trace_output (OP_VOID); |
2934d1c9 MH |
811 | } |
812 | ||
813 | /* brf0f.s */ | |
814 | void | |
815 | OP_4A00 () | |
816 | { | |
a18cb100 | 817 | trace_input ("brf0f.s", OP_CONSTANT8, OP_VOID, OP_VOID); |
2934d1c9 | 818 | if (State.F0 == 0) |
fd435e9f | 819 | JMP (PC + SEXT8 (OP[0])); |
87178dbd | 820 | trace_output (OP_FLAG); |
2934d1c9 MH |
821 | } |
822 | ||
823 | /* brf0f.l */ | |
824 | void | |
825 | OP_25000000 () | |
826 | { | |
87178dbd | 827 | trace_input ("brf0f.l", OP_CONSTANT16, OP_VOID, OP_VOID); |
2934d1c9 | 828 | if (State.F0 == 0) |
fd435e9f | 829 | JMP (PC + OP[0]); |
87178dbd | 830 | trace_output (OP_FLAG); |
2934d1c9 MH |
831 | } |
832 | ||
833 | /* brf0t.s */ | |
834 | void | |
835 | OP_4B00 () | |
836 | { | |
a18cb100 | 837 | trace_input ("brf0t.s", OP_CONSTANT8, OP_VOID, OP_VOID); |
2934d1c9 | 838 | if (State.F0) |
fd435e9f | 839 | JMP (PC + SEXT8 (OP[0])); |
87178dbd | 840 | trace_output (OP_FLAG); |
2934d1c9 MH |
841 | } |
842 | ||
843 | /* brf0t.l */ | |
844 | void | |
845 | OP_25800000 () | |
846 | { | |
87178dbd | 847 | trace_input ("brf0t.l", OP_CONSTANT16, OP_VOID, OP_VOID); |
2934d1c9 | 848 | if (State.F0) |
fd435e9f | 849 | JMP (PC + OP[0]); |
87178dbd | 850 | trace_output (OP_FLAG); |
2934d1c9 MH |
851 | } |
852 | ||
853 | /* bseti */ | |
854 | void | |
855 | OP_801 () | |
856 | { | |
87178dbd | 857 | trace_input ("bseti", OP_REG, OP_CONSTANT16, OP_VOID); |
2934d1c9 | 858 | State.regs[OP[0]] |= 0x8000 >> OP[1]; |
87178dbd | 859 | trace_output (OP_REG); |
2934d1c9 MH |
860 | } |
861 | ||
862 | /* btsti */ | |
863 | void | |
864 | OP_E01 () | |
865 | { | |
87178dbd | 866 | trace_input ("btsti", OP_REG, OP_CONSTANT16, OP_VOID); |
2934d1c9 MH |
867 | State.F1 = State.F0; |
868 | State.F0 = (State.regs[OP[0]] & (0x8000 >> OP[1])) ? 1 : 0; | |
87178dbd | 869 | trace_output (OP_FLAG); |
2934d1c9 MH |
870 | } |
871 | ||
872 | /* clrac */ | |
873 | void | |
874 | OP_5601 () | |
875 | { | |
87178dbd | 876 | trace_input ("clrac", OP_ACCUM_OUTPUT, OP_VOID, OP_VOID); |
2934d1c9 | 877 | State.a[OP[0]] = 0; |
87178dbd | 878 | trace_output (OP_ACCUM); |
2934d1c9 MH |
879 | } |
880 | ||
881 | /* cmp */ | |
882 | void | |
883 | OP_600 () | |
884 | { | |
87178dbd | 885 | trace_input ("cmp", OP_REG, OP_REG, OP_VOID); |
2934d1c9 MH |
886 | State.F1 = State.F0; |
887 | State.F0 = ((int16)(State.regs[OP[0]]) < (int16)(State.regs[OP[1]])) ? 1 : 0; | |
87178dbd | 888 | trace_output (OP_FLAG); |
2934d1c9 MH |
889 | } |
890 | ||
891 | /* cmp */ | |
892 | void | |
893 | OP_1603 () | |
894 | { | |
87178dbd | 895 | trace_input ("cmp", OP_ACCUM, OP_ACCUM, OP_VOID); |
4c38885c | 896 | State.F1 = State.F0; |
4f425a32 | 897 | State.F0 = (SEXT40(State.a[OP[0]]) < SEXT40(State.a[OP[1]])) ? 1 : 0; |
87178dbd | 898 | trace_output (OP_FLAG); |
2934d1c9 MH |
899 | } |
900 | ||
901 | /* cmpeq */ | |
902 | void | |
903 | OP_400 () | |
904 | { | |
87178dbd | 905 | trace_input ("cmpeq", OP_REG, OP_REG, OP_VOID); |
2934d1c9 MH |
906 | State.F1 = State.F0; |
907 | State.F0 = (State.regs[OP[0]] == State.regs[OP[1]]) ? 1 : 0; | |
87178dbd | 908 | trace_output (OP_FLAG); |
2934d1c9 MH |
909 | } |
910 | ||
911 | /* cmpeq */ | |
912 | void | |
913 | OP_1403 () | |
914 | { | |
87178dbd | 915 | trace_input ("cmpeq", OP_ACCUM, OP_ACCUM, OP_VOID); |
4c38885c | 916 | State.F1 = State.F0; |
fd435e9f | 917 | State.F0 = ((State.a[OP[0]] & MASK40) == (State.a[OP[1]] & MASK40)) ? 1 : 0; |
87178dbd | 918 | trace_output (OP_FLAG); |
2934d1c9 MH |
919 | } |
920 | ||
921 | /* cmpeqi.s */ | |
922 | void | |
923 | OP_401 () | |
924 | { | |
c12f5c67 | 925 | trace_input ("cmpeqi.s", OP_REG, OP_CONSTANT4, OP_VOID); |
2934d1c9 | 926 | State.F1 = State.F0; |
c12f5c67 | 927 | State.F0 = (State.regs[OP[0]] == (reg_t)SEXT4(OP[1])) ? 1 : 0; |
87178dbd | 928 | trace_output (OP_FLAG); |
2934d1c9 MH |
929 | } |
930 | ||
931 | /* cmpeqi.l */ | |
932 | void | |
933 | OP_2000000 () | |
934 | { | |
87178dbd | 935 | trace_input ("cmpeqi.l", OP_REG, OP_CONSTANT16, OP_VOID); |
2934d1c9 | 936 | State.F1 = State.F0; |
c12f5c67 | 937 | State.F0 = (State.regs[OP[0]] == (reg_t)OP[1]) ? 1 : 0; |
87178dbd | 938 | trace_output (OP_FLAG); |
2934d1c9 MH |
939 | } |
940 | ||
941 | /* cmpi.s */ | |
942 | void | |
943 | OP_601 () | |
944 | { | |
87178dbd | 945 | trace_input ("cmpi.s", OP_REG, OP_CONSTANT4, OP_VOID); |
2934d1c9 | 946 | State.F1 = State.F0; |
c12f5c67 | 947 | State.F0 = ((int16)(State.regs[OP[0]]) < (int16)SEXT4(OP[1])) ? 1 : 0; |
87178dbd | 948 | trace_output (OP_FLAG); |
2934d1c9 MH |
949 | } |
950 | ||
951 | /* cmpi.l */ | |
952 | void | |
953 | OP_3000000 () | |
954 | { | |
87178dbd | 955 | trace_input ("cmpi.l", OP_REG, OP_CONSTANT16, OP_VOID); |
2934d1c9 MH |
956 | State.F1 = State.F0; |
957 | State.F0 = ((int16)(State.regs[OP[0]]) < (int16)(OP[1])) ? 1 : 0; | |
87178dbd | 958 | trace_output (OP_FLAG); |
2934d1c9 MH |
959 | } |
960 | ||
961 | /* cmpu */ | |
962 | void | |
963 | OP_4600 () | |
964 | { | |
87178dbd | 965 | trace_input ("cmpu", OP_REG, OP_REG, OP_VOID); |
2934d1c9 MH |
966 | State.F1 = State.F0; |
967 | State.F0 = (State.regs[OP[0]] < State.regs[OP[1]]) ? 1 : 0; | |
87178dbd | 968 | trace_output (OP_FLAG); |
2934d1c9 MH |
969 | } |
970 | ||
971 | /* cmpui */ | |
972 | void | |
973 | OP_23000000 () | |
974 | { | |
87178dbd | 975 | trace_input ("cmpui", OP_REG, OP_CONSTANT16, OP_VOID); |
2934d1c9 | 976 | State.F1 = State.F0; |
c12f5c67 | 977 | State.F0 = (State.regs[OP[0]] < (reg_t)OP[1]) ? 1 : 0; |
87178dbd | 978 | trace_output (OP_FLAG); |
2934d1c9 MH |
979 | } |
980 | ||
981 | /* cpfg */ | |
982 | void | |
983 | OP_4E09 () | |
984 | { | |
985 | uint8 *src, *dst; | |
2934d1c9 | 986 | |
60fc5b72 | 987 | trace_input ("cpfg", OP_FLAG_OUTPUT, OP_FLAG, OP_VOID); |
2934d1c9 MH |
988 | if (OP[0] == 0) |
989 | dst = &State.F0; | |
990 | else | |
991 | dst = &State.F1; | |
992 | ||
993 | if (OP[1] == 0) | |
994 | src = &State.F0; | |
995 | else if (OP[1] == 1) | |
996 | src = &State.F1; | |
997 | else | |
998 | src = &State.C; | |
999 | ||
1000 | *dst = *src; | |
87178dbd | 1001 | trace_output (OP_FLAG); |
2934d1c9 MH |
1002 | } |
1003 | ||
1004 | /* dbt */ | |
1005 | void | |
1006 | OP_5F20 () | |
1007 | { | |
a49a15ad | 1008 | /* d10v_callback->printf_filtered(d10v_callback, "***** DBT ***** PC=%x\n",PC); */ |
4f425a32 | 1009 | State.exception = SIGTRAP; |
2934d1c9 MH |
1010 | } |
1011 | ||
1012 | /* divs */ | |
1013 | void | |
1014 | OP_14002800 () | |
1015 | { | |
1016 | uint16 foo, tmp, tmpf; | |
87178dbd MM |
1017 | |
1018 | trace_input ("divs", OP_DREG, OP_REG, OP_VOID); | |
2934d1c9 MH |
1019 | foo = (State.regs[OP[0]] << 1) | (State.regs[OP[0]+1] >> 15); |
1020 | tmp = (int16)foo - (int16)(State.regs[OP[1]]); | |
1021 | tmpf = (foo >= State.regs[OP[1]]) ? 1 : 0; | |
1022 | State.regs[OP[0]] = (tmpf == 1) ? tmp : foo; | |
1023 | State.regs[OP[0]+1] = (State.regs[OP[0]+1] << 1) | tmpf; | |
87178dbd | 1024 | trace_output (OP_DREG); |
2934d1c9 MH |
1025 | } |
1026 | ||
1027 | /* exef0f */ | |
1028 | void | |
1029 | OP_4E04 () | |
1030 | { | |
87178dbd | 1031 | trace_input ("exef0f", OP_VOID, OP_VOID, OP_VOID); |
293c76a3 | 1032 | State.exe = (State.F0 == 0); |
87178dbd | 1033 | trace_output (OP_FLAG); |
2934d1c9 MH |
1034 | } |
1035 | ||
1036 | /* exef0t */ | |
1037 | void | |
1038 | OP_4E24 () | |
1039 | { | |
87178dbd | 1040 | trace_input ("exef0t", OP_VOID, OP_VOID, OP_VOID); |
293c76a3 | 1041 | State.exe = (State.F0 != 0); |
87178dbd | 1042 | trace_output (OP_FLAG); |
2934d1c9 MH |
1043 | } |
1044 | ||
1045 | /* exef1f */ | |
1046 | void | |
1047 | OP_4E40 () | |
1048 | { | |
87178dbd | 1049 | trace_input ("exef1f", OP_VOID, OP_VOID, OP_VOID); |
293c76a3 | 1050 | State.exe = (State.F1 == 0); |
87178dbd | 1051 | trace_output (OP_FLAG); |
2934d1c9 MH |
1052 | } |
1053 | ||
1054 | /* exef1t */ | |
1055 | void | |
1056 | OP_4E42 () | |
1057 | { | |
87178dbd | 1058 | trace_input ("exef1t", OP_VOID, OP_VOID, OP_VOID); |
293c76a3 | 1059 | State.exe = (State.F1 != 0); |
87178dbd | 1060 | trace_output (OP_FLAG); |
2934d1c9 MH |
1061 | } |
1062 | ||
1063 | /* exefaf */ | |
1064 | void | |
1065 | OP_4E00 () | |
1066 | { | |
87178dbd | 1067 | trace_input ("exefaf", OP_VOID, OP_VOID, OP_VOID); |
293c76a3 | 1068 | State.exe = (State.F0 == 0) & (State.F1 == 0); |
87178dbd | 1069 | trace_output (OP_FLAG); |
2934d1c9 MH |
1070 | } |
1071 | ||
1072 | /* exefat */ | |
1073 | void | |
1074 | OP_4E02 () | |
1075 | { | |
87178dbd | 1076 | trace_input ("exefat", OP_VOID, OP_VOID, OP_VOID); |
293c76a3 | 1077 | State.exe = (State.F0 == 0) & (State.F1 != 0); |
87178dbd | 1078 | trace_output (OP_FLAG); |
2934d1c9 MH |
1079 | } |
1080 | ||
1081 | /* exetaf */ | |
1082 | void | |
1083 | OP_4E20 () | |
1084 | { | |
87178dbd | 1085 | trace_input ("exetaf", OP_VOID, OP_VOID, OP_VOID); |
293c76a3 | 1086 | State.exe = (State.F0 != 0) & (State.F1 == 0); |
87178dbd | 1087 | trace_output (OP_FLAG); |
2934d1c9 MH |
1088 | } |
1089 | ||
1090 | /* exetat */ | |
1091 | void | |
1092 | OP_4E22 () | |
1093 | { | |
87178dbd | 1094 | trace_input ("exetat", OP_VOID, OP_VOID, OP_VOID); |
293c76a3 | 1095 | State.exe = (State.F0 != 0) & (State.F1 != 0); |
87178dbd | 1096 | trace_output (OP_FLAG); |
2934d1c9 MH |
1097 | } |
1098 | ||
1099 | /* exp */ | |
1100 | void | |
1101 | OP_15002A00 () | |
1102 | { | |
1103 | uint32 tmp, foo; | |
1104 | int i; | |
1105 | ||
87178dbd | 1106 | trace_input ("exp", OP_REG_OUTPUT, OP_DREG, OP_VOID); |
4c38885c MH |
1107 | if (((int16)State.regs[OP[1]]) >= 0) |
1108 | tmp = (State.regs[OP[1]] << 16) | State.regs[OP[1]+1]; | |
2934d1c9 | 1109 | else |
4c38885c | 1110 | tmp = ~((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]); |
2934d1c9 MH |
1111 | |
1112 | foo = 0x40000000; | |
4c38885c | 1113 | for (i=1;i<17;i++) |
2934d1c9 MH |
1114 | { |
1115 | if (tmp & foo) | |
1116 | { | |
1117 | State.regs[OP[0]] = i-1; | |
87178dbd | 1118 | trace_output (OP_REG); |
2934d1c9 MH |
1119 | return; |
1120 | } | |
4c38885c | 1121 | foo >>= 1; |
2934d1c9 MH |
1122 | } |
1123 | State.regs[OP[0]] = 16; | |
87178dbd | 1124 | trace_output (OP_REG); |
2934d1c9 MH |
1125 | } |
1126 | ||
1127 | /* exp */ | |
1128 | void | |
1129 | OP_15002A02 () | |
1130 | { | |
4c38885c MH |
1131 | int64 tmp, foo; |
1132 | int i; | |
87178dbd MM |
1133 | |
1134 | trace_input ("exp", OP_REG_OUTPUT, OP_ACCUM, OP_VOID); | |
fd435e9f MM |
1135 | tmp = SEXT40(State.a[OP[1]]); |
1136 | if (tmp < 0) | |
1137 | tmp = ~tmp & MASK40; | |
4c38885c MH |
1138 | |
1139 | foo = 0x4000000000LL; | |
1140 | for (i=1;i<25;i++) | |
1141 | { | |
1142 | if (tmp & foo) | |
1143 | { | |
1144 | State.regs[OP[0]] = i-9; | |
87178dbd | 1145 | trace_output (OP_REG); |
4c38885c MH |
1146 | return; |
1147 | } | |
1148 | foo >>= 1; | |
1149 | } | |
1150 | State.regs[OP[0]] = 16; | |
87178dbd | 1151 | trace_output (OP_REG); |
2934d1c9 MH |
1152 | } |
1153 | ||
1154 | /* jl */ | |
1155 | void | |
1156 | OP_4D00 () | |
1157 | { | |
a18cb100 | 1158 | trace_input ("jl", OP_REG, OP_R2, OP_R3); |
2934d1c9 | 1159 | State.regs[13] = PC+1; |
fd435e9f | 1160 | JMP (State.regs[OP[0]]); |
87178dbd | 1161 | trace_output (OP_VOID); |
2934d1c9 MH |
1162 | } |
1163 | ||
1164 | /* jmp */ | |
1165 | void | |
1166 | OP_4C00 () | |
1167 | { | |
a18cb100 MM |
1168 | trace_input ("jmp", OP_REG, |
1169 | (OP[0] == 13) ? OP_R2 : OP_VOID, | |
1170 | (OP[0] == 13) ? OP_R3 : OP_VOID); | |
1171 | ||
fd435e9f | 1172 | JMP (State.regs[OP[0]]); |
87178dbd | 1173 | trace_output (OP_VOID); |
2934d1c9 MH |
1174 | } |
1175 | ||
1176 | /* ld */ | |
1177 | void | |
1178 | OP_30000000 () | |
1179 | { | |
87178dbd | 1180 | trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID); |
2934d1c9 | 1181 | State.regs[OP[0]] = RW (OP[1] + State.regs[OP[2]]); |
87178dbd | 1182 | trace_output (OP_REG); |
2934d1c9 MH |
1183 | } |
1184 | ||
1185 | /* ld */ | |
1186 | void | |
1187 | OP_6401 () | |
1188 | { | |
87178dbd | 1189 | trace_input ("ld", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID); |
fd435e9f MM |
1190 | if ( OP[1] == 15 ) |
1191 | { | |
1192 | (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot post-decrement register r15 (SP).\n"); | |
1193 | State.exception = SIGILL; | |
1194 | return; | |
1195 | } | |
4c38885c | 1196 | State.regs[OP[0]] = RW (State.regs[OP[1]]); |
4f425a32 | 1197 | INC_ADDR(State.regs[OP[1]],-2); |
87178dbd | 1198 | trace_output (OP_REG); |
2934d1c9 MH |
1199 | } |
1200 | ||
1201 | /* ld */ | |
1202 | void | |
1203 | OP_6001 () | |
1204 | { | |
87178dbd | 1205 | trace_input ("ld", OP_REG_OUTPUT, OP_POSTINC, OP_VOID); |
4c38885c | 1206 | State.regs[OP[0]] = RW (State.regs[OP[1]]); |
4f425a32 | 1207 | INC_ADDR(State.regs[OP[1]],2); |
87178dbd | 1208 | trace_output (OP_REG); |
2934d1c9 MH |
1209 | } |
1210 | ||
1211 | /* ld */ | |
1212 | void | |
1213 | OP_6000 () | |
1214 | { | |
87178dbd | 1215 | trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF, OP_VOID); |
2934d1c9 | 1216 | State.regs[OP[0]] = RW (State.regs[OP[1]]); |
87178dbd | 1217 | trace_output (OP_REG); |
2934d1c9 MH |
1218 | } |
1219 | ||
1220 | /* ld2w */ | |
1221 | void | |
1222 | OP_31000000 () | |
1223 | { | |
8918b3a7 | 1224 | uint16 addr = State.regs[OP[2]]; |
308f64d3 | 1225 | trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID); |
8918b3a7 MM |
1226 | State.regs[OP[0]] = RW (OP[1] + addr); |
1227 | State.regs[OP[0]+1] = RW (OP[1] + addr + 2); | |
87178dbd | 1228 | trace_output (OP_DREG); |
2934d1c9 MH |
1229 | } |
1230 | ||
1231 | /* ld2w */ | |
1232 | void | |
1233 | OP_6601 () | |
1234 | { | |
8918b3a7 | 1235 | uint16 addr = State.regs[OP[1]]; |
87178dbd | 1236 | trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID); |
fd435e9f MM |
1237 | if ( OP[1] == 15 ) |
1238 | { | |
1239 | (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot post-decrement register r15 (SP).\n"); | |
1240 | State.exception = SIGILL; | |
1241 | return; | |
1242 | } | |
8918b3a7 MM |
1243 | State.regs[OP[0]] = RW (addr); |
1244 | State.regs[OP[0]+1] = RW (addr+2); | |
4f425a32 | 1245 | INC_ADDR(State.regs[OP[1]],-4); |
87178dbd | 1246 | trace_output (OP_DREG); |
2934d1c9 MH |
1247 | } |
1248 | ||
1249 | /* ld2w */ | |
1250 | void | |
1251 | OP_6201 () | |
1252 | { | |
8918b3a7 | 1253 | uint16 addr = State.regs[OP[1]]; |
87178dbd | 1254 | trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTINC, OP_VOID); |
8918b3a7 MM |
1255 | State.regs[OP[0]] = RW (addr); |
1256 | State.regs[OP[0]+1] = RW (addr+2); | |
4f425a32 | 1257 | INC_ADDR(State.regs[OP[1]],4); |
8918b3a7 | 1258 | trace_output (OP_DREG); |
2934d1c9 MH |
1259 | } |
1260 | ||
1261 | /* ld2w */ | |
1262 | void | |
1263 | OP_6200 () | |
1264 | { | |
8918b3a7 | 1265 | uint16 addr = State.regs[OP[1]]; |
addb61a5 | 1266 | trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF, OP_VOID); |
8918b3a7 MM |
1267 | State.regs[OP[0]] = RW (addr); |
1268 | State.regs[OP[0]+1] = RW (addr+2); | |
1269 | trace_output (OP_DREG); | |
2934d1c9 MH |
1270 | } |
1271 | ||
1272 | /* ldb */ | |
1273 | void | |
1274 | OP_38000000 () | |
1275 | { | |
87178dbd | 1276 | trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID); |
c422ecc7 | 1277 | State.regs[OP[0]] = SEXT8 (RB (OP[1] + State.regs[OP[2]])); |
87178dbd | 1278 | trace_output (OP_REG); |
2934d1c9 MH |
1279 | } |
1280 | ||
1281 | /* ldb */ | |
1282 | void | |
1283 | OP_7000 () | |
1284 | { | |
87178dbd | 1285 | trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF, OP_VOID); |
c422ecc7 | 1286 | State.regs[OP[0]] = SEXT8 (RB (State.regs[OP[1]])); |
87178dbd | 1287 | trace_output (OP_REG); |
2934d1c9 MH |
1288 | } |
1289 | ||
1290 | /* ldi.s */ | |
1291 | void | |
1292 | OP_4001 () | |
1293 | { | |
87178dbd | 1294 | trace_input ("ldi.s", OP_REG_OUTPUT, OP_CONSTANT4, OP_VOID); |
2934d1c9 | 1295 | State.regs[OP[0]] = SEXT4(OP[1]); |
87178dbd | 1296 | trace_output (OP_REG); |
2934d1c9 MH |
1297 | } |
1298 | ||
1299 | /* ldi.l */ | |
1300 | void | |
1301 | OP_20000000 () | |
1302 | { | |
fd435e9f | 1303 | trace_input ("ldi.l", OP_REG_OUTPUT, OP_CONSTANT16, OP_VOID); |
2934d1c9 | 1304 | State.regs[OP[0]] = OP[1]; |
87178dbd | 1305 | trace_output (OP_REG); |
2934d1c9 MH |
1306 | } |
1307 | ||
1308 | /* ldub */ | |
1309 | void | |
1310 | OP_39000000 () | |
1311 | { | |
87178dbd | 1312 | trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID); |
2934d1c9 | 1313 | State.regs[OP[0]] = RB (OP[1] + State.regs[OP[2]]); |
87178dbd | 1314 | trace_output (OP_REG); |
2934d1c9 MH |
1315 | } |
1316 | ||
1317 | /* ldub */ | |
1318 | void | |
1319 | OP_7200 () | |
1320 | { | |
87178dbd | 1321 | trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF, OP_VOID); |
2934d1c9 | 1322 | State.regs[OP[0]] = RB (State.regs[OP[1]]); |
87178dbd | 1323 | trace_output (OP_REG); |
2934d1c9 MH |
1324 | } |
1325 | ||
1326 | /* mac */ | |
1327 | void | |
1328 | OP_2A00 () | |
1329 | { | |
4c38885c | 1330 | int64 tmp; |
87178dbd MM |
1331 | |
1332 | trace_input ("mac", OP_ACCUM, OP_REG, OP_REG); | |
4f425a32 | 1333 | tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]])); |
4c38885c MH |
1334 | |
1335 | if (State.FX) | |
4f425a32 | 1336 | tmp = SEXT40( (tmp << 1) & MASK40); |
4c38885c MH |
1337 | |
1338 | if (State.ST && tmp > MAX32) | |
1339 | tmp = MAX32; | |
1340 | ||
4f425a32 | 1341 | tmp += SEXT40(State.a[OP[0]]); |
4c38885c MH |
1342 | if (State.ST) |
1343 | { | |
1344 | if (tmp > MAX32) | |
1345 | State.a[OP[0]] = MAX32; | |
1346 | else if (tmp < MIN32) | |
1347 | State.a[OP[0]] = MIN32; | |
1348 | else | |
4f425a32 | 1349 | State.a[OP[0]] = tmp & MASK40; |
4c38885c MH |
1350 | } |
1351 | else | |
4f425a32 | 1352 | State.a[OP[0]] = tmp & MASK40; |
87178dbd | 1353 | trace_output (OP_ACCUM); |
2934d1c9 MH |
1354 | } |
1355 | ||
1356 | /* macsu */ | |
1357 | void | |
1358 | OP_1A00 () | |
1359 | { | |
4f425a32 | 1360 | int64 tmp; |
87178dbd MM |
1361 | |
1362 | trace_input ("macsu", OP_ACCUM, OP_REG, OP_REG); | |
4f425a32 MH |
1363 | tmp = SEXT40 ((int16)State.regs[OP[1]] * State.regs[OP[2]]); |
1364 | if (State.FX) | |
1365 | tmp = SEXT40( (tmp << 1) & MASK40); | |
1366 | ||
1367 | State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) + tmp) & MASK40; | |
87178dbd | 1368 | trace_output (OP_ACCUM); |
2934d1c9 MH |
1369 | } |
1370 | ||
1371 | /* macu */ | |
1372 | void | |
1373 | OP_3A00 () | |
1374 | { | |
4f425a32 | 1375 | int64 tmp; |
87178dbd MM |
1376 | |
1377 | trace_input ("macu", OP_ACCUM, OP_REG, OP_REG); | |
4f425a32 MH |
1378 | tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]); |
1379 | if (State.FX) | |
1380 | tmp = SEXT40( (tmp << 1) & MASK40); | |
1381 | State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) + tmp) & MASK40; | |
87178dbd | 1382 | trace_output (OP_ACCUM); |
2934d1c9 MH |
1383 | } |
1384 | ||
1385 | /* max */ | |
1386 | void | |
1387 | OP_2600 () | |
1388 | { | |
87178dbd | 1389 | trace_input ("max", OP_REG, OP_REG, OP_VOID); |
2934d1c9 | 1390 | State.F1 = State.F0; |
ea2155e8 | 1391 | if ((int16)State.regs[OP[1]] > (int16)State.regs[OP[0]]) |
2934d1c9 MH |
1392 | { |
1393 | State.regs[OP[0]] = State.regs[OP[1]]; | |
1394 | State.F0 = 1; | |
1395 | } | |
1396 | else | |
1397 | State.F0 = 0; | |
87178dbd | 1398 | trace_output (OP_REG); |
2934d1c9 MH |
1399 | } |
1400 | ||
1401 | /* max */ | |
1402 | void | |
1403 | OP_3600 () | |
1404 | { | |
4f425a32 | 1405 | int64 tmp; |
87178dbd MM |
1406 | |
1407 | trace_input ("max", OP_ACCUM, OP_DREG, OP_VOID); | |
4f425a32 MH |
1408 | State.F1 = State.F0; |
1409 | tmp = SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]; | |
1410 | if (tmp > SEXT40(State.a[OP[0]])) | |
1411 | { | |
1412 | State.a[OP[0]] = tmp & MASK40; | |
1413 | State.F0 = 1; | |
1414 | } | |
1415 | else | |
1416 | State.F0 = 0; | |
87178dbd | 1417 | trace_output (OP_ACCUM); |
2934d1c9 MH |
1418 | } |
1419 | ||
1420 | /* max */ | |
1421 | void | |
1422 | OP_3602 () | |
1423 | { | |
87178dbd | 1424 | trace_input ("max", OP_ACCUM, OP_ACCUM, OP_VOID); |
4f425a32 MH |
1425 | State.F1 = State.F0; |
1426 | if (SEXT40(State.a[OP[1]]) > SEXT40(State.a[OP[0]])) | |
1427 | { | |
1428 | State.a[OP[0]] = State.a[OP[1]]; | |
1429 | State.F0 = 1; | |
1430 | } | |
1431 | else | |
1432 | State.F0 = 0; | |
87178dbd | 1433 | trace_output (OP_ACCUM); |
2934d1c9 MH |
1434 | } |
1435 | ||
4f425a32 | 1436 | |
2934d1c9 MH |
1437 | /* min */ |
1438 | void | |
1439 | OP_2601 () | |
1440 | { | |
87178dbd | 1441 | trace_input ("min", OP_REG, OP_REG, OP_VOID); |
2934d1c9 | 1442 | State.F1 = State.F0; |
ea2155e8 | 1443 | if ((int16)State.regs[OP[1]] < (int16)State.regs[OP[0]]) |
2934d1c9 MH |
1444 | { |
1445 | State.regs[OP[0]] = State.regs[OP[1]]; | |
1446 | State.F0 = 1; | |
1447 | } | |
1448 | else | |
1449 | State.F0 = 0; | |
87178dbd | 1450 | trace_output (OP_REG); |
2934d1c9 MH |
1451 | } |
1452 | ||
1453 | /* min */ | |
1454 | void | |
1455 | OP_3601 () | |
1456 | { | |
4f425a32 | 1457 | int64 tmp; |
87178dbd MM |
1458 | |
1459 | trace_input ("min", OP_ACCUM, OP_DREG, OP_VOID); | |
4f425a32 MH |
1460 | State.F1 = State.F0; |
1461 | tmp = SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]; | |
1462 | if (tmp < SEXT40(State.a[OP[0]])) | |
1463 | { | |
1464 | State.a[OP[0]] = tmp & MASK40; | |
1465 | State.F0 = 1; | |
1466 | } | |
1467 | else | |
1468 | State.F0 = 0; | |
87178dbd | 1469 | trace_output (OP_ACCUM); |
2934d1c9 MH |
1470 | } |
1471 | ||
1472 | /* min */ | |
1473 | void | |
1474 | OP_3603 () | |
1475 | { | |
87178dbd | 1476 | trace_input ("min", OP_ACCUM, OP_ACCUM, OP_VOID); |
4f425a32 MH |
1477 | State.F1 = State.F0; |
1478 | if (SEXT40(State.a[OP[1]]) < SEXT40(State.a[OP[0]])) | |
1479 | { | |
1480 | State.a[OP[0]] = State.a[OP[1]]; | |
1481 | State.F0 = 1; | |
1482 | } | |
1483 | else | |
1484 | State.F0 = 0; | |
87178dbd | 1485 | trace_output (OP_ACCUM); |
2934d1c9 MH |
1486 | } |
1487 | ||
1488 | /* msb */ | |
1489 | void | |
1490 | OP_2800 () | |
1491 | { | |
4f425a32 | 1492 | int64 tmp; |
87178dbd MM |
1493 | |
1494 | trace_input ("msb", OP_ACCUM, OP_REG, OP_REG); | |
4f425a32 MH |
1495 | tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]])); |
1496 | ||
1497 | if (State.FX) | |
1498 | tmp = SEXT40 ((tmp << 1) & MASK40); | |
1499 | ||
1500 | if (State.ST && tmp > MAX32) | |
1501 | tmp = MAX32; | |
1502 | ||
1503 | tmp = SEXT40(State.a[OP[0]]) - tmp; | |
1504 | if (State.ST) | |
1505 | { | |
1506 | if (tmp > MAX32) | |
1507 | State.a[OP[0]] = MAX32; | |
1508 | else if (tmp < MIN32) | |
1509 | State.a[OP[0]] = MIN32; | |
1510 | else | |
1511 | State.a[OP[0]] = tmp & MASK40; | |
1512 | } | |
1513 | else | |
1514 | State.a[OP[0]] = tmp & MASK40; | |
87178dbd | 1515 | trace_output (OP_ACCUM); |
2934d1c9 MH |
1516 | } |
1517 | ||
1518 | /* msbsu */ | |
1519 | void | |
1520 | OP_1800 () | |
1521 | { | |
4f425a32 | 1522 | int64 tmp; |
87178dbd MM |
1523 | |
1524 | trace_input ("msbsu", OP_ACCUM, OP_REG, OP_REG); | |
4f425a32 MH |
1525 | tmp = SEXT40 ((int16)State.regs[OP[1]] * State.regs[OP[2]]); |
1526 | if (State.FX) | |
1527 | tmp = SEXT40( (tmp << 1) & MASK40); | |
1528 | ||
1529 | State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) - tmp) & MASK40; | |
87178dbd | 1530 | trace_output (OP_ACCUM); |
2934d1c9 MH |
1531 | } |
1532 | ||
1533 | /* msbu */ | |
1534 | void | |
1535 | OP_3800 () | |
1536 | { | |
4f425a32 | 1537 | int64 tmp; |
87178dbd MM |
1538 | |
1539 | trace_input ("msbu", OP_ACCUM, OP_REG, OP_REG); | |
4f425a32 MH |
1540 | tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]); |
1541 | if (State.FX) | |
1542 | tmp = SEXT40( (tmp << 1) & MASK40); | |
1543 | ||
1544 | State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) - tmp) & MASK40; | |
87178dbd | 1545 | trace_output (OP_ACCUM); |
2934d1c9 MH |
1546 | } |
1547 | ||
1548 | /* mul */ | |
1549 | void | |
1550 | OP_2E00 () | |
1551 | { | |
87178dbd | 1552 | trace_input ("mul", OP_REG, OP_REG, OP_VOID); |
2934d1c9 | 1553 | State.regs[OP[0]] *= State.regs[OP[1]]; |
87178dbd | 1554 | trace_output (OP_REG); |
2934d1c9 MH |
1555 | } |
1556 | ||
1557 | /* mulx */ | |
1558 | void | |
1559 | OP_2C00 () | |
1560 | { | |
4f425a32 | 1561 | int64 tmp; |
87178dbd MM |
1562 | |
1563 | trace_input ("mulx", OP_ACCUM_OUTPUT, OP_REG, OP_REG); | |
4f425a32 MH |
1564 | tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]])); |
1565 | ||
1566 | if (State.FX) | |
1567 | tmp = SEXT40 ((tmp << 1) & MASK40); | |
1568 | ||
1569 | if (State.ST && tmp > MAX32) | |
1570 | State.a[OP[0]] = MAX32; | |
1571 | else | |
1572 | State.a[OP[0]] = tmp & MASK40; | |
87178dbd | 1573 | trace_output (OP_ACCUM); |
2934d1c9 MH |
1574 | } |
1575 | ||
1576 | /* mulxsu */ | |
1577 | void | |
1578 | OP_1C00 () | |
1579 | { | |
4f425a32 | 1580 | int64 tmp; |
87178dbd MM |
1581 | |
1582 | trace_input ("mulxsu", OP_ACCUM_OUTPUT, OP_REG, OP_REG); | |
4f425a32 MH |
1583 | tmp = SEXT40 ((int16)(State.regs[OP[1]]) * State.regs[OP[2]]); |
1584 | ||
1585 | if (State.FX) | |
1586 | tmp <<= 1; | |
1587 | ||
1588 | State.a[OP[0]] = tmp & MASK40; | |
87178dbd | 1589 | trace_output (OP_ACCUM); |
2934d1c9 MH |
1590 | } |
1591 | ||
1592 | /* mulxu */ | |
1593 | void | |
1594 | OP_3C00 () | |
1595 | { | |
4f425a32 | 1596 | int64 tmp; |
87178dbd MM |
1597 | |
1598 | trace_input ("mulxu", OP_ACCUM_OUTPUT, OP_REG, OP_REG); | |
4f425a32 MH |
1599 | tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]); |
1600 | ||
1601 | if (State.FX) | |
1602 | tmp <<= 1; | |
1603 | ||
1604 | State.a[OP[0]] = tmp & MASK40; | |
87178dbd | 1605 | trace_output (OP_ACCUM); |
2934d1c9 MH |
1606 | } |
1607 | ||
1608 | /* mv */ | |
1609 | void | |
1610 | OP_4000 () | |
1611 | { | |
87178dbd | 1612 | trace_input ("mv", OP_REG_OUTPUT, OP_REG, OP_VOID); |
2934d1c9 | 1613 | State.regs[OP[0]] = State.regs[OP[1]]; |
87178dbd | 1614 | trace_output (OP_REG); |
2934d1c9 MH |
1615 | } |
1616 | ||
1617 | /* mv2w */ | |
1618 | void | |
1619 | OP_5000 () | |
1620 | { | |
87178dbd | 1621 | trace_input ("mv2w", OP_DREG_OUTPUT, OP_DREG, OP_VOID); |
2934d1c9 MH |
1622 | State.regs[OP[0]] = State.regs[OP[1]]; |
1623 | State.regs[OP[0]+1] = State.regs[OP[1]+1]; | |
87178dbd | 1624 | trace_output (OP_DREG); |
2934d1c9 MH |
1625 | } |
1626 | ||
1627 | /* mv2wfac */ | |
1628 | void | |
1629 | OP_3E00 () | |
1630 | { | |
87178dbd | 1631 | trace_input ("mv2wfac", OP_DREG_OUTPUT, OP_ACCUM, OP_VOID); |
2934d1c9 MH |
1632 | State.regs[OP[0]] = (State.a[OP[1]] >> 16) & 0xffff; |
1633 | State.regs[OP[0]+1] = State.a[OP[1]] & 0xffff; | |
87178dbd | 1634 | trace_output (OP_DREG); |
2934d1c9 MH |
1635 | } |
1636 | ||
1637 | /* mv2wtac */ | |
1638 | void | |
1639 | OP_3E01 () | |
1640 | { | |
fd435e9f | 1641 | trace_input ("mv2wtac", OP_DREG, OP_ACCUM_OUTPUT, OP_VOID); |
4f425a32 | 1642 | State.a[OP[1]] = (SEXT16 (State.regs[OP[0]]) << 16 | State.regs[OP[0]+1]) & MASK40; |
fd435e9f | 1643 | trace_output (OP_ACCUM_REVERSE); |
2934d1c9 MH |
1644 | } |
1645 | ||
1646 | /* mvac */ | |
1647 | void | |
1648 | OP_3E03 () | |
1649 | { | |
87178dbd | 1650 | trace_input ("mvac", OP_ACCUM_OUTPUT, OP_ACCUM, OP_VOID); |
2934d1c9 | 1651 | State.a[OP[0]] = State.a[OP[1]]; |
87178dbd | 1652 | trace_output (OP_ACCUM); |
2934d1c9 MH |
1653 | } |
1654 | ||
1655 | /* mvb */ | |
1656 | void | |
1657 | OP_5400 () | |
1658 | { | |
87178dbd | 1659 | trace_input ("mvb", OP_REG_OUTPUT, OP_REG, OP_VOID); |
2934d1c9 | 1660 | State.regs[OP[0]] = SEXT8 (State.regs[OP[1]] & 0xff); |
87178dbd | 1661 | trace_output (OP_REG); |
2934d1c9 MH |
1662 | } |
1663 | ||
1664 | /* mvf0f */ | |
1665 | void | |
1666 | OP_4400 () | |
1667 | { | |
87178dbd | 1668 | trace_input ("mf0f", OP_REG_OUTPUT, OP_REG, OP_VOID); |
2934d1c9 MH |
1669 | if (State.F0 == 0) |
1670 | State.regs[OP[0]] = State.regs[OP[1]]; | |
87178dbd | 1671 | trace_output (OP_REG); |
2934d1c9 MH |
1672 | } |
1673 | ||
1674 | /* mvf0t */ | |
1675 | void | |
1676 | OP_4401 () | |
1677 | { | |
87178dbd | 1678 | trace_input ("mf0t", OP_REG_OUTPUT, OP_REG, OP_VOID); |
2934d1c9 MH |
1679 | if (State.F0) |
1680 | State.regs[OP[0]] = State.regs[OP[1]]; | |
87178dbd | 1681 | trace_output (OP_REG); |
2934d1c9 MH |
1682 | } |
1683 | ||
1684 | /* mvfacg */ | |
1685 | void | |
1686 | OP_1E04 () | |
1687 | { | |
87178dbd | 1688 | trace_input ("mvfacg", OP_REG_OUTPUT, OP_ACCUM, OP_VOID); |
2934d1c9 | 1689 | State.regs[OP[0]] = (State.a[OP[1]] >> 32) & 0xff; |
87178dbd | 1690 | trace_output (OP_ACCUM); |
2934d1c9 MH |
1691 | } |
1692 | ||
1693 | /* mvfachi */ | |
1694 | void | |
1695 | OP_1E00 () | |
1696 | { | |
87178dbd | 1697 | trace_input ("mvfachi", OP_REG_OUTPUT, OP_ACCUM, OP_VOID); |
2934d1c9 | 1698 | State.regs[OP[0]] = (State.a[OP[1]] >> 16) & 0xffff; |
87178dbd | 1699 | trace_output (OP_REG); |
2934d1c9 MH |
1700 | } |
1701 | ||
1702 | /* mvfaclo */ | |
1703 | void | |
1704 | OP_1E02 () | |
1705 | { | |
87178dbd | 1706 | trace_input ("mvfaclo", OP_REG_OUTPUT, OP_ACCUM, OP_VOID); |
2934d1c9 | 1707 | State.regs[OP[0]] = State.a[OP[1]] & 0xffff; |
87178dbd | 1708 | trace_output (OP_REG); |
2934d1c9 MH |
1709 | } |
1710 | ||
1711 | /* mvfc */ | |
1712 | void | |
1713 | OP_5200 () | |
1714 | { | |
87178dbd | 1715 | trace_input ("mvfc", OP_REG_OUTPUT, OP_CR, OP_VOID); |
2934d1c9 MH |
1716 | if (OP[1] == 0) |
1717 | { | |
1718 | /* PSW is treated specially */ | |
1719 | PSW = 0; | |
1720 | if (State.SM) PSW |= 0x8000; | |
1721 | if (State.EA) PSW |= 0x2000; | |
1722 | if (State.DB) PSW |= 0x1000; | |
1723 | if (State.IE) PSW |= 0x400; | |
1724 | if (State.RP) PSW |= 0x200; | |
1725 | if (State.MD) PSW |= 0x100; | |
1726 | if (State.FX) PSW |= 0x80; | |
1727 | if (State.ST) PSW |= 0x40; | |
1728 | if (State.F0) PSW |= 8; | |
1729 | if (State.F1) PSW |= 4; | |
1730 | if (State.C) PSW |= 1; | |
1731 | } | |
1732 | State.regs[OP[0]] = State.cregs[OP[1]]; | |
87178dbd | 1733 | trace_output (OP_REG); |
2934d1c9 MH |
1734 | } |
1735 | ||
1736 | /* mvtacg */ | |
1737 | void | |
1738 | OP_1E41 () | |
1739 | { | |
87178dbd | 1740 | trace_input ("mvtacg", OP_REG, OP_ACCUM, OP_VOID); |
2934d1c9 MH |
1741 | State.a[OP[1]] &= MASK32; |
1742 | State.a[OP[1]] |= (int64)(State.regs[OP[0]] & 0xff) << 32; | |
87178dbd | 1743 | trace_output (OP_ACCUM_REVERSE); |
2934d1c9 MH |
1744 | } |
1745 | ||
1746 | /* mvtachi */ | |
1747 | void | |
1748 | OP_1E01 () | |
1749 | { | |
1750 | uint16 tmp; | |
87178dbd MM |
1751 | |
1752 | trace_input ("mvtachi", OP_REG, OP_ACCUM, OP_VOID); | |
2934d1c9 | 1753 | tmp = State.a[OP[1]] & 0xffff; |
4f425a32 | 1754 | State.a[OP[1]] = (SEXT16 (State.regs[OP[0]]) << 16 | tmp) & MASK40; |
87178dbd | 1755 | trace_output (OP_ACCUM_REVERSE); |
2934d1c9 MH |
1756 | } |
1757 | ||
1758 | /* mvtaclo */ | |
1759 | void | |
1760 | OP_1E21 () | |
1761 | { | |
87178dbd | 1762 | trace_input ("mvtaclo", OP_REG, OP_ACCUM, OP_VOID); |
4f425a32 | 1763 | State.a[OP[1]] = (SEXT16 (State.regs[OP[0]])) & MASK40; |
87178dbd | 1764 | trace_output (OP_ACCUM_REVERSE); |
2934d1c9 MH |
1765 | } |
1766 | ||
1767 | /* mvtc */ | |
1768 | void | |
1769 | OP_5600 () | |
1770 | { | |
87178dbd | 1771 | trace_input ("mvtc", OP_REG, OP_CR_OUTPUT, OP_VOID); |
2934d1c9 MH |
1772 | State.cregs[OP[1]] = State.regs[OP[0]]; |
1773 | if (OP[1] == 0) | |
1774 | { | |
1775 | /* PSW is treated specially */ | |
1776 | State.SM = (PSW & 0x8000) ? 1 : 0; | |
1777 | State.EA = (PSW & 0x2000) ? 1 : 0; | |
1778 | State.DB = (PSW & 0x1000) ? 1 : 0; | |
1779 | State.IE = (PSW & 0x400) ? 1 : 0; | |
1780 | State.RP = (PSW & 0x200) ? 1 : 0; | |
1781 | State.MD = (PSW & 0x100) ? 1 : 0; | |
1782 | State.FX = (PSW & 0x80) ? 1 : 0; | |
1783 | State.ST = (PSW & 0x40) ? 1 : 0; | |
1784 | State.F0 = (PSW & 8) ? 1 : 0; | |
1785 | State.F1 = (PSW & 4) ? 1 : 0; | |
1786 | State.C = PSW & 1; | |
1787 | if (State.ST && !State.FX) | |
1788 | { | |
7eebfc62 MM |
1789 | (*d10v_callback->printf_filtered) (d10v_callback, |
1790 | "ERROR at PC 0x%x: ST can only be set when FX is set.\n", | |
1791 | PC<<2); | |
4f425a32 | 1792 | State.exception = SIGILL; |
2934d1c9 MH |
1793 | } |
1794 | } | |
87178dbd | 1795 | trace_output (OP_CR_REVERSE); |
2934d1c9 MH |
1796 | } |
1797 | ||
1798 | /* mvub */ | |
1799 | void | |
1800 | OP_5401 () | |
1801 | { | |
87178dbd | 1802 | trace_input ("mvub", OP_REG_OUTPUT, OP_REG, OP_VOID); |
2934d1c9 | 1803 | State.regs[OP[0]] = State.regs[OP[1]] & 0xff; |
87178dbd | 1804 | trace_output (OP_REG); |
2934d1c9 MH |
1805 | } |
1806 | ||
1807 | /* neg */ | |
1808 | void | |
1809 | OP_4605 () | |
1810 | { | |
87178dbd | 1811 | trace_input ("neg", OP_REG, OP_VOID, OP_VOID); |
2934d1c9 | 1812 | State.regs[OP[0]] = 0 - State.regs[OP[0]]; |
87178dbd | 1813 | trace_output (OP_REG); |
2934d1c9 MH |
1814 | } |
1815 | ||
1816 | /* neg */ | |
1817 | void | |
1818 | OP_5605 () | |
1819 | { | |
1820 | int64 tmp; | |
87178dbd MM |
1821 | |
1822 | trace_input ("neg", OP_ACCUM, OP_VOID, OP_VOID); | |
4f425a32 | 1823 | tmp = -SEXT40(State.a[OP[0]]); |
2934d1c9 MH |
1824 | if (State.ST) |
1825 | { | |
4c38885c | 1826 | if ( tmp > MAX32) |
2934d1c9 | 1827 | State.a[OP[0]] = MAX32; |
4c38885c | 1828 | else if (tmp < MIN32) |
2934d1c9 MH |
1829 | State.a[OP[0]] = MIN32; |
1830 | else | |
4f425a32 | 1831 | State.a[OP[0]] = tmp & MASK40; |
2934d1c9 MH |
1832 | } |
1833 | else | |
4f425a32 | 1834 | State.a[OP[0]] = tmp & MASK40; |
87178dbd | 1835 | trace_output (OP_ACCUM); |
2934d1c9 MH |
1836 | } |
1837 | ||
1838 | ||
1839 | /* nop */ | |
1840 | void | |
1841 | OP_5E00 () | |
1842 | { | |
87178dbd | 1843 | trace_input ("nop", OP_VOID, OP_VOID, OP_VOID); |
7eebfc62 | 1844 | |
c422ecc7 MH |
1845 | ins_type_counters[ (int)State.ins_type ]--; /* don't count nops as normal instructions */ |
1846 | switch (State.ins_type) | |
1847 | { | |
1848 | default: | |
1849 | ins_type_counters[ (int)INS_UNKNOWN ]++; | |
1850 | break; | |
1851 | ||
1852 | case INS_LEFT_PARALLEL: | |
1853 | /* Don't count a parallel op that includes a NOP as a true parallel op */ | |
1854 | ins_type_counters[ (int)INS_RIGHT_PARALLEL ]--; | |
1855 | ins_type_counters[ (int)INS_RIGHT ]++; | |
1856 | ins_type_counters[ (int)INS_LEFT_NOPS ]++; | |
1857 | break; | |
1858 | ||
1859 | case INS_LEFT: | |
1860 | case INS_LEFT_COND_EXE: | |
1861 | ins_type_counters[ (int)INS_LEFT_NOPS ]++; | |
1862 | break; | |
1863 | ||
1864 | case INS_RIGHT_PARALLEL: | |
1865 | /* Don't count a parallel op that includes a NOP as a true parallel op */ | |
1866 | ins_type_counters[ (int)INS_LEFT_PARALLEL ]--; | |
1867 | ins_type_counters[ (int)INS_LEFT ]++; | |
1868 | ins_type_counters[ (int)INS_RIGHT_NOPS ]++; | |
1869 | break; | |
1870 | ||
1871 | case INS_RIGHT: | |
1872 | case INS_RIGHT_COND_EXE: | |
1873 | ins_type_counters[ (int)INS_RIGHT_NOPS ]++; | |
1874 | break; | |
1875 | } | |
1876 | ||
1877 | trace_output (OP_VOID); | |
2934d1c9 MH |
1878 | } |
1879 | ||
1880 | /* not */ | |
1881 | void | |
1882 | OP_4603 () | |
1883 | { | |
87178dbd | 1884 | trace_input ("not", OP_REG, OP_VOID, OP_VOID); |
2934d1c9 | 1885 | State.regs[OP[0]] = ~(State.regs[OP[0]]); |
87178dbd | 1886 | trace_output (OP_REG); |
2934d1c9 MH |
1887 | } |
1888 | ||
1889 | /* or */ | |
1890 | void | |
1891 | OP_800 () | |
1892 | { | |
87178dbd | 1893 | trace_input ("or", OP_REG, OP_REG, OP_VOID); |
2934d1c9 | 1894 | State.regs[OP[0]] |= State.regs[OP[1]]; |
87178dbd | 1895 | trace_output (OP_REG); |
2934d1c9 MH |
1896 | } |
1897 | ||
1898 | /* or3 */ | |
1899 | void | |
1900 | OP_4000000 () | |
1901 | { | |
87178dbd | 1902 | trace_input ("or3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16); |
2934d1c9 | 1903 | State.regs[OP[0]] = State.regs[OP[1]] | OP[2]; |
87178dbd | 1904 | trace_output (OP_REG); |
2934d1c9 MH |
1905 | } |
1906 | ||
1907 | /* rac */ | |
1908 | void | |
1909 | OP_5201 () | |
1910 | { | |
1911 | int64 tmp; | |
1912 | int shift = SEXT3 (OP[2]); | |
87178dbd MM |
1913 | |
1914 | trace_input ("rac", OP_DREG_OUTPUT, OP_ACCUM, OP_CONSTANT3); | |
166acb9f MH |
1915 | if (OP[1] != 0) |
1916 | { | |
7eebfc62 MM |
1917 | (*d10v_callback->printf_filtered) (d10v_callback, |
1918 | "ERROR at PC 0x%x: instruction only valid for A0\n", | |
1919 | PC<<2); | |
166acb9f MH |
1920 | State.exception = SIGILL; |
1921 | } | |
1922 | ||
2934d1c9 MH |
1923 | State.F1 = State.F0; |
1924 | if (shift >=0) | |
1925 | tmp = ((State.a[0] << 16) | (State.a[1] & 0xffff)) << shift; | |
1926 | else | |
1927 | tmp = ((State.a[0] << 16) | (State.a[1] & 0xffff)) >> -shift; | |
166acb9f | 1928 | tmp = ( SEXT60(tmp) + 0x8000 ) >> 16; |
4c38885c | 1929 | if (tmp > MAX32) |
2934d1c9 MH |
1930 | { |
1931 | State.regs[OP[0]] = 0x7fff; | |
1932 | State.regs[OP[0]+1] = 0xffff; | |
1933 | State.F0 = 1; | |
1934 | } | |
4c38885c | 1935 | else if (tmp < MIN32) |
2934d1c9 MH |
1936 | { |
1937 | State.regs[OP[0]] = 0x8000; | |
1938 | State.regs[OP[0]+1] = 0; | |
1939 | State.F0 = 1; | |
1940 | } | |
1941 | else | |
1942 | { | |
1943 | State.regs[OP[0]] = (tmp >> 16) & 0xffff; | |
1944 | State.regs[OP[0]+1] = tmp & 0xffff; | |
1945 | State.F0 = 0; | |
1946 | } | |
87178dbd | 1947 | trace_output (OP_DREG); |
2934d1c9 MH |
1948 | } |
1949 | ||
1950 | /* rachi */ | |
1951 | void | |
1952 | OP_4201 () | |
1953 | { | |
4c38885c MH |
1954 | int64 tmp; |
1955 | int shift = SEXT3 (OP[2]); | |
87178dbd MM |
1956 | |
1957 | trace_input ("rachi", OP_REG_OUTPUT, OP_ACCUM, OP_CONSTANT3); | |
4c38885c MH |
1958 | State.F1 = State.F0; |
1959 | if (shift >=0) | |
166acb9f | 1960 | tmp = SEXT44 (State.a[1]) << shift; |
4c38885c | 1961 | else |
166acb9f | 1962 | tmp = SEXT44 (State.a[1]) >> -shift; |
4c38885c | 1963 | tmp += 0x8000; |
63a91cfb | 1964 | |
4c38885c MH |
1965 | if (tmp > MAX32) |
1966 | { | |
1967 | State.regs[OP[0]] = 0x7fff; | |
1968 | State.F0 = 1; | |
1969 | } | |
1970 | else if (tmp < 0xfff80000000LL) | |
1971 | { | |
1972 | State.regs[OP[0]] = 0x8000; | |
1973 | State.F0 = 1; | |
1974 | } | |
1975 | else | |
1976 | { | |
1977 | State.regs[OP[0]] = (tmp >> 16) & 0xffff; | |
1978 | State.F0 = 0; | |
1979 | } | |
87178dbd | 1980 | trace_output (OP_REG); |
2934d1c9 MH |
1981 | } |
1982 | ||
1983 | /* rep */ | |
1984 | void | |
1985 | OP_27000000 () | |
1986 | { | |
87178dbd | 1987 | trace_input ("rep", OP_REG, OP_CONSTANT16, OP_VOID); |
2934d1c9 MH |
1988 | RPT_S = PC + 1; |
1989 | RPT_E = PC + OP[1]; | |
1990 | RPT_C = State.regs[OP[0]]; | |
1991 | State.RP = 1; | |
1992 | if (RPT_C == 0) | |
1993 | { | |
7eebfc62 | 1994 | (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep with count=0 is illegal.\n"); |
4f425a32 | 1995 | State.exception = SIGILL; |
2934d1c9 | 1996 | } |
4c38885c MH |
1997 | if (OP[1] < 4) |
1998 | { | |
7eebfc62 | 1999 | (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep must include at least 4 instructions.\n"); |
4f425a32 | 2000 | State.exception = SIGILL; |
4c38885c | 2001 | } |
87178dbd | 2002 | trace_output (OP_VOID); |
2934d1c9 MH |
2003 | } |
2004 | ||
2005 | /* repi */ | |
2006 | void | |
2007 | OP_2F000000 () | |
2008 | { | |
87178dbd | 2009 | trace_input ("repi", OP_CONSTANT16, OP_CONSTANT16, OP_VOID); |
2934d1c9 MH |
2010 | RPT_S = PC + 1; |
2011 | RPT_E = PC + OP[1]; | |
2012 | RPT_C = OP[0]; | |
2013 | State.RP = 1; | |
2014 | if (RPT_C == 0) | |
2015 | { | |
7eebfc62 | 2016 | (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi with count=0 is illegal.\n"); |
4f425a32 | 2017 | State.exception = SIGILL; |
4c38885c MH |
2018 | } |
2019 | if (OP[1] < 4) | |
2020 | { | |
7eebfc62 | 2021 | (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi must include at least 4 instructions.\n"); |
4f425a32 | 2022 | State.exception = SIGILL; |
2934d1c9 | 2023 | } |
87178dbd | 2024 | trace_output (OP_VOID); |
2934d1c9 MH |
2025 | } |
2026 | ||
2027 | /* rtd */ | |
2028 | void | |
2029 | OP_5F60 () | |
2030 | { | |
7eebfc62 | 2031 | d10v_callback->printf_filtered(d10v_callback, "ERROR: rtd - NOT IMPLEMENTED\n"); |
87178dbd | 2032 | State.exception = SIGILL; |
2934d1c9 MH |
2033 | } |
2034 | ||
2035 | /* rte */ | |
2036 | void | |
2037 | OP_5F40 () | |
2038 | { | |
87178dbd | 2039 | trace_input ("rte", OP_VOID, OP_VOID, OP_VOID); |
4c38885c MH |
2040 | PC = BPC; |
2041 | PSW = BPSW; | |
87178dbd | 2042 | trace_output (OP_VOID); |
2934d1c9 MH |
2043 | } |
2044 | ||
2045 | /* sadd */ | |
2046 | void | |
2047 | OP_1223 () | |
2048 | { | |
4c38885c | 2049 | int64 tmp; |
87178dbd MM |
2050 | |
2051 | trace_input ("sadd", OP_ACCUM, OP_ACCUM, OP_VOID); | |
4f425a32 | 2052 | tmp = SEXT40(State.a[OP[0]]) + (SEXT40(State.a[OP[1]]) >> 16); |
4c38885c MH |
2053 | if (State.ST) |
2054 | { | |
2055 | if (tmp > MAX32) | |
2056 | State.a[OP[0]] = MAX32; | |
2057 | else if (tmp < MIN32) | |
2058 | State.a[OP[0]] = MIN32; | |
2059 | else | |
4f425a32 | 2060 | State.a[OP[0]] = tmp & MASK40; |
4c38885c MH |
2061 | } |
2062 | else | |
4f425a32 | 2063 | State.a[OP[0]] = tmp & MASK40; |
87178dbd | 2064 | trace_output (OP_ACCUM); |
2934d1c9 MH |
2065 | } |
2066 | ||
2067 | /* setf0f */ | |
2068 | void | |
2069 | OP_4611 () | |
2070 | { | |
87178dbd | 2071 | trace_input ("setf0f", OP_REG_OUTPUT, OP_VOID, OP_VOID); |
4c38885c | 2072 | State.regs[OP[0]] = (State.F0 == 0) ? 1 : 0; |
87178dbd | 2073 | trace_output (OP_REG); |
2934d1c9 MH |
2074 | } |
2075 | ||
2076 | /* setf0t */ | |
2077 | void | |
2078 | OP_4613 () | |
2079 | { | |
87178dbd | 2080 | trace_input ("setf0t", OP_REG_OUTPUT, OP_VOID, OP_VOID); |
4c38885c | 2081 | State.regs[OP[0]] = (State.F0 == 1) ? 1 : 0; |
87178dbd | 2082 | trace_output (OP_REG); |
2934d1c9 MH |
2083 | } |
2084 | ||
2085 | /* sleep */ | |
2086 | void | |
2087 | OP_5FC0 () | |
2088 | { | |
87178dbd | 2089 | trace_input ("sleep", OP_VOID, OP_VOID, OP_VOID); |
4c38885c | 2090 | State.IE = 1; |
87178dbd | 2091 | trace_output (OP_VOID); |
2934d1c9 MH |
2092 | } |
2093 | ||
2094 | /* sll */ | |
2095 | void | |
2096 | OP_2200 () | |
2097 | { | |
87178dbd | 2098 | trace_input ("sll", OP_REG, OP_REG, OP_VOID); |
2934d1c9 | 2099 | State.regs[OP[0]] <<= (State.regs[OP[1]] & 0xf); |
87178dbd | 2100 | trace_output (OP_REG); |
2934d1c9 MH |
2101 | } |
2102 | ||
2103 | /* sll */ | |
2104 | void | |
2105 | OP_3200 () | |
2106 | { | |
4c38885c | 2107 | int64 tmp; |
87178dbd | 2108 | trace_input ("sll", OP_ACCUM, OP_REG, OP_VOID); |
069398aa | 2109 | if ((State.regs[OP[1]] & 31) <= 16) |
4c38885c | 2110 | tmp = SEXT40 (State.a[OP[0]]) << (State.regs[OP[1]] & 31); |
069398aa MM |
2111 | else |
2112 | { | |
2113 | (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31); | |
2114 | State.exception = SIGILL; | |
2115 | return; | |
2116 | } | |
4c38885c MH |
2117 | |
2118 | if (State.ST) | |
2119 | { | |
2120 | if (tmp > MAX32) | |
2121 | State.a[OP[0]] = MAX32; | |
2122 | else if (tmp < 0xffffff80000000LL) | |
2123 | State.a[OP[0]] = MIN32; | |
2124 | else | |
2125 | State.a[OP[0]] = tmp & MASK40; | |
2126 | } | |
2127 | else | |
2128 | State.a[OP[0]] = tmp & MASK40; | |
87178dbd | 2129 | trace_output (OP_ACCUM); |
2934d1c9 MH |
2130 | } |
2131 | ||
2132 | /* slli */ | |
2133 | void | |
2134 | OP_2201 () | |
2135 | { | |
87178dbd | 2136 | trace_input ("slli", OP_REG, OP_CONSTANT16, OP_VOID); |
2934d1c9 | 2137 | State.regs[OP[0]] <<= OP[1]; |
87178dbd | 2138 | trace_output (OP_REG); |
2934d1c9 MH |
2139 | } |
2140 | ||
2141 | /* slli */ | |
2142 | void | |
2143 | OP_3201 () | |
2144 | { | |
4c38885c | 2145 | int64 tmp; |
4f425a32 MH |
2146 | |
2147 | if (OP[1] == 0) | |
2148 | OP[1] = 16; | |
4f425a32 | 2149 | |
87178dbd | 2150 | trace_input ("slli", OP_ACCUM, OP_CONSTANT16, OP_VOID); |
4f425a32 | 2151 | tmp = SEXT40(State.a[OP[0]]) << OP[1]; |
4c38885c MH |
2152 | |
2153 | if (State.ST) | |
2154 | { | |
2155 | if (tmp > MAX32) | |
2156 | State.a[OP[0]] = MAX32; | |
2157 | else if (tmp < 0xffffff80000000LL) | |
2158 | State.a[OP[0]] = MIN32; | |
2159 | else | |
2160 | State.a[OP[0]] = tmp & MASK40; | |
2161 | } | |
2162 | else | |
2163 | State.a[OP[0]] = tmp & MASK40; | |
87178dbd | 2164 | trace_output (OP_ACCUM); |
2934d1c9 MH |
2165 | } |
2166 | ||
2167 | /* slx */ | |
2168 | void | |
2169 | OP_460B () | |
2170 | { | |
87178dbd | 2171 | trace_input ("slx", OP_REG, OP_FLAG, OP_VOID); |
2934d1c9 | 2172 | State.regs[OP[0]] = (State.regs[OP[0]] << 1) | State.F0; |
87178dbd | 2173 | trace_output (OP_REG); |
2934d1c9 MH |
2174 | } |
2175 | ||
2176 | /* sra */ | |
2177 | void | |
2178 | OP_2400 () | |
2179 | { | |
87178dbd | 2180 | trace_input ("sra", OP_REG, OP_REG, OP_VOID); |
2934d1c9 | 2181 | State.regs[OP[0]] = ((int16)(State.regs[OP[0]])) >> (State.regs[OP[1]] & 0xf); |
87178dbd | 2182 | trace_output (OP_REG); |
2934d1c9 MH |
2183 | } |
2184 | ||
2185 | /* sra */ | |
2186 | void | |
2187 | OP_3400 () | |
2188 | { | |
87178dbd | 2189 | trace_input ("sra", OP_ACCUM, OP_REG, OP_VOID); |
069398aa | 2190 | if ((State.regs[OP[1]] & 31) <= 16) |
fd435e9f | 2191 | State.a[OP[0]] = (SEXT40(State.a[OP[0]]) >> (State.regs[OP[1]] & 31)) & MASK40; |
069398aa MM |
2192 | else |
2193 | { | |
2194 | (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31); | |
2195 | State.exception = SIGILL; | |
2196 | return; | |
2197 | } | |
2198 | ||
87178dbd | 2199 | trace_output (OP_ACCUM); |
2934d1c9 MH |
2200 | } |
2201 | ||
2202 | /* srai */ | |
2203 | void | |
2204 | OP_2401 () | |
2205 | { | |
87178dbd | 2206 | trace_input ("srai", OP_REG, OP_CONSTANT16, OP_VOID); |
2934d1c9 | 2207 | State.regs[OP[0]] = ((int16)(State.regs[OP[0]])) >> OP[1]; |
87178dbd | 2208 | trace_output (OP_REG); |
2934d1c9 MH |
2209 | } |
2210 | ||
2211 | /* srai */ | |
2212 | void | |
2213 | OP_3401 () | |
2214 | { | |
4f425a32 MH |
2215 | if (OP[1] == 0) |
2216 | OP[1] = 16; | |
87178dbd MM |
2217 | |
2218 | trace_input ("srai", OP_ACCUM, OP_CONSTANT16, OP_VOID); | |
fd435e9f | 2219 | State.a[OP[0]] = (SEXT40(State.a[OP[0]]) >> OP[1]) & MASK40; |
87178dbd | 2220 | trace_output (OP_ACCUM); |
2934d1c9 MH |
2221 | } |
2222 | ||
2223 | /* srl */ | |
2224 | void | |
2225 | OP_2000 () | |
2226 | { | |
87178dbd | 2227 | trace_input ("srl", OP_REG, OP_REG, OP_VOID); |
2934d1c9 | 2228 | State.regs[OP[0]] >>= (State.regs[OP[1]] & 0xf); |
87178dbd | 2229 | trace_output (OP_REG); |
2934d1c9 MH |
2230 | } |
2231 | ||
2232 | /* srl */ | |
2233 | void | |
2234 | OP_3000 () | |
2235 | { | |
87178dbd | 2236 | trace_input ("srl", OP_ACCUM, OP_REG, OP_VOID); |
069398aa | 2237 | if ((State.regs[OP[1]] & 31) <= 16) |
fd435e9f | 2238 | State.a[OP[0]] = (uint64)((State.a[OP[0]] & MASK40) >> (State.regs[OP[1]] & 31)); |
069398aa MM |
2239 | else |
2240 | { | |
2241 | (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31); | |
2242 | State.exception = SIGILL; | |
2243 | return; | |
2244 | } | |
2245 | ||
87178dbd | 2246 | trace_output (OP_ACCUM); |
2934d1c9 MH |
2247 | } |
2248 | ||
2249 | /* srli */ | |
2250 | void | |
2251 | OP_2001 () | |
2252 | { | |
87178dbd | 2253 | trace_input ("srli", OP_REG, OP_CONSTANT16, OP_VOID); |
2934d1c9 | 2254 | State.regs[OP[0]] >>= OP[1]; |
87178dbd | 2255 | trace_output (OP_REG); |
2934d1c9 MH |
2256 | } |
2257 | ||
2258 | /* srli */ | |
2259 | void | |
2260 | OP_3001 () | |
2261 | { | |
4f425a32 MH |
2262 | if (OP[1] == 0) |
2263 | OP[1] = 16; | |
87178dbd MM |
2264 | |
2265 | trace_input ("srli", OP_ACCUM, OP_CONSTANT16, OP_VOID); | |
fd435e9f | 2266 | State.a[OP[0]] = (uint64)(State.a[OP[0]] & MASK40) >> OP[1]; |
87178dbd | 2267 | trace_output (OP_ACCUM); |
2934d1c9 MH |
2268 | } |
2269 | ||
2270 | /* srx */ | |
2271 | void | |
2272 | OP_4609 () | |
2273 | { | |
2274 | uint16 tmp; | |
87178dbd MM |
2275 | |
2276 | trace_input ("srx", OP_REG, OP_FLAG, OP_VOID); | |
2934d1c9 MH |
2277 | tmp = State.F0 << 15; |
2278 | State.regs[OP[0]] = (State.regs[OP[0]] >> 1) | tmp; | |
87178dbd | 2279 | trace_output (OP_REG); |
2934d1c9 MH |
2280 | } |
2281 | ||
2282 | /* st */ | |
2283 | void | |
2284 | OP_34000000 () | |
2285 | { | |
87178dbd | 2286 | trace_input ("st", OP_REG, OP_MEMREF2, OP_VOID); |
2934d1c9 | 2287 | SW (OP[1] + State.regs[OP[2]], State.regs[OP[0]]); |
87178dbd | 2288 | trace_output (OP_VOID); |
2934d1c9 MH |
2289 | } |
2290 | ||
2291 | /* st */ | |
2292 | void | |
2293 | OP_6800 () | |
2294 | { | |
87178dbd | 2295 | trace_input ("st", OP_REG, OP_MEMREF, OP_VOID); |
2934d1c9 | 2296 | SW (State.regs[OP[1]], State.regs[OP[0]]); |
87178dbd | 2297 | trace_output (OP_VOID); |
2934d1c9 MH |
2298 | } |
2299 | ||
2300 | /* st */ | |
2301 | void | |
2302 | OP_6C1F () | |
2303 | { | |
87178dbd | 2304 | trace_input ("st", OP_REG, OP_PREDEC, OP_VOID); |
4c38885c MH |
2305 | if ( OP[1] != 15 ) |
2306 | { | |
7eebfc62 | 2307 | (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n"); |
4f425a32 MH |
2308 | State.exception = SIGILL; |
2309 | return; | |
4c38885c MH |
2310 | } |
2311 | State.regs[OP[1]] -= 2; | |
2312 | SW (State.regs[OP[1]], State.regs[OP[0]]); | |
87178dbd | 2313 | trace_output (OP_VOID); |
2934d1c9 MH |
2314 | } |
2315 | ||
2316 | /* st */ | |
2317 | void | |
2318 | OP_6801 () | |
2319 | { | |
87178dbd | 2320 | trace_input ("st", OP_REG, OP_POSTINC, OP_VOID); |
4c38885c | 2321 | SW (State.regs[OP[1]], State.regs[OP[0]]); |
4f425a32 | 2322 | INC_ADDR (State.regs[OP[1]],2); |
87178dbd | 2323 | trace_output (OP_VOID); |
2934d1c9 MH |
2324 | } |
2325 | ||
2326 | /* st */ | |
2327 | void | |
2328 | OP_6C01 () | |
2329 | { | |
87178dbd | 2330 | trace_input ("st", OP_REG, OP_POSTDEC, OP_VOID); |
fd435e9f MM |
2331 | if ( OP[1] == 15 ) |
2332 | { | |
2333 | (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot post-decrement register r15 (SP).\n"); | |
2334 | State.exception = SIGILL; | |
2335 | return; | |
2336 | } | |
4c38885c | 2337 | SW (State.regs[OP[1]], State.regs[OP[0]]); |
4f425a32 | 2338 | INC_ADDR (State.regs[OP[1]],-2); |
87178dbd | 2339 | trace_output (OP_VOID); |
2934d1c9 MH |
2340 | } |
2341 | ||
2342 | /* st2w */ | |
2343 | void | |
2344 | OP_35000000 () | |
2345 | { | |
87178dbd | 2346 | trace_input ("st2w", OP_DREG, OP_MEMREF2, OP_VOID); |
4f425a32 MH |
2347 | SW (State.regs[OP[2]]+OP[1], State.regs[OP[0]]); |
2348 | SW (State.regs[OP[2]]+OP[1]+2, State.regs[OP[0]+1]); | |
87178dbd | 2349 | trace_output (OP_VOID); |
2934d1c9 MH |
2350 | } |
2351 | ||
2352 | /* st2w */ | |
2353 | void | |
2354 | OP_6A00 () | |
2355 | { | |
a18cb100 | 2356 | trace_input ("st2w", OP_DREG, OP_MEMREF, OP_VOID); |
4c38885c MH |
2357 | SW (State.regs[OP[1]], State.regs[OP[0]]); |
2358 | SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]); | |
87178dbd | 2359 | trace_output (OP_VOID); |
2934d1c9 MH |
2360 | } |
2361 | ||
2362 | /* st2w */ | |
2363 | void | |
2364 | OP_6E1F () | |
2365 | { | |
a18cb100 | 2366 | trace_input ("st2w", OP_DREG, OP_PREDEC, OP_VOID); |
4c38885c MH |
2367 | if ( OP[1] != 15 ) |
2368 | { | |
7eebfc62 | 2369 | (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n"); |
4f425a32 MH |
2370 | State.exception = SIGILL; |
2371 | return; | |
4c38885c MH |
2372 | } |
2373 | State.regs[OP[1]] -= 4; | |
2374 | SW (State.regs[OP[1]], State.regs[OP[0]]); | |
2375 | SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]); | |
87178dbd | 2376 | trace_output (OP_VOID); |
2934d1c9 MH |
2377 | } |
2378 | ||
2379 | /* st2w */ | |
2380 | void | |
2381 | OP_6A01 () | |
2382 | { | |
a18cb100 | 2383 | trace_input ("st2w", OP_DREG, OP_POSTDEC, OP_VOID); |
fd435e9f MM |
2384 | if ( OP[1] == 15 ) |
2385 | { | |
2386 | (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot post-decrement register r15 (SP).\n"); | |
2387 | State.exception = SIGILL; | |
2388 | return; | |
2389 | } | |
4c38885c MH |
2390 | SW (State.regs[OP[1]], State.regs[OP[0]]); |
2391 | SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]); | |
4f425a32 | 2392 | INC_ADDR (State.regs[OP[1]],4); |
87178dbd | 2393 | trace_output (OP_VOID); |
2934d1c9 MH |
2394 | } |
2395 | ||
2396 | /* st2w */ | |
2397 | void | |
2398 | OP_6E01 () | |
2399 | { | |
a18cb100 | 2400 | trace_input ("st2w", OP_DREG, OP_POSTINC, OP_VOID); |
4c38885c MH |
2401 | SW (State.regs[OP[1]], State.regs[OP[0]]); |
2402 | SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]); | |
4f425a32 | 2403 | INC_ADDR (State.regs[OP[1]],-4); |
87178dbd | 2404 | trace_output (OP_VOID); |
2934d1c9 MH |
2405 | } |
2406 | ||
2407 | /* stb */ | |
2408 | void | |
2409 | OP_3C000000 () | |
2410 | { | |
87178dbd | 2411 | trace_input ("stb", OP_REG, OP_MEMREF2, OP_VOID); |
4f425a32 | 2412 | SB (State.regs[OP[2]]+OP[1], State.regs[OP[0]]); |
87178dbd | 2413 | trace_output (OP_VOID); |
2934d1c9 MH |
2414 | } |
2415 | ||
2416 | /* stb */ | |
2417 | void | |
2418 | OP_7800 () | |
2419 | { | |
87178dbd | 2420 | trace_input ("stb", OP_REG, OP_MEMREF, OP_VOID); |
4c38885c | 2421 | SB (State.regs[OP[1]], State.regs[OP[0]]); |
87178dbd | 2422 | trace_output (OP_VOID); |
2934d1c9 MH |
2423 | } |
2424 | ||
2425 | /* stop */ | |
2426 | void | |
2427 | OP_5FE0 () | |
2428 | { | |
87178dbd | 2429 | trace_input ("stop", OP_VOID, OP_VOID, OP_VOID); |
a49a15ad | 2430 | State.exception = SIG_D10V_STOP; |
87178dbd | 2431 | trace_output (OP_VOID); |
2934d1c9 MH |
2432 | } |
2433 | ||
2434 | /* sub */ | |
2435 | void | |
2436 | OP_0 () | |
4c38885c MH |
2437 | { |
2438 | int32 tmp; | |
87178dbd MM |
2439 | |
2440 | trace_input ("sub", OP_REG, OP_REG, OP_VOID); | |
4c38885c MH |
2441 | tmp = (int16)State.regs[OP[0]]- (int16)State.regs[OP[1]]; |
2442 | State.C = (tmp & 0xffff0000) ? 1 : 0; | |
2443 | State.regs[OP[0]] = tmp & 0xffff; | |
87178dbd | 2444 | trace_output (OP_REG); |
4c38885c MH |
2445 | } |
2446 | ||
2447 | /* sub */ | |
2448 | void | |
2449 | OP_1001 () | |
2450 | { | |
4f425a32 | 2451 | int64 tmp; |
87178dbd MM |
2452 | |
2453 | trace_input ("sub", OP_ACCUM, OP_DREG, OP_VOID); | |
4f425a32 MH |
2454 | tmp = SEXT40(State.a[OP[0]]) - (SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]); |
2455 | if (State.ST) | |
2456 | { | |
2457 | if ( tmp > MAX32) | |
2458 | State.a[OP[0]] = MAX32; | |
2459 | else if ( tmp < MIN32) | |
2460 | State.a[OP[0]] = MIN32; | |
2461 | else | |
2462 | State.a[OP[0]] = tmp & MASK40; | |
2463 | } | |
2464 | else | |
2465 | State.a[OP[0]] = tmp & MASK40; | |
87178dbd MM |
2466 | |
2467 | trace_output (OP_ACCUM); | |
4c38885c MH |
2468 | } |
2469 | ||
2470 | /* sub */ | |
2471 | ||
2472 | void | |
2473 | OP_1003 () | |
2934d1c9 | 2474 | { |
4f425a32 | 2475 | int64 tmp; |
87178dbd MM |
2476 | |
2477 | trace_input ("sub", OP_ACCUM, OP_ACCUM, OP_VOID); | |
4f425a32 MH |
2478 | tmp = SEXT40(State.a[OP[0]]) - SEXT40(State.a[OP[1]]); |
2479 | if (State.ST) | |
2480 | { | |
2481 | if (tmp > MAX32) | |
2482 | State.a[OP[0]] = MAX32; | |
2483 | else if ( tmp < MIN32) | |
2484 | State.a[OP[0]] = MIN32; | |
2485 | else | |
2486 | State.a[OP[0]] = tmp & MASK40; | |
2487 | } | |
2488 | else | |
2489 | State.a[OP[0]] = tmp & MASK40; | |
87178dbd MM |
2490 | |
2491 | trace_output (OP_ACCUM); | |
2934d1c9 MH |
2492 | } |
2493 | ||
2494 | /* sub2w */ | |
2495 | void | |
2496 | OP_1000 () | |
2497 | { | |
4c38885c | 2498 | int64 tmp; |
fd435e9f | 2499 | uint32 a,b; |
4c38885c | 2500 | |
87178dbd | 2501 | trace_input ("sub2w", OP_DREG, OP_DREG, OP_VOID); |
4c38885c MH |
2502 | a = (int32)((State.regs[OP[0]] << 16) | State.regs[OP[0]+1]); |
2503 | b = (int32)((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]); | |
fd435e9f | 2504 | tmp = (int64)a-b; |
4c38885c MH |
2505 | State.C = (tmp & 0xffffffff00000000LL) ? 1 : 0; |
2506 | State.regs[OP[0]] = (tmp >> 16) & 0xffff; | |
2507 | State.regs[OP[0]+1] = tmp & 0xffff; | |
87178dbd | 2508 | trace_output (OP_DREG); |
2934d1c9 MH |
2509 | } |
2510 | ||
2511 | /* subac3 */ | |
2512 | void | |
2513 | OP_17000000 () | |
2514 | { | |
4f425a32 | 2515 | int64 tmp; |
87178dbd MM |
2516 | |
2517 | trace_input ("subac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM); | |
4f425a32 MH |
2518 | tmp = SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]) - SEXT40 (State.a[OP[2]]); |
2519 | State.regs[OP[0]] = (tmp >> 16) & 0xffff; | |
2520 | State.regs[OP[0]+1] = tmp & 0xffff; | |
87178dbd | 2521 | trace_output (OP_DREG); |
2934d1c9 MH |
2522 | } |
2523 | ||
2524 | /* subac3 */ | |
2525 | void | |
2526 | OP_17000002 () | |
2527 | { | |
4f425a32 | 2528 | int64 tmp; |
87178dbd MM |
2529 | |
2530 | trace_input ("subac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM); | |
4f425a32 MH |
2531 | tmp = SEXT40(State.a[OP[1]]) - SEXT40(State.a[OP[2]]); |
2532 | State.regs[OP[0]] = (tmp >> 16) & 0xffff; | |
2533 | State.regs[OP[0]+1] = tmp & 0xffff; | |
87178dbd | 2534 | trace_output (OP_DREG); |
2934d1c9 MH |
2535 | } |
2536 | ||
2537 | /* subac3s */ | |
2538 | void | |
2539 | OP_17001000 () | |
2540 | { | |
4f425a32 | 2541 | int64 tmp; |
87178dbd MM |
2542 | |
2543 | trace_input ("subac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM); | |
4f425a32 MH |
2544 | State.F1 = State.F0; |
2545 | tmp = SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]) - SEXT40(State.a[OP[2]]); | |
2546 | if ( tmp > MAX32) | |
2547 | { | |
2548 | State.regs[OP[0]] = 0x7fff; | |
2549 | State.regs[OP[0]+1] = 0xffff; | |
2550 | State.F0 = 1; | |
2551 | } | |
2552 | else if (tmp < MIN32) | |
2553 | { | |
2554 | State.regs[OP[0]] = 0x8000; | |
2555 | State.regs[OP[0]+1] = 0; | |
2556 | State.F0 = 1; | |
2557 | } | |
2558 | else | |
2559 | { | |
2560 | State.regs[OP[0]] = (tmp >> 16) & 0xffff; | |
2561 | State.regs[OP[0]+1] = tmp & 0xffff; | |
2562 | State.F0 = 0; | |
2563 | } | |
87178dbd | 2564 | trace_output (OP_DREG); |
2934d1c9 MH |
2565 | } |
2566 | ||
2567 | /* subac3s */ | |
2568 | void | |
2569 | OP_17001002 () | |
2570 | { | |
4f425a32 | 2571 | int64 tmp; |
87178dbd MM |
2572 | |
2573 | trace_input ("subac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM); | |
4f425a32 MH |
2574 | State.F1 = State.F0; |
2575 | tmp = SEXT40(State.a[OP[1]]) - SEXT40(State.a[OP[2]]); | |
2576 | if ( tmp > MAX32) | |
2577 | { | |
2578 | State.regs[OP[0]] = 0x7fff; | |
2579 | State.regs[OP[0]+1] = 0xffff; | |
2580 | State.F0 = 1; | |
2581 | } | |
2582 | else if (tmp < MIN32) | |
2583 | { | |
2584 | State.regs[OP[0]] = 0x8000; | |
2585 | State.regs[OP[0]+1] = 0; | |
2586 | State.F0 = 1; | |
2587 | } | |
2588 | else | |
2589 | { | |
2590 | State.regs[OP[0]] = (tmp >> 16) & 0xffff; | |
2591 | State.regs[OP[0]+1] = tmp & 0xffff; | |
2592 | State.F0 = 0; | |
2593 | } | |
87178dbd | 2594 | trace_output (OP_DREG); |
2934d1c9 MH |
2595 | } |
2596 | ||
2597 | /* subi */ | |
2598 | void | |
2599 | OP_1 () | |
2600 | { | |
4c38885c | 2601 | int32 tmp; |
4f425a32 MH |
2602 | if (OP[1] == 0) |
2603 | OP[1] = 16; | |
87178dbd MM |
2604 | |
2605 | trace_input ("subi", OP_REG, OP_CONSTANT16, OP_VOID); | |
4c38885c MH |
2606 | tmp = (int16)State.regs[OP[0]] - OP[1]; |
2607 | State.C = (tmp & 0xffff0000) ? 1 : 0; | |
2608 | State.regs[OP[0]] = tmp & 0xffff; | |
87178dbd | 2609 | trace_output (OP_REG); |
2934d1c9 MH |
2610 | } |
2611 | ||
2612 | /* trap */ | |
2613 | void | |
2614 | OP_5F00 () | |
2615 | { | |
a5719092 | 2616 | trace_input ("trap", OP_CONSTANT4, OP_VOID, OP_VOID); |
87178dbd | 2617 | trace_output (OP_VOID); |
8918b3a7 | 2618 | |
63a91cfb | 2619 | switch (OP[0]) |
2934d1c9 | 2620 | { |
63a91cfb | 2621 | default: |
19d44375 | 2622 | #if 0 |
7eebfc62 | 2623 | (*d10v_callback->printf_filtered) (d10v_callback, "Unknown trap code %d\n", OP[0]); |
63a91cfb | 2624 | State.exception = SIGILL; |
19d44375 MM |
2625 | #else |
2626 | /* Use any other traps for batch debugging. */ | |
2627 | { | |
2628 | int i; | |
2629 | static int first_time = 1; | |
2630 | ||
2631 | if (first_time) | |
2632 | { | |
2633 | first_time = 0; | |
2634 | (*d10v_callback->printf_filtered) (d10v_callback, "Trap # PC "); | |
2635 | for (i = 0; i < 16; i++) | |
2636 | (*d10v_callback->printf_filtered) (d10v_callback, " %sr%d", (i > 9) ? "" : " ", i); | |
2637 | (*d10v_callback->printf_filtered) (d10v_callback, " a0 a1 f0 f1 c\n"); | |
2638 | } | |
2639 | ||
2640 | (*d10v_callback->printf_filtered) (d10v_callback, "Trap %2d 0x%.4x:", (int)OP[0], (int)PC); | |
2641 | ||
2642 | for (i = 0; i < 16; i++) | |
2643 | (*d10v_callback->printf_filtered) (d10v_callback, " %.4x", (int) State.regs[i]); | |
2644 | ||
2645 | for (i = 0; i < 2; i++) | |
2646 | (*d10v_callback->printf_filtered) (d10v_callback, " %.2x%.8lx", | |
11ec4de6 MM |
2647 | ((int)(State.a[i] >> 32) & 0xff), |
2648 | ((unsigned long)State.a[i]) & 0xffffffff); | |
19d44375 MM |
2649 | |
2650 | (*d10v_callback->printf_filtered) (d10v_callback, " %d %d %d\n", | |
2651 | State.F0 != 0, State.F1 != 0, State.C != 0); | |
fd435e9f | 2652 | (*d10v_callback->flush_stdout) (d10v_callback); |
19d44375 MM |
2653 | break; |
2654 | #endif | |
63a91cfb MM |
2655 | |
2656 | case 0: | |
2657 | /* Trap 0 is used for simulating low-level I/O */ | |
2658 | { | |
63a91cfb MM |
2659 | errno = 0; |
2660 | ||
2661 | /* Registers passed to trap 0 */ | |
2662 | ||
65c0d7de MA |
2663 | #define FUNC State.regs[6] /* function number */ |
2664 | #define PARM1 State.regs[2] /* optional parm 1 */ | |
2665 | #define PARM2 State.regs[3] /* optional parm 2 */ | |
2666 | #define PARM3 State.regs[4] /* optional parm 3 */ | |
2667 | #define PARM4 State.regs[5] /* optional parm 3 */ | |
63a91cfb MM |
2668 | |
2669 | /* Registers set by trap 0 */ | |
2670 | ||
65c0d7de MA |
2671 | #define RETVAL State.regs[2] /* return value */ |
2672 | #define RETVAL_HIGH State.regs[2] /* return value */ | |
2673 | #define RETVAL_LOW State.regs[3] /* return value */ | |
2674 | #define RETERR State.regs[4] /* return error code */ | |
63a91cfb MM |
2675 | |
2676 | /* Turn a pointer in a register into a pointer into real memory. */ | |
2677 | ||
c422ecc7 | 2678 | #define MEMPTR(x) ((char *)(dmem_addr(x))) |
63a91cfb MM |
2679 | |
2680 | switch (FUNC) | |
2681 | { | |
2682 | #if !defined(__GO32__) && !defined(_WIN32) | |
63a91cfb MM |
2683 | case SYS_fork: |
2684 | RETVAL = fork (); | |
8918b3a7 MM |
2685 | trace_input ("<fork>", OP_VOID, OP_VOID, OP_VOID); |
2686 | trace_output (OP_R2); | |
63a91cfb | 2687 | break; |
8918b3a7 | 2688 | |
57bc1a72 MM |
2689 | case SYS_getpid: |
2690 | trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID); | |
2691 | RETVAL = getpid (); | |
2692 | trace_output (OP_R2); | |
2693 | break; | |
2694 | ||
2695 | case SYS_kill: | |
2696 | trace_input ("<kill>", OP_REG, OP_REG, OP_VOID); | |
2697 | if (PARM1 == getpid ()) | |
2698 | { | |
2699 | trace_output (OP_VOID); | |
2700 | State.exception = PARM2; | |
2701 | } | |
2702 | else | |
2703 | { | |
2704 | int os_sig = -1; | |
2705 | switch (PARM2) | |
2706 | { | |
2707 | #ifdef SIGHUP | |
2708 | case 1: os_sig = SIGHUP; break; | |
2709 | #endif | |
2710 | #ifdef SIGINT | |
2711 | case 2: os_sig = SIGINT; break; | |
2712 | #endif | |
2713 | #ifdef SIGQUIT | |
2714 | case 3: os_sig = SIGQUIT; break; | |
2715 | #endif | |
2716 | #ifdef SIGILL | |
2717 | case 4: os_sig = SIGILL; break; | |
2718 | #endif | |
2719 | #ifdef SIGTRAP | |
2720 | case 5: os_sig = SIGTRAP; break; | |
2721 | #endif | |
2722 | #ifdef SIGABRT | |
2723 | case 6: os_sig = SIGABRT; break; | |
2724 | #elif defined(SIGIOT) | |
2725 | case 6: os_sig = SIGIOT; break; | |
2726 | #endif | |
2727 | #ifdef SIGEMT | |
2728 | case 7: os_sig = SIGEMT; break; | |
2729 | #endif | |
2730 | #ifdef SIGFPE | |
2731 | case 8: os_sig = SIGFPE; break; | |
2732 | #endif | |
2733 | #ifdef SIGKILL | |
2734 | case 9: os_sig = SIGKILL; break; | |
2735 | #endif | |
2736 | #ifdef SIGBUS | |
2737 | case 10: os_sig = SIGBUS; break; | |
2738 | #endif | |
2739 | #ifdef SIGSEGV | |
2740 | case 11: os_sig = SIGSEGV; break; | |
2741 | #endif | |
2742 | #ifdef SIGSYS | |
2743 | case 12: os_sig = SIGSYS; break; | |
2744 | #endif | |
2745 | #ifdef SIGPIPE | |
2746 | case 13: os_sig = SIGPIPE; break; | |
2747 | #endif | |
2748 | #ifdef SIGALRM | |
2749 | case 14: os_sig = SIGALRM; break; | |
2750 | #endif | |
2751 | #ifdef SIGTERM | |
2752 | case 15: os_sig = SIGTERM; break; | |
2753 | #endif | |
2754 | #ifdef SIGURG | |
2755 | case 16: os_sig = SIGURG; break; | |
2756 | #endif | |
2757 | #ifdef SIGSTOP | |
2758 | case 17: os_sig = SIGSTOP; break; | |
2759 | #endif | |
2760 | #ifdef SIGTSTP | |
2761 | case 18: os_sig = SIGTSTP; break; | |
2762 | #endif | |
2763 | #ifdef SIGCONT | |
2764 | case 19: os_sig = SIGCONT; break; | |
2765 | #endif | |
2766 | #ifdef SIGCHLD | |
2767 | case 20: os_sig = SIGCHLD; break; | |
2768 | #elif defined(SIGCLD) | |
2769 | case 20: os_sig = SIGCLD; break; | |
2770 | #endif | |
2771 | #ifdef SIGTTIN | |
2772 | case 21: os_sig = SIGTTIN; break; | |
2773 | #endif | |
2774 | #ifdef SIGTTOU | |
2775 | case 22: os_sig = SIGTTOU; break; | |
2776 | #endif | |
2777 | #ifdef SIGIO | |
2778 | case 23: os_sig = SIGIO; break; | |
2779 | #elif defined (SIGPOLL) | |
2780 | case 23: os_sig = SIGPOLL; break; | |
2781 | #endif | |
2782 | #ifdef SIGXCPU | |
2783 | case 24: os_sig = SIGXCPU; break; | |
2784 | #endif | |
2785 | #ifdef SIGXFSZ | |
2786 | case 25: os_sig = SIGXFSZ; break; | |
2787 | #endif | |
2788 | #ifdef SIGVTALRM | |
2789 | case 26: os_sig = SIGVTALRM; break; | |
2790 | #endif | |
2791 | #ifdef SIGPROF | |
2792 | case 27: os_sig = SIGPROF; break; | |
2793 | #endif | |
2794 | #ifdef SIGWINCH | |
2795 | case 28: os_sig = SIGWINCH; break; | |
2796 | #endif | |
2797 | #ifdef SIGLOST | |
2798 | case 29: os_sig = SIGLOST; break; | |
2799 | #endif | |
2800 | #ifdef SIGUSR1 | |
2801 | case 30: os_sig = SIGUSR1; break; | |
2802 | #endif | |
2803 | #ifdef SIGUSR2 | |
2804 | case 31: os_sig = SIGUSR2; break; | |
2805 | #endif | |
2806 | } | |
2807 | ||
2808 | if (os_sig == -1) | |
2809 | { | |
2810 | trace_output (OP_VOID); | |
2811 | (*d10v_callback->printf_filtered) (d10v_callback, "Unknown signal %d\n", PARM2); | |
fd435e9f | 2812 | (*d10v_callback->flush_stdout) (d10v_callback); |
57bc1a72 MM |
2813 | State.exception = SIGILL; |
2814 | } | |
2815 | else | |
2816 | { | |
2817 | RETVAL = kill (PARM1, PARM2); | |
2818 | trace_output (OP_R2); | |
2819 | } | |
2820 | } | |
2821 | break; | |
2822 | ||
63a91cfb MM |
2823 | case SYS_execve: |
2824 | RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), | |
2825 | (char **)MEMPTR (PARM3)); | |
8918b3a7 MM |
2826 | trace_input ("<execve>", OP_R2, OP_R3, OP_R4); |
2827 | trace_output (OP_R2); | |
63a91cfb | 2828 | break; |
8918b3a7 | 2829 | |
63a91cfb MM |
2830 | case SYS_execv: |
2831 | RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL); | |
8918b3a7 MM |
2832 | trace_input ("<execv>", OP_R2, OP_R3, OP_VOID); |
2833 | trace_output (OP_R2); | |
63a91cfb | 2834 | break; |
8918b3a7 | 2835 | |
63a91cfb MM |
2836 | case SYS_pipe: |
2837 | { | |
2838 | reg_t buf; | |
2839 | int host_fd[2]; | |
2840 | ||
2841 | buf = PARM1; | |
2842 | RETVAL = pipe (host_fd); | |
2843 | SW (buf, host_fd[0]); | |
2844 | buf += sizeof(uint16); | |
2845 | SW (buf, host_fd[1]); | |
8918b3a7 MM |
2846 | trace_input ("<pipe>", OP_R2, OP_VOID, OP_VOID); |
2847 | trace_output (OP_R2); | |
63a91cfb MM |
2848 | } |
2849 | break; | |
8918b3a7 | 2850 | |
63a91cfb MM |
2851 | case SYS_wait: |
2852 | { | |
2853 | int status; | |
2854 | ||
2855 | RETVAL = wait (&status); | |
8918b3a7 MM |
2856 | if (PARM1) |
2857 | SW (PARM1, status); | |
2858 | trace_input ("<wait>", OP_R2, OP_VOID, OP_VOID); | |
2859 | trace_output (OP_R2); | |
63a91cfb MM |
2860 | } |
2861 | break; | |
57bc1a72 MM |
2862 | #else |
2863 | case SYS_getpid: | |
2864 | trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID); | |
2865 | RETVAL = 1; | |
2866 | trace_output (OP_R2); | |
2867 | break; | |
2868 | ||
2869 | case SYS_kill: | |
2870 | trace_input ("<kill>", OP_REG, OP_REG, OP_VOID); | |
2871 | trace_output (OP_VOID); | |
2872 | State.exception = PARM2; | |
2873 | break; | |
63a91cfb | 2874 | #endif |
8918b3a7 | 2875 | |
63a91cfb MM |
2876 | case SYS_read: |
2877 | RETVAL = d10v_callback->read (d10v_callback, PARM1, MEMPTR (PARM2), | |
2878 | PARM3); | |
8918b3a7 MM |
2879 | trace_input ("<read>", OP_R2, OP_R3, OP_R4); |
2880 | trace_output (OP_R2); | |
63a91cfb | 2881 | break; |
8918b3a7 | 2882 | |
63a91cfb MM |
2883 | case SYS_write: |
2884 | if (PARM1 == 1) | |
2885 | RETVAL = (int)d10v_callback->write_stdout (d10v_callback, | |
2886 | MEMPTR (PARM2), PARM3); | |
2887 | else | |
2888 | RETVAL = (int)d10v_callback->write (d10v_callback, PARM1, | |
2889 | MEMPTR (PARM2), PARM3); | |
8918b3a7 MM |
2890 | trace_input ("<write>", OP_R2, OP_R3, OP_R4); |
2891 | trace_output (OP_R2); | |
63a91cfb | 2892 | break; |
8918b3a7 | 2893 | |
63a91cfb | 2894 | case SYS_lseek: |
65c0d7de MA |
2895 | { |
2896 | unsigned long ret = d10v_callback->lseek (d10v_callback, PARM1, | |
2897 | (((unsigned long)PARM2) << 16) || (unsigned long)PARM3, | |
2898 | PARM4); | |
2899 | RETVAL_HIGH = ret >> 16; | |
2900 | RETVAL_LOW = ret & 0xffff; | |
2901 | } | |
8918b3a7 MM |
2902 | trace_input ("<lseek>", OP_R2, OP_R3, OP_R4); |
2903 | trace_output (OP_R2R3); | |
63a91cfb | 2904 | break; |
8918b3a7 | 2905 | |
63a91cfb MM |
2906 | case SYS_close: |
2907 | RETVAL = d10v_callback->close (d10v_callback, PARM1); | |
8918b3a7 MM |
2908 | trace_input ("<close>", OP_R2, OP_VOID, OP_VOID); |
2909 | trace_output (OP_R2); | |
63a91cfb | 2910 | break; |
8918b3a7 | 2911 | |
63a91cfb MM |
2912 | case SYS_open: |
2913 | RETVAL = d10v_callback->open (d10v_callback, MEMPTR (PARM1), PARM2); | |
8918b3a7 MM |
2914 | trace_input ("<open>", OP_R2, OP_R3, OP_R4); |
2915 | trace_output (OP_R2); | |
2916 | trace_input ("<open>", OP_R2, OP_R3, OP_R4); | |
2917 | trace_output (OP_R2); | |
63a91cfb | 2918 | break; |
8918b3a7 | 2919 | |
63a91cfb | 2920 | case SYS_exit: |
a49a15ad | 2921 | State.exception = SIG_D10V_EXIT; |
8918b3a7 MM |
2922 | trace_input ("<exit>", OP_R2, OP_VOID, OP_VOID); |
2923 | trace_output (OP_VOID); | |
63a91cfb | 2924 | break; |
63a91cfb | 2925 | |
8719be26 | 2926 | case SYS_stat: |
63a91cfb MM |
2927 | /* stat system call */ |
2928 | { | |
2929 | struct stat host_stat; | |
2930 | reg_t buf; | |
2931 | ||
2932 | RETVAL = stat (MEMPTR (PARM1), &host_stat); | |
2933 | ||
2934 | buf = PARM2; | |
2935 | ||
2936 | /* The hard-coded offsets and sizes were determined by using | |
2937 | * the D10V compiler on a test program that used struct stat. | |
2938 | */ | |
2939 | SW (buf, host_stat.st_dev); | |
2940 | SW (buf+2, host_stat.st_ino); | |
2941 | SW (buf+4, host_stat.st_mode); | |
2942 | SW (buf+6, host_stat.st_nlink); | |
2943 | SW (buf+8, host_stat.st_uid); | |
2944 | SW (buf+10, host_stat.st_gid); | |
2945 | SW (buf+12, host_stat.st_rdev); | |
2946 | SLW (buf+16, host_stat.st_size); | |
2947 | SLW (buf+20, host_stat.st_atime); | |
2948 | SLW (buf+28, host_stat.st_mtime); | |
2949 | SLW (buf+36, host_stat.st_ctime); | |
2950 | } | |
8918b3a7 MM |
2951 | trace_input ("<stat>", OP_R2, OP_R3, OP_VOID); |
2952 | trace_output (OP_R2); | |
63a91cfb | 2953 | break; |
63a91cfb | 2954 | |
63a91cfb MM |
2955 | case SYS_chown: |
2956 | RETVAL = chown (MEMPTR (PARM1), PARM2, PARM3); | |
8918b3a7 MM |
2957 | trace_input ("<chown>", OP_R2, OP_R3, OP_R4); |
2958 | trace_output (OP_R2); | |
63a91cfb | 2959 | break; |
8918b3a7 | 2960 | |
63a91cfb MM |
2961 | case SYS_chmod: |
2962 | RETVAL = chmod (MEMPTR (PARM1), PARM2); | |
8918b3a7 MM |
2963 | trace_input ("<chmod>", OP_R2, OP_R3, OP_R4); |
2964 | trace_output (OP_R2); | |
63a91cfb | 2965 | break; |
8918b3a7 | 2966 | |
63a91cfb MM |
2967 | case SYS_utime: |
2968 | /* Cast the second argument to void *, to avoid type mismatch | |
2969 | if a prototype is present. */ | |
2970 | RETVAL = utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2)); | |
8918b3a7 MM |
2971 | trace_input ("<utime>", OP_R2, OP_R3, OP_R4); |
2972 | trace_output (OP_R2); | |
2973 | break; | |
2974 | ||
2975 | case SYS_time: | |
2976 | { | |
2977 | unsigned long ret = time (PARM1 ? MEMPTR (PARM1) : NULL); | |
2978 | RETVAL_HIGH = ret >> 16; | |
2979 | RETVAL_LOW = ret & 0xffff; | |
2980 | } | |
2981 | trace_input ("<time>", OP_R2, OP_R3, OP_R4); | |
2982 | trace_output (OP_R2R3); | |
63a91cfb | 2983 | break; |
8918b3a7 | 2984 | |
63a91cfb MM |
2985 | default: |
2986 | abort (); | |
2987 | } | |
65c0d7de | 2988 | RETERR = d10v_callback->get_errno(d10v_callback); |
63a91cfb MM |
2989 | break; |
2990 | } | |
2991 | ||
2992 | case 1: | |
2993 | /* Trap 1 prints a string */ | |
2994 | { | |
c422ecc7 | 2995 | char *fstr = dmem_addr(State.regs[2]); |
63a91cfb MM |
2996 | fputs (fstr, stdout); |
2997 | break; | |
2998 | } | |
2999 | ||
3000 | case 2: | |
3001 | /* Trap 2 calls printf */ | |
3002 | { | |
c422ecc7 | 3003 | char *fstr = dmem_addr(State.regs[2]); |
7eebfc62 MM |
3004 | (*d10v_callback->printf_filtered) (d10v_callback, fstr, |
3005 | (int16)State.regs[3], | |
3006 | (int16)State.regs[4], | |
3007 | (int16)State.regs[5]); | |
fd435e9f | 3008 | (*d10v_callback->flush_stdout) (d10v_callback); |
63a91cfb MM |
3009 | break; |
3010 | } | |
3011 | ||
3012 | case 3: | |
3013 | /* Trap 3 writes a character */ | |
3014 | putchar (State.regs[2]); | |
3015 | break; | |
19d44375 | 3016 | } |
2934d1c9 MH |
3017 | } |
3018 | } | |
3019 | ||
3020 | /* tst0i */ | |
3021 | void | |
3022 | OP_7000000 () | |
3023 | { | |
87178dbd | 3024 | trace_input ("tst0i", OP_REG, OP_CONSTANT16, OP_VOID); |
4c38885c | 3025 | State.F1 = State.F0; |
4f425a32 | 3026 | State.F0 = (State.regs[OP[0]] & OP[1]) ? 1 : 0; |
87178dbd | 3027 | trace_output (OP_FLAG); |
2934d1c9 MH |
3028 | } |
3029 | ||
3030 | /* tst1i */ | |
3031 | void | |
3032 | OP_F000000 () | |
3033 | { | |
87178dbd | 3034 | trace_input ("tst1i", OP_REG, OP_CONSTANT16, OP_VOID); |
4c38885c | 3035 | State.F1 = State.F0; |
4f425a32 | 3036 | State.F0 = (~(State.regs[OP[0]]) & OP[1]) ? 1 : 0; |
87178dbd | 3037 | trace_output (OP_FLAG); |
2934d1c9 MH |
3038 | } |
3039 | ||
3040 | /* wait */ | |
3041 | void | |
3042 | OP_5F80 () | |
3043 | { | |
87178dbd | 3044 | trace_input ("wait", OP_VOID, OP_VOID, OP_VOID); |
4c38885c | 3045 | State.IE = 1; |
87178dbd | 3046 | trace_output (OP_VOID); |
2934d1c9 MH |
3047 | } |
3048 | ||
3049 | /* xor */ | |
3050 | void | |
3051 | OP_A00 () | |
3052 | { | |
87178dbd | 3053 | trace_input ("xor", OP_REG, OP_REG, OP_VOID); |
4c38885c | 3054 | State.regs[OP[0]] ^= State.regs[OP[1]]; |
87178dbd | 3055 | trace_output (OP_REG); |
2934d1c9 MH |
3056 | } |
3057 | ||
3058 | /* xor3 */ | |
3059 | void | |
3060 | OP_5000000 () | |
3061 | { | |
87178dbd | 3062 | trace_input ("xor3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16); |
4c38885c | 3063 | State.regs[OP[0]] = State.regs[OP[1]] ^ OP[2]; |
87178dbd | 3064 | trace_output (OP_REG); |
2934d1c9 MH |
3065 | } |
3066 |