Commit | Line | Data |
---|---|---|
fd435e9f MM |
1 | #include "config.h" |
2 | ||
4f425a32 | 3 | #include <signal.h> |
63a91cfb MM |
4 | #include <errno.h> |
5 | #include <sys/types.h> | |
6 | #include <sys/stat.h> | |
fd435e9f | 7 | #ifdef HAVE_UNISTD_H |
63a91cfb | 8 | #include <unistd.h> |
fd435e9f | 9 | #endif |
63a91cfb | 10 | |
2934d1c9 MH |
11 | #include "d10v_sim.h" |
12 | #include "simops.h" | |
8719be26 | 13 | #include "sys/syscall.h" |
2934d1c9 | 14 | |
c422ecc7 MH |
15 | extern char *strrchr (); |
16 | ||
87178dbd MM |
17 | enum op_types { |
18 | OP_VOID, | |
19 | OP_REG, | |
20 | OP_REG_OUTPUT, | |
21 | OP_DREG, | |
22 | OP_DREG_OUTPUT, | |
23 | OP_ACCUM, | |
24 | OP_ACCUM_OUTPUT, | |
25 | OP_ACCUM_REVERSE, | |
26 | OP_CR, | |
27 | OP_CR_OUTPUT, | |
28 | OP_CR_REVERSE, | |
29 | OP_FLAG, | |
60fc5b72 | 30 | OP_FLAG_OUTPUT, |
87178dbd | 31 | OP_CONSTANT16, |
a18cb100 | 32 | OP_CONSTANT8, |
87178dbd MM |
33 | OP_CONSTANT3, |
34 | OP_CONSTANT4, | |
35 | OP_MEMREF, | |
36 | OP_MEMREF2, | |
37 | OP_POSTDEC, | |
38 | OP_POSTINC, | |
a18cb100 MM |
39 | OP_PREDEC, |
40 | OP_R2, | |
8918b3a7 MM |
41 | OP_R3, |
42 | OP_R4, | |
43 | OP_R2R3 | |
87178dbd MM |
44 | }; |
45 | ||
7eebfc62 | 46 | #ifdef DEBUG |
a49a15ad MM |
47 | static void trace_input_func PARAMS ((char *name, |
48 | enum op_types in1, | |
49 | enum op_types in2, | |
50 | enum op_types in3)); | |
87178dbd | 51 | |
a49a15ad MM |
52 | #define trace_input(name, in1, in2, in3) do { if (d10v_debug) trace_input_func (name, in1, in2, in3); } while (0) |
53 | ||
54 | static void trace_output_func PARAMS ((enum op_types result)); | |
55 | ||
56 | #define trace_output(result) do { if (d10v_debug) trace_output_func (result); } while (0) | |
57 | ||
87178dbd | 58 | #ifndef SIZE_INSTRUCTION |
a49a15ad | 59 | #define SIZE_INSTRUCTION 8 |
87178dbd MM |
60 | #endif |
61 | ||
62 | #ifndef SIZE_OPERANDS | |
a49a15ad | 63 | #define SIZE_OPERANDS 18 |
87178dbd MM |
64 | #endif |
65 | ||
66 | #ifndef SIZE_VALUES | |
67 | #define SIZE_VALUES 13 | |
68 | #endif | |
69 | ||
a49a15ad MM |
70 | #ifndef SIZE_LOCATION |
71 | #define SIZE_LOCATION 20 | |
72 | #endif | |
73 | ||
891513ee MM |
74 | #ifndef SIZE_PC |
75 | #define SIZE_PC 6 | |
76 | #endif | |
77 | ||
78 | #ifndef SIZE_LINE_NUMBER | |
79 | #define SIZE_LINE_NUMBER 4 | |
80 | #endif | |
81 | ||
87178dbd | 82 | static void |
a49a15ad | 83 | trace_input_func (name, in1, in2, in3) |
87178dbd MM |
84 | char *name; |
85 | enum op_types in1; | |
86 | enum op_types in2; | |
87 | enum op_types in3; | |
88 | { | |
89 | char *comma; | |
90 | enum op_types in[3]; | |
91 | int i; | |
a49a15ad | 92 | char buf[1024]; |
87178dbd MM |
93 | char *p; |
94 | long tmp; | |
95 | char *type; | |
a49a15ad MM |
96 | const char *filename; |
97 | const char *functionname; | |
98 | unsigned int linenumber; | |
99 | bfd_vma byte_pc; | |
87178dbd | 100 | |
7eebfc62 MM |
101 | if ((d10v_debug & DEBUG_TRACE) == 0) |
102 | return; | |
103 | ||
87178dbd MM |
104 | switch (State.ins_type) |
105 | { | |
106 | default: | |
107 | case INS_UNKNOWN: type = " ?"; break; | |
108 | case INS_LEFT: type = " L"; break; | |
109 | case INS_RIGHT: type = " R"; break; | |
110 | case INS_LEFT_PARALLEL: type = "*L"; break; | |
111 | case INS_RIGHT_PARALLEL: type = "*R"; break; | |
c422ecc7 MH |
112 | case INS_LEFT_COND_TEST: type = "?L"; break; |
113 | case INS_RIGHT_COND_TEST: type = "?R"; break; | |
114 | case INS_LEFT_COND_EXE: type = "&L"; break; | |
115 | case INS_RIGHT_COND_EXE: type = "&R"; break; | |
87178dbd MM |
116 | case INS_LONG: type = " B"; break; |
117 | } | |
118 | ||
a49a15ad MM |
119 | if ((d10v_debug & DEBUG_LINE_NUMBER) == 0) |
120 | (*d10v_callback->printf_filtered) (d10v_callback, | |
f061ddf6 | 121 | "0x%.*x %s: %-*s ", |
891513ee MM |
122 | SIZE_PC, (unsigned)PC, |
123 | type, | |
a49a15ad MM |
124 | SIZE_INSTRUCTION, name); |
125 | ||
126 | else | |
127 | { | |
891513ee | 128 | buf[0] = '\0'; |
b30cdd35 | 129 | byte_pc = decode_pc (); |
a49a15ad MM |
130 | if (text && byte_pc >= text_start && byte_pc < text_end) |
131 | { | |
132 | filename = (const char *)0; | |
133 | functionname = (const char *)0; | |
134 | linenumber = 0; | |
b83093ff | 135 | if (bfd_find_nearest_line (prog_bfd, text, (struct symbol_cache_entry **)0, byte_pc - text_start, |
a49a15ad MM |
136 | &filename, &functionname, &linenumber)) |
137 | { | |
138 | p = buf; | |
139 | if (linenumber) | |
140 | { | |
891513ee | 141 | sprintf (p, "#%-*d ", SIZE_LINE_NUMBER, linenumber); |
a49a15ad MM |
142 | p += strlen (p); |
143 | } | |
891513ee MM |
144 | else |
145 | { | |
146 | sprintf (p, "%-*s ", SIZE_LINE_NUMBER+1, "---"); | |
147 | p += SIZE_LINE_NUMBER+2; | |
148 | } | |
a49a15ad MM |
149 | |
150 | if (functionname) | |
151 | { | |
152 | sprintf (p, "%s ", functionname); | |
153 | p += strlen (p); | |
154 | } | |
155 | else if (filename) | |
156 | { | |
c422ecc7 | 157 | char *q = strrchr (filename, '/'); |
a49a15ad MM |
158 | sprintf (p, "%s ", (q) ? q+1 : filename); |
159 | p += strlen (p); | |
160 | } | |
161 | ||
162 | if (*p == ' ') | |
163 | *p = '\0'; | |
164 | } | |
165 | } | |
166 | ||
167 | (*d10v_callback->printf_filtered) (d10v_callback, | |
f061ddf6 | 168 | "0x%.*x %s: %-*.*s %-*s ", |
891513ee MM |
169 | SIZE_PC, (unsigned)PC, |
170 | type, | |
a49a15ad MM |
171 | SIZE_LOCATION, SIZE_LOCATION, buf, |
172 | SIZE_INSTRUCTION, name); | |
173 | } | |
87178dbd MM |
174 | |
175 | in[0] = in1; | |
176 | in[1] = in2; | |
177 | in[2] = in3; | |
178 | comma = ""; | |
179 | p = buf; | |
180 | for (i = 0; i < 3; i++) | |
181 | { | |
182 | switch (in[i]) | |
183 | { | |
184 | case OP_VOID: | |
a18cb100 MM |
185 | case OP_R2: |
186 | case OP_R3: | |
8918b3a7 | 187 | case OP_R4: |
c422ecc7 | 188 | case OP_R2R3: |
87178dbd MM |
189 | break; |
190 | ||
191 | case OP_REG: | |
192 | case OP_REG_OUTPUT: | |
193 | case OP_DREG: | |
194 | case OP_DREG_OUTPUT: | |
195 | sprintf (p, "%sr%d", comma, OP[i]); | |
196 | p += strlen (p); | |
197 | comma = ","; | |
198 | break; | |
199 | ||
200 | case OP_CR: | |
201 | case OP_CR_OUTPUT: | |
202 | case OP_CR_REVERSE: | |
203 | sprintf (p, "%scr%d", comma, OP[i]); | |
204 | p += strlen (p); | |
205 | comma = ","; | |
206 | break; | |
207 | ||
208 | case OP_ACCUM: | |
209 | case OP_ACCUM_OUTPUT: | |
210 | case OP_ACCUM_REVERSE: | |
211 | sprintf (p, "%sa%d", comma, OP[i]); | |
212 | p += strlen (p); | |
213 | comma = ","; | |
214 | break; | |
215 | ||
216 | case OP_CONSTANT16: | |
217 | sprintf (p, "%s%d", comma, OP[i]); | |
218 | p += strlen (p); | |
219 | comma = ","; | |
220 | break; | |
221 | ||
a18cb100 MM |
222 | case OP_CONSTANT8: |
223 | sprintf (p, "%s%d", comma, SEXT8(OP[i])); | |
224 | p += strlen (p); | |
225 | comma = ","; | |
226 | break; | |
227 | ||
87178dbd MM |
228 | case OP_CONSTANT4: |
229 | sprintf (p, "%s%d", comma, SEXT4(OP[i])); | |
230 | p += strlen (p); | |
231 | comma = ","; | |
232 | break; | |
233 | ||
234 | case OP_CONSTANT3: | |
235 | sprintf (p, "%s%d", comma, SEXT3(OP[i])); | |
236 | p += strlen (p); | |
237 | comma = ","; | |
238 | break; | |
239 | ||
240 | case OP_MEMREF: | |
241 | sprintf (p, "%s@r%d", comma, OP[i]); | |
242 | p += strlen (p); | |
243 | comma = ","; | |
244 | break; | |
245 | ||
246 | case OP_MEMREF2: | |
247 | sprintf (p, "%s@(%d,r%d)", comma, (int16)OP[i], OP[i+1]); | |
248 | p += strlen (p); | |
249 | comma = ","; | |
250 | break; | |
251 | ||
252 | case OP_POSTINC: | |
253 | sprintf (p, "%s@r%d+", comma, OP[i]); | |
254 | p += strlen (p); | |
255 | comma = ","; | |
256 | break; | |
257 | ||
258 | case OP_POSTDEC: | |
259 | sprintf (p, "%s@r%d-", comma, OP[i]); | |
260 | p += strlen (p); | |
261 | comma = ","; | |
262 | break; | |
263 | ||
264 | case OP_PREDEC: | |
265 | sprintf (p, "%s@-r%d", comma, OP[i]); | |
266 | p += strlen (p); | |
267 | comma = ","; | |
268 | break; | |
269 | ||
270 | case OP_FLAG: | |
60fc5b72 | 271 | case OP_FLAG_OUTPUT: |
87178dbd MM |
272 | if (OP[i] == 0) |
273 | sprintf (p, "%sf0", comma); | |
274 | ||
275 | else if (OP[i] == 1) | |
276 | sprintf (p, "%sf1", comma); | |
277 | ||
278 | else | |
60fc5b72 | 279 | sprintf (p, "%sc", comma); |
87178dbd MM |
280 | |
281 | p += strlen (p); | |
282 | comma = ","; | |
283 | break; | |
284 | } | |
285 | } | |
286 | ||
7eebfc62 MM |
287 | if ((d10v_debug & DEBUG_VALUES) == 0) |
288 | { | |
289 | *p++ = '\n'; | |
290 | *p = '\0'; | |
291 | (*d10v_callback->printf_filtered) (d10v_callback, "%s", buf); | |
292 | } | |
293 | else | |
294 | { | |
295 | *p = '\0'; | |
296 | (*d10v_callback->printf_filtered) (d10v_callback, "%-*s", SIZE_OPERANDS, buf); | |
87178dbd | 297 | |
7eebfc62 MM |
298 | p = buf; |
299 | for (i = 0; i < 3; i++) | |
300 | { | |
301 | buf[0] = '\0'; | |
302 | switch (in[i]) | |
303 | { | |
304 | case OP_VOID: | |
305 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, ""); | |
306 | break; | |
307 | ||
308 | case OP_REG_OUTPUT: | |
309 | case OP_DREG_OUTPUT: | |
310 | case OP_CR_OUTPUT: | |
311 | case OP_ACCUM_OUTPUT: | |
60fc5b72 | 312 | case OP_FLAG_OUTPUT: |
7eebfc62 MM |
313 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "---"); |
314 | break; | |
315 | ||
316 | case OP_REG: | |
317 | case OP_MEMREF: | |
318 | case OP_POSTDEC: | |
319 | case OP_POSTINC: | |
320 | case OP_PREDEC: | |
321 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", | |
322 | (uint16)State.regs[OP[i]]); | |
323 | break; | |
324 | ||
325 | case OP_DREG: | |
326 | tmp = (long)((((uint32) State.regs[OP[i]]) << 16) | ((uint32) State.regs[OP[i]+1])); | |
327 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.8lx", SIZE_VALUES-10, "", tmp); | |
328 | break; | |
329 | ||
330 | case OP_CR: | |
331 | case OP_CR_REVERSE: | |
332 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", | |
333 | (uint16)State.cregs[OP[i]]); | |
334 | break; | |
335 | ||
336 | case OP_ACCUM: | |
337 | case OP_ACCUM_REVERSE: | |
338 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.2x%.8lx", SIZE_VALUES-12, "", | |
339 | ((int)(State.a[OP[i]] >> 32) & 0xff), | |
340 | ((unsigned long)State.a[OP[i]]) & 0xffffffff); | |
341 | break; | |
342 | ||
343 | case OP_CONSTANT16: | |
344 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", | |
345 | (uint16)OP[i]); | |
346 | break; | |
347 | ||
348 | case OP_CONSTANT4: | |
349 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", | |
350 | (uint16)SEXT4(OP[i])); | |
351 | break; | |
352 | ||
a18cb100 MM |
353 | case OP_CONSTANT8: |
354 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", | |
355 | (uint16)SEXT8(OP[i])); | |
356 | break; | |
357 | ||
7eebfc62 MM |
358 | case OP_CONSTANT3: |
359 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", | |
360 | (uint16)SEXT3(OP[i])); | |
361 | break; | |
362 | ||
363 | case OP_FLAG: | |
364 | if (OP[i] == 0) | |
365 | (*d10v_callback->printf_filtered) (d10v_callback, "%*sF0 = %d", SIZE_VALUES-6, "", | |
366 | State.F0 != 0); | |
367 | ||
368 | else if (OP[i] == 1) | |
369 | (*d10v_callback->printf_filtered) (d10v_callback, "%*sF1 = %d", SIZE_VALUES-6, "", | |
370 | State.F1 != 0); | |
371 | ||
372 | else | |
373 | (*d10v_callback->printf_filtered) (d10v_callback, "%*sC = %d", SIZE_VALUES-5, "", | |
374 | State.C != 0); | |
375 | ||
376 | break; | |
377 | ||
378 | case OP_MEMREF2: | |
379 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", | |
380 | (uint16)OP[i]); | |
381 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", | |
382 | (uint16)State.regs[OP[++i]]); | |
383 | break; | |
a18cb100 MM |
384 | |
385 | case OP_R2: | |
386 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", | |
387 | (uint16)State.regs[2]); | |
388 | break; | |
389 | ||
390 | case OP_R3: | |
391 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", | |
392 | (uint16)State.regs[3]); | |
393 | break; | |
8918b3a7 MM |
394 | |
395 | case OP_R4: | |
396 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", | |
397 | (uint16)State.regs[4]); | |
398 | break; | |
c422ecc7 MH |
399 | |
400 | case OP_R2R3: | |
401 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", | |
402 | (uint16)State.regs[2]); | |
403 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", | |
404 | (uint16)State.regs[3]); | |
405 | i++; | |
406 | break; | |
7eebfc62 MM |
407 | } |
408 | } | |
409 | } | |
fd435e9f MM |
410 | |
411 | (*d10v_callback->flush_stdout) (d10v_callback); | |
7eebfc62 | 412 | } |
87178dbd | 413 | |
7eebfc62 | 414 | static void |
a49a15ad | 415 | trace_output_func (result) |
7eebfc62 MM |
416 | enum op_types result; |
417 | { | |
418 | if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES)) | |
87178dbd | 419 | { |
7eebfc62 | 420 | long tmp; |
87178dbd | 421 | |
7eebfc62 MM |
422 | switch (result) |
423 | { | |
424 | default: | |
425 | putchar ('\n'); | |
87178dbd MM |
426 | break; |
427 | ||
428 | case OP_REG: | |
7eebfc62 MM |
429 | case OP_REG_OUTPUT: |
430 | (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "", | |
431 | (uint16)State.regs[OP[0]], | |
432 | State.F0 != 0, State.F1 != 0, State.C != 0); | |
87178dbd MM |
433 | break; |
434 | ||
435 | case OP_DREG: | |
7eebfc62 MM |
436 | case OP_DREG_OUTPUT: |
437 | tmp = (long)((((uint32) State.regs[OP[0]]) << 16) | ((uint32) State.regs[OP[0]+1])); | |
438 | (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-10, "", tmp, | |
439 | State.F0 != 0, State.F1 != 0, State.C != 0); | |
87178dbd MM |
440 | break; |
441 | ||
442 | case OP_CR: | |
7eebfc62 MM |
443 | case OP_CR_OUTPUT: |
444 | (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "", | |
445 | (uint16)State.cregs[OP[0]], | |
446 | State.F0 != 0, State.F1 != 0, State.C != 0); | |
87178dbd MM |
447 | break; |
448 | ||
7eebfc62 MM |
449 | case OP_CR_REVERSE: |
450 | (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "", | |
451 | (uint16)State.cregs[OP[1]], | |
452 | State.F0 != 0, State.F1 != 0, State.C != 0); | |
87178dbd MM |
453 | break; |
454 | ||
7eebfc62 MM |
455 | case OP_ACCUM: |
456 | case OP_ACCUM_OUTPUT: | |
069398aa | 457 | (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-12, "", |
7eebfc62 MM |
458 | ((int)(State.a[OP[0]] >> 32) & 0xff), |
459 | ((unsigned long)State.a[OP[0]]) & 0xffffffff, | |
460 | State.F0 != 0, State.F1 != 0, State.C != 0); | |
87178dbd MM |
461 | break; |
462 | ||
7eebfc62 | 463 | case OP_ACCUM_REVERSE: |
069398aa | 464 | (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-12, "", |
7eebfc62 MM |
465 | ((int)(State.a[OP[1]] >> 32) & 0xff), |
466 | ((unsigned long)State.a[OP[1]]) & 0xffffffff, | |
467 | State.F0 != 0, State.F1 != 0, State.C != 0); | |
87178dbd MM |
468 | break; |
469 | ||
470 | case OP_FLAG: | |
60fc5b72 | 471 | case OP_FLAG_OUTPUT: |
7eebfc62 MM |
472 | (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s F0=%d F1=%d C=%d\n", SIZE_VALUES, "", |
473 | State.F0 != 0, State.F1 != 0, State.C != 0); | |
87178dbd | 474 | break; |
8918b3a7 MM |
475 | |
476 | case OP_R2: | |
477 | (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "", | |
478 | (uint16)State.regs[2], | |
479 | State.F0 != 0, State.F1 != 0, State.C != 0); | |
480 | break; | |
481 | ||
482 | case OP_R2R3: | |
483 | (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-10, "", | |
484 | (uint16)State.regs[2], (uint16)State.regs[3], | |
485 | State.F0 != 0, State.F1 != 0, State.C != 0); | |
486 | break; | |
87178dbd MM |
487 | } |
488 | } | |
fd435e9f MM |
489 | |
490 | (*d10v_callback->flush_stdout) (d10v_callback); | |
87178dbd MM |
491 | } |
492 | ||
493 | #else | |
494 | #define trace_input(NAME, IN1, IN2, IN3) | |
495 | #define trace_output(RESULT) | |
496 | #endif | |
2934d1c9 MH |
497 | |
498 | /* abs */ | |
499 | void | |
500 | OP_4607 () | |
501 | { | |
87178dbd | 502 | trace_input ("abs", OP_REG, OP_VOID, OP_VOID); |
2934d1c9 MH |
503 | State.F1 = State.F0; |
504 | if ((int16)(State.regs[OP[0]]) < 0) | |
505 | { | |
506 | State.regs[OP[0]] = -(int16)(State.regs[OP[0]]); | |
507 | State.F0 = 1; | |
508 | } | |
509 | else | |
510 | State.F0 = 0; | |
87178dbd | 511 | trace_output (OP_REG); |
2934d1c9 MH |
512 | } |
513 | ||
514 | /* abs */ | |
515 | void | |
516 | OP_5607 () | |
517 | { | |
518 | int64 tmp; | |
519 | ||
87178dbd | 520 | trace_input ("abs", OP_ACCUM, OP_VOID, OP_VOID); |
4f425a32 MH |
521 | State.F1 = State.F0; |
522 | State.a[OP[0]] = SEXT40(State.a[OP[0]]); | |
523 | ||
4c38885c | 524 | if (State.a[OP[0]] < 0 ) |
2934d1c9 | 525 | { |
4c38885c | 526 | tmp = -State.a[OP[0]]; |
2934d1c9 MH |
527 | if (State.ST) |
528 | { | |
4c38885c | 529 | if (tmp > MAX32) |
2934d1c9 | 530 | State.a[OP[0]] = MAX32; |
4c38885c | 531 | else if (tmp < MIN32) |
2934d1c9 MH |
532 | State.a[OP[0]] = MIN32; |
533 | else | |
4f425a32 | 534 | State.a[OP[0]] = tmp & MASK40; |
2934d1c9 MH |
535 | } |
536 | else | |
4f425a32 | 537 | State.a[OP[0]] = tmp & MASK40; |
2934d1c9 MH |
538 | State.F0 = 1; |
539 | } | |
540 | else | |
541 | State.F0 = 0; | |
87178dbd | 542 | trace_output (OP_ACCUM); |
2934d1c9 MH |
543 | } |
544 | ||
545 | /* add */ | |
546 | void | |
547 | OP_200 () | |
548 | { | |
549 | uint16 tmp = State.regs[OP[0]]; | |
87178dbd | 550 | trace_input ("add", OP_REG, OP_REG, OP_VOID); |
2934d1c9 MH |
551 | State.regs[OP[0]] += State.regs[OP[1]]; |
552 | if ( tmp > State.regs[OP[0]]) | |
553 | State.C = 1; | |
554 | else | |
555 | State.C = 0; | |
87178dbd | 556 | trace_output (OP_REG); |
2934d1c9 MH |
557 | } |
558 | ||
559 | /* add */ | |
560 | void | |
561 | OP_1201 () | |
562 | { | |
4c38885c | 563 | int64 tmp; |
4f425a32 | 564 | tmp = SEXT40(State.a[OP[0]]) + (SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]); |
87178dbd MM |
565 | |
566 | trace_input ("add", OP_ACCUM, OP_REG, OP_VOID); | |
4c38885c MH |
567 | if (State.ST) |
568 | { | |
569 | if ( tmp > MAX32) | |
570 | State.a[OP[0]] = MAX32; | |
571 | else if ( tmp < MIN32) | |
572 | State.a[OP[0]] = MIN32; | |
573 | else | |
4f425a32 | 574 | State.a[OP[0]] = tmp & MASK40; |
4c38885c MH |
575 | } |
576 | else | |
4f425a32 | 577 | State.a[OP[0]] = tmp & MASK40; |
87178dbd | 578 | trace_output (OP_ACCUM); |
2934d1c9 MH |
579 | } |
580 | ||
581 | /* add */ | |
582 | void | |
583 | OP_1203 () | |
584 | { | |
4c38885c | 585 | int64 tmp; |
4f425a32 | 586 | tmp = SEXT40(State.a[OP[0]]) + SEXT40(State.a[OP[1]]); |
87178dbd MM |
587 | |
588 | trace_input ("add", OP_ACCUM, OP_ACCUM, OP_VOID); | |
4c38885c MH |
589 | if (State.ST) |
590 | { | |
591 | if (tmp > MAX32) | |
592 | State.a[OP[0]] = MAX32; | |
593 | else if ( tmp < MIN32) | |
594 | State.a[OP[0]] = MIN32; | |
595 | else | |
4f425a32 | 596 | State.a[OP[0]] = tmp & MASK40; |
4c38885c MH |
597 | } |
598 | else | |
4f425a32 | 599 | State.a[OP[0]] = tmp & MASK40; |
87178dbd | 600 | trace_output (OP_ACCUM); |
2934d1c9 MH |
601 | } |
602 | ||
603 | /* add2w */ | |
604 | void | |
605 | OP_1200 () | |
606 | { | |
607 | uint32 tmp; | |
f4b022d3 MM |
608 | uint32 a = (State.regs[OP[0]]) << 16 | State.regs[OP[0]+1]; |
609 | uint32 b = (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]; | |
87178dbd MM |
610 | |
611 | trace_input ("add2w", OP_DREG, OP_DREG, OP_VOID); | |
f4b022d3 MM |
612 | tmp = a + b; |
613 | State.C = (tmp < a); | |
2934d1c9 MH |
614 | State.regs[OP[0]] = tmp >> 16; |
615 | State.regs[OP[0]+1] = tmp & 0xFFFF; | |
87178dbd | 616 | trace_output (OP_DREG); |
2934d1c9 MH |
617 | } |
618 | ||
619 | /* add3 */ | |
620 | void | |
621 | OP_1000000 () | |
622 | { | |
f4b022d3 MM |
623 | uint16 tmp = State.regs[OP[1]]; |
624 | State.regs[OP[0]] = tmp + OP[2]; | |
87178dbd MM |
625 | |
626 | trace_input ("add3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16); | |
f4b022d3 | 627 | State.C = (State.regs[OP[0]] < tmp); |
87178dbd | 628 | trace_output (OP_REG); |
2934d1c9 MH |
629 | } |
630 | ||
631 | /* addac3 */ | |
632 | void | |
633 | OP_17000200 () | |
634 | { | |
4c38885c | 635 | int64 tmp; |
4f425a32 | 636 | tmp = SEXT40(State.a[OP[2]]) + SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]); |
87178dbd MM |
637 | |
638 | trace_input ("addac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM); | |
4c38885c MH |
639 | State.regs[OP[0]] = (tmp >> 16) & 0xffff; |
640 | State.regs[OP[0]+1] = tmp & 0xffff; | |
87178dbd | 641 | trace_output (OP_DREG); |
2934d1c9 MH |
642 | } |
643 | ||
644 | /* addac3 */ | |
645 | void | |
646 | OP_17000202 () | |
647 | { | |
4c38885c | 648 | int64 tmp; |
4f425a32 | 649 | tmp = SEXT40(State.a[OP[1]]) + SEXT40(State.a[OP[2]]); |
87178dbd MM |
650 | |
651 | trace_input ("addac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM); | |
4c38885c MH |
652 | State.regs[OP[0]] = (tmp >> 16) & 0xffff; |
653 | State.regs[OP[0]+1] = tmp & 0xffff; | |
87178dbd | 654 | trace_output (OP_DREG); |
2934d1c9 MH |
655 | } |
656 | ||
657 | /* addac3s */ | |
658 | void | |
659 | OP_17001200 () | |
660 | { | |
4c38885c | 661 | int64 tmp; |
4c38885c | 662 | State.F1 = State.F0; |
87178dbd MM |
663 | |
664 | trace_input ("addac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM); | |
4f425a32 | 665 | tmp = SEXT40(State.a[OP[2]]) + SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]); |
4c38885c MH |
666 | if ( tmp > MAX32) |
667 | { | |
668 | State.regs[OP[0]] = 0x7fff; | |
669 | State.regs[OP[0]+1] = 0xffff; | |
670 | State.F0 = 1; | |
671 | } | |
672 | else if (tmp < MIN32) | |
673 | { | |
674 | State.regs[OP[0]] = 0x8000; | |
675 | State.regs[OP[0]+1] = 0; | |
676 | State.F0 = 1; | |
677 | } | |
678 | else | |
679 | { | |
680 | State.regs[OP[0]] = (tmp >> 16) & 0xffff; | |
681 | State.regs[OP[0]+1] = tmp & 0xffff; | |
682 | State.F0 = 0; | |
683 | } | |
87178dbd | 684 | trace_output (OP_DREG); |
2934d1c9 MH |
685 | } |
686 | ||
687 | /* addac3s */ | |
688 | void | |
689 | OP_17001202 () | |
690 | { | |
4c38885c | 691 | int64 tmp; |
4c38885c | 692 | State.F1 = State.F0; |
87178dbd MM |
693 | |
694 | trace_input ("addac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM); | |
4f425a32 | 695 | tmp = SEXT40(State.a[OP[1]]) + SEXT40(State.a[OP[2]]); |
4c38885c MH |
696 | if ( tmp > MAX32) |
697 | { | |
698 | State.regs[OP[0]] = 0x7fff; | |
699 | State.regs[OP[0]+1] = 0xffff; | |
700 | State.F0 = 1; | |
701 | } | |
702 | else if (tmp < MIN32) | |
703 | { | |
704 | State.regs[OP[0]] = 0x8000; | |
705 | State.regs[OP[0]+1] = 0; | |
706 | State.F0 = 1; | |
707 | } | |
708 | else | |
709 | { | |
710 | State.regs[OP[0]] = (tmp >> 16) & 0xffff; | |
711 | State.regs[OP[0]+1] = tmp & 0xffff; | |
712 | State.F0 = 0; | |
713 | } | |
87178dbd | 714 | trace_output (OP_DREG); |
2934d1c9 MH |
715 | } |
716 | ||
717 | /* addi */ | |
718 | void | |
719 | OP_201 () | |
720 | { | |
2254cd90 | 721 | uint tmp = State.regs[OP[0]]; |
4f425a32 MH |
722 | if (OP[1] == 0) |
723 | OP[1] = 16; | |
f4b022d3 | 724 | |
87178dbd | 725 | trace_input ("addi", OP_REG, OP_CONSTANT16, OP_VOID); |
2934d1c9 | 726 | State.regs[OP[0]] += OP[1]; |
f4b022d3 | 727 | State.C = (State.regs[OP[0]] < tmp); |
87178dbd | 728 | trace_output (OP_REG); |
2934d1c9 MH |
729 | } |
730 | ||
731 | /* and */ | |
732 | void | |
733 | OP_C00 () | |
734 | { | |
87178dbd | 735 | trace_input ("and", OP_REG, OP_REG, OP_VOID); |
2934d1c9 | 736 | State.regs[OP[0]] &= State.regs[OP[1]]; |
87178dbd | 737 | trace_output (OP_REG); |
2934d1c9 MH |
738 | } |
739 | ||
740 | /* and3 */ | |
741 | void | |
742 | OP_6000000 () | |
743 | { | |
87178dbd | 744 | trace_input ("and3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16); |
2934d1c9 | 745 | State.regs[OP[0]] = State.regs[OP[1]] & OP[2]; |
87178dbd | 746 | trace_output (OP_REG); |
2934d1c9 MH |
747 | } |
748 | ||
749 | /* bclri */ | |
750 | void | |
751 | OP_C01 () | |
752 | { | |
87178dbd | 753 | trace_input ("bclri", OP_REG, OP_CONSTANT16, OP_VOID); |
2934d1c9 | 754 | State.regs[OP[0]] &= ~(0x8000 >> OP[1]); |
87178dbd | 755 | trace_output (OP_REG); |
2934d1c9 MH |
756 | } |
757 | ||
758 | /* bl.s */ | |
759 | void | |
760 | OP_4900 () | |
761 | { | |
a18cb100 | 762 | trace_input ("bl.s", OP_CONSTANT8, OP_R2, OP_R3); |
2934d1c9 | 763 | State.regs[13] = PC+1; |
fd435e9f | 764 | JMP( PC + SEXT8 (OP[0])); |
87178dbd | 765 | trace_output (OP_VOID); |
2934d1c9 MH |
766 | } |
767 | ||
768 | /* bl.l */ | |
769 | void | |
770 | OP_24800000 () | |
771 | { | |
a18cb100 | 772 | trace_input ("bl.l", OP_CONSTANT16, OP_R2, OP_R3); |
2934d1c9 | 773 | State.regs[13] = PC+1; |
fd435e9f | 774 | JMP (PC + OP[0]); |
87178dbd | 775 | trace_output (OP_VOID); |
2934d1c9 MH |
776 | } |
777 | ||
778 | /* bnoti */ | |
779 | void | |
780 | OP_A01 () | |
781 | { | |
87178dbd | 782 | trace_input ("bnoti", OP_REG, OP_CONSTANT16, OP_VOID); |
2934d1c9 | 783 | State.regs[OP[0]] ^= 0x8000 >> OP[1]; |
87178dbd | 784 | trace_output (OP_REG); |
2934d1c9 MH |
785 | } |
786 | ||
787 | /* bra.s */ | |
788 | void | |
789 | OP_4800 () | |
790 | { | |
a18cb100 | 791 | trace_input ("bra.s", OP_CONSTANT8, OP_VOID, OP_VOID); |
fd435e9f | 792 | JMP (PC + SEXT8 (OP[0])); |
87178dbd | 793 | trace_output (OP_VOID); |
2934d1c9 MH |
794 | } |
795 | ||
796 | /* bra.l */ | |
797 | void | |
798 | OP_24000000 () | |
799 | { | |
87178dbd | 800 | trace_input ("bra.l", OP_CONSTANT16, OP_VOID, OP_VOID); |
fd435e9f | 801 | JMP (PC + OP[0]); |
87178dbd | 802 | trace_output (OP_VOID); |
2934d1c9 MH |
803 | } |
804 | ||
805 | /* brf0f.s */ | |
806 | void | |
807 | OP_4A00 () | |
808 | { | |
a18cb100 | 809 | trace_input ("brf0f.s", OP_CONSTANT8, OP_VOID, OP_VOID); |
2934d1c9 | 810 | if (State.F0 == 0) |
fd435e9f | 811 | JMP (PC + SEXT8 (OP[0])); |
87178dbd | 812 | trace_output (OP_FLAG); |
2934d1c9 MH |
813 | } |
814 | ||
815 | /* brf0f.l */ | |
816 | void | |
817 | OP_25000000 () | |
818 | { | |
87178dbd | 819 | trace_input ("brf0f.l", OP_CONSTANT16, OP_VOID, OP_VOID); |
2934d1c9 | 820 | if (State.F0 == 0) |
fd435e9f | 821 | JMP (PC + OP[0]); |
87178dbd | 822 | trace_output (OP_FLAG); |
2934d1c9 MH |
823 | } |
824 | ||
825 | /* brf0t.s */ | |
826 | void | |
827 | OP_4B00 () | |
828 | { | |
a18cb100 | 829 | trace_input ("brf0t.s", OP_CONSTANT8, OP_VOID, OP_VOID); |
2934d1c9 | 830 | if (State.F0) |
fd435e9f | 831 | JMP (PC + SEXT8 (OP[0])); |
87178dbd | 832 | trace_output (OP_FLAG); |
2934d1c9 MH |
833 | } |
834 | ||
835 | /* brf0t.l */ | |
836 | void | |
837 | OP_25800000 () | |
838 | { | |
87178dbd | 839 | trace_input ("brf0t.l", OP_CONSTANT16, OP_VOID, OP_VOID); |
2934d1c9 | 840 | if (State.F0) |
fd435e9f | 841 | JMP (PC + OP[0]); |
87178dbd | 842 | trace_output (OP_FLAG); |
2934d1c9 MH |
843 | } |
844 | ||
845 | /* bseti */ | |
846 | void | |
847 | OP_801 () | |
848 | { | |
87178dbd | 849 | trace_input ("bseti", OP_REG, OP_CONSTANT16, OP_VOID); |
2934d1c9 | 850 | State.regs[OP[0]] |= 0x8000 >> OP[1]; |
87178dbd | 851 | trace_output (OP_REG); |
2934d1c9 MH |
852 | } |
853 | ||
854 | /* btsti */ | |
855 | void | |
856 | OP_E01 () | |
857 | { | |
87178dbd | 858 | trace_input ("btsti", OP_REG, OP_CONSTANT16, OP_VOID); |
2934d1c9 MH |
859 | State.F1 = State.F0; |
860 | State.F0 = (State.regs[OP[0]] & (0x8000 >> OP[1])) ? 1 : 0; | |
87178dbd | 861 | trace_output (OP_FLAG); |
2934d1c9 MH |
862 | } |
863 | ||
864 | /* clrac */ | |
865 | void | |
866 | OP_5601 () | |
867 | { | |
87178dbd | 868 | trace_input ("clrac", OP_ACCUM_OUTPUT, OP_VOID, OP_VOID); |
2934d1c9 | 869 | State.a[OP[0]] = 0; |
87178dbd | 870 | trace_output (OP_ACCUM); |
2934d1c9 MH |
871 | } |
872 | ||
873 | /* cmp */ | |
874 | void | |
875 | OP_600 () | |
876 | { | |
87178dbd | 877 | trace_input ("cmp", OP_REG, OP_REG, OP_VOID); |
2934d1c9 MH |
878 | State.F1 = State.F0; |
879 | State.F0 = ((int16)(State.regs[OP[0]]) < (int16)(State.regs[OP[1]])) ? 1 : 0; | |
87178dbd | 880 | trace_output (OP_FLAG); |
2934d1c9 MH |
881 | } |
882 | ||
883 | /* cmp */ | |
884 | void | |
885 | OP_1603 () | |
886 | { | |
87178dbd | 887 | trace_input ("cmp", OP_ACCUM, OP_ACCUM, OP_VOID); |
4c38885c | 888 | State.F1 = State.F0; |
4f425a32 | 889 | State.F0 = (SEXT40(State.a[OP[0]]) < SEXT40(State.a[OP[1]])) ? 1 : 0; |
87178dbd | 890 | trace_output (OP_FLAG); |
2934d1c9 MH |
891 | } |
892 | ||
893 | /* cmpeq */ | |
894 | void | |
895 | OP_400 () | |
896 | { | |
87178dbd | 897 | trace_input ("cmpeq", OP_REG, OP_REG, OP_VOID); |
2934d1c9 MH |
898 | State.F1 = State.F0; |
899 | State.F0 = (State.regs[OP[0]] == State.regs[OP[1]]) ? 1 : 0; | |
87178dbd | 900 | trace_output (OP_FLAG); |
2934d1c9 MH |
901 | } |
902 | ||
903 | /* cmpeq */ | |
904 | void | |
905 | OP_1403 () | |
906 | { | |
87178dbd | 907 | trace_input ("cmpeq", OP_ACCUM, OP_ACCUM, OP_VOID); |
4c38885c | 908 | State.F1 = State.F0; |
fd435e9f | 909 | State.F0 = ((State.a[OP[0]] & MASK40) == (State.a[OP[1]] & MASK40)) ? 1 : 0; |
87178dbd | 910 | trace_output (OP_FLAG); |
2934d1c9 MH |
911 | } |
912 | ||
913 | /* cmpeqi.s */ | |
914 | void | |
915 | OP_401 () | |
916 | { | |
c12f5c67 | 917 | trace_input ("cmpeqi.s", OP_REG, OP_CONSTANT4, OP_VOID); |
2934d1c9 | 918 | State.F1 = State.F0; |
c12f5c67 | 919 | State.F0 = (State.regs[OP[0]] == (reg_t)SEXT4(OP[1])) ? 1 : 0; |
87178dbd | 920 | trace_output (OP_FLAG); |
2934d1c9 MH |
921 | } |
922 | ||
923 | /* cmpeqi.l */ | |
924 | void | |
925 | OP_2000000 () | |
926 | { | |
87178dbd | 927 | trace_input ("cmpeqi.l", OP_REG, OP_CONSTANT16, OP_VOID); |
2934d1c9 | 928 | State.F1 = State.F0; |
c12f5c67 | 929 | State.F0 = (State.regs[OP[0]] == (reg_t)OP[1]) ? 1 : 0; |
87178dbd | 930 | trace_output (OP_FLAG); |
2934d1c9 MH |
931 | } |
932 | ||
933 | /* cmpi.s */ | |
934 | void | |
935 | OP_601 () | |
936 | { | |
87178dbd | 937 | trace_input ("cmpi.s", OP_REG, OP_CONSTANT4, OP_VOID); |
2934d1c9 | 938 | State.F1 = State.F0; |
c12f5c67 | 939 | State.F0 = ((int16)(State.regs[OP[0]]) < (int16)SEXT4(OP[1])) ? 1 : 0; |
87178dbd | 940 | trace_output (OP_FLAG); |
2934d1c9 MH |
941 | } |
942 | ||
943 | /* cmpi.l */ | |
944 | void | |
945 | OP_3000000 () | |
946 | { | |
87178dbd | 947 | trace_input ("cmpi.l", OP_REG, OP_CONSTANT16, OP_VOID); |
2934d1c9 MH |
948 | State.F1 = State.F0; |
949 | State.F0 = ((int16)(State.regs[OP[0]]) < (int16)(OP[1])) ? 1 : 0; | |
87178dbd | 950 | trace_output (OP_FLAG); |
2934d1c9 MH |
951 | } |
952 | ||
953 | /* cmpu */ | |
954 | void | |
955 | OP_4600 () | |
956 | { | |
87178dbd | 957 | trace_input ("cmpu", OP_REG, OP_REG, OP_VOID); |
2934d1c9 MH |
958 | State.F1 = State.F0; |
959 | State.F0 = (State.regs[OP[0]] < State.regs[OP[1]]) ? 1 : 0; | |
87178dbd | 960 | trace_output (OP_FLAG); |
2934d1c9 MH |
961 | } |
962 | ||
963 | /* cmpui */ | |
964 | void | |
965 | OP_23000000 () | |
966 | { | |
87178dbd | 967 | trace_input ("cmpui", OP_REG, OP_CONSTANT16, OP_VOID); |
2934d1c9 | 968 | State.F1 = State.F0; |
c12f5c67 | 969 | State.F0 = (State.regs[OP[0]] < (reg_t)OP[1]) ? 1 : 0; |
87178dbd | 970 | trace_output (OP_FLAG); |
2934d1c9 MH |
971 | } |
972 | ||
973 | /* cpfg */ | |
974 | void | |
975 | OP_4E09 () | |
976 | { | |
977 | uint8 *src, *dst; | |
2934d1c9 | 978 | |
60fc5b72 | 979 | trace_input ("cpfg", OP_FLAG_OUTPUT, OP_FLAG, OP_VOID); |
2934d1c9 MH |
980 | if (OP[0] == 0) |
981 | dst = &State.F0; | |
982 | else | |
983 | dst = &State.F1; | |
984 | ||
985 | if (OP[1] == 0) | |
986 | src = &State.F0; | |
987 | else if (OP[1] == 1) | |
988 | src = &State.F1; | |
989 | else | |
990 | src = &State.C; | |
991 | ||
992 | *dst = *src; | |
87178dbd | 993 | trace_output (OP_FLAG); |
2934d1c9 MH |
994 | } |
995 | ||
996 | /* dbt */ | |
997 | void | |
998 | OP_5F20 () | |
999 | { | |
a49a15ad | 1000 | /* d10v_callback->printf_filtered(d10v_callback, "***** DBT ***** PC=%x\n",PC); */ |
4f425a32 | 1001 | State.exception = SIGTRAP; |
2934d1c9 MH |
1002 | } |
1003 | ||
1004 | /* divs */ | |
1005 | void | |
1006 | OP_14002800 () | |
1007 | { | |
1008 | uint16 foo, tmp, tmpf; | |
87178dbd MM |
1009 | |
1010 | trace_input ("divs", OP_DREG, OP_REG, OP_VOID); | |
2934d1c9 MH |
1011 | foo = (State.regs[OP[0]] << 1) | (State.regs[OP[0]+1] >> 15); |
1012 | tmp = (int16)foo - (int16)(State.regs[OP[1]]); | |
1013 | tmpf = (foo >= State.regs[OP[1]]) ? 1 : 0; | |
1014 | State.regs[OP[0]] = (tmpf == 1) ? tmp : foo; | |
1015 | State.regs[OP[0]+1] = (State.regs[OP[0]+1] << 1) | tmpf; | |
87178dbd | 1016 | trace_output (OP_DREG); |
2934d1c9 MH |
1017 | } |
1018 | ||
1019 | /* exef0f */ | |
1020 | void | |
1021 | OP_4E04 () | |
1022 | { | |
87178dbd | 1023 | trace_input ("exef0f", OP_VOID, OP_VOID, OP_VOID); |
293c76a3 | 1024 | State.exe = (State.F0 == 0); |
87178dbd | 1025 | trace_output (OP_FLAG); |
2934d1c9 MH |
1026 | } |
1027 | ||
1028 | /* exef0t */ | |
1029 | void | |
1030 | OP_4E24 () | |
1031 | { | |
87178dbd | 1032 | trace_input ("exef0t", OP_VOID, OP_VOID, OP_VOID); |
293c76a3 | 1033 | State.exe = (State.F0 != 0); |
87178dbd | 1034 | trace_output (OP_FLAG); |
2934d1c9 MH |
1035 | } |
1036 | ||
1037 | /* exef1f */ | |
1038 | void | |
1039 | OP_4E40 () | |
1040 | { | |
87178dbd | 1041 | trace_input ("exef1f", OP_VOID, OP_VOID, OP_VOID); |
293c76a3 | 1042 | State.exe = (State.F1 == 0); |
87178dbd | 1043 | trace_output (OP_FLAG); |
2934d1c9 MH |
1044 | } |
1045 | ||
1046 | /* exef1t */ | |
1047 | void | |
1048 | OP_4E42 () | |
1049 | { | |
87178dbd | 1050 | trace_input ("exef1t", OP_VOID, OP_VOID, OP_VOID); |
293c76a3 | 1051 | State.exe = (State.F1 != 0); |
87178dbd | 1052 | trace_output (OP_FLAG); |
2934d1c9 MH |
1053 | } |
1054 | ||
1055 | /* exefaf */ | |
1056 | void | |
1057 | OP_4E00 () | |
1058 | { | |
87178dbd | 1059 | trace_input ("exefaf", OP_VOID, OP_VOID, OP_VOID); |
293c76a3 | 1060 | State.exe = (State.F0 == 0) & (State.F1 == 0); |
87178dbd | 1061 | trace_output (OP_FLAG); |
2934d1c9 MH |
1062 | } |
1063 | ||
1064 | /* exefat */ | |
1065 | void | |
1066 | OP_4E02 () | |
1067 | { | |
87178dbd | 1068 | trace_input ("exefat", OP_VOID, OP_VOID, OP_VOID); |
293c76a3 | 1069 | State.exe = (State.F0 == 0) & (State.F1 != 0); |
87178dbd | 1070 | trace_output (OP_FLAG); |
2934d1c9 MH |
1071 | } |
1072 | ||
1073 | /* exetaf */ | |
1074 | void | |
1075 | OP_4E20 () | |
1076 | { | |
87178dbd | 1077 | trace_input ("exetaf", OP_VOID, OP_VOID, OP_VOID); |
293c76a3 | 1078 | State.exe = (State.F0 != 0) & (State.F1 == 0); |
87178dbd | 1079 | trace_output (OP_FLAG); |
2934d1c9 MH |
1080 | } |
1081 | ||
1082 | /* exetat */ | |
1083 | void | |
1084 | OP_4E22 () | |
1085 | { | |
87178dbd | 1086 | trace_input ("exetat", OP_VOID, OP_VOID, OP_VOID); |
293c76a3 | 1087 | State.exe = (State.F0 != 0) & (State.F1 != 0); |
87178dbd | 1088 | trace_output (OP_FLAG); |
2934d1c9 MH |
1089 | } |
1090 | ||
1091 | /* exp */ | |
1092 | void | |
1093 | OP_15002A00 () | |
1094 | { | |
1095 | uint32 tmp, foo; | |
1096 | int i; | |
1097 | ||
87178dbd | 1098 | trace_input ("exp", OP_REG_OUTPUT, OP_DREG, OP_VOID); |
4c38885c MH |
1099 | if (((int16)State.regs[OP[1]]) >= 0) |
1100 | tmp = (State.regs[OP[1]] << 16) | State.regs[OP[1]+1]; | |
2934d1c9 | 1101 | else |
4c38885c | 1102 | tmp = ~((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]); |
2934d1c9 MH |
1103 | |
1104 | foo = 0x40000000; | |
4c38885c | 1105 | for (i=1;i<17;i++) |
2934d1c9 MH |
1106 | { |
1107 | if (tmp & foo) | |
1108 | { | |
1109 | State.regs[OP[0]] = i-1; | |
87178dbd | 1110 | trace_output (OP_REG); |
2934d1c9 MH |
1111 | return; |
1112 | } | |
4c38885c | 1113 | foo >>= 1; |
2934d1c9 MH |
1114 | } |
1115 | State.regs[OP[0]] = 16; | |
87178dbd | 1116 | trace_output (OP_REG); |
2934d1c9 MH |
1117 | } |
1118 | ||
1119 | /* exp */ | |
1120 | void | |
1121 | OP_15002A02 () | |
1122 | { | |
4c38885c MH |
1123 | int64 tmp, foo; |
1124 | int i; | |
87178dbd MM |
1125 | |
1126 | trace_input ("exp", OP_REG_OUTPUT, OP_ACCUM, OP_VOID); | |
fd435e9f MM |
1127 | tmp = SEXT40(State.a[OP[1]]); |
1128 | if (tmp < 0) | |
1129 | tmp = ~tmp & MASK40; | |
4c38885c MH |
1130 | |
1131 | foo = 0x4000000000LL; | |
1132 | for (i=1;i<25;i++) | |
1133 | { | |
1134 | if (tmp & foo) | |
1135 | { | |
1136 | State.regs[OP[0]] = i-9; | |
87178dbd | 1137 | trace_output (OP_REG); |
4c38885c MH |
1138 | return; |
1139 | } | |
1140 | foo >>= 1; | |
1141 | } | |
1142 | State.regs[OP[0]] = 16; | |
87178dbd | 1143 | trace_output (OP_REG); |
2934d1c9 MH |
1144 | } |
1145 | ||
1146 | /* jl */ | |
1147 | void | |
1148 | OP_4D00 () | |
1149 | { | |
a18cb100 | 1150 | trace_input ("jl", OP_REG, OP_R2, OP_R3); |
2934d1c9 | 1151 | State.regs[13] = PC+1; |
fd435e9f | 1152 | JMP (State.regs[OP[0]]); |
87178dbd | 1153 | trace_output (OP_VOID); |
2934d1c9 MH |
1154 | } |
1155 | ||
1156 | /* jmp */ | |
1157 | void | |
1158 | OP_4C00 () | |
1159 | { | |
a18cb100 MM |
1160 | trace_input ("jmp", OP_REG, |
1161 | (OP[0] == 13) ? OP_R2 : OP_VOID, | |
1162 | (OP[0] == 13) ? OP_R3 : OP_VOID); | |
1163 | ||
fd435e9f | 1164 | JMP (State.regs[OP[0]]); |
87178dbd | 1165 | trace_output (OP_VOID); |
2934d1c9 MH |
1166 | } |
1167 | ||
1168 | /* ld */ | |
1169 | void | |
1170 | OP_30000000 () | |
1171 | { | |
87178dbd | 1172 | trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID); |
2934d1c9 | 1173 | State.regs[OP[0]] = RW (OP[1] + State.regs[OP[2]]); |
87178dbd | 1174 | trace_output (OP_REG); |
2934d1c9 MH |
1175 | } |
1176 | ||
1177 | /* ld */ | |
1178 | void | |
1179 | OP_6401 () | |
1180 | { | |
87178dbd | 1181 | trace_input ("ld", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID); |
4c38885c | 1182 | State.regs[OP[0]] = RW (State.regs[OP[1]]); |
4f425a32 | 1183 | INC_ADDR(State.regs[OP[1]],-2); |
87178dbd | 1184 | trace_output (OP_REG); |
2934d1c9 MH |
1185 | } |
1186 | ||
1187 | /* ld */ | |
1188 | void | |
1189 | OP_6001 () | |
1190 | { | |
87178dbd | 1191 | trace_input ("ld", OP_REG_OUTPUT, OP_POSTINC, OP_VOID); |
4c38885c | 1192 | State.regs[OP[0]] = RW (State.regs[OP[1]]); |
4f425a32 | 1193 | INC_ADDR(State.regs[OP[1]],2); |
87178dbd | 1194 | trace_output (OP_REG); |
2934d1c9 MH |
1195 | } |
1196 | ||
1197 | /* ld */ | |
1198 | void | |
1199 | OP_6000 () | |
1200 | { | |
87178dbd | 1201 | trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF, OP_VOID); |
2934d1c9 | 1202 | State.regs[OP[0]] = RW (State.regs[OP[1]]); |
87178dbd | 1203 | trace_output (OP_REG); |
2934d1c9 MH |
1204 | } |
1205 | ||
1206 | /* ld2w */ | |
1207 | void | |
1208 | OP_31000000 () | |
1209 | { | |
8918b3a7 | 1210 | uint16 addr = State.regs[OP[2]]; |
308f64d3 | 1211 | trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID); |
8918b3a7 MM |
1212 | State.regs[OP[0]] = RW (OP[1] + addr); |
1213 | State.regs[OP[0]+1] = RW (OP[1] + addr + 2); | |
87178dbd | 1214 | trace_output (OP_DREG); |
2934d1c9 MH |
1215 | } |
1216 | ||
1217 | /* ld2w */ | |
1218 | void | |
1219 | OP_6601 () | |
1220 | { | |
8918b3a7 | 1221 | uint16 addr = State.regs[OP[1]]; |
87178dbd | 1222 | trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID); |
8918b3a7 MM |
1223 | State.regs[OP[0]] = RW (addr); |
1224 | State.regs[OP[0]+1] = RW (addr+2); | |
4f425a32 | 1225 | INC_ADDR(State.regs[OP[1]],-4); |
87178dbd | 1226 | trace_output (OP_DREG); |
2934d1c9 MH |
1227 | } |
1228 | ||
1229 | /* ld2w */ | |
1230 | void | |
1231 | OP_6201 () | |
1232 | { | |
8918b3a7 | 1233 | uint16 addr = State.regs[OP[1]]; |
87178dbd | 1234 | trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTINC, OP_VOID); |
8918b3a7 MM |
1235 | State.regs[OP[0]] = RW (addr); |
1236 | State.regs[OP[0]+1] = RW (addr+2); | |
4f425a32 | 1237 | INC_ADDR(State.regs[OP[1]],4); |
8918b3a7 | 1238 | trace_output (OP_DREG); |
2934d1c9 MH |
1239 | } |
1240 | ||
1241 | /* ld2w */ | |
1242 | void | |
1243 | OP_6200 () | |
1244 | { | |
8918b3a7 | 1245 | uint16 addr = State.regs[OP[1]]; |
addb61a5 | 1246 | trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF, OP_VOID); |
8918b3a7 MM |
1247 | State.regs[OP[0]] = RW (addr); |
1248 | State.regs[OP[0]+1] = RW (addr+2); | |
1249 | trace_output (OP_DREG); | |
2934d1c9 MH |
1250 | } |
1251 | ||
1252 | /* ldb */ | |
1253 | void | |
1254 | OP_38000000 () | |
1255 | { | |
87178dbd | 1256 | trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID); |
c422ecc7 | 1257 | State.regs[OP[0]] = SEXT8 (RB (OP[1] + State.regs[OP[2]])); |
87178dbd | 1258 | trace_output (OP_REG); |
2934d1c9 MH |
1259 | } |
1260 | ||
1261 | /* ldb */ | |
1262 | void | |
1263 | OP_7000 () | |
1264 | { | |
87178dbd | 1265 | trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF, OP_VOID); |
c422ecc7 | 1266 | State.regs[OP[0]] = SEXT8 (RB (State.regs[OP[1]])); |
87178dbd | 1267 | trace_output (OP_REG); |
2934d1c9 MH |
1268 | } |
1269 | ||
1270 | /* ldi.s */ | |
1271 | void | |
1272 | OP_4001 () | |
1273 | { | |
87178dbd | 1274 | trace_input ("ldi.s", OP_REG_OUTPUT, OP_CONSTANT4, OP_VOID); |
2934d1c9 | 1275 | State.regs[OP[0]] = SEXT4(OP[1]); |
87178dbd | 1276 | trace_output (OP_REG); |
2934d1c9 MH |
1277 | } |
1278 | ||
1279 | /* ldi.l */ | |
1280 | void | |
1281 | OP_20000000 () | |
1282 | { | |
fd435e9f | 1283 | trace_input ("ldi.l", OP_REG_OUTPUT, OP_CONSTANT16, OP_VOID); |
2934d1c9 | 1284 | State.regs[OP[0]] = OP[1]; |
87178dbd | 1285 | trace_output (OP_REG); |
2934d1c9 MH |
1286 | } |
1287 | ||
1288 | /* ldub */ | |
1289 | void | |
1290 | OP_39000000 () | |
1291 | { | |
87178dbd | 1292 | trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID); |
2934d1c9 | 1293 | State.regs[OP[0]] = RB (OP[1] + State.regs[OP[2]]); |
87178dbd | 1294 | trace_output (OP_REG); |
2934d1c9 MH |
1295 | } |
1296 | ||
1297 | /* ldub */ | |
1298 | void | |
1299 | OP_7200 () | |
1300 | { | |
87178dbd | 1301 | trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF, OP_VOID); |
2934d1c9 | 1302 | State.regs[OP[0]] = RB (State.regs[OP[1]]); |
87178dbd | 1303 | trace_output (OP_REG); |
2934d1c9 MH |
1304 | } |
1305 | ||
1306 | /* mac */ | |
1307 | void | |
1308 | OP_2A00 () | |
1309 | { | |
4c38885c | 1310 | int64 tmp; |
87178dbd MM |
1311 | |
1312 | trace_input ("mac", OP_ACCUM, OP_REG, OP_REG); | |
4f425a32 | 1313 | tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]])); |
4c38885c MH |
1314 | |
1315 | if (State.FX) | |
4f425a32 | 1316 | tmp = SEXT40( (tmp << 1) & MASK40); |
4c38885c MH |
1317 | |
1318 | if (State.ST && tmp > MAX32) | |
1319 | tmp = MAX32; | |
1320 | ||
4f425a32 | 1321 | tmp += SEXT40(State.a[OP[0]]); |
4c38885c MH |
1322 | if (State.ST) |
1323 | { | |
1324 | if (tmp > MAX32) | |
1325 | State.a[OP[0]] = MAX32; | |
1326 | else if (tmp < MIN32) | |
1327 | State.a[OP[0]] = MIN32; | |
1328 | else | |
4f425a32 | 1329 | State.a[OP[0]] = tmp & MASK40; |
4c38885c MH |
1330 | } |
1331 | else | |
4f425a32 | 1332 | State.a[OP[0]] = tmp & MASK40; |
87178dbd | 1333 | trace_output (OP_ACCUM); |
2934d1c9 MH |
1334 | } |
1335 | ||
1336 | /* macsu */ | |
1337 | void | |
1338 | OP_1A00 () | |
1339 | { | |
4f425a32 | 1340 | int64 tmp; |
87178dbd MM |
1341 | |
1342 | trace_input ("macsu", OP_ACCUM, OP_REG, OP_REG); | |
4f425a32 MH |
1343 | tmp = SEXT40 ((int16)State.regs[OP[1]] * State.regs[OP[2]]); |
1344 | if (State.FX) | |
1345 | tmp = SEXT40( (tmp << 1) & MASK40); | |
1346 | ||
1347 | State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) + tmp) & MASK40; | |
87178dbd | 1348 | trace_output (OP_ACCUM); |
2934d1c9 MH |
1349 | } |
1350 | ||
1351 | /* macu */ | |
1352 | void | |
1353 | OP_3A00 () | |
1354 | { | |
ae558075 AC |
1355 | uint64 tmp; |
1356 | uint32 src1; | |
1357 | uint32 src2; | |
87178dbd MM |
1358 | |
1359 | trace_input ("macu", OP_ACCUM, OP_REG, OP_REG); | |
ae558075 AC |
1360 | src1 = (uint16) State.regs[OP[1]]; |
1361 | src2 = (uint16) State.regs[OP[2]]; | |
1362 | tmp = src1 * src2; | |
4f425a32 | 1363 | if (State.FX) |
ae558075 AC |
1364 | tmp = (tmp << 1); |
1365 | State.a[OP[0]] = (State.a[OP[0]] + tmp) & MASK40; | |
87178dbd | 1366 | trace_output (OP_ACCUM); |
2934d1c9 MH |
1367 | } |
1368 | ||
1369 | /* max */ | |
1370 | void | |
1371 | OP_2600 () | |
1372 | { | |
87178dbd | 1373 | trace_input ("max", OP_REG, OP_REG, OP_VOID); |
2934d1c9 | 1374 | State.F1 = State.F0; |
ea2155e8 | 1375 | if ((int16)State.regs[OP[1]] > (int16)State.regs[OP[0]]) |
2934d1c9 MH |
1376 | { |
1377 | State.regs[OP[0]] = State.regs[OP[1]]; | |
1378 | State.F0 = 1; | |
1379 | } | |
1380 | else | |
1381 | State.F0 = 0; | |
87178dbd | 1382 | trace_output (OP_REG); |
2934d1c9 MH |
1383 | } |
1384 | ||
1385 | /* max */ | |
1386 | void | |
1387 | OP_3600 () | |
1388 | { | |
4f425a32 | 1389 | int64 tmp; |
87178dbd MM |
1390 | |
1391 | trace_input ("max", OP_ACCUM, OP_DREG, OP_VOID); | |
4f425a32 MH |
1392 | State.F1 = State.F0; |
1393 | tmp = SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]; | |
1394 | if (tmp > SEXT40(State.a[OP[0]])) | |
1395 | { | |
1396 | State.a[OP[0]] = tmp & MASK40; | |
1397 | State.F0 = 1; | |
1398 | } | |
1399 | else | |
1400 | State.F0 = 0; | |
87178dbd | 1401 | trace_output (OP_ACCUM); |
2934d1c9 MH |
1402 | } |
1403 | ||
1404 | /* max */ | |
1405 | void | |
1406 | OP_3602 () | |
1407 | { | |
87178dbd | 1408 | trace_input ("max", OP_ACCUM, OP_ACCUM, OP_VOID); |
4f425a32 MH |
1409 | State.F1 = State.F0; |
1410 | if (SEXT40(State.a[OP[1]]) > SEXT40(State.a[OP[0]])) | |
1411 | { | |
1412 | State.a[OP[0]] = State.a[OP[1]]; | |
1413 | State.F0 = 1; | |
1414 | } | |
1415 | else | |
1416 | State.F0 = 0; | |
87178dbd | 1417 | trace_output (OP_ACCUM); |
2934d1c9 MH |
1418 | } |
1419 | ||
4f425a32 | 1420 | |
2934d1c9 MH |
1421 | /* min */ |
1422 | void | |
1423 | OP_2601 () | |
1424 | { | |
87178dbd | 1425 | trace_input ("min", OP_REG, OP_REG, OP_VOID); |
2934d1c9 | 1426 | State.F1 = State.F0; |
ea2155e8 | 1427 | if ((int16)State.regs[OP[1]] < (int16)State.regs[OP[0]]) |
2934d1c9 MH |
1428 | { |
1429 | State.regs[OP[0]] = State.regs[OP[1]]; | |
1430 | State.F0 = 1; | |
1431 | } | |
1432 | else | |
1433 | State.F0 = 0; | |
87178dbd | 1434 | trace_output (OP_REG); |
2934d1c9 MH |
1435 | } |
1436 | ||
1437 | /* min */ | |
1438 | void | |
1439 | OP_3601 () | |
1440 | { | |
4f425a32 | 1441 | int64 tmp; |
87178dbd MM |
1442 | |
1443 | trace_input ("min", OP_ACCUM, OP_DREG, OP_VOID); | |
4f425a32 MH |
1444 | State.F1 = State.F0; |
1445 | tmp = SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]; | |
1446 | if (tmp < SEXT40(State.a[OP[0]])) | |
1447 | { | |
1448 | State.a[OP[0]] = tmp & MASK40; | |
1449 | State.F0 = 1; | |
1450 | } | |
1451 | else | |
1452 | State.F0 = 0; | |
87178dbd | 1453 | trace_output (OP_ACCUM); |
2934d1c9 MH |
1454 | } |
1455 | ||
1456 | /* min */ | |
1457 | void | |
1458 | OP_3603 () | |
1459 | { | |
87178dbd | 1460 | trace_input ("min", OP_ACCUM, OP_ACCUM, OP_VOID); |
4f425a32 MH |
1461 | State.F1 = State.F0; |
1462 | if (SEXT40(State.a[OP[1]]) < SEXT40(State.a[OP[0]])) | |
1463 | { | |
1464 | State.a[OP[0]] = State.a[OP[1]]; | |
1465 | State.F0 = 1; | |
1466 | } | |
1467 | else | |
1468 | State.F0 = 0; | |
87178dbd | 1469 | trace_output (OP_ACCUM); |
2934d1c9 MH |
1470 | } |
1471 | ||
1472 | /* msb */ | |
1473 | void | |
1474 | OP_2800 () | |
1475 | { | |
4f425a32 | 1476 | int64 tmp; |
87178dbd MM |
1477 | |
1478 | trace_input ("msb", OP_ACCUM, OP_REG, OP_REG); | |
4f425a32 MH |
1479 | tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]])); |
1480 | ||
1481 | if (State.FX) | |
1482 | tmp = SEXT40 ((tmp << 1) & MASK40); | |
1483 | ||
1484 | if (State.ST && tmp > MAX32) | |
1485 | tmp = MAX32; | |
1486 | ||
1487 | tmp = SEXT40(State.a[OP[0]]) - tmp; | |
1488 | if (State.ST) | |
1489 | { | |
1490 | if (tmp > MAX32) | |
1491 | State.a[OP[0]] = MAX32; | |
1492 | else if (tmp < MIN32) | |
1493 | State.a[OP[0]] = MIN32; | |
1494 | else | |
1495 | State.a[OP[0]] = tmp & MASK40; | |
1496 | } | |
1497 | else | |
1498 | State.a[OP[0]] = tmp & MASK40; | |
87178dbd | 1499 | trace_output (OP_ACCUM); |
2934d1c9 MH |
1500 | } |
1501 | ||
1502 | /* msbsu */ | |
1503 | void | |
1504 | OP_1800 () | |
1505 | { | |
4f425a32 | 1506 | int64 tmp; |
87178dbd MM |
1507 | |
1508 | trace_input ("msbsu", OP_ACCUM, OP_REG, OP_REG); | |
4f425a32 MH |
1509 | tmp = SEXT40 ((int16)State.regs[OP[1]] * State.regs[OP[2]]); |
1510 | if (State.FX) | |
1511 | tmp = SEXT40( (tmp << 1) & MASK40); | |
1512 | ||
1513 | State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) - tmp) & MASK40; | |
87178dbd | 1514 | trace_output (OP_ACCUM); |
2934d1c9 MH |
1515 | } |
1516 | ||
1517 | /* msbu */ | |
1518 | void | |
1519 | OP_3800 () | |
1520 | { | |
d294a657 AC |
1521 | uint64 tmp; |
1522 | uint32 src1; | |
1523 | uint32 src2; | |
87178dbd MM |
1524 | |
1525 | trace_input ("msbu", OP_ACCUM, OP_REG, OP_REG); | |
d294a657 AC |
1526 | src1 = (uint16) State.regs[OP[1]]; |
1527 | src2 = (uint16) State.regs[OP[2]]; | |
1528 | tmp = src1 * src2; | |
4f425a32 | 1529 | if (State.FX) |
d294a657 | 1530 | tmp = (tmp << 1); |
4f425a32 | 1531 | |
d294a657 | 1532 | State.a[OP[0]] = (State.a[OP[0]] - tmp) & MASK40; |
87178dbd | 1533 | trace_output (OP_ACCUM); |
2934d1c9 MH |
1534 | } |
1535 | ||
1536 | /* mul */ | |
1537 | void | |
1538 | OP_2E00 () | |
1539 | { | |
87178dbd | 1540 | trace_input ("mul", OP_REG, OP_REG, OP_VOID); |
2934d1c9 | 1541 | State.regs[OP[0]] *= State.regs[OP[1]]; |
87178dbd | 1542 | trace_output (OP_REG); |
2934d1c9 MH |
1543 | } |
1544 | ||
1545 | /* mulx */ | |
1546 | void | |
1547 | OP_2C00 () | |
1548 | { | |
4f425a32 | 1549 | int64 tmp; |
87178dbd MM |
1550 | |
1551 | trace_input ("mulx", OP_ACCUM_OUTPUT, OP_REG, OP_REG); | |
4f425a32 MH |
1552 | tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]])); |
1553 | ||
1554 | if (State.FX) | |
1555 | tmp = SEXT40 ((tmp << 1) & MASK40); | |
1556 | ||
1557 | if (State.ST && tmp > MAX32) | |
1558 | State.a[OP[0]] = MAX32; | |
1559 | else | |
1560 | State.a[OP[0]] = tmp & MASK40; | |
87178dbd | 1561 | trace_output (OP_ACCUM); |
2934d1c9 MH |
1562 | } |
1563 | ||
1564 | /* mulxsu */ | |
1565 | void | |
1566 | OP_1C00 () | |
1567 | { | |
4f425a32 | 1568 | int64 tmp; |
87178dbd MM |
1569 | |
1570 | trace_input ("mulxsu", OP_ACCUM_OUTPUT, OP_REG, OP_REG); | |
4f425a32 MH |
1571 | tmp = SEXT40 ((int16)(State.regs[OP[1]]) * State.regs[OP[2]]); |
1572 | ||
1573 | if (State.FX) | |
1574 | tmp <<= 1; | |
1575 | ||
1576 | State.a[OP[0]] = tmp & MASK40; | |
87178dbd | 1577 | trace_output (OP_ACCUM); |
2934d1c9 MH |
1578 | } |
1579 | ||
1580 | /* mulxu */ | |
1581 | void | |
1582 | OP_3C00 () | |
1583 | { | |
9420287e AC |
1584 | uint64 tmp; |
1585 | uint32 src1; | |
1586 | uint32 src2; | |
87178dbd MM |
1587 | |
1588 | trace_input ("mulxu", OP_ACCUM_OUTPUT, OP_REG, OP_REG); | |
9420287e AC |
1589 | src1 = (uint16) State.regs[OP[1]]; |
1590 | src2 = (uint16) State.regs[OP[2]]; | |
1591 | tmp = src1 * src2; | |
4f425a32 MH |
1592 | if (State.FX) |
1593 | tmp <<= 1; | |
1594 | ||
1595 | State.a[OP[0]] = tmp & MASK40; | |
87178dbd | 1596 | trace_output (OP_ACCUM); |
2934d1c9 MH |
1597 | } |
1598 | ||
1599 | /* mv */ | |
1600 | void | |
1601 | OP_4000 () | |
1602 | { | |
87178dbd | 1603 | trace_input ("mv", OP_REG_OUTPUT, OP_REG, OP_VOID); |
2934d1c9 | 1604 | State.regs[OP[0]] = State.regs[OP[1]]; |
87178dbd | 1605 | trace_output (OP_REG); |
2934d1c9 MH |
1606 | } |
1607 | ||
1608 | /* mv2w */ | |
1609 | void | |
1610 | OP_5000 () | |
1611 | { | |
87178dbd | 1612 | trace_input ("mv2w", OP_DREG_OUTPUT, OP_DREG, OP_VOID); |
2934d1c9 MH |
1613 | State.regs[OP[0]] = State.regs[OP[1]]; |
1614 | State.regs[OP[0]+1] = State.regs[OP[1]+1]; | |
87178dbd | 1615 | trace_output (OP_DREG); |
2934d1c9 MH |
1616 | } |
1617 | ||
1618 | /* mv2wfac */ | |
1619 | void | |
1620 | OP_3E00 () | |
1621 | { | |
87178dbd | 1622 | trace_input ("mv2wfac", OP_DREG_OUTPUT, OP_ACCUM, OP_VOID); |
2934d1c9 MH |
1623 | State.regs[OP[0]] = (State.a[OP[1]] >> 16) & 0xffff; |
1624 | State.regs[OP[0]+1] = State.a[OP[1]] & 0xffff; | |
87178dbd | 1625 | trace_output (OP_DREG); |
2934d1c9 MH |
1626 | } |
1627 | ||
1628 | /* mv2wtac */ | |
1629 | void | |
1630 | OP_3E01 () | |
1631 | { | |
fd435e9f | 1632 | trace_input ("mv2wtac", OP_DREG, OP_ACCUM_OUTPUT, OP_VOID); |
4f425a32 | 1633 | State.a[OP[1]] = (SEXT16 (State.regs[OP[0]]) << 16 | State.regs[OP[0]+1]) & MASK40; |
fd435e9f | 1634 | trace_output (OP_ACCUM_REVERSE); |
2934d1c9 MH |
1635 | } |
1636 | ||
1637 | /* mvac */ | |
1638 | void | |
1639 | OP_3E03 () | |
1640 | { | |
87178dbd | 1641 | trace_input ("mvac", OP_ACCUM_OUTPUT, OP_ACCUM, OP_VOID); |
2934d1c9 | 1642 | State.a[OP[0]] = State.a[OP[1]]; |
87178dbd | 1643 | trace_output (OP_ACCUM); |
2934d1c9 MH |
1644 | } |
1645 | ||
1646 | /* mvb */ | |
1647 | void | |
1648 | OP_5400 () | |
1649 | { | |
87178dbd | 1650 | trace_input ("mvb", OP_REG_OUTPUT, OP_REG, OP_VOID); |
2934d1c9 | 1651 | State.regs[OP[0]] = SEXT8 (State.regs[OP[1]] & 0xff); |
87178dbd | 1652 | trace_output (OP_REG); |
2934d1c9 MH |
1653 | } |
1654 | ||
1655 | /* mvf0f */ | |
1656 | void | |
1657 | OP_4400 () | |
1658 | { | |
87178dbd | 1659 | trace_input ("mf0f", OP_REG_OUTPUT, OP_REG, OP_VOID); |
2934d1c9 MH |
1660 | if (State.F0 == 0) |
1661 | State.regs[OP[0]] = State.regs[OP[1]]; | |
87178dbd | 1662 | trace_output (OP_REG); |
2934d1c9 MH |
1663 | } |
1664 | ||
1665 | /* mvf0t */ | |
1666 | void | |
1667 | OP_4401 () | |
1668 | { | |
87178dbd | 1669 | trace_input ("mf0t", OP_REG_OUTPUT, OP_REG, OP_VOID); |
2934d1c9 MH |
1670 | if (State.F0) |
1671 | State.regs[OP[0]] = State.regs[OP[1]]; | |
87178dbd | 1672 | trace_output (OP_REG); |
2934d1c9 MH |
1673 | } |
1674 | ||
1675 | /* mvfacg */ | |
1676 | void | |
1677 | OP_1E04 () | |
1678 | { | |
87178dbd | 1679 | trace_input ("mvfacg", OP_REG_OUTPUT, OP_ACCUM, OP_VOID); |
2934d1c9 | 1680 | State.regs[OP[0]] = (State.a[OP[1]] >> 32) & 0xff; |
87178dbd | 1681 | trace_output (OP_ACCUM); |
2934d1c9 MH |
1682 | } |
1683 | ||
1684 | /* mvfachi */ | |
1685 | void | |
1686 | OP_1E00 () | |
1687 | { | |
87178dbd | 1688 | trace_input ("mvfachi", OP_REG_OUTPUT, OP_ACCUM, OP_VOID); |
2934d1c9 | 1689 | State.regs[OP[0]] = (State.a[OP[1]] >> 16) & 0xffff; |
87178dbd | 1690 | trace_output (OP_REG); |
2934d1c9 MH |
1691 | } |
1692 | ||
1693 | /* mvfaclo */ | |
1694 | void | |
1695 | OP_1E02 () | |
1696 | { | |
87178dbd | 1697 | trace_input ("mvfaclo", OP_REG_OUTPUT, OP_ACCUM, OP_VOID); |
2934d1c9 | 1698 | State.regs[OP[0]] = State.a[OP[1]] & 0xffff; |
87178dbd | 1699 | trace_output (OP_REG); |
2934d1c9 MH |
1700 | } |
1701 | ||
1702 | /* mvfc */ | |
1703 | void | |
1704 | OP_5200 () | |
1705 | { | |
87178dbd | 1706 | trace_input ("mvfc", OP_REG_OUTPUT, OP_CR, OP_VOID); |
2934d1c9 MH |
1707 | if (OP[1] == 0) |
1708 | { | |
1709 | /* PSW is treated specially */ | |
1710 | PSW = 0; | |
1711 | if (State.SM) PSW |= 0x8000; | |
1712 | if (State.EA) PSW |= 0x2000; | |
1713 | if (State.DB) PSW |= 0x1000; | |
1714 | if (State.IE) PSW |= 0x400; | |
1715 | if (State.RP) PSW |= 0x200; | |
1716 | if (State.MD) PSW |= 0x100; | |
1717 | if (State.FX) PSW |= 0x80; | |
1718 | if (State.ST) PSW |= 0x40; | |
1719 | if (State.F0) PSW |= 8; | |
1720 | if (State.F1) PSW |= 4; | |
1721 | if (State.C) PSW |= 1; | |
1722 | } | |
1723 | State.regs[OP[0]] = State.cregs[OP[1]]; | |
87178dbd | 1724 | trace_output (OP_REG); |
2934d1c9 MH |
1725 | } |
1726 | ||
1727 | /* mvtacg */ | |
1728 | void | |
1729 | OP_1E41 () | |
1730 | { | |
87178dbd | 1731 | trace_input ("mvtacg", OP_REG, OP_ACCUM, OP_VOID); |
2934d1c9 MH |
1732 | State.a[OP[1]] &= MASK32; |
1733 | State.a[OP[1]] |= (int64)(State.regs[OP[0]] & 0xff) << 32; | |
87178dbd | 1734 | trace_output (OP_ACCUM_REVERSE); |
2934d1c9 MH |
1735 | } |
1736 | ||
1737 | /* mvtachi */ | |
1738 | void | |
1739 | OP_1E01 () | |
1740 | { | |
1741 | uint16 tmp; | |
87178dbd MM |
1742 | |
1743 | trace_input ("mvtachi", OP_REG, OP_ACCUM, OP_VOID); | |
2934d1c9 | 1744 | tmp = State.a[OP[1]] & 0xffff; |
4f425a32 | 1745 | State.a[OP[1]] = (SEXT16 (State.regs[OP[0]]) << 16 | tmp) & MASK40; |
87178dbd | 1746 | trace_output (OP_ACCUM_REVERSE); |
2934d1c9 MH |
1747 | } |
1748 | ||
1749 | /* mvtaclo */ | |
1750 | void | |
1751 | OP_1E21 () | |
1752 | { | |
87178dbd | 1753 | trace_input ("mvtaclo", OP_REG, OP_ACCUM, OP_VOID); |
4f425a32 | 1754 | State.a[OP[1]] = (SEXT16 (State.regs[OP[0]])) & MASK40; |
87178dbd | 1755 | trace_output (OP_ACCUM_REVERSE); |
2934d1c9 MH |
1756 | } |
1757 | ||
1758 | /* mvtc */ | |
1759 | void | |
1760 | OP_5600 () | |
1761 | { | |
87178dbd | 1762 | trace_input ("mvtc", OP_REG, OP_CR_OUTPUT, OP_VOID); |
2934d1c9 MH |
1763 | State.cregs[OP[1]] = State.regs[OP[0]]; |
1764 | if (OP[1] == 0) | |
1765 | { | |
1766 | /* PSW is treated specially */ | |
1767 | State.SM = (PSW & 0x8000) ? 1 : 0; | |
1768 | State.EA = (PSW & 0x2000) ? 1 : 0; | |
1769 | State.DB = (PSW & 0x1000) ? 1 : 0; | |
1770 | State.IE = (PSW & 0x400) ? 1 : 0; | |
1771 | State.RP = (PSW & 0x200) ? 1 : 0; | |
1772 | State.MD = (PSW & 0x100) ? 1 : 0; | |
1773 | State.FX = (PSW & 0x80) ? 1 : 0; | |
1774 | State.ST = (PSW & 0x40) ? 1 : 0; | |
1775 | State.F0 = (PSW & 8) ? 1 : 0; | |
1776 | State.F1 = (PSW & 4) ? 1 : 0; | |
1777 | State.C = PSW & 1; | |
1778 | if (State.ST && !State.FX) | |
1779 | { | |
7eebfc62 MM |
1780 | (*d10v_callback->printf_filtered) (d10v_callback, |
1781 | "ERROR at PC 0x%x: ST can only be set when FX is set.\n", | |
1782 | PC<<2); | |
4f425a32 | 1783 | State.exception = SIGILL; |
2934d1c9 MH |
1784 | } |
1785 | } | |
87178dbd | 1786 | trace_output (OP_CR_REVERSE); |
2934d1c9 MH |
1787 | } |
1788 | ||
1789 | /* mvub */ | |
1790 | void | |
1791 | OP_5401 () | |
1792 | { | |
87178dbd | 1793 | trace_input ("mvub", OP_REG_OUTPUT, OP_REG, OP_VOID); |
2934d1c9 | 1794 | State.regs[OP[0]] = State.regs[OP[1]] & 0xff; |
87178dbd | 1795 | trace_output (OP_REG); |
2934d1c9 MH |
1796 | } |
1797 | ||
1798 | /* neg */ | |
1799 | void | |
1800 | OP_4605 () | |
1801 | { | |
87178dbd | 1802 | trace_input ("neg", OP_REG, OP_VOID, OP_VOID); |
2934d1c9 | 1803 | State.regs[OP[0]] = 0 - State.regs[OP[0]]; |
87178dbd | 1804 | trace_output (OP_REG); |
2934d1c9 MH |
1805 | } |
1806 | ||
1807 | /* neg */ | |
1808 | void | |
1809 | OP_5605 () | |
1810 | { | |
1811 | int64 tmp; | |
87178dbd MM |
1812 | |
1813 | trace_input ("neg", OP_ACCUM, OP_VOID, OP_VOID); | |
4f425a32 | 1814 | tmp = -SEXT40(State.a[OP[0]]); |
2934d1c9 MH |
1815 | if (State.ST) |
1816 | { | |
4c38885c | 1817 | if ( tmp > MAX32) |
2934d1c9 | 1818 | State.a[OP[0]] = MAX32; |
4c38885c | 1819 | else if (tmp < MIN32) |
2934d1c9 MH |
1820 | State.a[OP[0]] = MIN32; |
1821 | else | |
4f425a32 | 1822 | State.a[OP[0]] = tmp & MASK40; |
2934d1c9 MH |
1823 | } |
1824 | else | |
4f425a32 | 1825 | State.a[OP[0]] = tmp & MASK40; |
87178dbd | 1826 | trace_output (OP_ACCUM); |
2934d1c9 MH |
1827 | } |
1828 | ||
1829 | ||
1830 | /* nop */ | |
1831 | void | |
1832 | OP_5E00 () | |
1833 | { | |
87178dbd | 1834 | trace_input ("nop", OP_VOID, OP_VOID, OP_VOID); |
7eebfc62 | 1835 | |
c422ecc7 MH |
1836 | ins_type_counters[ (int)State.ins_type ]--; /* don't count nops as normal instructions */ |
1837 | switch (State.ins_type) | |
1838 | { | |
1839 | default: | |
1840 | ins_type_counters[ (int)INS_UNKNOWN ]++; | |
1841 | break; | |
1842 | ||
1843 | case INS_LEFT_PARALLEL: | |
1844 | /* Don't count a parallel op that includes a NOP as a true parallel op */ | |
1845 | ins_type_counters[ (int)INS_RIGHT_PARALLEL ]--; | |
1846 | ins_type_counters[ (int)INS_RIGHT ]++; | |
1847 | ins_type_counters[ (int)INS_LEFT_NOPS ]++; | |
1848 | break; | |
1849 | ||
1850 | case INS_LEFT: | |
1851 | case INS_LEFT_COND_EXE: | |
1852 | ins_type_counters[ (int)INS_LEFT_NOPS ]++; | |
1853 | break; | |
1854 | ||
1855 | case INS_RIGHT_PARALLEL: | |
1856 | /* Don't count a parallel op that includes a NOP as a true parallel op */ | |
1857 | ins_type_counters[ (int)INS_LEFT_PARALLEL ]--; | |
1858 | ins_type_counters[ (int)INS_LEFT ]++; | |
1859 | ins_type_counters[ (int)INS_RIGHT_NOPS ]++; | |
1860 | break; | |
1861 | ||
1862 | case INS_RIGHT: | |
1863 | case INS_RIGHT_COND_EXE: | |
1864 | ins_type_counters[ (int)INS_RIGHT_NOPS ]++; | |
1865 | break; | |
1866 | } | |
1867 | ||
1868 | trace_output (OP_VOID); | |
2934d1c9 MH |
1869 | } |
1870 | ||
1871 | /* not */ | |
1872 | void | |
1873 | OP_4603 () | |
1874 | { | |
87178dbd | 1875 | trace_input ("not", OP_REG, OP_VOID, OP_VOID); |
2934d1c9 | 1876 | State.regs[OP[0]] = ~(State.regs[OP[0]]); |
87178dbd | 1877 | trace_output (OP_REG); |
2934d1c9 MH |
1878 | } |
1879 | ||
1880 | /* or */ | |
1881 | void | |
1882 | OP_800 () | |
1883 | { | |
87178dbd | 1884 | trace_input ("or", OP_REG, OP_REG, OP_VOID); |
2934d1c9 | 1885 | State.regs[OP[0]] |= State.regs[OP[1]]; |
87178dbd | 1886 | trace_output (OP_REG); |
2934d1c9 MH |
1887 | } |
1888 | ||
1889 | /* or3 */ | |
1890 | void | |
1891 | OP_4000000 () | |
1892 | { | |
87178dbd | 1893 | trace_input ("or3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16); |
2934d1c9 | 1894 | State.regs[OP[0]] = State.regs[OP[1]] | OP[2]; |
87178dbd | 1895 | trace_output (OP_REG); |
2934d1c9 MH |
1896 | } |
1897 | ||
1898 | /* rac */ | |
1899 | void | |
1900 | OP_5201 () | |
1901 | { | |
1902 | int64 tmp; | |
1903 | int shift = SEXT3 (OP[2]); | |
87178dbd MM |
1904 | |
1905 | trace_input ("rac", OP_DREG_OUTPUT, OP_ACCUM, OP_CONSTANT3); | |
166acb9f MH |
1906 | if (OP[1] != 0) |
1907 | { | |
7eebfc62 MM |
1908 | (*d10v_callback->printf_filtered) (d10v_callback, |
1909 | "ERROR at PC 0x%x: instruction only valid for A0\n", | |
1910 | PC<<2); | |
166acb9f MH |
1911 | State.exception = SIGILL; |
1912 | } | |
1913 | ||
2934d1c9 MH |
1914 | State.F1 = State.F0; |
1915 | if (shift >=0) | |
1916 | tmp = ((State.a[0] << 16) | (State.a[1] & 0xffff)) << shift; | |
1917 | else | |
1918 | tmp = ((State.a[0] << 16) | (State.a[1] & 0xffff)) >> -shift; | |
166acb9f | 1919 | tmp = ( SEXT60(tmp) + 0x8000 ) >> 16; |
4c38885c | 1920 | if (tmp > MAX32) |
2934d1c9 MH |
1921 | { |
1922 | State.regs[OP[0]] = 0x7fff; | |
1923 | State.regs[OP[0]+1] = 0xffff; | |
1924 | State.F0 = 1; | |
1925 | } | |
4c38885c | 1926 | else if (tmp < MIN32) |
2934d1c9 MH |
1927 | { |
1928 | State.regs[OP[0]] = 0x8000; | |
1929 | State.regs[OP[0]+1] = 0; | |
1930 | State.F0 = 1; | |
1931 | } | |
1932 | else | |
1933 | { | |
1934 | State.regs[OP[0]] = (tmp >> 16) & 0xffff; | |
1935 | State.regs[OP[0]+1] = tmp & 0xffff; | |
1936 | State.F0 = 0; | |
1937 | } | |
87178dbd | 1938 | trace_output (OP_DREG); |
2934d1c9 MH |
1939 | } |
1940 | ||
1941 | /* rachi */ | |
1942 | void | |
1943 | OP_4201 () | |
1944 | { | |
70ee56c5 | 1945 | signed64 tmp; |
4c38885c | 1946 | int shift = SEXT3 (OP[2]); |
87178dbd MM |
1947 | |
1948 | trace_input ("rachi", OP_REG_OUTPUT, OP_ACCUM, OP_CONSTANT3); | |
4c38885c MH |
1949 | State.F1 = State.F0; |
1950 | if (shift >=0) | |
70ee56c5 | 1951 | tmp = SEXT40 (State.a[OP[1]]) << shift; |
4c38885c | 1952 | else |
70ee56c5 | 1953 | tmp = SEXT40 (State.a[OP[1]]) >> -shift; |
4c38885c | 1954 | tmp += 0x8000; |
63a91cfb | 1955 | |
70ee56c5 | 1956 | if (tmp > SEXT44 (SIGNED64 (0x0007fffffff))) |
4c38885c MH |
1957 | { |
1958 | State.regs[OP[0]] = 0x7fff; | |
1959 | State.F0 = 1; | |
1960 | } | |
70ee56c5 | 1961 | else if (tmp < SEXT44 (SIGNED64 (0xfff80000000))) |
4c38885c MH |
1962 | { |
1963 | State.regs[OP[0]] = 0x8000; | |
1964 | State.F0 = 1; | |
1965 | } | |
1966 | else | |
1967 | { | |
1968 | State.regs[OP[0]] = (tmp >> 16) & 0xffff; | |
1969 | State.F0 = 0; | |
1970 | } | |
87178dbd | 1971 | trace_output (OP_REG); |
2934d1c9 MH |
1972 | } |
1973 | ||
1974 | /* rep */ | |
1975 | void | |
1976 | OP_27000000 () | |
1977 | { | |
87178dbd | 1978 | trace_input ("rep", OP_REG, OP_CONSTANT16, OP_VOID); |
2934d1c9 MH |
1979 | RPT_S = PC + 1; |
1980 | RPT_E = PC + OP[1]; | |
1981 | RPT_C = State.regs[OP[0]]; | |
1982 | State.RP = 1; | |
1983 | if (RPT_C == 0) | |
1984 | { | |
7eebfc62 | 1985 | (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep with count=0 is illegal.\n"); |
4f425a32 | 1986 | State.exception = SIGILL; |
2934d1c9 | 1987 | } |
4c38885c MH |
1988 | if (OP[1] < 4) |
1989 | { | |
7eebfc62 | 1990 | (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep must include at least 4 instructions.\n"); |
4f425a32 | 1991 | State.exception = SIGILL; |
4c38885c | 1992 | } |
87178dbd | 1993 | trace_output (OP_VOID); |
2934d1c9 MH |
1994 | } |
1995 | ||
1996 | /* repi */ | |
1997 | void | |
1998 | OP_2F000000 () | |
1999 | { | |
87178dbd | 2000 | trace_input ("repi", OP_CONSTANT16, OP_CONSTANT16, OP_VOID); |
2934d1c9 MH |
2001 | RPT_S = PC + 1; |
2002 | RPT_E = PC + OP[1]; | |
2003 | RPT_C = OP[0]; | |
2004 | State.RP = 1; | |
2005 | if (RPT_C == 0) | |
2006 | { | |
7eebfc62 | 2007 | (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi with count=0 is illegal.\n"); |
4f425a32 | 2008 | State.exception = SIGILL; |
4c38885c MH |
2009 | } |
2010 | if (OP[1] < 4) | |
2011 | { | |
7eebfc62 | 2012 | (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi must include at least 4 instructions.\n"); |
4f425a32 | 2013 | State.exception = SIGILL; |
2934d1c9 | 2014 | } |
87178dbd | 2015 | trace_output (OP_VOID); |
2934d1c9 MH |
2016 | } |
2017 | ||
2018 | /* rtd */ | |
2019 | void | |
2020 | OP_5F60 () | |
2021 | { | |
7eebfc62 | 2022 | d10v_callback->printf_filtered(d10v_callback, "ERROR: rtd - NOT IMPLEMENTED\n"); |
87178dbd | 2023 | State.exception = SIGILL; |
2934d1c9 MH |
2024 | } |
2025 | ||
2026 | /* rte */ | |
2027 | void | |
2028 | OP_5F40 () | |
2029 | { | |
87178dbd | 2030 | trace_input ("rte", OP_VOID, OP_VOID, OP_VOID); |
4c38885c MH |
2031 | PC = BPC; |
2032 | PSW = BPSW; | |
87178dbd | 2033 | trace_output (OP_VOID); |
2934d1c9 MH |
2034 | } |
2035 | ||
2036 | /* sadd */ | |
2037 | void | |
2038 | OP_1223 () | |
2039 | { | |
4c38885c | 2040 | int64 tmp; |
87178dbd MM |
2041 | |
2042 | trace_input ("sadd", OP_ACCUM, OP_ACCUM, OP_VOID); | |
4f425a32 | 2043 | tmp = SEXT40(State.a[OP[0]]) + (SEXT40(State.a[OP[1]]) >> 16); |
4c38885c MH |
2044 | if (State.ST) |
2045 | { | |
2046 | if (tmp > MAX32) | |
2047 | State.a[OP[0]] = MAX32; | |
2048 | else if (tmp < MIN32) | |
2049 | State.a[OP[0]] = MIN32; | |
2050 | else | |
4f425a32 | 2051 | State.a[OP[0]] = tmp & MASK40; |
4c38885c MH |
2052 | } |
2053 | else | |
4f425a32 | 2054 | State.a[OP[0]] = tmp & MASK40; |
87178dbd | 2055 | trace_output (OP_ACCUM); |
2934d1c9 MH |
2056 | } |
2057 | ||
2058 | /* setf0f */ | |
2059 | void | |
2060 | OP_4611 () | |
2061 | { | |
87178dbd | 2062 | trace_input ("setf0f", OP_REG_OUTPUT, OP_VOID, OP_VOID); |
4c38885c | 2063 | State.regs[OP[0]] = (State.F0 == 0) ? 1 : 0; |
87178dbd | 2064 | trace_output (OP_REG); |
2934d1c9 MH |
2065 | } |
2066 | ||
2067 | /* setf0t */ | |
2068 | void | |
2069 | OP_4613 () | |
2070 | { | |
87178dbd | 2071 | trace_input ("setf0t", OP_REG_OUTPUT, OP_VOID, OP_VOID); |
4c38885c | 2072 | State.regs[OP[0]] = (State.F0 == 1) ? 1 : 0; |
87178dbd | 2073 | trace_output (OP_REG); |
2934d1c9 MH |
2074 | } |
2075 | ||
2076 | /* sleep */ | |
2077 | void | |
2078 | OP_5FC0 () | |
2079 | { | |
87178dbd | 2080 | trace_input ("sleep", OP_VOID, OP_VOID, OP_VOID); |
4c38885c | 2081 | State.IE = 1; |
87178dbd | 2082 | trace_output (OP_VOID); |
2934d1c9 MH |
2083 | } |
2084 | ||
2085 | /* sll */ | |
2086 | void | |
2087 | OP_2200 () | |
2088 | { | |
87178dbd | 2089 | trace_input ("sll", OP_REG, OP_REG, OP_VOID); |
2934d1c9 | 2090 | State.regs[OP[0]] <<= (State.regs[OP[1]] & 0xf); |
87178dbd | 2091 | trace_output (OP_REG); |
2934d1c9 MH |
2092 | } |
2093 | ||
2094 | /* sll */ | |
2095 | void | |
2096 | OP_3200 () | |
2097 | { | |
4c38885c | 2098 | int64 tmp; |
87178dbd | 2099 | trace_input ("sll", OP_ACCUM, OP_REG, OP_VOID); |
069398aa | 2100 | if ((State.regs[OP[1]] & 31) <= 16) |
4c38885c | 2101 | tmp = SEXT40 (State.a[OP[0]]) << (State.regs[OP[1]] & 31); |
069398aa MM |
2102 | else |
2103 | { | |
2104 | (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31); | |
2105 | State.exception = SIGILL; | |
2106 | return; | |
2107 | } | |
4c38885c MH |
2108 | |
2109 | if (State.ST) | |
2110 | { | |
2111 | if (tmp > MAX32) | |
2112 | State.a[OP[0]] = MAX32; | |
2113 | else if (tmp < 0xffffff80000000LL) | |
2114 | State.a[OP[0]] = MIN32; | |
2115 | else | |
2116 | State.a[OP[0]] = tmp & MASK40; | |
2117 | } | |
2118 | else | |
2119 | State.a[OP[0]] = tmp & MASK40; | |
87178dbd | 2120 | trace_output (OP_ACCUM); |
2934d1c9 MH |
2121 | } |
2122 | ||
2123 | /* slli */ | |
2124 | void | |
2125 | OP_2201 () | |
2126 | { | |
87178dbd | 2127 | trace_input ("slli", OP_REG, OP_CONSTANT16, OP_VOID); |
2934d1c9 | 2128 | State.regs[OP[0]] <<= OP[1]; |
87178dbd | 2129 | trace_output (OP_REG); |
2934d1c9 MH |
2130 | } |
2131 | ||
2132 | /* slli */ | |
2133 | void | |
2134 | OP_3201 () | |
2135 | { | |
4c38885c | 2136 | int64 tmp; |
4f425a32 MH |
2137 | |
2138 | if (OP[1] == 0) | |
2139 | OP[1] = 16; | |
4f425a32 | 2140 | |
87178dbd | 2141 | trace_input ("slli", OP_ACCUM, OP_CONSTANT16, OP_VOID); |
4f425a32 | 2142 | tmp = SEXT40(State.a[OP[0]]) << OP[1]; |
4c38885c MH |
2143 | |
2144 | if (State.ST) | |
2145 | { | |
2146 | if (tmp > MAX32) | |
2147 | State.a[OP[0]] = MAX32; | |
2148 | else if (tmp < 0xffffff80000000LL) | |
2149 | State.a[OP[0]] = MIN32; | |
2150 | else | |
2151 | State.a[OP[0]] = tmp & MASK40; | |
2152 | } | |
2153 | else | |
2154 | State.a[OP[0]] = tmp & MASK40; | |
87178dbd | 2155 | trace_output (OP_ACCUM); |
2934d1c9 MH |
2156 | } |
2157 | ||
2158 | /* slx */ | |
2159 | void | |
2160 | OP_460B () | |
2161 | { | |
87178dbd | 2162 | trace_input ("slx", OP_REG, OP_FLAG, OP_VOID); |
2934d1c9 | 2163 | State.regs[OP[0]] = (State.regs[OP[0]] << 1) | State.F0; |
87178dbd | 2164 | trace_output (OP_REG); |
2934d1c9 MH |
2165 | } |
2166 | ||
2167 | /* sra */ | |
2168 | void | |
2169 | OP_2400 () | |
2170 | { | |
87178dbd | 2171 | trace_input ("sra", OP_REG, OP_REG, OP_VOID); |
2934d1c9 | 2172 | State.regs[OP[0]] = ((int16)(State.regs[OP[0]])) >> (State.regs[OP[1]] & 0xf); |
87178dbd | 2173 | trace_output (OP_REG); |
2934d1c9 MH |
2174 | } |
2175 | ||
2176 | /* sra */ | |
2177 | void | |
2178 | OP_3400 () | |
2179 | { | |
87178dbd | 2180 | trace_input ("sra", OP_ACCUM, OP_REG, OP_VOID); |
069398aa | 2181 | if ((State.regs[OP[1]] & 31) <= 16) |
fd435e9f | 2182 | State.a[OP[0]] = (SEXT40(State.a[OP[0]]) >> (State.regs[OP[1]] & 31)) & MASK40; |
069398aa MM |
2183 | else |
2184 | { | |
2185 | (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31); | |
2186 | State.exception = SIGILL; | |
2187 | return; | |
2188 | } | |
2189 | ||
87178dbd | 2190 | trace_output (OP_ACCUM); |
2934d1c9 MH |
2191 | } |
2192 | ||
2193 | /* srai */ | |
2194 | void | |
2195 | OP_2401 () | |
2196 | { | |
87178dbd | 2197 | trace_input ("srai", OP_REG, OP_CONSTANT16, OP_VOID); |
2934d1c9 | 2198 | State.regs[OP[0]] = ((int16)(State.regs[OP[0]])) >> OP[1]; |
87178dbd | 2199 | trace_output (OP_REG); |
2934d1c9 MH |
2200 | } |
2201 | ||
2202 | /* srai */ | |
2203 | void | |
2204 | OP_3401 () | |
2205 | { | |
4f425a32 MH |
2206 | if (OP[1] == 0) |
2207 | OP[1] = 16; | |
87178dbd MM |
2208 | |
2209 | trace_input ("srai", OP_ACCUM, OP_CONSTANT16, OP_VOID); | |
fd435e9f | 2210 | State.a[OP[0]] = (SEXT40(State.a[OP[0]]) >> OP[1]) & MASK40; |
87178dbd | 2211 | trace_output (OP_ACCUM); |
2934d1c9 MH |
2212 | } |
2213 | ||
2214 | /* srl */ | |
2215 | void | |
2216 | OP_2000 () | |
2217 | { | |
87178dbd | 2218 | trace_input ("srl", OP_REG, OP_REG, OP_VOID); |
2934d1c9 | 2219 | State.regs[OP[0]] >>= (State.regs[OP[1]] & 0xf); |
87178dbd | 2220 | trace_output (OP_REG); |
2934d1c9 MH |
2221 | } |
2222 | ||
2223 | /* srl */ | |
2224 | void | |
2225 | OP_3000 () | |
2226 | { | |
87178dbd | 2227 | trace_input ("srl", OP_ACCUM, OP_REG, OP_VOID); |
069398aa | 2228 | if ((State.regs[OP[1]] & 31) <= 16) |
fd435e9f | 2229 | State.a[OP[0]] = (uint64)((State.a[OP[0]] & MASK40) >> (State.regs[OP[1]] & 31)); |
069398aa MM |
2230 | else |
2231 | { | |
2232 | (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31); | |
2233 | State.exception = SIGILL; | |
2234 | return; | |
2235 | } | |
2236 | ||
87178dbd | 2237 | trace_output (OP_ACCUM); |
2934d1c9 MH |
2238 | } |
2239 | ||
2240 | /* srli */ | |
2241 | void | |
2242 | OP_2001 () | |
2243 | { | |
87178dbd | 2244 | trace_input ("srli", OP_REG, OP_CONSTANT16, OP_VOID); |
2934d1c9 | 2245 | State.regs[OP[0]] >>= OP[1]; |
87178dbd | 2246 | trace_output (OP_REG); |
2934d1c9 MH |
2247 | } |
2248 | ||
2249 | /* srli */ | |
2250 | void | |
2251 | OP_3001 () | |
2252 | { | |
4f425a32 MH |
2253 | if (OP[1] == 0) |
2254 | OP[1] = 16; | |
87178dbd MM |
2255 | |
2256 | trace_input ("srli", OP_ACCUM, OP_CONSTANT16, OP_VOID); | |
fd435e9f | 2257 | State.a[OP[0]] = (uint64)(State.a[OP[0]] & MASK40) >> OP[1]; |
87178dbd | 2258 | trace_output (OP_ACCUM); |
2934d1c9 MH |
2259 | } |
2260 | ||
2261 | /* srx */ | |
2262 | void | |
2263 | OP_4609 () | |
2264 | { | |
2265 | uint16 tmp; | |
87178dbd MM |
2266 | |
2267 | trace_input ("srx", OP_REG, OP_FLAG, OP_VOID); | |
2934d1c9 MH |
2268 | tmp = State.F0 << 15; |
2269 | State.regs[OP[0]] = (State.regs[OP[0]] >> 1) | tmp; | |
87178dbd | 2270 | trace_output (OP_REG); |
2934d1c9 MH |
2271 | } |
2272 | ||
2273 | /* st */ | |
2274 | void | |
2275 | OP_34000000 () | |
2276 | { | |
87178dbd | 2277 | trace_input ("st", OP_REG, OP_MEMREF2, OP_VOID); |
2934d1c9 | 2278 | SW (OP[1] + State.regs[OP[2]], State.regs[OP[0]]); |
87178dbd | 2279 | trace_output (OP_VOID); |
2934d1c9 MH |
2280 | } |
2281 | ||
2282 | /* st */ | |
2283 | void | |
2284 | OP_6800 () | |
2285 | { | |
87178dbd | 2286 | trace_input ("st", OP_REG, OP_MEMREF, OP_VOID); |
2934d1c9 | 2287 | SW (State.regs[OP[1]], State.regs[OP[0]]); |
87178dbd | 2288 | trace_output (OP_VOID); |
2934d1c9 MH |
2289 | } |
2290 | ||
2291 | /* st */ | |
2292 | void | |
2293 | OP_6C1F () | |
2294 | { | |
87178dbd | 2295 | trace_input ("st", OP_REG, OP_PREDEC, OP_VOID); |
4c38885c MH |
2296 | if ( OP[1] != 15 ) |
2297 | { | |
7eebfc62 | 2298 | (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n"); |
4f425a32 MH |
2299 | State.exception = SIGILL; |
2300 | return; | |
4c38885c MH |
2301 | } |
2302 | State.regs[OP[1]] -= 2; | |
2303 | SW (State.regs[OP[1]], State.regs[OP[0]]); | |
87178dbd | 2304 | trace_output (OP_VOID); |
2934d1c9 MH |
2305 | } |
2306 | ||
2307 | /* st */ | |
2308 | void | |
2309 | OP_6801 () | |
2310 | { | |
87178dbd | 2311 | trace_input ("st", OP_REG, OP_POSTINC, OP_VOID); |
4c38885c | 2312 | SW (State.regs[OP[1]], State.regs[OP[0]]); |
4f425a32 | 2313 | INC_ADDR (State.regs[OP[1]],2); |
87178dbd | 2314 | trace_output (OP_VOID); |
2934d1c9 MH |
2315 | } |
2316 | ||
2317 | /* st */ | |
2318 | void | |
2319 | OP_6C01 () | |
2320 | { | |
87178dbd | 2321 | trace_input ("st", OP_REG, OP_POSTDEC, OP_VOID); |
fd435e9f MM |
2322 | if ( OP[1] == 15 ) |
2323 | { | |
2324 | (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot post-decrement register r15 (SP).\n"); | |
2325 | State.exception = SIGILL; | |
2326 | return; | |
2327 | } | |
4c38885c | 2328 | SW (State.regs[OP[1]], State.regs[OP[0]]); |
4f425a32 | 2329 | INC_ADDR (State.regs[OP[1]],-2); |
87178dbd | 2330 | trace_output (OP_VOID); |
2934d1c9 MH |
2331 | } |
2332 | ||
2333 | /* st2w */ | |
2334 | void | |
2335 | OP_35000000 () | |
2336 | { | |
87178dbd | 2337 | trace_input ("st2w", OP_DREG, OP_MEMREF2, OP_VOID); |
4f425a32 MH |
2338 | SW (State.regs[OP[2]]+OP[1], State.regs[OP[0]]); |
2339 | SW (State.regs[OP[2]]+OP[1]+2, State.regs[OP[0]+1]); | |
87178dbd | 2340 | trace_output (OP_VOID); |
2934d1c9 MH |
2341 | } |
2342 | ||
2343 | /* st2w */ | |
2344 | void | |
2345 | OP_6A00 () | |
2346 | { | |
a18cb100 | 2347 | trace_input ("st2w", OP_DREG, OP_MEMREF, OP_VOID); |
4c38885c MH |
2348 | SW (State.regs[OP[1]], State.regs[OP[0]]); |
2349 | SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]); | |
87178dbd | 2350 | trace_output (OP_VOID); |
2934d1c9 MH |
2351 | } |
2352 | ||
2353 | /* st2w */ | |
2354 | void | |
2355 | OP_6E1F () | |
2356 | { | |
a18cb100 | 2357 | trace_input ("st2w", OP_DREG, OP_PREDEC, OP_VOID); |
4c38885c MH |
2358 | if ( OP[1] != 15 ) |
2359 | { | |
7eebfc62 | 2360 | (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n"); |
4f425a32 MH |
2361 | State.exception = SIGILL; |
2362 | return; | |
4c38885c MH |
2363 | } |
2364 | State.regs[OP[1]] -= 4; | |
2365 | SW (State.regs[OP[1]], State.regs[OP[0]]); | |
2366 | SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]); | |
87178dbd | 2367 | trace_output (OP_VOID); |
2934d1c9 MH |
2368 | } |
2369 | ||
2370 | /* st2w */ | |
2371 | void | |
2372 | OP_6A01 () | |
2373 | { | |
1155e06e | 2374 | trace_input ("st2w", OP_DREG, OP_POSTINC, OP_VOID); |
4c38885c MH |
2375 | SW (State.regs[OP[1]], State.regs[OP[0]]); |
2376 | SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]); | |
4f425a32 | 2377 | INC_ADDR (State.regs[OP[1]],4); |
87178dbd | 2378 | trace_output (OP_VOID); |
2934d1c9 MH |
2379 | } |
2380 | ||
2381 | /* st2w */ | |
2382 | void | |
2383 | OP_6E01 () | |
2384 | { | |
1155e06e FF |
2385 | trace_input ("st2w", OP_DREG, OP_POSTDEC, OP_VOID); |
2386 | if ( OP[1] == 15 ) | |
2387 | { | |
2388 | (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot post-decrement register r15 (SP).\n"); | |
2389 | State.exception = SIGILL; | |
2390 | return; | |
2391 | } | |
4c38885c MH |
2392 | SW (State.regs[OP[1]], State.regs[OP[0]]); |
2393 | SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]); | |
4f425a32 | 2394 | INC_ADDR (State.regs[OP[1]],-4); |
87178dbd | 2395 | trace_output (OP_VOID); |
2934d1c9 MH |
2396 | } |
2397 | ||
2398 | /* stb */ | |
2399 | void | |
2400 | OP_3C000000 () | |
2401 | { | |
87178dbd | 2402 | trace_input ("stb", OP_REG, OP_MEMREF2, OP_VOID); |
4f425a32 | 2403 | SB (State.regs[OP[2]]+OP[1], State.regs[OP[0]]); |
87178dbd | 2404 | trace_output (OP_VOID); |
2934d1c9 MH |
2405 | } |
2406 | ||
2407 | /* stb */ | |
2408 | void | |
2409 | OP_7800 () | |
2410 | { | |
87178dbd | 2411 | trace_input ("stb", OP_REG, OP_MEMREF, OP_VOID); |
4c38885c | 2412 | SB (State.regs[OP[1]], State.regs[OP[0]]); |
87178dbd | 2413 | trace_output (OP_VOID); |
2934d1c9 MH |
2414 | } |
2415 | ||
2416 | /* stop */ | |
2417 | void | |
2418 | OP_5FE0 () | |
2419 | { | |
87178dbd | 2420 | trace_input ("stop", OP_VOID, OP_VOID, OP_VOID); |
a49a15ad | 2421 | State.exception = SIG_D10V_STOP; |
87178dbd | 2422 | trace_output (OP_VOID); |
2934d1c9 MH |
2423 | } |
2424 | ||
2425 | /* sub */ | |
2426 | void | |
2427 | OP_0 () | |
4c38885c | 2428 | { |
f4b022d3 | 2429 | uint16 tmp; |
87178dbd MM |
2430 | |
2431 | trace_input ("sub", OP_REG, OP_REG, OP_VOID); | |
f4b022d3 MM |
2432 | tmp = State.regs[OP[0]] - State.regs[OP[1]]; |
2433 | State.C = (tmp > State.regs[OP[0]]); | |
2434 | State.regs[OP[0]] = tmp; | |
87178dbd | 2435 | trace_output (OP_REG); |
4c38885c MH |
2436 | } |
2437 | ||
2438 | /* sub */ | |
2439 | void | |
2440 | OP_1001 () | |
2441 | { | |
4f425a32 | 2442 | int64 tmp; |
87178dbd MM |
2443 | |
2444 | trace_input ("sub", OP_ACCUM, OP_DREG, OP_VOID); | |
4f425a32 MH |
2445 | tmp = SEXT40(State.a[OP[0]]) - (SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]); |
2446 | if (State.ST) | |
2447 | { | |
2448 | if ( tmp > MAX32) | |
2449 | State.a[OP[0]] = MAX32; | |
2450 | else if ( tmp < MIN32) | |
2451 | State.a[OP[0]] = MIN32; | |
2452 | else | |
2453 | State.a[OP[0]] = tmp & MASK40; | |
2454 | } | |
2455 | else | |
2456 | State.a[OP[0]] = tmp & MASK40; | |
87178dbd MM |
2457 | |
2458 | trace_output (OP_ACCUM); | |
4c38885c MH |
2459 | } |
2460 | ||
2461 | /* sub */ | |
2462 | ||
2463 | void | |
2464 | OP_1003 () | |
2934d1c9 | 2465 | { |
4f425a32 | 2466 | int64 tmp; |
87178dbd MM |
2467 | |
2468 | trace_input ("sub", OP_ACCUM, OP_ACCUM, OP_VOID); | |
4f425a32 MH |
2469 | tmp = SEXT40(State.a[OP[0]]) - SEXT40(State.a[OP[1]]); |
2470 | if (State.ST) | |
2471 | { | |
2472 | if (tmp > MAX32) | |
2473 | State.a[OP[0]] = MAX32; | |
2474 | else if ( tmp < MIN32) | |
2475 | State.a[OP[0]] = MIN32; | |
2476 | else | |
2477 | State.a[OP[0]] = tmp & MASK40; | |
2478 | } | |
2479 | else | |
2480 | State.a[OP[0]] = tmp & MASK40; | |
87178dbd MM |
2481 | |
2482 | trace_output (OP_ACCUM); | |
2934d1c9 MH |
2483 | } |
2484 | ||
2485 | /* sub2w */ | |
2486 | void | |
2487 | OP_1000 () | |
2488 | { | |
f4b022d3 | 2489 | uint32 tmp,a,b; |
4c38885c | 2490 | |
87178dbd | 2491 | trace_input ("sub2w", OP_DREG, OP_DREG, OP_VOID); |
f4b022d3 MM |
2492 | a = (uint32)((State.regs[OP[0]] << 16) | State.regs[OP[0]+1]); |
2493 | b = (uint32)((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]); | |
70ee56c5 AC |
2494 | /* see ../common/sim-alu.h for a more extensive discussion on how to |
2495 | compute the carry/overflow bits */ | |
2496 | tmp = a - b; | |
51b057f2 | 2497 | State.C = (a >= b); |
4c38885c MH |
2498 | State.regs[OP[0]] = (tmp >> 16) & 0xffff; |
2499 | State.regs[OP[0]+1] = tmp & 0xffff; | |
87178dbd | 2500 | trace_output (OP_DREG); |
2934d1c9 MH |
2501 | } |
2502 | ||
2503 | /* subac3 */ | |
2504 | void | |
2505 | OP_17000000 () | |
2506 | { | |
4f425a32 | 2507 | int64 tmp; |
87178dbd MM |
2508 | |
2509 | trace_input ("subac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM); | |
4f425a32 MH |
2510 | tmp = SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]) - SEXT40 (State.a[OP[2]]); |
2511 | State.regs[OP[0]] = (tmp >> 16) & 0xffff; | |
2512 | State.regs[OP[0]+1] = tmp & 0xffff; | |
87178dbd | 2513 | trace_output (OP_DREG); |
2934d1c9 MH |
2514 | } |
2515 | ||
2516 | /* subac3 */ | |
2517 | void | |
2518 | OP_17000002 () | |
2519 | { | |
4f425a32 | 2520 | int64 tmp; |
87178dbd MM |
2521 | |
2522 | trace_input ("subac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM); | |
4f425a32 MH |
2523 | tmp = SEXT40(State.a[OP[1]]) - SEXT40(State.a[OP[2]]); |
2524 | State.regs[OP[0]] = (tmp >> 16) & 0xffff; | |
2525 | State.regs[OP[0]+1] = tmp & 0xffff; | |
87178dbd | 2526 | trace_output (OP_DREG); |
2934d1c9 MH |
2527 | } |
2528 | ||
2529 | /* subac3s */ | |
2530 | void | |
2531 | OP_17001000 () | |
2532 | { | |
4f425a32 | 2533 | int64 tmp; |
87178dbd MM |
2534 | |
2535 | trace_input ("subac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM); | |
4f425a32 MH |
2536 | State.F1 = State.F0; |
2537 | tmp = SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]) - SEXT40(State.a[OP[2]]); | |
2538 | if ( tmp > MAX32) | |
2539 | { | |
2540 | State.regs[OP[0]] = 0x7fff; | |
2541 | State.regs[OP[0]+1] = 0xffff; | |
2542 | State.F0 = 1; | |
2543 | } | |
2544 | else if (tmp < MIN32) | |
2545 | { | |
2546 | State.regs[OP[0]] = 0x8000; | |
2547 | State.regs[OP[0]+1] = 0; | |
2548 | State.F0 = 1; | |
2549 | } | |
2550 | else | |
2551 | { | |
2552 | State.regs[OP[0]] = (tmp >> 16) & 0xffff; | |
2553 | State.regs[OP[0]+1] = tmp & 0xffff; | |
2554 | State.F0 = 0; | |
2555 | } | |
87178dbd | 2556 | trace_output (OP_DREG); |
2934d1c9 MH |
2557 | } |
2558 | ||
2559 | /* subac3s */ | |
2560 | void | |
2561 | OP_17001002 () | |
2562 | { | |
4f425a32 | 2563 | int64 tmp; |
87178dbd MM |
2564 | |
2565 | trace_input ("subac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM); | |
4f425a32 MH |
2566 | State.F1 = State.F0; |
2567 | tmp = SEXT40(State.a[OP[1]]) - SEXT40(State.a[OP[2]]); | |
2568 | if ( tmp > MAX32) | |
2569 | { | |
2570 | State.regs[OP[0]] = 0x7fff; | |
2571 | State.regs[OP[0]+1] = 0xffff; | |
2572 | State.F0 = 1; | |
2573 | } | |
2574 | else if (tmp < MIN32) | |
2575 | { | |
2576 | State.regs[OP[0]] = 0x8000; | |
2577 | State.regs[OP[0]+1] = 0; | |
2578 | State.F0 = 1; | |
2579 | } | |
2580 | else | |
2581 | { | |
2582 | State.regs[OP[0]] = (tmp >> 16) & 0xffff; | |
2583 | State.regs[OP[0]+1] = tmp & 0xffff; | |
2584 | State.F0 = 0; | |
2585 | } | |
87178dbd | 2586 | trace_output (OP_DREG); |
2934d1c9 MH |
2587 | } |
2588 | ||
2589 | /* subi */ | |
2590 | void | |
2591 | OP_1 () | |
2592 | { | |
70ee56c5 | 2593 | unsigned tmp; |
4f425a32 MH |
2594 | if (OP[1] == 0) |
2595 | OP[1] = 16; | |
87178dbd MM |
2596 | |
2597 | trace_input ("subi", OP_REG, OP_CONSTANT16, OP_VOID); | |
70ee56c5 | 2598 | /* see ../common/sim-alu.h for a more extensive discussion on how to |
51b057f2 AC |
2599 | compute the carry/overflow bits. */ |
2600 | /* since OP[1] is never <= 0, -OP[1] == ~OP[1]+1 can never overflow */ | |
70ee56c5 AC |
2601 | tmp = ((unsigned)(unsigned16) State.regs[OP[0]] |
2602 | + (unsigned)(unsigned16) ( - OP[1])); | |
2603 | State.C = (tmp >= (1 << 16)); | |
2604 | State.regs[OP[0]] = tmp; | |
87178dbd | 2605 | trace_output (OP_REG); |
2934d1c9 MH |
2606 | } |
2607 | ||
2608 | /* trap */ | |
2609 | void | |
2610 | OP_5F00 () | |
2611 | { | |
a5719092 | 2612 | trace_input ("trap", OP_CONSTANT4, OP_VOID, OP_VOID); |
87178dbd | 2613 | trace_output (OP_VOID); |
8918b3a7 | 2614 | |
63a91cfb | 2615 | switch (OP[0]) |
2934d1c9 | 2616 | { |
63a91cfb | 2617 | default: |
19d44375 | 2618 | #if 0 |
7eebfc62 | 2619 | (*d10v_callback->printf_filtered) (d10v_callback, "Unknown trap code %d\n", OP[0]); |
63a91cfb | 2620 | State.exception = SIGILL; |
19d44375 MM |
2621 | #else |
2622 | /* Use any other traps for batch debugging. */ | |
2623 | { | |
2624 | int i; | |
2625 | static int first_time = 1; | |
2626 | ||
2627 | if (first_time) | |
2628 | { | |
2629 | first_time = 0; | |
2630 | (*d10v_callback->printf_filtered) (d10v_callback, "Trap # PC "); | |
2631 | for (i = 0; i < 16; i++) | |
2632 | (*d10v_callback->printf_filtered) (d10v_callback, " %sr%d", (i > 9) ? "" : " ", i); | |
2633 | (*d10v_callback->printf_filtered) (d10v_callback, " a0 a1 f0 f1 c\n"); | |
2634 | } | |
2635 | ||
87e43259 | 2636 | (*d10v_callback->printf_filtered) (d10v_callback, "Trap %2d 0x%.4x:", (int)OP[0], (int)PC); |
19d44375 | 2637 | |
87e43259 AC |
2638 | for (i = 0; i < 16; i++) |
2639 | (*d10v_callback->printf_filtered) (d10v_callback, " %.4x", (int) State.regs[i]); | |
19d44375 | 2640 | |
87e43259 AC |
2641 | for (i = 0; i < 2; i++) |
2642 | (*d10v_callback->printf_filtered) (d10v_callback, " %.2x%.8lx", | |
2643 | ((int)(State.a[i] >> 32) & 0xff), | |
2644 | ((unsigned long)State.a[i]) & 0xffffffff); | |
19d44375 | 2645 | |
87e43259 AC |
2646 | (*d10v_callback->printf_filtered) (d10v_callback, " %d %d %d\n", |
2647 | State.F0 != 0, State.F1 != 0, State.C != 0); | |
2648 | (*d10v_callback->flush_stdout) (d10v_callback); | |
2649 | break; | |
2650 | } | |
19d44375 | 2651 | #endif |
63a91cfb | 2652 | |
87e43259 AC |
2653 | case 0: /* old system call trap, to be deleted */ |
2654 | case 15: /* new system call trap */ | |
2655 | /* Trap 15 is used for simulating low-level I/O */ | |
63a91cfb | 2656 | { |
63a91cfb MM |
2657 | errno = 0; |
2658 | ||
2659 | /* Registers passed to trap 0 */ | |
2660 | ||
65c0d7de MA |
2661 | #define FUNC State.regs[6] /* function number */ |
2662 | #define PARM1 State.regs[2] /* optional parm 1 */ | |
2663 | #define PARM2 State.regs[3] /* optional parm 2 */ | |
2664 | #define PARM3 State.regs[4] /* optional parm 3 */ | |
2665 | #define PARM4 State.regs[5] /* optional parm 3 */ | |
63a91cfb MM |
2666 | |
2667 | /* Registers set by trap 0 */ | |
2668 | ||
65c0d7de MA |
2669 | #define RETVAL State.regs[2] /* return value */ |
2670 | #define RETVAL_HIGH State.regs[2] /* return value */ | |
2671 | #define RETVAL_LOW State.regs[3] /* return value */ | |
2672 | #define RETERR State.regs[4] /* return error code */ | |
63a91cfb MM |
2673 | |
2674 | /* Turn a pointer in a register into a pointer into real memory. */ | |
2675 | ||
c422ecc7 | 2676 | #define MEMPTR(x) ((char *)(dmem_addr(x))) |
63a91cfb MM |
2677 | |
2678 | switch (FUNC) | |
2679 | { | |
2680 | #if !defined(__GO32__) && !defined(_WIN32) | |
63a91cfb MM |
2681 | case SYS_fork: |
2682 | RETVAL = fork (); | |
8918b3a7 MM |
2683 | trace_input ("<fork>", OP_VOID, OP_VOID, OP_VOID); |
2684 | trace_output (OP_R2); | |
63a91cfb | 2685 | break; |
8918b3a7 | 2686 | |
57bc1a72 MM |
2687 | case SYS_getpid: |
2688 | trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID); | |
2689 | RETVAL = getpid (); | |
2690 | trace_output (OP_R2); | |
2691 | break; | |
2692 | ||
2693 | case SYS_kill: | |
2694 | trace_input ("<kill>", OP_REG, OP_REG, OP_VOID); | |
2695 | if (PARM1 == getpid ()) | |
2696 | { | |
2697 | trace_output (OP_VOID); | |
2698 | State.exception = PARM2; | |
2699 | } | |
2700 | else | |
2701 | { | |
2702 | int os_sig = -1; | |
2703 | switch (PARM2) | |
2704 | { | |
2705 | #ifdef SIGHUP | |
2706 | case 1: os_sig = SIGHUP; break; | |
2707 | #endif | |
2708 | #ifdef SIGINT | |
2709 | case 2: os_sig = SIGINT; break; | |
2710 | #endif | |
2711 | #ifdef SIGQUIT | |
2712 | case 3: os_sig = SIGQUIT; break; | |
2713 | #endif | |
2714 | #ifdef SIGILL | |
2715 | case 4: os_sig = SIGILL; break; | |
2716 | #endif | |
2717 | #ifdef SIGTRAP | |
2718 | case 5: os_sig = SIGTRAP; break; | |
2719 | #endif | |
2720 | #ifdef SIGABRT | |
2721 | case 6: os_sig = SIGABRT; break; | |
2722 | #elif defined(SIGIOT) | |
2723 | case 6: os_sig = SIGIOT; break; | |
2724 | #endif | |
2725 | #ifdef SIGEMT | |
2726 | case 7: os_sig = SIGEMT; break; | |
2727 | #endif | |
2728 | #ifdef SIGFPE | |
2729 | case 8: os_sig = SIGFPE; break; | |
2730 | #endif | |
2731 | #ifdef SIGKILL | |
2732 | case 9: os_sig = SIGKILL; break; | |
2733 | #endif | |
2734 | #ifdef SIGBUS | |
2735 | case 10: os_sig = SIGBUS; break; | |
2736 | #endif | |
2737 | #ifdef SIGSEGV | |
2738 | case 11: os_sig = SIGSEGV; break; | |
2739 | #endif | |
2740 | #ifdef SIGSYS | |
2741 | case 12: os_sig = SIGSYS; break; | |
2742 | #endif | |
2743 | #ifdef SIGPIPE | |
2744 | case 13: os_sig = SIGPIPE; break; | |
2745 | #endif | |
2746 | #ifdef SIGALRM | |
2747 | case 14: os_sig = SIGALRM; break; | |
2748 | #endif | |
2749 | #ifdef SIGTERM | |
2750 | case 15: os_sig = SIGTERM; break; | |
2751 | #endif | |
2752 | #ifdef SIGURG | |
2753 | case 16: os_sig = SIGURG; break; | |
2754 | #endif | |
2755 | #ifdef SIGSTOP | |
2756 | case 17: os_sig = SIGSTOP; break; | |
2757 | #endif | |
2758 | #ifdef SIGTSTP | |
2759 | case 18: os_sig = SIGTSTP; break; | |
2760 | #endif | |
2761 | #ifdef SIGCONT | |
2762 | case 19: os_sig = SIGCONT; break; | |
2763 | #endif | |
2764 | #ifdef SIGCHLD | |
2765 | case 20: os_sig = SIGCHLD; break; | |
2766 | #elif defined(SIGCLD) | |
2767 | case 20: os_sig = SIGCLD; break; | |
2768 | #endif | |
2769 | #ifdef SIGTTIN | |
2770 | case 21: os_sig = SIGTTIN; break; | |
2771 | #endif | |
2772 | #ifdef SIGTTOU | |
2773 | case 22: os_sig = SIGTTOU; break; | |
2774 | #endif | |
2775 | #ifdef SIGIO | |
2776 | case 23: os_sig = SIGIO; break; | |
2777 | #elif defined (SIGPOLL) | |
2778 | case 23: os_sig = SIGPOLL; break; | |
2779 | #endif | |
2780 | #ifdef SIGXCPU | |
2781 | case 24: os_sig = SIGXCPU; break; | |
2782 | #endif | |
2783 | #ifdef SIGXFSZ | |
2784 | case 25: os_sig = SIGXFSZ; break; | |
2785 | #endif | |
2786 | #ifdef SIGVTALRM | |
2787 | case 26: os_sig = SIGVTALRM; break; | |
2788 | #endif | |
2789 | #ifdef SIGPROF | |
2790 | case 27: os_sig = SIGPROF; break; | |
2791 | #endif | |
2792 | #ifdef SIGWINCH | |
2793 | case 28: os_sig = SIGWINCH; break; | |
2794 | #endif | |
2795 | #ifdef SIGLOST | |
2796 | case 29: os_sig = SIGLOST; break; | |
2797 | #endif | |
2798 | #ifdef SIGUSR1 | |
2799 | case 30: os_sig = SIGUSR1; break; | |
2800 | #endif | |
2801 | #ifdef SIGUSR2 | |
2802 | case 31: os_sig = SIGUSR2; break; | |
2803 | #endif | |
2804 | } | |
2805 | ||
2806 | if (os_sig == -1) | |
2807 | { | |
2808 | trace_output (OP_VOID); | |
2809 | (*d10v_callback->printf_filtered) (d10v_callback, "Unknown signal %d\n", PARM2); | |
fd435e9f | 2810 | (*d10v_callback->flush_stdout) (d10v_callback); |
57bc1a72 MM |
2811 | State.exception = SIGILL; |
2812 | } | |
2813 | else | |
2814 | { | |
2815 | RETVAL = kill (PARM1, PARM2); | |
2816 | trace_output (OP_R2); | |
2817 | } | |
2818 | } | |
2819 | break; | |
2820 | ||
63a91cfb MM |
2821 | case SYS_execve: |
2822 | RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), | |
2823 | (char **)MEMPTR (PARM3)); | |
8918b3a7 MM |
2824 | trace_input ("<execve>", OP_R2, OP_R3, OP_R4); |
2825 | trace_output (OP_R2); | |
63a91cfb | 2826 | break; |
8918b3a7 | 2827 | |
87e43259 | 2828 | #ifdef SYS_execv |
63a91cfb MM |
2829 | case SYS_execv: |
2830 | RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL); | |
8918b3a7 MM |
2831 | trace_input ("<execv>", OP_R2, OP_R3, OP_VOID); |
2832 | trace_output (OP_R2); | |
63a91cfb | 2833 | break; |
87e43259 | 2834 | #endif |
8918b3a7 | 2835 | |
63a91cfb MM |
2836 | case SYS_pipe: |
2837 | { | |
2838 | reg_t buf; | |
2839 | int host_fd[2]; | |
2840 | ||
2841 | buf = PARM1; | |
2842 | RETVAL = pipe (host_fd); | |
2843 | SW (buf, host_fd[0]); | |
2844 | buf += sizeof(uint16); | |
2845 | SW (buf, host_fd[1]); | |
8918b3a7 MM |
2846 | trace_input ("<pipe>", OP_R2, OP_VOID, OP_VOID); |
2847 | trace_output (OP_R2); | |
63a91cfb MM |
2848 | } |
2849 | break; | |
8918b3a7 | 2850 | |
87e43259 | 2851 | #ifdef SYS_wait |
63a91cfb MM |
2852 | case SYS_wait: |
2853 | { | |
2854 | int status; | |
2855 | ||
2856 | RETVAL = wait (&status); | |
8918b3a7 MM |
2857 | if (PARM1) |
2858 | SW (PARM1, status); | |
2859 | trace_input ("<wait>", OP_R2, OP_VOID, OP_VOID); | |
2860 | trace_output (OP_R2); | |
63a91cfb MM |
2861 | } |
2862 | break; | |
87e43259 | 2863 | #endif |
57bc1a72 MM |
2864 | #else |
2865 | case SYS_getpid: | |
2866 | trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID); | |
2867 | RETVAL = 1; | |
2868 | trace_output (OP_R2); | |
2869 | break; | |
2870 | ||
2871 | case SYS_kill: | |
2872 | trace_input ("<kill>", OP_REG, OP_REG, OP_VOID); | |
2873 | trace_output (OP_VOID); | |
2874 | State.exception = PARM2; | |
2875 | break; | |
63a91cfb | 2876 | #endif |
8918b3a7 | 2877 | |
63a91cfb MM |
2878 | case SYS_read: |
2879 | RETVAL = d10v_callback->read (d10v_callback, PARM1, MEMPTR (PARM2), | |
2880 | PARM3); | |
8918b3a7 MM |
2881 | trace_input ("<read>", OP_R2, OP_R3, OP_R4); |
2882 | trace_output (OP_R2); | |
63a91cfb | 2883 | break; |
8918b3a7 | 2884 | |
63a91cfb MM |
2885 | case SYS_write: |
2886 | if (PARM1 == 1) | |
2887 | RETVAL = (int)d10v_callback->write_stdout (d10v_callback, | |
2888 | MEMPTR (PARM2), PARM3); | |
2889 | else | |
2890 | RETVAL = (int)d10v_callback->write (d10v_callback, PARM1, | |
2891 | MEMPTR (PARM2), PARM3); | |
8918b3a7 MM |
2892 | trace_input ("<write>", OP_R2, OP_R3, OP_R4); |
2893 | trace_output (OP_R2); | |
63a91cfb | 2894 | break; |
8918b3a7 | 2895 | |
63a91cfb | 2896 | case SYS_lseek: |
65c0d7de MA |
2897 | { |
2898 | unsigned long ret = d10v_callback->lseek (d10v_callback, PARM1, | |
2899 | (((unsigned long)PARM2) << 16) || (unsigned long)PARM3, | |
2900 | PARM4); | |
2901 | RETVAL_HIGH = ret >> 16; | |
2902 | RETVAL_LOW = ret & 0xffff; | |
2903 | } | |
8918b3a7 MM |
2904 | trace_input ("<lseek>", OP_R2, OP_R3, OP_R4); |
2905 | trace_output (OP_R2R3); | |
63a91cfb | 2906 | break; |
8918b3a7 | 2907 | |
63a91cfb MM |
2908 | case SYS_close: |
2909 | RETVAL = d10v_callback->close (d10v_callback, PARM1); | |
8918b3a7 MM |
2910 | trace_input ("<close>", OP_R2, OP_VOID, OP_VOID); |
2911 | trace_output (OP_R2); | |
63a91cfb | 2912 | break; |
8918b3a7 | 2913 | |
63a91cfb MM |
2914 | case SYS_open: |
2915 | RETVAL = d10v_callback->open (d10v_callback, MEMPTR (PARM1), PARM2); | |
8918b3a7 MM |
2916 | trace_input ("<open>", OP_R2, OP_R3, OP_R4); |
2917 | trace_output (OP_R2); | |
2918 | trace_input ("<open>", OP_R2, OP_R3, OP_R4); | |
2919 | trace_output (OP_R2); | |
63a91cfb | 2920 | break; |
8918b3a7 | 2921 | |
63a91cfb | 2922 | case SYS_exit: |
a49a15ad | 2923 | State.exception = SIG_D10V_EXIT; |
8918b3a7 MM |
2924 | trace_input ("<exit>", OP_R2, OP_VOID, OP_VOID); |
2925 | trace_output (OP_VOID); | |
63a91cfb | 2926 | break; |
63a91cfb | 2927 | |
8719be26 | 2928 | case SYS_stat: |
63a91cfb MM |
2929 | /* stat system call */ |
2930 | { | |
2931 | struct stat host_stat; | |
2932 | reg_t buf; | |
2933 | ||
2934 | RETVAL = stat (MEMPTR (PARM1), &host_stat); | |
2935 | ||
2936 | buf = PARM2; | |
2937 | ||
2938 | /* The hard-coded offsets and sizes were determined by using | |
2939 | * the D10V compiler on a test program that used struct stat. | |
2940 | */ | |
2941 | SW (buf, host_stat.st_dev); | |
2942 | SW (buf+2, host_stat.st_ino); | |
2943 | SW (buf+4, host_stat.st_mode); | |
2944 | SW (buf+6, host_stat.st_nlink); | |
2945 | SW (buf+8, host_stat.st_uid); | |
2946 | SW (buf+10, host_stat.st_gid); | |
2947 | SW (buf+12, host_stat.st_rdev); | |
2948 | SLW (buf+16, host_stat.st_size); | |
2949 | SLW (buf+20, host_stat.st_atime); | |
2950 | SLW (buf+28, host_stat.st_mtime); | |
2951 | SLW (buf+36, host_stat.st_ctime); | |
2952 | } | |
8918b3a7 MM |
2953 | trace_input ("<stat>", OP_R2, OP_R3, OP_VOID); |
2954 | trace_output (OP_R2); | |
63a91cfb | 2955 | break; |
63a91cfb | 2956 | |
63a91cfb MM |
2957 | case SYS_chown: |
2958 | RETVAL = chown (MEMPTR (PARM1), PARM2, PARM3); | |
8918b3a7 MM |
2959 | trace_input ("<chown>", OP_R2, OP_R3, OP_R4); |
2960 | trace_output (OP_R2); | |
63a91cfb | 2961 | break; |
8918b3a7 | 2962 | |
63a91cfb MM |
2963 | case SYS_chmod: |
2964 | RETVAL = chmod (MEMPTR (PARM1), PARM2); | |
8918b3a7 MM |
2965 | trace_input ("<chmod>", OP_R2, OP_R3, OP_R4); |
2966 | trace_output (OP_R2); | |
63a91cfb | 2967 | break; |
8918b3a7 | 2968 | |
87e43259 | 2969 | #ifdef SYS_utime |
63a91cfb MM |
2970 | case SYS_utime: |
2971 | /* Cast the second argument to void *, to avoid type mismatch | |
2972 | if a prototype is present. */ | |
2973 | RETVAL = utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2)); | |
8918b3a7 MM |
2974 | trace_input ("<utime>", OP_R2, OP_R3, OP_R4); |
2975 | trace_output (OP_R2); | |
2976 | break; | |
87e43259 | 2977 | #endif |
8918b3a7 | 2978 | |
87e43259 | 2979 | #ifdef SYS_time |
8918b3a7 MM |
2980 | case SYS_time: |
2981 | { | |
2982 | unsigned long ret = time (PARM1 ? MEMPTR (PARM1) : NULL); | |
2983 | RETVAL_HIGH = ret >> 16; | |
2984 | RETVAL_LOW = ret & 0xffff; | |
2985 | } | |
2986 | trace_input ("<time>", OP_R2, OP_R3, OP_R4); | |
2987 | trace_output (OP_R2R3); | |
63a91cfb | 2988 | break; |
87e43259 | 2989 | #endif |
8918b3a7 | 2990 | |
63a91cfb MM |
2991 | default: |
2992 | abort (); | |
2993 | } | |
87e43259 | 2994 | RETERR = (RETVAL == (uint16) -1) ? d10v_callback->get_errno(d10v_callback) : 0; |
63a91cfb MM |
2995 | break; |
2996 | } | |
2934d1c9 MH |
2997 | } |
2998 | } | |
2999 | ||
3000 | /* tst0i */ | |
3001 | void | |
3002 | OP_7000000 () | |
3003 | { | |
87178dbd | 3004 | trace_input ("tst0i", OP_REG, OP_CONSTANT16, OP_VOID); |
4c38885c | 3005 | State.F1 = State.F0; |
4f425a32 | 3006 | State.F0 = (State.regs[OP[0]] & OP[1]) ? 1 : 0; |
87178dbd | 3007 | trace_output (OP_FLAG); |
2934d1c9 MH |
3008 | } |
3009 | ||
3010 | /* tst1i */ | |
3011 | void | |
3012 | OP_F000000 () | |
3013 | { | |
87178dbd | 3014 | trace_input ("tst1i", OP_REG, OP_CONSTANT16, OP_VOID); |
4c38885c | 3015 | State.F1 = State.F0; |
4f425a32 | 3016 | State.F0 = (~(State.regs[OP[0]]) & OP[1]) ? 1 : 0; |
87178dbd | 3017 | trace_output (OP_FLAG); |
2934d1c9 MH |
3018 | } |
3019 | ||
3020 | /* wait */ | |
3021 | void | |
3022 | OP_5F80 () | |
3023 | { | |
87178dbd | 3024 | trace_input ("wait", OP_VOID, OP_VOID, OP_VOID); |
4c38885c | 3025 | State.IE = 1; |
87178dbd | 3026 | trace_output (OP_VOID); |
2934d1c9 MH |
3027 | } |
3028 | ||
3029 | /* xor */ | |
3030 | void | |
3031 | OP_A00 () | |
3032 | { | |
87178dbd | 3033 | trace_input ("xor", OP_REG, OP_REG, OP_VOID); |
4c38885c | 3034 | State.regs[OP[0]] ^= State.regs[OP[1]]; |
87178dbd | 3035 | trace_output (OP_REG); |
2934d1c9 MH |
3036 | } |
3037 | ||
3038 | /* xor3 */ | |
3039 | void | |
3040 | OP_5000000 () | |
3041 | { | |
87178dbd | 3042 | trace_input ("xor3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16); |
4c38885c | 3043 | State.regs[OP[0]] = State.regs[OP[1]] ^ OP[2]; |
87178dbd | 3044 | trace_output (OP_REG); |
2934d1c9 MH |
3045 | } |
3046 |