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* m32r/tm-m32r.h (TARGET_M32R): Define, for wingdb.
[deliverable/binutils-gdb.git] / sim / d10v / simops.c
CommitLineData
4f425a32 1#include <signal.h>
63a91cfb
MM		 2#include <errno.h>
3#include <sys/types.h>
4#include <sys/stat.h>
5#include <unistd.h>
6
2934d1c9
MH		 7#include "d10v_sim.h"
8#include "simops.h"
8719be26 9#include "sys/syscall.h"
2934d1c9 10
c422ecc7
MH		 11extern char *strrchr ();
12
87178dbd
MM		 13enum op_types {
14 OP_VOID,
15 OP_REG,
16 OP_REG_OUTPUT,
17 OP_DREG,
18 OP_DREG_OUTPUT,
19 OP_ACCUM,
20 OP_ACCUM_OUTPUT,
21 OP_ACCUM_REVERSE,
22 OP_CR,
23 OP_CR_OUTPUT,
24 OP_CR_REVERSE,
25 OP_FLAG,
60fc5b72 26 OP_FLAG_OUTPUT,
87178dbd 27 OP_CONSTANT16,
a18cb100 28 OP_CONSTANT8,
87178dbd
MM		 29 OP_CONSTANT3,
30 OP_CONSTANT4,
31 OP_MEMREF,
32 OP_MEMREF2,
33 OP_POSTDEC,
34 OP_POSTINC,
a18cb100
MM		 35 OP_PREDEC,
36 OP_R2,
8918b3a7
MM		 37 OP_R3,
38 OP_R4,
39 OP_R2R3
87178dbd
MM		 40};
41
7eebfc62 42#ifdef DEBUG
a49a15ad
MM		 43static void trace_input_func PARAMS ((char *name,
44 enum op_types in1,
45 enum op_types in2,
46 enum op_types in3));
87178dbd 47
a49a15ad
MM		 48#define trace_input(name, in1, in2, in3) do { if (d10v_debug) trace_input_func (name, in1, in2, in3); } while (0)
49
50static void trace_output_func PARAMS ((enum op_types result));
51
52#define trace_output(result) do { if (d10v_debug) trace_output_func (result); } while (0)
53
87178dbd 54#ifndef SIZE_INSTRUCTION
a49a15ad 55#define SIZE_INSTRUCTION 8
87178dbd
MM		 56#endif
57
58#ifndef SIZE_OPERANDS
a49a15ad 59#define SIZE_OPERANDS 18
87178dbd
MM		 60#endif
61
62#ifndef SIZE_VALUES
63#define SIZE_VALUES 13
64#endif
65
a49a15ad
MM		 66#ifndef SIZE_LOCATION
67#define SIZE_LOCATION 20
68#endif
69
891513ee
MM		 70#ifndef SIZE_PC
71#define SIZE_PC 6
72#endif
73
74#ifndef SIZE_LINE_NUMBER
75#define SIZE_LINE_NUMBER 4
76#endif
77
87178dbd 78static void
a49a15ad 79trace_input_func (name, in1, in2, in3)
87178dbd
MM		 80 char *name;
81 enum op_types in1;
82 enum op_types in2;
83 enum op_types in3;
84{
85 char *comma;
86 enum op_types in[3];
87 int i;
a49a15ad 88 char buf[1024];
87178dbd
MM		 89 char *p;
90 long tmp;
91 char *type;
a49a15ad
MM		 92 const char *filename;
93 const char *functionname;
94 unsigned int linenumber;
95 bfd_vma byte_pc;
87178dbd 96
7eebfc62
MM		 97 if ((d10v_debug & DEBUG_TRACE) == 0)
98 return;
99
87178dbd
MM		 100 switch (State.ins_type)
101 {
102 default:
103 case INS_UNKNOWN: type = " ?"; break;
104 case INS_LEFT: type = " L"; break;
105 case INS_RIGHT: type = " R"; break;
106 case INS_LEFT_PARALLEL: type = "*L"; break;
107 case INS_RIGHT_PARALLEL: type = "*R"; break;
c422ecc7
MH		 108 case INS_LEFT_COND_TEST: type = "?L"; break;
109 case INS_RIGHT_COND_TEST: type = "?R"; break;
110 case INS_LEFT_COND_EXE: type = "&L"; break;
111 case INS_RIGHT_COND_EXE: type = "&R"; break;
87178dbd
MM		 112 case INS_LONG: type = " B"; break;
113 }
114
a49a15ad
MM		 115 if ((d10v_debug & DEBUG_LINE_NUMBER) == 0)
116 (*d10v_callback->printf_filtered) (d10v_callback,
f061ddf6 117 "0x%.*x %s: %-*s ",
891513ee
MM		 118 SIZE_PC, (unsigned)PC,
119 type,
a49a15ad
MM		 120 SIZE_INSTRUCTION, name);
121
122 else
123 {
891513ee 124 buf[0] = '\0';
b30cdd35 125 byte_pc = decode_pc ();
a49a15ad
MM		 126 if (text && byte_pc >= text_start && byte_pc < text_end)
127 {
128 filename = (const char *)0;
129 functionname = (const char *)0;
130 linenumber = 0;
0535fa1a 131 if (bfd_find_nearest_line (exec_bfd, text, (struct symbol_cache_entry **)0, byte_pc - text_start,
a49a15ad
MM		 132 &filename, &functionname, &linenumber))
133 {
134 p = buf;
135 if (linenumber)
136 {
891513ee 137 sprintf (p, "#%-*d ", SIZE_LINE_NUMBER, linenumber);
a49a15ad
MM		 138 p += strlen (p);
139 }
891513ee
MM		 140 else
141 {
142 sprintf (p, "%-*s ", SIZE_LINE_NUMBER+1, "---");
143 p += SIZE_LINE_NUMBER+2;
144 }
a49a15ad
MM		 145
146 if (functionname)
147 {
148 sprintf (p, "%s ", functionname);
149 p += strlen (p);
150 }
151 else if (filename)
152 {
c422ecc7 153 char *q = strrchr (filename, '/');
a49a15ad
MM		 154 sprintf (p, "%s ", (q) ? q+1 : filename);
155 p += strlen (p);
156 }
157
158 if (*p == ' ')
159 *p = '\0';
160 }
161 }
162
163 (*d10v_callback->printf_filtered) (d10v_callback,
f061ddf6 164 "0x%.*x %s: %-*.*s %-*s ",
891513ee
MM		 165 SIZE_PC, (unsigned)PC,
166 type,
a49a15ad
MM		 167 SIZE_LOCATION, SIZE_LOCATION, buf,
168 SIZE_INSTRUCTION, name);
169 }
87178dbd
MM		 170
171 in[0] = in1;
172 in[1] = in2;
173 in[2] = in3;
174 comma = "";
175 p = buf;
176 for (i = 0; i < 3; i++)
177 {
178 switch (in[i])
179 {
180 case OP_VOID:
a18cb100
MM		 181 case OP_R2:
182 case OP_R3:
8918b3a7 183 case OP_R4:
c422ecc7 184 case OP_R2R3:
87178dbd
MM		 185 break;
186
187 case OP_REG:
188 case OP_REG_OUTPUT:
189 case OP_DREG:
190 case OP_DREG_OUTPUT:
191 sprintf (p, "%sr%d", comma, OP[i]);
192 p += strlen (p);
193 comma = ",";
194 break;
195
196 case OP_CR:
197 case OP_CR_OUTPUT:
198 case OP_CR_REVERSE:
199 sprintf (p, "%scr%d", comma, OP[i]);
200 p += strlen (p);
201 comma = ",";
202 break;
203
204 case OP_ACCUM:
205 case OP_ACCUM_OUTPUT:
206 case OP_ACCUM_REVERSE:
207 sprintf (p, "%sa%d", comma, OP[i]);
208 p += strlen (p);
209 comma = ",";
210 break;
211
212 case OP_CONSTANT16:
213 sprintf (p, "%s%d", comma, OP[i]);
214 p += strlen (p);
215 comma = ",";
216 break;
217
a18cb100
MM		 218 case OP_CONSTANT8:
219 sprintf (p, "%s%d", comma, SEXT8(OP[i]));
220 p += strlen (p);
221 comma = ",";
222 break;
223
87178dbd
MM		 224 case OP_CONSTANT4:
225 sprintf (p, "%s%d", comma, SEXT4(OP[i]));
226 p += strlen (p);
227 comma = ",";
228 break;
229
230 case OP_CONSTANT3:
231 sprintf (p, "%s%d", comma, SEXT3(OP[i]));
232 p += strlen (p);
233 comma = ",";
234 break;
235
236 case OP_MEMREF:
237 sprintf (p, "%s@r%d", comma, OP[i]);
238 p += strlen (p);
239 comma = ",";
240 break;
241
242 case OP_MEMREF2:
243 sprintf (p, "%s@(%d,r%d)", comma, (int16)OP[i], OP[i+1]);
244 p += strlen (p);
245 comma = ",";
246 break;
247
248 case OP_POSTINC:
249 sprintf (p, "%s@r%d+", comma, OP[i]);
250 p += strlen (p);
251 comma = ",";
252 break;
253
254 case OP_POSTDEC:
255 sprintf (p, "%s@r%d-", comma, OP[i]);
256 p += strlen (p);
257 comma = ",";
258 break;
259
260 case OP_PREDEC:
261 sprintf (p, "%s@-r%d", comma, OP[i]);
262 p += strlen (p);
263 comma = ",";
264 break;
265
266 case OP_FLAG:
60fc5b72 267 case OP_FLAG_OUTPUT:
87178dbd
MM		 268 if (OP[i] == 0)
269 sprintf (p, "%sf0", comma);
270
271 else if (OP[i] == 1)
272 sprintf (p, "%sf1", comma);
273
274 else
60fc5b72 275 sprintf (p, "%sc", comma);
87178dbd
MM		 276
277 p += strlen (p);
278 comma = ",";
279 break;
280 }
281 }
282
7eebfc62
MM		 283 if ((d10v_debug & DEBUG_VALUES) == 0)
284 {
285 *p++ = '\n';
286 *p = '\0';
287 (*d10v_callback->printf_filtered) (d10v_callback, "%s", buf);
288 }
289 else
290 {
291 *p = '\0';
292 (*d10v_callback->printf_filtered) (d10v_callback, "%-*s", SIZE_OPERANDS, buf);
87178dbd 293
7eebfc62
MM		 294 p = buf;
295 for (i = 0; i < 3; i++)
296 {
297 buf[0] = '\0';
298 switch (in[i])
299 {
300 case OP_VOID:
301 (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "");
302 break;
303
304 case OP_REG_OUTPUT:
305 case OP_DREG_OUTPUT:
306 case OP_CR_OUTPUT:
307 case OP_ACCUM_OUTPUT:
60fc5b72 308 case OP_FLAG_OUTPUT:
7eebfc62
MM		 309 (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "---");
310 break;
311
312 case OP_REG:
313 case OP_MEMREF:
314 case OP_POSTDEC:
315 case OP_POSTINC:
316 case OP_PREDEC:
317 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
318 (uint16)State.regs[OP[i]]);
319 break;
320
321 case OP_DREG:
322 tmp = (long)((((uint32) State.regs[OP[i]]) << 16) | ((uint32) State.regs[OP[i]+1]));
323 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.8lx", SIZE_VALUES-10, "", tmp);
324 break;
325
326 case OP_CR:
327 case OP_CR_REVERSE:
328 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
329 (uint16)State.cregs[OP[i]]);
330 break;
331
332 case OP_ACCUM:
333 case OP_ACCUM_REVERSE:
334 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.2x%.8lx", SIZE_VALUES-12, "",
335 ((int)(State.a[OP[i]] >> 32) & 0xff),
336 ((unsigned long)State.a[OP[i]]) & 0xffffffff);
337 break;
338
339 case OP_CONSTANT16:
340 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
341 (uint16)OP[i]);
342 break;
343
344 case OP_CONSTANT4:
345 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
346 (uint16)SEXT4(OP[i]));
347 break;
348
a18cb100
MM		 349 case OP_CONSTANT8:
350 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
351 (uint16)SEXT8(OP[i]));
352 break;
353
7eebfc62
MM		 354 case OP_CONSTANT3:
355 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
356 (uint16)SEXT3(OP[i]));
357 break;
358
359 case OP_FLAG:
360 if (OP[i] == 0)
361 (*d10v_callback->printf_filtered) (d10v_callback, "%*sF0 = %d", SIZE_VALUES-6, "",
362 State.F0 != 0);
363
364 else if (OP[i] == 1)
365 (*d10v_callback->printf_filtered) (d10v_callback, "%*sF1 = %d", SIZE_VALUES-6, "",
366 State.F1 != 0);
367
368 else
369 (*d10v_callback->printf_filtered) (d10v_callback, "%*sC = %d", SIZE_VALUES-5, "",
370 State.C != 0);
371
372 break;
373
374 case OP_MEMREF2:
375 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
376 (uint16)OP[i]);
377 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
378 (uint16)State.regs[OP[++i]]);
379 break;
a18cb100
MM		 380
381 case OP_R2:
382 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
383 (uint16)State.regs[2]);
384 break;
385
386 case OP_R3:
387 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
388 (uint16)State.regs[3]);
389 break;
8918b3a7
MM		 390
391 case OP_R4:
392 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
393 (uint16)State.regs[4]);
394 break;
c422ecc7
MH		 395
396 case OP_R2R3:
397 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
398 (uint16)State.regs[2]);
399 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
400 (uint16)State.regs[3]);
401 i++;
402 break;
7eebfc62
MM		 403 }
404 }
405 }
406}
87178dbd 407
7eebfc62 408static void
a49a15ad 409trace_output_func (result)
7eebfc62
MM		 410 enum op_types result;
411{
412 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
87178dbd 413 {
7eebfc62 414 long tmp;
87178dbd 415
7eebfc62
MM		 416 switch (result)
417 {
418 default:
419 putchar ('\n');
87178dbd
MM		 420 break;
421
422 case OP_REG:
7eebfc62
MM		 423 case OP_REG_OUTPUT:
424 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
425 (uint16)State.regs[OP[0]],
426 State.F0 != 0, State.F1 != 0, State.C != 0);
87178dbd
MM		 427 break;
428
429 case OP_DREG:
7eebfc62
MM		 430 case OP_DREG_OUTPUT:
431 tmp = (long)((((uint32) State.regs[OP[0]]) << 16) | ((uint32) State.regs[OP[0]+1]));
432 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-10, "", tmp,
433 State.F0 != 0, State.F1 != 0, State.C != 0);
87178dbd
MM		 434 break;
435
436 case OP_CR:
7eebfc62
MM		 437 case OP_CR_OUTPUT:
438 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
439 (uint16)State.cregs[OP[0]],
440 State.F0 != 0, State.F1 != 0, State.C != 0);
87178dbd
MM		 441 break;
442
7eebfc62
MM		 443 case OP_CR_REVERSE:
444 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
445 (uint16)State.cregs[OP[1]],
446 State.F0 != 0, State.F1 != 0, State.C != 0);
87178dbd
MM		 447 break;
448
7eebfc62
MM		 449 case OP_ACCUM:
450 case OP_ACCUM_OUTPUT:
069398aa 451 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-12, "",
7eebfc62
MM		 452 ((int)(State.a[OP[0]] >> 32) & 0xff),
453 ((unsigned long)State.a[OP[0]]) & 0xffffffff,
454 State.F0 != 0, State.F1 != 0, State.C != 0);
87178dbd
MM		 455 break;
456
7eebfc62 457 case OP_ACCUM_REVERSE:
069398aa 458 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-12, "",
7eebfc62
MM		 459 ((int)(State.a[OP[1]] >> 32) & 0xff),
460 ((unsigned long)State.a[OP[1]]) & 0xffffffff,
461 State.F0 != 0, State.F1 != 0, State.C != 0);
87178dbd
MM		 462 break;
463
464 case OP_FLAG:
60fc5b72 465 case OP_FLAG_OUTPUT:
7eebfc62
MM		 466 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s F0=%d F1=%d C=%d\n", SIZE_VALUES, "",
467 State.F0 != 0, State.F1 != 0, State.C != 0);
87178dbd 468 break;
8918b3a7
MM		 469
470 case OP_R2:
471 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
472 (uint16)State.regs[2],
473 State.F0 != 0, State.F1 != 0, State.C != 0);
474 break;
475
476 case OP_R2R3:
477 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-10, "",
478 (uint16)State.regs[2], (uint16)State.regs[3],
479 State.F0 != 0, State.F1 != 0, State.C != 0);
480 break;
87178dbd
MM		 481 }
482 }
87178dbd
MM		 483}
484
485#else
486#define trace_input(NAME, IN1, IN2, IN3)
487#define trace_output(RESULT)
488#endif
2934d1c9
MH		 489
490/* abs */
491void
492OP_4607 ()
493{
87178dbd 494 trace_input ("abs", OP_REG, OP_VOID, OP_VOID);
2934d1c9
MH		 495 State.F1 = State.F0;
496 if ((int16)(State.regs[OP[0]]) < 0)
497 {
498 State.regs[OP[0]] = -(int16)(State.regs[OP[0]]);
499 State.F0 = 1;
500 }
501 else
502 State.F0 = 0;
87178dbd 503 trace_output (OP_REG);
2934d1c9
MH		 504}
505
506/* abs */
507void
508OP_5607 ()
509{
510 int64 tmp;
511
87178dbd 512 trace_input ("abs", OP_ACCUM, OP_VOID, OP_VOID);
4f425a32
MH		 513 State.F1 = State.F0;
514 State.a[OP[0]] = SEXT40(State.a[OP[0]]);
515
4c38885c 516 if (State.a[OP[0]] < 0 )
2934d1c9 517 {
4c38885c 518 tmp = -State.a[OP[0]];
2934d1c9
MH		 519 if (State.ST)
520 {
4c38885c 521 if (tmp > MAX32)
2934d1c9 522 State.a[OP[0]] = MAX32;
4c38885c 523 else if (tmp < MIN32)
2934d1c9
MH		 524 State.a[OP[0]] = MIN32;
525 else
4f425a32 526 State.a[OP[0]] = tmp & MASK40;
2934d1c9
MH		 527 }
528 else
4f425a32 529 State.a[OP[0]] = tmp & MASK40;
2934d1c9
MH		 530 State.F0 = 1;
531 }
532 else
533 State.F0 = 0;
87178dbd 534 trace_output (OP_ACCUM);
2934d1c9
MH		 535}
536
537/* add */
538void
539OP_200 ()
540{
541 uint16 tmp = State.regs[OP[0]];
87178dbd 542 trace_input ("add", OP_REG, OP_REG, OP_VOID);
2934d1c9
MH		 543 State.regs[OP[0]] += State.regs[OP[1]];
544 if ( tmp > State.regs[OP[0]])
545 State.C = 1;
546 else
547 State.C = 0;
87178dbd 548 trace_output (OP_REG);
2934d1c9
MH		 549}
550
551/* add */
552void
553OP_1201 ()
554{
4c38885c 555 int64 tmp;
4f425a32 556 tmp = SEXT40(State.a[OP[0]]) + (SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]);
87178dbd
MM		 557
558 trace_input ("add", OP_ACCUM, OP_REG, OP_VOID);
4c38885c
MH		 559 if (State.ST)
560 {
561 if ( tmp > MAX32)
562 State.a[OP[0]] = MAX32;
563 else if ( tmp < MIN32)
564 State.a[OP[0]] = MIN32;
565 else
4f425a32 566 State.a[OP[0]] = tmp & MASK40;
4c38885c
MH		 567 }
568 else
4f425a32 569 State.a[OP[0]] = tmp & MASK40;
87178dbd 570 trace_output (OP_ACCUM);
2934d1c9
MH		 571}
572
573/* add */
574void
575OP_1203 ()
576{
4c38885c 577 int64 tmp;
4f425a32 578 tmp = SEXT40(State.a[OP[0]]) + SEXT40(State.a[OP[1]]);
87178dbd
MM		 579
580 trace_input ("add", OP_ACCUM, OP_ACCUM, OP_VOID);
4c38885c
MH		 581 if (State.ST)
582 {
583 if (tmp > MAX32)
584 State.a[OP[0]] = MAX32;
585 else if ( tmp < MIN32)
586 State.a[OP[0]] = MIN32;
587 else
4f425a32 588 State.a[OP[0]] = tmp & MASK40;
4c38885c
MH		 589 }
590 else
4f425a32 591 State.a[OP[0]] = tmp & MASK40;
87178dbd 592 trace_output (OP_ACCUM);
2934d1c9
MH		 593}
594
595/* add2w */
596void
597OP_1200 ()
598{
599 uint32 tmp;
600 uint32 tmp1 = (State.regs[OP[0]]) << 16 | State.regs[OP[0]+1];
601 uint32 tmp2 = (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
87178dbd
MM		 602
603 trace_input ("add2w", OP_DREG, OP_DREG, OP_VOID);
2934d1c9
MH		 604 tmp = tmp1 + tmp2;
605 if ( (tmp < tmp1) || (tmp < tmp2) )
606 State.C = 1;
607 else
608 State.C = 0;
609 State.regs[OP[0]] = tmp >> 16;
610 State.regs[OP[0]+1] = tmp & 0xFFFF;
87178dbd 611 trace_output (OP_DREG);
2934d1c9
MH		 612}
613
614/* add3 */
615void
616OP_1000000 ()
617{
618 uint16 tmp = State.regs[OP[0]];
2934d1c9 619 State.regs[OP[0]] = State.regs[OP[1]] + OP[2];
87178dbd
MM		 620
621 trace_input ("add3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
2934d1c9
MH		 622 if ( tmp > State.regs[OP[0]])
623 State.C = 1;
624 else
625 State.C = 0;
87178dbd 626 trace_output (OP_REG);
2934d1c9
MH		 627}
628
629/* addac3 */
630void
631OP_17000200 ()
632{
4c38885c 633 int64 tmp;
4f425a32 634 tmp = SEXT40(State.a[OP[2]]) + SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
87178dbd
MM		 635
636 trace_input ("addac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
4c38885c
MH		 637 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
638 State.regs[OP[0]+1] = tmp & 0xffff;
87178dbd 639 trace_output (OP_DREG);
2934d1c9
MH		 640}
641
642/* addac3 */
643void
644OP_17000202 ()
645{
4c38885c 646 int64 tmp;
4f425a32 647 tmp = SEXT40(State.a[OP[1]]) + SEXT40(State.a[OP[2]]);
87178dbd
MM		 648
649 trace_input ("addac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
4c38885c
MH		 650 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
651 State.regs[OP[0]+1] = tmp & 0xffff;
87178dbd 652 trace_output (OP_DREG);
2934d1c9
MH		 653}
654
655/* addac3s */
656void
657OP_17001200 ()
658{
4c38885c 659 int64 tmp;
4c38885c 660 State.F1 = State.F0;
87178dbd
MM		 661
662 trace_input ("addac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
4f425a32 663 tmp = SEXT40(State.a[OP[2]]) + SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
4c38885c
MH		 664 if ( tmp > MAX32)
665 {
666 State.regs[OP[0]] = 0x7fff;
667 State.regs[OP[0]+1] = 0xffff;
668 State.F0 = 1;
669 }
670 else if (tmp < MIN32)
671 {
672 State.regs[OP[0]] = 0x8000;
673 State.regs[OP[0]+1] = 0;
674 State.F0 = 1;
675 }
676 else
677 {
678 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
679 State.regs[OP[0]+1] = tmp & 0xffff;
680 State.F0 = 0;
681 }
87178dbd 682 trace_output (OP_DREG);
2934d1c9
MH		 683}
684
685/* addac3s */
686void
687OP_17001202 ()
688{
4c38885c 689 int64 tmp;
4c38885c 690 State.F1 = State.F0;
87178dbd
MM		 691
692 trace_input ("addac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
4f425a32 693 tmp = SEXT40(State.a[OP[1]]) + SEXT40(State.a[OP[2]]);
4c38885c
MH		 694 if ( tmp > MAX32)
695 {
696 State.regs[OP[0]] = 0x7fff;
697 State.regs[OP[0]+1] = 0xffff;
698 State.F0 = 1;
699 }
700 else if (tmp < MIN32)
701 {
702 State.regs[OP[0]] = 0x8000;
703 State.regs[OP[0]+1] = 0;
704 State.F0 = 1;
705 }
706 else
707 {
708 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
709 State.regs[OP[0]+1] = tmp & 0xffff;
710 State.F0 = 0;
711 }
87178dbd 712 trace_output (OP_DREG);
2934d1c9
MH		 713}
714
715/* addi */
716void
717OP_201 ()
718{
2254cd90 719 uint tmp = State.regs[OP[0]];
4f425a32
MH		 720 if (OP[1] == 0)
721 OP[1] = 16;
87178dbd 722 trace_input ("addi", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 723 State.regs[OP[0]] += OP[1];
2254cd90
MM		 724 if (tmp > State.regs[OP[0]])
725 State.C = 1;
726 else
727 State.C = 0;
87178dbd 728 trace_output (OP_REG);
2934d1c9
MH		 729}
730
731/* and */
732void
733OP_C00 ()
734{
87178dbd 735 trace_input ("and", OP_REG, OP_REG, OP_VOID);
2934d1c9 736 State.regs[OP[0]] &= State.regs[OP[1]];
87178dbd 737 trace_output (OP_REG);
2934d1c9
MH		 738}
739
740/* and3 */
741void
742OP_6000000 ()
743{
87178dbd 744 trace_input ("and3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
2934d1c9 745 State.regs[OP[0]] = State.regs[OP[1]] & OP[2];
87178dbd 746 trace_output (OP_REG);
2934d1c9
MH		 747}
748
749/* bclri */
750void
751OP_C01 ()
752{
87178dbd 753 trace_input ("bclri", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 754 State.regs[OP[0]] &= ~(0x8000 >> OP[1]);
87178dbd 755 trace_output (OP_REG);
2934d1c9
MH		 756}
757
758/* bl.s */
759void
760OP_4900 ()
761{
a18cb100 762 trace_input ("bl.s", OP_CONSTANT8, OP_R2, OP_R3);
2934d1c9
MH		 763 State.regs[13] = PC+1;
764 PC += SEXT8 (OP[0]);
87178dbd 765 trace_output (OP_VOID);
2934d1c9
MH		 766}
767
768/* bl.l */
769void
770OP_24800000 ()
771{
a18cb100 772 trace_input ("bl.l", OP_CONSTANT16, OP_R2, OP_R3);
2934d1c9
MH		 773 State.regs[13] = PC+1;
774 PC += OP[0];
87178dbd 775 trace_output (OP_VOID);
2934d1c9
MH		 776}
777
778/* bnoti */
779void
780OP_A01 ()
781{
87178dbd 782 trace_input ("bnoti", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 783 State.regs[OP[0]] ^= 0x8000 >> OP[1];
87178dbd 784 trace_output (OP_REG);
2934d1c9
MH		 785}
786
787/* bra.s */
788void
789OP_4800 ()
790{
a18cb100 791 trace_input ("bra.s", OP_CONSTANT8, OP_VOID, OP_VOID);
2934d1c9 792 PC += SEXT8 (OP[0]);
87178dbd 793 trace_output (OP_VOID);
2934d1c9
MH		 794}
795
796/* bra.l */
797void
798OP_24000000 ()
799{
87178dbd 800 trace_input ("bra.l", OP_CONSTANT16, OP_VOID, OP_VOID);
2934d1c9 801 PC += OP[0];
87178dbd 802 trace_output (OP_VOID);
2934d1c9
MH		 803}
804
805/* brf0f.s */
806void
807OP_4A00 ()
808{
a18cb100 809 trace_input ("brf0f.s", OP_CONSTANT8, OP_VOID, OP_VOID);
2934d1c9
MH		 810 if (State.F0 == 0)
811 PC += SEXT8 (OP[0]);
87178dbd 812 trace_output (OP_FLAG);
2934d1c9
MH		 813}
814
815/* brf0f.l */
816void
817OP_25000000 ()
818{
87178dbd 819 trace_input ("brf0f.l", OP_CONSTANT16, OP_VOID, OP_VOID);
2934d1c9
MH		 820 if (State.F0 == 0)
821 PC += OP[0];
87178dbd 822 trace_output (OP_FLAG);
2934d1c9
MH		 823}
824
825/* brf0t.s */
826void
827OP_4B00 ()
828{
a18cb100 829 trace_input ("brf0t.s", OP_CONSTANT8, OP_VOID, OP_VOID);
2934d1c9
MH		 830 if (State.F0)
831 PC += SEXT8 (OP[0]);
87178dbd 832 trace_output (OP_FLAG);
2934d1c9
MH		 833}
834
835/* brf0t.l */
836void
837OP_25800000 ()
838{
87178dbd 839 trace_input ("brf0t.l", OP_CONSTANT16, OP_VOID, OP_VOID);
2934d1c9
MH		 840 if (State.F0)
841 PC += OP[0];
87178dbd 842 trace_output (OP_FLAG);
2934d1c9
MH		 843}
844
845/* bseti */
846void
847OP_801 ()
848{
87178dbd 849 trace_input ("bseti", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 850 State.regs[OP[0]] |= 0x8000 >> OP[1];
87178dbd 851 trace_output (OP_REG);
2934d1c9
MH		 852}
853
854/* btsti */
855void
856OP_E01 ()
857{
87178dbd 858 trace_input ("btsti", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9
MH		 859 State.F1 = State.F0;
860 State.F0 = (State.regs[OP[0]] & (0x8000 >> OP[1])) ? 1 : 0;
87178dbd 861 trace_output (OP_FLAG);
2934d1c9
MH		 862}
863
864/* clrac */
865void
866OP_5601 ()
867{
87178dbd 868 trace_input ("clrac", OP_ACCUM_OUTPUT, OP_VOID, OP_VOID);
2934d1c9 869 State.a[OP[0]] = 0;
87178dbd 870 trace_output (OP_ACCUM);
2934d1c9
MH		 871}
872
873/* cmp */
874void
875OP_600 ()
876{
87178dbd 877 trace_input ("cmp", OP_REG, OP_REG, OP_VOID);
2934d1c9
MH		 878 State.F1 = State.F0;
879 State.F0 = ((int16)(State.regs[OP[0]]) < (int16)(State.regs[OP[1]])) ? 1 : 0;
87178dbd 880 trace_output (OP_FLAG);
2934d1c9
MH		 881}
882
883/* cmp */
884void
885OP_1603 ()
886{
87178dbd 887 trace_input ("cmp", OP_ACCUM, OP_ACCUM, OP_VOID);
4c38885c 888 State.F1 = State.F0;
4f425a32 889 State.F0 = (SEXT40(State.a[OP[0]]) < SEXT40(State.a[OP[1]])) ? 1 : 0;
87178dbd 890 trace_output (OP_FLAG);
2934d1c9
MH		 891}
892
893/* cmpeq */
894void
895OP_400 ()
896{
87178dbd 897 trace_input ("cmpeq", OP_REG, OP_REG, OP_VOID);
2934d1c9
MH		 898 State.F1 = State.F0;
899 State.F0 = (State.regs[OP[0]] == State.regs[OP[1]]) ? 1 : 0;
87178dbd 900 trace_output (OP_FLAG);
2934d1c9
MH		 901}
902
903/* cmpeq */
904void
905OP_1403 ()
906{
87178dbd 907 trace_input ("cmpeq", OP_ACCUM, OP_ACCUM, OP_VOID);
4c38885c
MH		 908 State.F1 = State.F0;
909 State.F0 = (State.a[OP[0]] == State.a[OP[1]]) ? 1 : 0;
87178dbd 910 trace_output (OP_FLAG);
2934d1c9
MH		 911}
912
913/* cmpeqi.s */
914void
915OP_401 ()
916{
c12f5c67 917 trace_input ("cmpeqi.s", OP_REG, OP_CONSTANT4, OP_VOID);
2934d1c9 918 State.F1 = State.F0;
c12f5c67 919 State.F0 = (State.regs[OP[0]] == (reg_t)SEXT4(OP[1])) ? 1 : 0;
87178dbd 920 trace_output (OP_FLAG);
2934d1c9
MH		 921}
922
923/* cmpeqi.l */
924void
925OP_2000000 ()
926{
87178dbd 927 trace_input ("cmpeqi.l", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 928 State.F1 = State.F0;
c12f5c67 929 State.F0 = (State.regs[OP[0]] == (reg_t)OP[1]) ? 1 : 0;
87178dbd 930 trace_output (OP_FLAG);
2934d1c9
MH		 931}
932
933/* cmpi.s */
934void
935OP_601 ()
936{
87178dbd 937 trace_input ("cmpi.s", OP_REG, OP_CONSTANT4, OP_VOID);
2934d1c9 938 State.F1 = State.F0;
c12f5c67 939 State.F0 = ((int16)(State.regs[OP[0]]) < (int16)SEXT4(OP[1])) ? 1 : 0;
87178dbd 940 trace_output (OP_FLAG);
2934d1c9
MH		 941}
942
943/* cmpi.l */
944void
945OP_3000000 ()
946{
87178dbd 947 trace_input ("cmpi.l", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9
MH		 948 State.F1 = State.F0;
949 State.F0 = ((int16)(State.regs[OP[0]]) < (int16)(OP[1])) ? 1 : 0;
87178dbd 950 trace_output (OP_FLAG);
2934d1c9
MH		 951}
952
953/* cmpu */
954void
955OP_4600 ()
956{
87178dbd 957 trace_input ("cmpu", OP_REG, OP_REG, OP_VOID);
2934d1c9
MH		 958 State.F1 = State.F0;
959 State.F0 = (State.regs[OP[0]] < State.regs[OP[1]]) ? 1 : 0;
87178dbd 960 trace_output (OP_FLAG);
2934d1c9
MH		 961}
962
963/* cmpui */
964void
965OP_23000000 ()
966{
87178dbd 967 trace_input ("cmpui", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 968 State.F1 = State.F0;
c12f5c67 969 State.F0 = (State.regs[OP[0]] < (reg_t)OP[1]) ? 1 : 0;
87178dbd 970 trace_output (OP_FLAG);
2934d1c9
MH		 971}
972
973/* cpfg */
974void
975OP_4E09 ()
976{
977 uint8 *src, *dst;
2934d1c9 978
60fc5b72 979 trace_input ("cpfg", OP_FLAG_OUTPUT, OP_FLAG, OP_VOID);
2934d1c9
MH		 980 if (OP[0] == 0)
981 dst = &State.F0;
982 else
983 dst = &State.F1;
984
985 if (OP[1] == 0)
986 src = &State.F0;
987 else if (OP[1] == 1)
988 src = &State.F1;
989 else
990 src = &State.C;
991
992 *dst = *src;
87178dbd 993 trace_output (OP_FLAG);
2934d1c9
MH		 994}
995
996/* dbt */
997void
998OP_5F20 ()
999{
a49a15ad 1000 /* d10v_callback->printf_filtered(d10v_callback, "***** DBT ***** PC=%x\n",PC); */
4f425a32 1001 State.exception = SIGTRAP;
2934d1c9
MH		 1002}
1003
1004/* divs */
1005void
1006OP_14002800 ()
1007{
1008 uint16 foo, tmp, tmpf;
87178dbd
MM		 1009
1010 trace_input ("divs", OP_DREG, OP_REG, OP_VOID);
2934d1c9
MH		 1011 foo = (State.regs[OP[0]] << 1) | (State.regs[OP[0]+1] >> 15);
1012 tmp = (int16)foo - (int16)(State.regs[OP[1]]);
1013 tmpf = (foo >= State.regs[OP[1]]) ? 1 : 0;
1014 State.regs[OP[0]] = (tmpf == 1) ? tmp : foo;
1015 State.regs[OP[0]+1] = (State.regs[OP[0]+1] << 1) | tmpf;
87178dbd 1016 trace_output (OP_DREG);
2934d1c9
MH		 1017}
1018
1019/* exef0f */
1020void
1021OP_4E04 ()
1022{
87178dbd 1023 trace_input ("exef0f", OP_VOID, OP_VOID, OP_VOID);
293c76a3 1024 State.exe = (State.F0 == 0);
87178dbd 1025 trace_output (OP_FLAG);
2934d1c9
MH		 1026}
1027
1028/* exef0t */
1029void
1030OP_4E24 ()
1031{
87178dbd 1032 trace_input ("exef0t", OP_VOID, OP_VOID, OP_VOID);
293c76a3 1033 State.exe = (State.F0 != 0);
87178dbd 1034 trace_output (OP_FLAG);
2934d1c9
MH		 1035}
1036
1037/* exef1f */
1038void
1039OP_4E40 ()
1040{
87178dbd 1041 trace_input ("exef1f", OP_VOID, OP_VOID, OP_VOID);
293c76a3 1042 State.exe = (State.F1 == 0);
87178dbd 1043 trace_output (OP_FLAG);
2934d1c9
MH		 1044}
1045
1046/* exef1t */
1047void
1048OP_4E42 ()
1049{
87178dbd 1050 trace_input ("exef1t", OP_VOID, OP_VOID, OP_VOID);
293c76a3 1051 State.exe = (State.F1 != 0);
87178dbd 1052 trace_output (OP_FLAG);
2934d1c9
MH		 1053}
1054
1055/* exefaf */
1056void
1057OP_4E00 ()
1058{
87178dbd 1059 trace_input ("exefaf", OP_VOID, OP_VOID, OP_VOID);
293c76a3 1060 State.exe = (State.F0 == 0) & (State.F1 == 0);
87178dbd 1061 trace_output (OP_FLAG);
2934d1c9
MH		 1062}
1063
1064/* exefat */
1065void
1066OP_4E02 ()
1067{
87178dbd 1068 trace_input ("exefat", OP_VOID, OP_VOID, OP_VOID);
293c76a3 1069 State.exe = (State.F0 == 0) & (State.F1 != 0);
87178dbd 1070 trace_output (OP_FLAG);
2934d1c9
MH		 1071}
1072
1073/* exetaf */
1074void
1075OP_4E20 ()
1076{
87178dbd 1077 trace_input ("exetaf", OP_VOID, OP_VOID, OP_VOID);
293c76a3 1078 State.exe = (State.F0 != 0) & (State.F1 == 0);
87178dbd 1079 trace_output (OP_FLAG);
2934d1c9
MH		 1080}
1081
1082/* exetat */
1083void
1084OP_4E22 ()
1085{
87178dbd 1086 trace_input ("exetat", OP_VOID, OP_VOID, OP_VOID);
293c76a3 1087 State.exe = (State.F0 != 0) & (State.F1 != 0);
87178dbd 1088 trace_output (OP_FLAG);
2934d1c9
MH		 1089}
1090
1091/* exp */
1092void
1093OP_15002A00 ()
1094{
1095 uint32 tmp, foo;
1096 int i;
1097
87178dbd 1098 trace_input ("exp", OP_REG_OUTPUT, OP_DREG, OP_VOID);
4c38885c
MH		 1099 if (((int16)State.regs[OP[1]]) >= 0)
1100 tmp = (State.regs[OP[1]] << 16) | State.regs[OP[1]+1];
2934d1c9 1101 else
4c38885c 1102 tmp = ~((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
2934d1c9
MH		 1103
1104 foo = 0x40000000;
4c38885c 1105 for (i=1;i<17;i++)
2934d1c9
MH		 1106 {
1107 if (tmp & foo)
1108 {
1109 State.regs[OP[0]] = i-1;
87178dbd 1110 trace_output (OP_REG);
2934d1c9
MH		 1111 return;
1112 }
4c38885c 1113 foo >>= 1;
2934d1c9
MH		 1114 }
1115 State.regs[OP[0]] = 16;
87178dbd 1116 trace_output (OP_REG);
2934d1c9
MH		 1117}
1118
1119/* exp */
1120void
1121OP_15002A02 ()
1122{
4c38885c
MH		 1123 int64 tmp, foo;
1124 int i;
87178dbd
MM		 1125
1126 trace_input ("exp", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
4f425a32 1127 if (SEXT40(State.a[OP[1]]) >= 0)
4c38885c
MH		 1128 tmp = State.a[OP[1]];
1129 else
1130 tmp = ~(State.a[OP[1]]);
1131
1132 foo = 0x4000000000LL;
1133 for (i=1;i<25;i++)
1134 {
1135 if (tmp & foo)
1136 {
1137 State.regs[OP[0]] = i-9;
87178dbd 1138 trace_output (OP_REG);
4c38885c
MH		 1139 return;
1140 }
1141 foo >>= 1;
1142 }
1143 State.regs[OP[0]] = 16;
87178dbd 1144 trace_output (OP_REG);
2934d1c9
MH		 1145}
1146
1147/* jl */
1148void
1149OP_4D00 ()
1150{
a18cb100 1151 trace_input ("jl", OP_REG, OP_R2, OP_R3);
2934d1c9
MH		 1152 State.regs[13] = PC+1;
1153 PC = State.regs[OP[0]];
87178dbd 1154 trace_output (OP_VOID);
2934d1c9
MH		 1155}
1156
1157/* jmp */
1158void
1159OP_4C00 ()
1160{
a18cb100
MM		 1161 trace_input ("jmp", OP_REG,
1162 (OP[0] == 13) ? OP_R2 : OP_VOID,
1163 (OP[0] == 13) ? OP_R3 : OP_VOID);
1164
2934d1c9 1165 PC = State.regs[OP[0]];
87178dbd 1166 trace_output (OP_VOID);
2934d1c9
MH		 1167}
1168
1169/* ld */
1170void
1171OP_30000000 ()
1172{
87178dbd 1173 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
2934d1c9 1174 State.regs[OP[0]] = RW (OP[1] + State.regs[OP[2]]);
87178dbd 1175 trace_output (OP_REG);
2934d1c9
MH		 1176}
1177
1178/* ld */
1179void
1180OP_6401 ()
1181{
87178dbd 1182 trace_input ("ld", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
4c38885c 1183 State.regs[OP[0]] = RW (State.regs[OP[1]]);
4f425a32 1184 INC_ADDR(State.regs[OP[1]],-2);
87178dbd 1185 trace_output (OP_REG);
2934d1c9
MH		 1186}
1187
1188/* ld */
1189void
1190OP_6001 ()
1191{
87178dbd 1192 trace_input ("ld", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
4c38885c 1193 State.regs[OP[0]] = RW (State.regs[OP[1]]);
4f425a32 1194 INC_ADDR(State.regs[OP[1]],2);
87178dbd 1195 trace_output (OP_REG);
2934d1c9
MH		 1196}
1197
1198/* ld */
1199void
1200OP_6000 ()
1201{
87178dbd 1202 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
2934d1c9 1203 State.regs[OP[0]] = RW (State.regs[OP[1]]);
87178dbd 1204 trace_output (OP_REG);
2934d1c9
MH		 1205}
1206
1207/* ld2w */
1208void
1209OP_31000000 ()
1210{
8918b3a7 1211 uint16 addr = State.regs[OP[2]];
308f64d3 1212 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
8918b3a7
MM		 1213 State.regs[OP[0]] = RW (OP[1] + addr);
1214 State.regs[OP[0]+1] = RW (OP[1] + addr + 2);
87178dbd 1215 trace_output (OP_DREG);
2934d1c9
MH		 1216}
1217
1218/* ld2w */
1219void
1220OP_6601 ()
1221{
8918b3a7 1222 uint16 addr = State.regs[OP[1]];
87178dbd 1223 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
8918b3a7
MM		 1224 State.regs[OP[0]] = RW (addr);
1225 State.regs[OP[0]+1] = RW (addr+2);
4f425a32 1226 INC_ADDR(State.regs[OP[1]],-4);
87178dbd 1227 trace_output (OP_DREG);
2934d1c9
MH		 1228}
1229
1230/* ld2w */
1231void
1232OP_6201 ()
1233{
8918b3a7 1234 uint16 addr = State.regs[OP[1]];
87178dbd 1235 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
8918b3a7
MM		 1236 State.regs[OP[0]] = RW (addr);
1237 State.regs[OP[0]+1] = RW (addr+2);
4f425a32 1238 INC_ADDR(State.regs[OP[1]],4);
8918b3a7 1239 trace_output (OP_DREG);
2934d1c9
MH		 1240}
1241
1242/* ld2w */
1243void
1244OP_6200 ()
1245{
8918b3a7 1246 uint16 addr = State.regs[OP[1]];
addb61a5 1247 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
8918b3a7
MM		 1248 State.regs[OP[0]] = RW (addr);
1249 State.regs[OP[0]+1] = RW (addr+2);
1250 trace_output (OP_DREG);
2934d1c9
MH		 1251}
1252
1253/* ldb */
1254void
1255OP_38000000 ()
1256{
87178dbd 1257 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
c422ecc7 1258 State.regs[OP[0]] = SEXT8 (RB (OP[1] + State.regs[OP[2]]));
87178dbd 1259 trace_output (OP_REG);
2934d1c9
MH		 1260}
1261
1262/* ldb */
1263void
1264OP_7000 ()
1265{
87178dbd 1266 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
c422ecc7 1267 State.regs[OP[0]] = SEXT8 (RB (State.regs[OP[1]]));
87178dbd 1268 trace_output (OP_REG);
2934d1c9
MH		 1269}
1270
1271/* ldi.s */
1272void
1273OP_4001 ()
1274{
87178dbd 1275 trace_input ("ldi.s", OP_REG_OUTPUT, OP_CONSTANT4, OP_VOID);
2934d1c9 1276 State.regs[OP[0]] = SEXT4(OP[1]);
87178dbd 1277 trace_output (OP_REG);
2934d1c9
MH		 1278}
1279
1280/* ldi.l */
1281void
1282OP_20000000 ()
1283{
87178dbd 1284 trace_input ("ldi.s", OP_REG_OUTPUT, OP_CONSTANT16, OP_VOID);
2934d1c9 1285 State.regs[OP[0]] = OP[1];
87178dbd 1286 trace_output (OP_REG);
2934d1c9
MH		 1287}
1288
1289/* ldub */
1290void
1291OP_39000000 ()
1292{
87178dbd 1293 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
2934d1c9 1294 State.regs[OP[0]] = RB (OP[1] + State.regs[OP[2]]);
87178dbd 1295 trace_output (OP_REG);
2934d1c9
MH		 1296}
1297
1298/* ldub */
1299void
1300OP_7200 ()
1301{
87178dbd 1302 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
2934d1c9 1303 State.regs[OP[0]] = RB (State.regs[OP[1]]);
87178dbd 1304 trace_output (OP_REG);
2934d1c9
MH		 1305}
1306
1307/* mac */
1308void
1309OP_2A00 ()
1310{
4c38885c 1311 int64 tmp;
87178dbd
MM		 1312
1313 trace_input ("mac", OP_ACCUM, OP_REG, OP_REG);
4f425a32 1314 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
4c38885c
MH		 1315
1316 if (State.FX)
4f425a32 1317 tmp = SEXT40( (tmp << 1) & MASK40);
4c38885c
MH		 1318
1319 if (State.ST && tmp > MAX32)
1320 tmp = MAX32;
1321
4f425a32 1322 tmp += SEXT40(State.a[OP[0]]);
4c38885c
MH		 1323 if (State.ST)
1324 {
1325 if (tmp > MAX32)
1326 State.a[OP[0]] = MAX32;
1327 else if (tmp < MIN32)
1328 State.a[OP[0]] = MIN32;
1329 else
4f425a32 1330 State.a[OP[0]] = tmp & MASK40;
4c38885c
MH		 1331 }
1332 else
4f425a32 1333 State.a[OP[0]] = tmp & MASK40;
87178dbd 1334 trace_output (OP_ACCUM);
2934d1c9
MH		 1335}
1336
1337/* macsu */
1338void
1339OP_1A00 ()
1340{
4f425a32 1341 int64 tmp;
87178dbd
MM		 1342
1343 trace_input ("macsu", OP_ACCUM, OP_REG, OP_REG);
4f425a32
MH		 1344 tmp = SEXT40 ((int16)State.regs[OP[1]] * State.regs[OP[2]]);
1345 if (State.FX)
1346 tmp = SEXT40( (tmp << 1) & MASK40);
1347
1348 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) + tmp) & MASK40;
87178dbd 1349 trace_output (OP_ACCUM);
2934d1c9
MH		 1350}
1351
1352/* macu */
1353void
1354OP_3A00 ()
1355{
4f425a32 1356 int64 tmp;
87178dbd
MM		 1357
1358 trace_input ("macu", OP_ACCUM, OP_REG, OP_REG);
4f425a32
MH		 1359 tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
1360 if (State.FX)
1361 tmp = SEXT40( (tmp << 1) & MASK40);
1362 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) + tmp) & MASK40;
87178dbd 1363 trace_output (OP_ACCUM);
2934d1c9
MH		 1364}
1365
1366/* max */
1367void
1368OP_2600 ()
1369{
87178dbd 1370 trace_input ("max", OP_REG, OP_REG, OP_VOID);
2934d1c9 1371 State.F1 = State.F0;
ea2155e8 1372 if ((int16)State.regs[OP[1]] > (int16)State.regs[OP[0]])
2934d1c9
MH		 1373 {
1374 State.regs[OP[0]] = State.regs[OP[1]];
1375 State.F0 = 1;
1376 }
1377 else
1378 State.F0 = 0;
87178dbd 1379 trace_output (OP_REG);
2934d1c9
MH		 1380}
1381
1382/* max */
1383void
1384OP_3600 ()
1385{
4f425a32 1386 int64 tmp;
87178dbd
MM		 1387
1388 trace_input ("max", OP_ACCUM, OP_DREG, OP_VOID);
4f425a32
MH		 1389 State.F1 = State.F0;
1390 tmp = SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
1391 if (tmp > SEXT40(State.a[OP[0]]))
1392 {
1393 State.a[OP[0]] = tmp & MASK40;
1394 State.F0 = 1;
1395 }
1396 else
1397 State.F0 = 0;
87178dbd 1398 trace_output (OP_ACCUM);
2934d1c9
MH		 1399}
1400
1401/* max */
1402void
1403OP_3602 ()
1404{
87178dbd 1405 trace_input ("max", OP_ACCUM, OP_ACCUM, OP_VOID);
4f425a32
MH		 1406 State.F1 = State.F0;
1407 if (SEXT40(State.a[OP[1]]) > SEXT40(State.a[OP[0]]))
1408 {
1409 State.a[OP[0]] = State.a[OP[1]];
1410 State.F0 = 1;
1411 }
1412 else
1413 State.F0 = 0;
87178dbd 1414 trace_output (OP_ACCUM);
2934d1c9
MH		 1415}
1416
4f425a32 1417
2934d1c9
MH		 1418/* min */
1419void
1420OP_2601 ()
1421{
87178dbd 1422 trace_input ("min", OP_REG, OP_REG, OP_VOID);
2934d1c9 1423 State.F1 = State.F0;
ea2155e8 1424 if ((int16)State.regs[OP[1]] < (int16)State.regs[OP[0]])
2934d1c9
MH		 1425 {
1426 State.regs[OP[0]] = State.regs[OP[1]];
1427 State.F0 = 1;
1428 }
1429 else
1430 State.F0 = 0;
87178dbd 1431 trace_output (OP_REG);
2934d1c9
MH		 1432}
1433
1434/* min */
1435void
1436OP_3601 ()
1437{
4f425a32 1438 int64 tmp;
87178dbd
MM		 1439
1440 trace_input ("min", OP_ACCUM, OP_DREG, OP_VOID);
4f425a32
MH		 1441 State.F1 = State.F0;
1442 tmp = SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
1443 if (tmp < SEXT40(State.a[OP[0]]))
1444 {
1445 State.a[OP[0]] = tmp & MASK40;
1446 State.F0 = 1;
1447 }
1448 else
1449 State.F0 = 0;
87178dbd 1450 trace_output (OP_ACCUM);
2934d1c9
MH		 1451}
1452
1453/* min */
1454void
1455OP_3603 ()
1456{
87178dbd 1457 trace_input ("min", OP_ACCUM, OP_ACCUM, OP_VOID);
4f425a32
MH		 1458 State.F1 = State.F0;
1459 if (SEXT40(State.a[OP[1]]) < SEXT40(State.a[OP[0]]))
1460 {
1461 State.a[OP[0]] = State.a[OP[1]];
1462 State.F0 = 1;
1463 }
1464 else
1465 State.F0 = 0;
87178dbd 1466 trace_output (OP_ACCUM);
2934d1c9
MH		 1467}
1468
1469/* msb */
1470void
1471OP_2800 ()
1472{
4f425a32 1473 int64 tmp;
87178dbd
MM		 1474
1475 trace_input ("msb", OP_ACCUM, OP_REG, OP_REG);
4f425a32
MH		 1476 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
1477
1478 if (State.FX)
1479 tmp = SEXT40 ((tmp << 1) & MASK40);
1480
1481 if (State.ST && tmp > MAX32)
1482 tmp = MAX32;
1483
1484 tmp = SEXT40(State.a[OP[0]]) - tmp;
1485 if (State.ST)
1486 {
1487 if (tmp > MAX32)
1488 State.a[OP[0]] = MAX32;
1489 else if (tmp < MIN32)
1490 State.a[OP[0]] = MIN32;
1491 else
1492 State.a[OP[0]] = tmp & MASK40;
1493 }
1494 else
1495 State.a[OP[0]] = tmp & MASK40;
87178dbd 1496 trace_output (OP_ACCUM);
2934d1c9
MH		 1497}
1498
1499/* msbsu */
1500void
1501OP_1800 ()
1502{
4f425a32 1503 int64 tmp;
87178dbd
MM		 1504
1505 trace_input ("msbsu", OP_ACCUM, OP_REG, OP_REG);
4f425a32
MH		 1506 tmp = SEXT40 ((int16)State.regs[OP[1]] * State.regs[OP[2]]);
1507 if (State.FX)
1508 tmp = SEXT40( (tmp << 1) & MASK40);
1509
1510 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) - tmp) & MASK40;
87178dbd 1511 trace_output (OP_ACCUM);
2934d1c9
MH		 1512}
1513
1514/* msbu */
1515void
1516OP_3800 ()
1517{
4f425a32 1518 int64 tmp;
87178dbd
MM		 1519
1520 trace_input ("msbu", OP_ACCUM, OP_REG, OP_REG);
4f425a32
MH		 1521 tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
1522 if (State.FX)
1523 tmp = SEXT40( (tmp << 1) & MASK40);
1524
1525 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) - tmp) & MASK40;
87178dbd 1526 trace_output (OP_ACCUM);
2934d1c9
MH		 1527}
1528
1529/* mul */
1530void
1531OP_2E00 ()
1532{
87178dbd 1533 trace_input ("mul", OP_REG, OP_REG, OP_VOID);
2934d1c9 1534 State.regs[OP[0]] *= State.regs[OP[1]];
87178dbd 1535 trace_output (OP_REG);
2934d1c9
MH		 1536}
1537
1538/* mulx */
1539void
1540OP_2C00 ()
1541{
4f425a32 1542 int64 tmp;
87178dbd
MM		 1543
1544 trace_input ("mulx", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
4f425a32
MH		 1545 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
1546
1547 if (State.FX)
1548 tmp = SEXT40 ((tmp << 1) & MASK40);
1549
1550 if (State.ST && tmp > MAX32)
1551 State.a[OP[0]] = MAX32;
1552 else
1553 State.a[OP[0]] = tmp & MASK40;
87178dbd 1554 trace_output (OP_ACCUM);
2934d1c9
MH		 1555}
1556
1557/* mulxsu */
1558void
1559OP_1C00 ()
1560{
4f425a32 1561 int64 tmp;
87178dbd
MM		 1562
1563 trace_input ("mulxsu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
4f425a32
MH		 1564 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * State.regs[OP[2]]);
1565
1566 if (State.FX)
1567 tmp <<= 1;
1568
1569 State.a[OP[0]] = tmp & MASK40;
87178dbd 1570 trace_output (OP_ACCUM);
2934d1c9
MH		 1571}
1572
1573/* mulxu */
1574void
1575OP_3C00 ()
1576{
4f425a32 1577 int64 tmp;
87178dbd
MM		 1578
1579 trace_input ("mulxu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
4f425a32
MH		 1580 tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
1581
1582 if (State.FX)
1583 tmp <<= 1;
1584
1585 State.a[OP[0]] = tmp & MASK40;
87178dbd 1586 trace_output (OP_ACCUM);
2934d1c9
MH		 1587}
1588
1589/* mv */
1590void
1591OP_4000 ()
1592{
87178dbd 1593 trace_input ("mv", OP_REG_OUTPUT, OP_REG, OP_VOID);
2934d1c9 1594 State.regs[OP[0]] = State.regs[OP[1]];
87178dbd 1595 trace_output (OP_REG);
2934d1c9
MH		 1596}
1597
1598/* mv2w */
1599void
1600OP_5000 ()
1601{
87178dbd 1602 trace_input ("mv2w", OP_DREG_OUTPUT, OP_DREG, OP_VOID);
2934d1c9
MH		 1603 State.regs[OP[0]] = State.regs[OP[1]];
1604 State.regs[OP[0]+1] = State.regs[OP[1]+1];
87178dbd 1605 trace_output (OP_DREG);
2934d1c9
MH		 1606}
1607
1608/* mv2wfac */
1609void
1610OP_3E00 ()
1611{
87178dbd 1612 trace_input ("mv2wfac", OP_DREG_OUTPUT, OP_ACCUM, OP_VOID);
2934d1c9
MH		 1613 State.regs[OP[0]] = (State.a[OP[1]] >> 16) & 0xffff;
1614 State.regs[OP[0]+1] = State.a[OP[1]] & 0xffff;
87178dbd 1615 trace_output (OP_DREG);
2934d1c9
MH		 1616}
1617
1618/* mv2wtac */
1619void
1620OP_3E01 ()
1621{
87178dbd 1622 trace_input ("mv2wtac", OP_ACCUM_OUTPUT, OP_DREG, OP_VOID);
4f425a32 1623 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]]) << 16 | State.regs[OP[0]+1]) & MASK40;
87178dbd 1624 trace_output (OP_ACCUM);
2934d1c9
MH		 1625}
1626
1627/* mvac */
1628void
1629OP_3E03 ()
1630{
87178dbd 1631 trace_input ("mvac", OP_ACCUM_OUTPUT, OP_ACCUM, OP_VOID);
2934d1c9 1632 State.a[OP[0]] = State.a[OP[1]];
87178dbd 1633 trace_output (OP_ACCUM);
2934d1c9
MH		 1634}
1635
1636/* mvb */
1637void
1638OP_5400 ()
1639{
87178dbd 1640 trace_input ("mvb", OP_REG_OUTPUT, OP_REG, OP_VOID);
2934d1c9 1641 State.regs[OP[0]] = SEXT8 (State.regs[OP[1]] & 0xff);
87178dbd 1642 trace_output (OP_REG);
2934d1c9
MH		 1643}
1644
1645/* mvf0f */
1646void
1647OP_4400 ()
1648{
87178dbd 1649 trace_input ("mf0f", OP_REG_OUTPUT, OP_REG, OP_VOID);
2934d1c9
MH		 1650 if (State.F0 == 0)
1651 State.regs[OP[0]] = State.regs[OP[1]];
87178dbd 1652 trace_output (OP_REG);
2934d1c9
MH		 1653}
1654
1655/* mvf0t */
1656void
1657OP_4401 ()
1658{
87178dbd 1659 trace_input ("mf0t", OP_REG_OUTPUT, OP_REG, OP_VOID);
2934d1c9
MH		 1660 if (State.F0)
1661 State.regs[OP[0]] = State.regs[OP[1]];
87178dbd 1662 trace_output (OP_REG);
2934d1c9
MH		 1663}
1664
1665/* mvfacg */
1666void
1667OP_1E04 ()
1668{
87178dbd 1669 trace_input ("mvfacg", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2934d1c9 1670 State.regs[OP[0]] = (State.a[OP[1]] >> 32) & 0xff;
87178dbd 1671 trace_output (OP_ACCUM);
2934d1c9
MH		 1672}
1673
1674/* mvfachi */
1675void
1676OP_1E00 ()
1677{
87178dbd 1678 trace_input ("mvfachi", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2934d1c9 1679 State.regs[OP[0]] = (State.a[OP[1]] >> 16) & 0xffff;
87178dbd 1680 trace_output (OP_REG);
2934d1c9
MH		 1681}
1682
1683/* mvfaclo */
1684void
1685OP_1E02 ()
1686{
87178dbd 1687 trace_input ("mvfaclo", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2934d1c9 1688 State.regs[OP[0]] = State.a[OP[1]] & 0xffff;
87178dbd 1689 trace_output (OP_REG);
2934d1c9
MH		 1690}
1691
1692/* mvfc */
1693void
1694OP_5200 ()
1695{
87178dbd 1696 trace_input ("mvfc", OP_REG_OUTPUT, OP_CR, OP_VOID);
2934d1c9
MH		 1697 if (OP[1] == 0)
1698 {
1699 /* PSW is treated specially */
1700 PSW = 0;
1701 if (State.SM) PSW |= 0x8000;
1702 if (State.EA) PSW |= 0x2000;
1703 if (State.DB) PSW |= 0x1000;
1704 if (State.IE) PSW |= 0x400;
1705 if (State.RP) PSW |= 0x200;
1706 if (State.MD) PSW |= 0x100;
1707 if (State.FX) PSW |= 0x80;
1708 if (State.ST) PSW |= 0x40;
1709 if (State.F0) PSW |= 8;
1710 if (State.F1) PSW |= 4;
1711 if (State.C) PSW |= 1;
1712 }
1713 State.regs[OP[0]] = State.cregs[OP[1]];
87178dbd 1714 trace_output (OP_REG);
2934d1c9
MH		 1715}
1716
1717/* mvtacg */
1718void
1719OP_1E41 ()
1720{
87178dbd 1721 trace_input ("mvtacg", OP_REG, OP_ACCUM, OP_VOID);
2934d1c9
MH		 1722 State.a[OP[1]] &= MASK32;
1723 State.a[OP[1]] |= (int64)(State.regs[OP[0]] & 0xff) << 32;
87178dbd 1724 trace_output (OP_ACCUM_REVERSE);
2934d1c9
MH		 1725}
1726
1727/* mvtachi */
1728void
1729OP_1E01 ()
1730{
1731 uint16 tmp;
87178dbd
MM		 1732
1733 trace_input ("mvtachi", OP_REG, OP_ACCUM, OP_VOID);
2934d1c9 1734 tmp = State.a[OP[1]] & 0xffff;
4f425a32 1735 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]]) << 16 | tmp) & MASK40;
87178dbd 1736 trace_output (OP_ACCUM_REVERSE);
2934d1c9
MH		 1737}
1738
1739/* mvtaclo */
1740void
1741OP_1E21 ()
1742{
87178dbd 1743 trace_input ("mvtaclo", OP_REG, OP_ACCUM, OP_VOID);
4f425a32 1744 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]])) & MASK40;
87178dbd 1745 trace_output (OP_ACCUM_REVERSE);
2934d1c9
MH		 1746}
1747
1748/* mvtc */
1749void
1750OP_5600 ()
1751{
87178dbd 1752 trace_input ("mvtc", OP_REG, OP_CR_OUTPUT, OP_VOID);
2934d1c9
MH		 1753 State.cregs[OP[1]] = State.regs[OP[0]];
1754 if (OP[1] == 0)
1755 {
1756 /* PSW is treated specially */
1757 State.SM = (PSW & 0x8000) ? 1 : 0;
1758 State.EA = (PSW & 0x2000) ? 1 : 0;
1759 State.DB = (PSW & 0x1000) ? 1 : 0;
1760 State.IE = (PSW & 0x400) ? 1 : 0;
1761 State.RP = (PSW & 0x200) ? 1 : 0;
1762 State.MD = (PSW & 0x100) ? 1 : 0;
1763 State.FX = (PSW & 0x80) ? 1 : 0;
1764 State.ST = (PSW & 0x40) ? 1 : 0;
1765 State.F0 = (PSW & 8) ? 1 : 0;
1766 State.F1 = (PSW & 4) ? 1 : 0;
1767 State.C = PSW & 1;
1768 if (State.ST && !State.FX)
1769 {
7eebfc62
MM		 1770 (*d10v_callback->printf_filtered) (d10v_callback,
1771 "ERROR at PC 0x%x: ST can only be set when FX is set.\n",
1772 PC<<2);
4f425a32 1773 State.exception = SIGILL;
2934d1c9
MH		 1774 }
1775 }
87178dbd 1776 trace_output (OP_CR_REVERSE);
2934d1c9
MH		 1777}
1778
1779/* mvub */
1780void
1781OP_5401 ()
1782{
87178dbd 1783 trace_input ("mvub", OP_REG_OUTPUT, OP_REG, OP_VOID);
2934d1c9 1784 State.regs[OP[0]] = State.regs[OP[1]] & 0xff;
87178dbd 1785 trace_output (OP_REG);
2934d1c9
MH		 1786}
1787
1788/* neg */
1789void
1790OP_4605 ()
1791{
87178dbd 1792 trace_input ("neg", OP_REG, OP_VOID, OP_VOID);
2934d1c9 1793 State.regs[OP[0]] = 0 - State.regs[OP[0]];
87178dbd 1794 trace_output (OP_REG);
2934d1c9
MH		 1795}
1796
1797/* neg */
1798void
1799OP_5605 ()
1800{
1801 int64 tmp;
87178dbd
MM		 1802
1803 trace_input ("neg", OP_ACCUM, OP_VOID, OP_VOID);
4f425a32 1804 tmp = -SEXT40(State.a[OP[0]]);
2934d1c9
MH		 1805 if (State.ST)
1806 {
4c38885c 1807 if ( tmp > MAX32)
2934d1c9 1808 State.a[OP[0]] = MAX32;
4c38885c 1809 else if (tmp < MIN32)
2934d1c9
MH		 1810 State.a[OP[0]] = MIN32;
1811 else
4f425a32 1812 State.a[OP[0]] = tmp & MASK40;
2934d1c9
MH		 1813 }
1814 else
4f425a32 1815 State.a[OP[0]] = tmp & MASK40;
87178dbd 1816 trace_output (OP_ACCUM);
2934d1c9
MH		 1817}
1818
1819
1820/* nop */
1821void
1822OP_5E00 ()
1823{
87178dbd 1824 trace_input ("nop", OP_VOID, OP_VOID, OP_VOID);
7eebfc62 1825
c422ecc7
MH		 1826 ins_type_counters[ (int)State.ins_type ]--; /* don't count nops as normal instructions */
1827 switch (State.ins_type)
1828 {
1829 default:
1830 ins_type_counters[ (int)INS_UNKNOWN ]++;
1831 break;
1832
1833 case INS_LEFT_PARALLEL:
1834 /* Don't count a parallel op that includes a NOP as a true parallel op */
1835 ins_type_counters[ (int)INS_RIGHT_PARALLEL ]--;
1836 ins_type_counters[ (int)INS_RIGHT ]++;
1837 ins_type_counters[ (int)INS_LEFT_NOPS ]++;
1838 break;
1839
1840 case INS_LEFT:
1841 case INS_LEFT_COND_EXE:
1842 ins_type_counters[ (int)INS_LEFT_NOPS ]++;
1843 break;
1844
1845 case INS_RIGHT_PARALLEL:
1846 /* Don't count a parallel op that includes a NOP as a true parallel op */
1847 ins_type_counters[ (int)INS_LEFT_PARALLEL ]--;
1848 ins_type_counters[ (int)INS_LEFT ]++;
1849 ins_type_counters[ (int)INS_RIGHT_NOPS ]++;
1850 break;
1851
1852 case INS_RIGHT:
1853 case INS_RIGHT_COND_EXE:
1854 ins_type_counters[ (int)INS_RIGHT_NOPS ]++;
1855 break;
1856 }
1857
1858 trace_output (OP_VOID);
2934d1c9
MH		 1859}
1860
1861/* not */
1862void
1863OP_4603 ()
1864{
87178dbd 1865 trace_input ("not", OP_REG, OP_VOID, OP_VOID);
2934d1c9 1866 State.regs[OP[0]] = ~(State.regs[OP[0]]);
87178dbd 1867 trace_output (OP_REG);
2934d1c9
MH		 1868}
1869
1870/* or */
1871void
1872OP_800 ()
1873{
87178dbd 1874 trace_input ("or", OP_REG, OP_REG, OP_VOID);
2934d1c9 1875 State.regs[OP[0]] |= State.regs[OP[1]];
87178dbd 1876 trace_output (OP_REG);
2934d1c9
MH		 1877}
1878
1879/* or3 */
1880void
1881OP_4000000 ()
1882{
87178dbd 1883 trace_input ("or3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
2934d1c9 1884 State.regs[OP[0]] = State.regs[OP[1]] | OP[2];
87178dbd 1885 trace_output (OP_REG);
2934d1c9
MH		 1886}
1887
1888/* rac */
1889void
1890OP_5201 ()
1891{
1892 int64 tmp;
1893 int shift = SEXT3 (OP[2]);
87178dbd
MM		 1894
1895 trace_input ("rac", OP_DREG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
166acb9f
MH		 1896 if (OP[1] != 0)
1897 {
7eebfc62
MM		 1898 (*d10v_callback->printf_filtered) (d10v_callback,
1899 "ERROR at PC 0x%x: instruction only valid for A0\n",
1900 PC<<2);
166acb9f
MH		 1901 State.exception = SIGILL;
1902 }
1903
2934d1c9
MH		 1904 State.F1 = State.F0;
1905 if (shift >=0)
1906 tmp = ((State.a[0] << 16) | (State.a[1] & 0xffff)) << shift;
1907 else
1908 tmp = ((State.a[0] << 16) | (State.a[1] & 0xffff)) >> -shift;
166acb9f 1909 tmp = ( SEXT60(tmp) + 0x8000 ) >> 16;
4c38885c 1910 if (tmp > MAX32)
2934d1c9
MH		 1911 {
1912 State.regs[OP[0]] = 0x7fff;
1913 State.regs[OP[0]+1] = 0xffff;
1914 State.F0 = 1;
1915 }
4c38885c 1916 else if (tmp < MIN32)
2934d1c9
MH		 1917 {
1918 State.regs[OP[0]] = 0x8000;
1919 State.regs[OP[0]+1] = 0;
1920 State.F0 = 1;
1921 }
1922 else
1923 {
1924 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
1925 State.regs[OP[0]+1] = tmp & 0xffff;
1926 State.F0 = 0;
1927 }
87178dbd 1928 trace_output (OP_DREG);
2934d1c9
MH		 1929}
1930
1931/* rachi */
1932void
1933OP_4201 ()
1934{
4c38885c
MH		 1935 int64 tmp;
1936 int shift = SEXT3 (OP[2]);
87178dbd
MM		 1937
1938 trace_input ("rachi", OP_REG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
4c38885c
MH		 1939 State.F1 = State.F0;
1940 if (shift >=0)
166acb9f 1941 tmp = SEXT44 (State.a[1]) << shift;
4c38885c 1942 else
166acb9f 1943 tmp = SEXT44 (State.a[1]) >> -shift;
4c38885c 1944 tmp += 0x8000;
63a91cfb 1945
4c38885c
MH		 1946 if (tmp > MAX32)
1947 {
1948 State.regs[OP[0]] = 0x7fff;
1949 State.F0 = 1;
1950 }
1951 else if (tmp < 0xfff80000000LL)
1952 {
1953 State.regs[OP[0]] = 0x8000;
1954 State.F0 = 1;
1955 }
1956 else
1957 {
1958 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
1959 State.F0 = 0;
1960 }
87178dbd 1961 trace_output (OP_REG);
2934d1c9
MH		 1962}
1963
1964/* rep */
1965void
1966OP_27000000 ()
1967{
87178dbd 1968 trace_input ("rep", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9
MH		 1969 RPT_S = PC + 1;
1970 RPT_E = PC + OP[1];
1971 RPT_C = State.regs[OP[0]];
1972 State.RP = 1;
1973 if (RPT_C == 0)
1974 {
7eebfc62 1975 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep with count=0 is illegal.\n");
4f425a32 1976 State.exception = SIGILL;
2934d1c9 1977 }
4c38885c
MH		 1978 if (OP[1] < 4)
1979 {
7eebfc62 1980 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep must include at least 4 instructions.\n");
4f425a32 1981 State.exception = SIGILL;
4c38885c 1982 }
87178dbd 1983 trace_output (OP_VOID);
2934d1c9
MH		 1984}
1985
1986/* repi */
1987void
1988OP_2F000000 ()
1989{
87178dbd 1990 trace_input ("repi", OP_CONSTANT16, OP_CONSTANT16, OP_VOID);
2934d1c9
MH		 1991 RPT_S = PC + 1;
1992 RPT_E = PC + OP[1];
1993 RPT_C = OP[0];
1994 State.RP = 1;
1995 if (RPT_C == 0)
1996 {
7eebfc62 1997 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi with count=0 is illegal.\n");
4f425a32 1998 State.exception = SIGILL;
4c38885c
MH		 1999 }
2000 if (OP[1] < 4)
2001 {
7eebfc62 2002 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi must include at least 4 instructions.\n");
4f425a32 2003 State.exception = SIGILL;
2934d1c9 2004 }
87178dbd 2005 trace_output (OP_VOID);
2934d1c9
MH		 2006}
2007
2008/* rtd */
2009void
2010OP_5F60 ()
2011{
7eebfc62 2012 d10v_callback->printf_filtered(d10v_callback, "ERROR: rtd - NOT IMPLEMENTED\n");
87178dbd 2013 State.exception = SIGILL;
2934d1c9
MH		 2014}
2015
2016/* rte */
2017void
2018OP_5F40 ()
2019{
87178dbd 2020 trace_input ("rte", OP_VOID, OP_VOID, OP_VOID);
4c38885c
MH		 2021 PC = BPC;
2022 PSW = BPSW;
87178dbd 2023 trace_output (OP_VOID);
2934d1c9
MH		 2024}
2025
2026/* sadd */
2027void
2028OP_1223 ()
2029{
4c38885c 2030 int64 tmp;
87178dbd
MM		 2031
2032 trace_input ("sadd", OP_ACCUM, OP_ACCUM, OP_VOID);
4f425a32 2033 tmp = SEXT40(State.a[OP[0]]) + (SEXT40(State.a[OP[1]]) >> 16);
4c38885c
MH		 2034 if (State.ST)
2035 {
2036 if (tmp > MAX32)
2037 State.a[OP[0]] = MAX32;
2038 else if (tmp < MIN32)
2039 State.a[OP[0]] = MIN32;
2040 else
4f425a32 2041 State.a[OP[0]] = tmp & MASK40;
4c38885c
MH		 2042 }
2043 else
4f425a32 2044 State.a[OP[0]] = tmp & MASK40;
87178dbd 2045 trace_output (OP_ACCUM);
2934d1c9
MH		 2046}
2047
2048/* setf0f */
2049void
2050OP_4611 ()
2051{
87178dbd 2052 trace_input ("setf0f", OP_REG_OUTPUT, OP_VOID, OP_VOID);
4c38885c 2053 State.regs[OP[0]] = (State.F0 == 0) ? 1 : 0;
87178dbd 2054 trace_output (OP_REG);
2934d1c9
MH		 2055}
2056
2057/* setf0t */
2058void
2059OP_4613 ()
2060{
87178dbd 2061 trace_input ("setf0t", OP_REG_OUTPUT, OP_VOID, OP_VOID);
4c38885c 2062 State.regs[OP[0]] = (State.F0 == 1) ? 1 : 0;
87178dbd 2063 trace_output (OP_REG);
2934d1c9
MH		 2064}
2065
2066/* sleep */
2067void
2068OP_5FC0 ()
2069{
87178dbd 2070 trace_input ("sleep", OP_VOID, OP_VOID, OP_VOID);
4c38885c 2071 State.IE = 1;
87178dbd 2072 trace_output (OP_VOID);
2934d1c9
MH		 2073}
2074
2075/* sll */
2076void
2077OP_2200 ()
2078{
87178dbd 2079 trace_input ("sll", OP_REG, OP_REG, OP_VOID);
2934d1c9 2080 State.regs[OP[0]] <<= (State.regs[OP[1]] & 0xf);
87178dbd 2081 trace_output (OP_REG);
2934d1c9
MH		 2082}
2083
2084/* sll */
2085void
2086OP_3200 ()
2087{
4c38885c 2088 int64 tmp;
87178dbd 2089 trace_input ("sll", OP_ACCUM, OP_REG, OP_VOID);
069398aa 2090 if ((State.regs[OP[1]] & 31) <= 16)
4c38885c 2091 tmp = SEXT40 (State.a[OP[0]]) << (State.regs[OP[1]] & 31);
069398aa
MM		 2092 else
2093 {
2094 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31);
2095 State.exception = SIGILL;
2096 return;
2097 }
4c38885c
MH		 2098
2099 if (State.ST)
2100 {
2101 if (tmp > MAX32)
2102 State.a[OP[0]] = MAX32;
2103 else if (tmp < 0xffffff80000000LL)
2104 State.a[OP[0]] = MIN32;
2105 else
2106 State.a[OP[0]] = tmp & MASK40;
2107 }
2108 else
2109 State.a[OP[0]] = tmp & MASK40;
87178dbd 2110 trace_output (OP_ACCUM);
2934d1c9
MH		 2111}
2112
2113/* slli */
2114void
2115OP_2201 ()
2116{
87178dbd 2117 trace_input ("slli", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 2118 State.regs[OP[0]] <<= OP[1];
87178dbd 2119 trace_output (OP_REG);
2934d1c9
MH		 2120}
2121
2122/* slli */
2123void
2124OP_3201 ()
2125{
4c38885c 2126 int64 tmp;
4f425a32
MH		 2127
2128 if (OP[1] == 0)
2129 OP[1] = 16;
4f425a32 2130
87178dbd 2131 trace_input ("slli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
4f425a32 2132 tmp = SEXT40(State.a[OP[0]]) << OP[1];
4c38885c
MH		 2133
2134 if (State.ST)
2135 {
2136 if (tmp > MAX32)
2137 State.a[OP[0]] = MAX32;
2138 else if (tmp < 0xffffff80000000LL)
2139 State.a[OP[0]] = MIN32;
2140 else
2141 State.a[OP[0]] = tmp & MASK40;
2142 }
2143 else
2144 State.a[OP[0]] = tmp & MASK40;
87178dbd 2145 trace_output (OP_ACCUM);
2934d1c9
MH		 2146}
2147
2148/* slx */
2149void
2150OP_460B ()
2151{
87178dbd 2152 trace_input ("slx", OP_REG, OP_FLAG, OP_VOID);
2934d1c9 2153 State.regs[OP[0]] = (State.regs[OP[0]] << 1) | State.F0;
87178dbd 2154 trace_output (OP_REG);
2934d1c9
MH		 2155}
2156
2157/* sra */
2158void
2159OP_2400 ()
2160{
87178dbd 2161 trace_input ("sra", OP_REG, OP_REG, OP_VOID);
2934d1c9 2162 State.regs[OP[0]] = ((int16)(State.regs[OP[0]])) >> (State.regs[OP[1]] & 0xf);
87178dbd 2163 trace_output (OP_REG);
2934d1c9
MH		 2164}
2165
2166/* sra */
2167void
2168OP_3400 ()
2169{
87178dbd 2170 trace_input ("sra", OP_ACCUM, OP_REG, OP_VOID);
069398aa 2171 if ((State.regs[OP[1]] & 31) <= 16)
4c38885c 2172 State.a[OP[0]] >>= (State.regs[OP[1]] & 31);
069398aa
MM		 2173 else
2174 {
2175 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31);
2176 State.exception = SIGILL;
2177 return;
2178 }
2179
87178dbd 2180 trace_output (OP_ACCUM);
2934d1c9
MH		 2181}
2182
2183/* srai */
2184void
2185OP_2401 ()
2186{
87178dbd 2187 trace_input ("srai", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 2188 State.regs[OP[0]] = ((int16)(State.regs[OP[0]])) >> OP[1];
87178dbd 2189 trace_output (OP_REG);
2934d1c9
MH		 2190}
2191
2192/* srai */
2193void
2194OP_3401 ()
2195{
4f425a32
MH		 2196 if (OP[1] == 0)
2197 OP[1] = 16;
87178dbd
MM		 2198
2199 trace_input ("srai", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2200 State.a[OP[0]] >>= OP[1];
2201 trace_output (OP_ACCUM);
2934d1c9
MH		 2202}
2203
2204/* srl */
2205void
2206OP_2000 ()
2207{
87178dbd 2208 trace_input ("srl", OP_REG, OP_REG, OP_VOID);
2934d1c9 2209 State.regs[OP[0]] >>= (State.regs[OP[1]] & 0xf);
87178dbd 2210 trace_output (OP_REG);
2934d1c9
MH		 2211}
2212
2213/* srl */
2214void
2215OP_3000 ()
2216{
87178dbd 2217 trace_input ("srl", OP_ACCUM, OP_REG, OP_VOID);
069398aa 2218 if ((State.regs[OP[1]] & 31) <= 16)
4c38885c 2219 State.a[OP[0]] >>= (State.regs[OP[1]] & 31);
069398aa
MM		 2220 else
2221 {
2222 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31);
2223 State.exception = SIGILL;
2224 return;
2225 }
2226
87178dbd 2227 trace_output (OP_ACCUM);
2934d1c9
MH		 2228}
2229
2230/* srli */
2231void
2232OP_2001 ()
2233{
87178dbd 2234 trace_input ("srli", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 2235 State.regs[OP[0]] >>= OP[1];
87178dbd 2236 trace_output (OP_REG);
2934d1c9
MH		 2237}
2238
2239/* srli */
2240void
2241OP_3001 ()
2242{
4f425a32
MH		 2243 if (OP[1] == 0)
2244 OP[1] = 16;
87178dbd
MM		 2245
2246 trace_input ("srli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2247 State.a[OP[0]] >>= OP[1];
2248 trace_output (OP_ACCUM);
2934d1c9
MH		 2249}
2250
2251/* srx */
2252void
2253OP_4609 ()
2254{
2255 uint16 tmp;
87178dbd
MM		 2256
2257 trace_input ("srx", OP_REG, OP_FLAG, OP_VOID);
2934d1c9
MH		 2258 tmp = State.F0 << 15;
2259 State.regs[OP[0]] = (State.regs[OP[0]] >> 1) | tmp;
87178dbd 2260 trace_output (OP_REG);
2934d1c9
MH		 2261}
2262
2263/* st */
2264void
2265OP_34000000 ()
2266{
87178dbd 2267 trace_input ("st", OP_REG, OP_MEMREF2, OP_VOID);
2934d1c9 2268 SW (OP[1] + State.regs[OP[2]], State.regs[OP[0]]);
87178dbd 2269 trace_output (OP_VOID);
2934d1c9
MH		 2270}
2271
2272/* st */
2273void
2274OP_6800 ()
2275{
87178dbd 2276 trace_input ("st", OP_REG, OP_MEMREF, OP_VOID);
2934d1c9 2277 SW (State.regs[OP[1]], State.regs[OP[0]]);
87178dbd 2278 trace_output (OP_VOID);
2934d1c9
MH		 2279}
2280
2281/* st */
2282void
2283OP_6C1F ()
2284{
87178dbd 2285 trace_input ("st", OP_REG, OP_PREDEC, OP_VOID);
4c38885c
MH		 2286 if ( OP[1] != 15 )
2287 {
7eebfc62 2288 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
4f425a32
MH		 2289 State.exception = SIGILL;
2290 return;
4c38885c
MH		 2291 }
2292 State.regs[OP[1]] -= 2;
2293 SW (State.regs[OP[1]], State.regs[OP[0]]);
87178dbd 2294 trace_output (OP_VOID);
2934d1c9
MH		 2295}
2296
2297/* st */
2298void
2299OP_6801 ()
2300{
87178dbd 2301 trace_input ("st", OP_REG, OP_POSTINC, OP_VOID);
4c38885c 2302 SW (State.regs[OP[1]], State.regs[OP[0]]);
4f425a32 2303 INC_ADDR (State.regs[OP[1]],2);
87178dbd 2304 trace_output (OP_VOID);
2934d1c9
MH		 2305}
2306
2307/* st */
2308void
2309OP_6C01 ()
2310{
87178dbd 2311 trace_input ("st", OP_REG, OP_POSTDEC, OP_VOID);
4c38885c 2312 SW (State.regs[OP[1]], State.regs[OP[0]]);
4f425a32 2313 INC_ADDR (State.regs[OP[1]],-2);
87178dbd 2314 trace_output (OP_VOID);
2934d1c9
MH		 2315}
2316
2317/* st2w */
2318void
2319OP_35000000 ()
2320{
87178dbd 2321 trace_input ("st2w", OP_DREG, OP_MEMREF2, OP_VOID);
4f425a32
MH		 2322 SW (State.regs[OP[2]]+OP[1], State.regs[OP[0]]);
2323 SW (State.regs[OP[2]]+OP[1]+2, State.regs[OP[0]+1]);
87178dbd 2324 trace_output (OP_VOID);
2934d1c9
MH		 2325}
2326
2327/* st2w */
2328void
2329OP_6A00 ()
2330{
a18cb100 2331 trace_input ("st2w", OP_DREG, OP_MEMREF, OP_VOID);
4c38885c
MH		 2332 SW (State.regs[OP[1]], State.regs[OP[0]]);
2333 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
87178dbd 2334 trace_output (OP_VOID);
2934d1c9
MH		 2335}
2336
2337/* st2w */
2338void
2339OP_6E1F ()
2340{
a18cb100 2341 trace_input ("st2w", OP_DREG, OP_PREDEC, OP_VOID);
4c38885c
MH		 2342 if ( OP[1] != 15 )
2343 {
7eebfc62 2344 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
4f425a32
MH		 2345 State.exception = SIGILL;
2346 return;
4c38885c
MH		 2347 }
2348 State.regs[OP[1]] -= 4;
2349 SW (State.regs[OP[1]], State.regs[OP[0]]);
2350 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
87178dbd 2351 trace_output (OP_VOID);
2934d1c9
MH		 2352}
2353
2354/* st2w */
2355void
2356OP_6A01 ()
2357{
a18cb100 2358 trace_input ("st2w", OP_DREG, OP_POSTDEC, OP_VOID);
4c38885c
MH		 2359 SW (State.regs[OP[1]], State.regs[OP[0]]);
2360 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
4f425a32 2361 INC_ADDR (State.regs[OP[1]],4);
87178dbd 2362 trace_output (OP_VOID);
2934d1c9
MH		 2363}
2364
2365/* st2w */
2366void
2367OP_6E01 ()
2368{
a18cb100 2369 trace_input ("st2w", OP_DREG, OP_POSTINC, OP_VOID);
4c38885c
MH		 2370 SW (State.regs[OP[1]], State.regs[OP[0]]);
2371 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
4f425a32 2372 INC_ADDR (State.regs[OP[1]],-4);
87178dbd 2373 trace_output (OP_VOID);
2934d1c9
MH		 2374}
2375
2376/* stb */
2377void
2378OP_3C000000 ()
2379{
87178dbd 2380 trace_input ("stb", OP_REG, OP_MEMREF2, OP_VOID);
4f425a32 2381 SB (State.regs[OP[2]]+OP[1], State.regs[OP[0]]);
87178dbd 2382 trace_output (OP_VOID);
2934d1c9
MH		 2383}
2384
2385/* stb */
2386void
2387OP_7800 ()
2388{
87178dbd 2389 trace_input ("stb", OP_REG, OP_MEMREF, OP_VOID);
4c38885c 2390 SB (State.regs[OP[1]], State.regs[OP[0]]);
87178dbd 2391 trace_output (OP_VOID);
2934d1c9
MH		 2392}
2393
2394/* stop */
2395void
2396OP_5FE0 ()
2397{
87178dbd 2398 trace_input ("stop", OP_VOID, OP_VOID, OP_VOID);
a49a15ad 2399 State.exception = SIG_D10V_STOP;
87178dbd 2400 trace_output (OP_VOID);
2934d1c9
MH		 2401}
2402
2403/* sub */
2404void
2405OP_0 ()
4c38885c
MH		 2406{
2407 int32 tmp;
87178dbd
MM		 2408
2409 trace_input ("sub", OP_REG, OP_REG, OP_VOID);
4c38885c
MH		 2410 tmp = (int16)State.regs[OP[0]]- (int16)State.regs[OP[1]];
2411 State.C = (tmp & 0xffff0000) ? 1 : 0;
2412 State.regs[OP[0]] = tmp & 0xffff;
87178dbd 2413 trace_output (OP_REG);
4c38885c
MH		 2414}
2415
2416/* sub */
2417void
2418OP_1001 ()
2419{
4f425a32 2420 int64 tmp;
87178dbd
MM		 2421
2422 trace_input ("sub", OP_ACCUM, OP_DREG, OP_VOID);
4f425a32
MH		 2423 tmp = SEXT40(State.a[OP[0]]) - (SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]);
2424 if (State.ST)
2425 {
2426 if ( tmp > MAX32)
2427 State.a[OP[0]] = MAX32;
2428 else if ( tmp < MIN32)
2429 State.a[OP[0]] = MIN32;
2430 else
2431 State.a[OP[0]] = tmp & MASK40;
2432 }
2433 else
2434 State.a[OP[0]] = tmp & MASK40;
87178dbd
MM		 2435
2436 trace_output (OP_ACCUM);
4c38885c
MH		 2437}
2438
2439/* sub */
2440
2441void
2442OP_1003 ()
2934d1c9 2443{
4f425a32 2444 int64 tmp;
87178dbd
MM		 2445
2446 trace_input ("sub", OP_ACCUM, OP_ACCUM, OP_VOID);
4f425a32
MH		 2447 tmp = SEXT40(State.a[OP[0]]) - SEXT40(State.a[OP[1]]);
2448 if (State.ST)
2449 {
2450 if (tmp > MAX32)
2451 State.a[OP[0]] = MAX32;
2452 else if ( tmp < MIN32)
2453 State.a[OP[0]] = MIN32;
2454 else
2455 State.a[OP[0]] = tmp & MASK40;
2456 }
2457 else
2458 State.a[OP[0]] = tmp & MASK40;
87178dbd
MM		 2459
2460 trace_output (OP_ACCUM);
2934d1c9
MH		 2461}
2462
2463/* sub2w */
2464void
2465OP_1000 ()
2466{
4c38885c
MH		 2467 int64 tmp;
2468 int32 a,b;
4c38885c 2469
87178dbd 2470 trace_input ("sub2w", OP_DREG, OP_DREG, OP_VOID);
4c38885c
MH		 2471 a = (int32)((State.regs[OP[0]] << 16) | State.regs[OP[0]+1]);
2472 b = (int32)((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
2473 tmp = a-b;
2474 State.C = (tmp & 0xffffffff00000000LL) ? 1 : 0;
2475 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2476 State.regs[OP[0]+1] = tmp & 0xffff;
87178dbd 2477 trace_output (OP_DREG);
2934d1c9
MH		 2478}
2479
2480/* subac3 */
2481void
2482OP_17000000 ()
2483{
4f425a32 2484 int64 tmp;
87178dbd
MM		 2485
2486 trace_input ("subac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
4f425a32
MH		 2487 tmp = SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]) - SEXT40 (State.a[OP[2]]);
2488 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2489 State.regs[OP[0]+1] = tmp & 0xffff;
87178dbd 2490 trace_output (OP_DREG);
2934d1c9
MH		 2491}
2492
2493/* subac3 */
2494void
2495OP_17000002 ()
2496{
4f425a32 2497 int64 tmp;
87178dbd
MM		 2498
2499 trace_input ("subac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
4f425a32
MH		 2500 tmp = SEXT40(State.a[OP[1]]) - SEXT40(State.a[OP[2]]);
2501 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2502 State.regs[OP[0]+1] = tmp & 0xffff;
87178dbd 2503 trace_output (OP_DREG);
2934d1c9
MH		 2504}
2505
2506/* subac3s */
2507void
2508OP_17001000 ()
2509{
4f425a32 2510 int64 tmp;
87178dbd
MM		 2511
2512 trace_input ("subac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
4f425a32
MH		 2513 State.F1 = State.F0;
2514 tmp = SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]) - SEXT40(State.a[OP[2]]);
2515 if ( tmp > MAX32)
2516 {
2517 State.regs[OP[0]] = 0x7fff;
2518 State.regs[OP[0]+1] = 0xffff;
2519 State.F0 = 1;
2520 }
2521 else if (tmp < MIN32)
2522 {
2523 State.regs[OP[0]] = 0x8000;
2524 State.regs[OP[0]+1] = 0;
2525 State.F0 = 1;
2526 }
2527 else
2528 {
2529 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2530 State.regs[OP[0]+1] = tmp & 0xffff;
2531 State.F0 = 0;
2532 }
87178dbd 2533 trace_output (OP_DREG);
2934d1c9
MH		 2534}
2535
2536/* subac3s */
2537void
2538OP_17001002 ()
2539{
4f425a32 2540 int64 tmp;
87178dbd
MM		 2541
2542 trace_input ("subac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
4f425a32
MH		 2543 State.F1 = State.F0;
2544 tmp = SEXT40(State.a[OP[1]]) - SEXT40(State.a[OP[2]]);
2545 if ( tmp > MAX32)
2546 {
2547 State.regs[OP[0]] = 0x7fff;
2548 State.regs[OP[0]+1] = 0xffff;
2549 State.F0 = 1;
2550 }
2551 else if (tmp < MIN32)
2552 {
2553 State.regs[OP[0]] = 0x8000;
2554 State.regs[OP[0]+1] = 0;
2555 State.F0 = 1;
2556 }
2557 else
2558 {
2559 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2560 State.regs[OP[0]+1] = tmp & 0xffff;
2561 State.F0 = 0;
2562 }
87178dbd 2563 trace_output (OP_DREG);
2934d1c9
MH		 2564}
2565
2566/* subi */
2567void
2568OP_1 ()
2569{
4c38885c 2570 int32 tmp;
4f425a32
MH		 2571 if (OP[1] == 0)
2572 OP[1] = 16;
87178dbd
MM		 2573
2574 trace_input ("subi", OP_REG, OP_CONSTANT16, OP_VOID);
4c38885c
MH		 2575 tmp = (int16)State.regs[OP[0]] - OP[1];
2576 State.C = (tmp & 0xffff0000) ? 1 : 0;
2577 State.regs[OP[0]] = tmp & 0xffff;
87178dbd 2578 trace_output (OP_REG);
2934d1c9
MH		 2579}
2580
2581/* trap */
2582void
2583OP_5F00 ()
2584{
a5719092 2585 trace_input ("trap", OP_CONSTANT4, OP_VOID, OP_VOID);
87178dbd 2586 trace_output (OP_VOID);
8918b3a7 2587
63a91cfb 2588 switch (OP[0])
2934d1c9 2589 {
63a91cfb 2590 default:
19d44375 2591#if 0
7eebfc62 2592 (*d10v_callback->printf_filtered) (d10v_callback, "Unknown trap code %d\n", OP[0]);
63a91cfb 2593 State.exception = SIGILL;
19d44375
MM		 2594#else
2595 /* Use any other traps for batch debugging. */
2596 {
2597 int i;
2598 static int first_time = 1;
2599
2600 if (first_time)
2601 {
2602 first_time = 0;
2603 (*d10v_callback->printf_filtered) (d10v_callback, "Trap # PC ");
2604 for (i = 0; i < 16; i++)
2605 (*d10v_callback->printf_filtered) (d10v_callback, " %sr%d", (i > 9) ? "" : " ", i);
2606 (*d10v_callback->printf_filtered) (d10v_callback, " a0 a1 f0 f1 c\n");
2607 }
2608
2609 (*d10v_callback->printf_filtered) (d10v_callback, "Trap %2d 0x%.4x:", (int)OP[0], (int)PC);
2610
2611 for (i = 0; i < 16; i++)
2612 (*d10v_callback->printf_filtered) (d10v_callback, " %.4x", (int) State.regs[i]);
2613
2614 for (i = 0; i < 2; i++)
2615 (*d10v_callback->printf_filtered) (d10v_callback, " %.2x%.8lx",
11ec4de6
MM		 2616 ((int)(State.a[i] >> 32) & 0xff),
2617 ((unsigned long)State.a[i]) & 0xffffffff);
19d44375
MM		 2618
2619 (*d10v_callback->printf_filtered) (d10v_callback, " %d %d %d\n",
2620 State.F0 != 0, State.F1 != 0, State.C != 0);
2621 break;
2622#endif
63a91cfb
MM		 2623
2624 case 0:
2625 /* Trap 0 is used for simulating low-level I/O */
2626 {
63a91cfb
MM		 2627 errno = 0;
2628
2629/* Registers passed to trap 0 */
2630
65c0d7de
MA		 2631#define FUNC State.regs[6] /* function number */
2632#define PARM1 State.regs[2] /* optional parm 1 */
2633#define PARM2 State.regs[3] /* optional parm 2 */
2634#define PARM3 State.regs[4] /* optional parm 3 */
2635#define PARM4 State.regs[5] /* optional parm 3 */
63a91cfb
MM		 2636
2637/* Registers set by trap 0 */
2638
65c0d7de
MA		 2639#define RETVAL State.regs[2] /* return value */
2640#define RETVAL_HIGH State.regs[2] /* return value */
2641#define RETVAL_LOW State.regs[3] /* return value */
2642#define RETERR State.regs[4] /* return error code */
63a91cfb
MM		 2643
2644/* Turn a pointer in a register into a pointer into real memory. */
2645
c422ecc7 2646#define MEMPTR(x) ((char *)(dmem_addr(x)))
63a91cfb
MM		 2647
2648 switch (FUNC)
2649 {
2650#if !defined(__GO32__) && !defined(_WIN32)
63a91cfb
MM		 2651 case SYS_fork:
2652 RETVAL = fork ();
8918b3a7
MM		 2653 trace_input ("<fork>", OP_VOID, OP_VOID, OP_VOID);
2654 trace_output (OP_R2);
63a91cfb 2655 break;
8918b3a7 2656
57bc1a72
MM		 2657 case SYS_getpid:
2658 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
2659 RETVAL = getpid ();
2660 trace_output (OP_R2);
2661 break;
2662
2663 case SYS_kill:
2664 trace_input ("<kill>", OP_REG, OP_REG, OP_VOID);
2665 if (PARM1 == getpid ())
2666 {
2667 trace_output (OP_VOID);
2668 State.exception = PARM2;
2669 }
2670 else
2671 {
2672 int os_sig = -1;
2673 switch (PARM2)
2674 {
2675#ifdef SIGHUP
2676 case 1: os_sig = SIGHUP; break;
2677#endif
2678#ifdef SIGINT
2679 case 2: os_sig = SIGINT; break;
2680#endif
2681#ifdef SIGQUIT
2682 case 3: os_sig = SIGQUIT; break;
2683#endif
2684#ifdef SIGILL
2685 case 4: os_sig = SIGILL; break;
2686#endif
2687#ifdef SIGTRAP
2688 case 5: os_sig = SIGTRAP; break;
2689#endif
2690#ifdef SIGABRT
2691 case 6: os_sig = SIGABRT; break;
2692#elif defined(SIGIOT)
2693 case 6: os_sig = SIGIOT; break;
2694#endif
2695#ifdef SIGEMT
2696 case 7: os_sig = SIGEMT; break;
2697#endif
2698#ifdef SIGFPE
2699 case 8: os_sig = SIGFPE; break;
2700#endif
2701#ifdef SIGKILL
2702 case 9: os_sig = SIGKILL; break;
2703#endif
2704#ifdef SIGBUS
2705 case 10: os_sig = SIGBUS; break;
2706#endif
2707#ifdef SIGSEGV
2708 case 11: os_sig = SIGSEGV; break;
2709#endif
2710#ifdef SIGSYS
2711 case 12: os_sig = SIGSYS; break;
2712#endif
2713#ifdef SIGPIPE
2714 case 13: os_sig = SIGPIPE; break;
2715#endif
2716#ifdef SIGALRM
2717 case 14: os_sig = SIGALRM; break;
2718#endif
2719#ifdef SIGTERM
2720 case 15: os_sig = SIGTERM; break;
2721#endif
2722#ifdef SIGURG
2723 case 16: os_sig = SIGURG; break;
2724#endif
2725#ifdef SIGSTOP
2726 case 17: os_sig = SIGSTOP; break;
2727#endif
2728#ifdef SIGTSTP
2729 case 18: os_sig = SIGTSTP; break;
2730#endif
2731#ifdef SIGCONT
2732 case 19: os_sig = SIGCONT; break;
2733#endif
2734#ifdef SIGCHLD
2735 case 20: os_sig = SIGCHLD; break;
2736#elif defined(SIGCLD)
2737 case 20: os_sig = SIGCLD; break;
2738#endif
2739#ifdef SIGTTIN
2740 case 21: os_sig = SIGTTIN; break;
2741#endif
2742#ifdef SIGTTOU
2743 case 22: os_sig = SIGTTOU; break;
2744#endif
2745#ifdef SIGIO
2746 case 23: os_sig = SIGIO; break;
2747#elif defined (SIGPOLL)
2748 case 23: os_sig = SIGPOLL; break;
2749#endif
2750#ifdef SIGXCPU
2751 case 24: os_sig = SIGXCPU; break;
2752#endif
2753#ifdef SIGXFSZ
2754 case 25: os_sig = SIGXFSZ; break;
2755#endif
2756#ifdef SIGVTALRM
2757 case 26: os_sig = SIGVTALRM; break;
2758#endif
2759#ifdef SIGPROF
2760 case 27: os_sig = SIGPROF; break;
2761#endif
2762#ifdef SIGWINCH
2763 case 28: os_sig = SIGWINCH; break;
2764#endif
2765#ifdef SIGLOST
2766 case 29: os_sig = SIGLOST; break;
2767#endif
2768#ifdef SIGUSR1
2769 case 30: os_sig = SIGUSR1; break;
2770#endif
2771#ifdef SIGUSR2
2772 case 31: os_sig = SIGUSR2; break;
2773#endif
2774 }
2775
2776 if (os_sig == -1)
2777 {
2778 trace_output (OP_VOID);
2779 (*d10v_callback->printf_filtered) (d10v_callback, "Unknown signal %d\n", PARM2);
2780 State.exception = SIGILL;
2781 }
2782 else
2783 {
2784 RETVAL = kill (PARM1, PARM2);
2785 trace_output (OP_R2);
2786 }
2787 }
2788 break;
2789
63a91cfb
MM		 2790 case SYS_execve:
2791 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2),
2792 (char **)MEMPTR (PARM3));
8918b3a7
MM		 2793 trace_input ("<execve>", OP_R2, OP_R3, OP_R4);
2794 trace_output (OP_R2);
63a91cfb 2795 break;
8918b3a7 2796
63a91cfb
MM		 2797 case SYS_execv:
2798 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL);
8918b3a7
MM		 2799 trace_input ("<execv>", OP_R2, OP_R3, OP_VOID);
2800 trace_output (OP_R2);
63a91cfb 2801 break;
8918b3a7 2802
63a91cfb
MM		 2803 case SYS_pipe:
2804 {
2805 reg_t buf;
2806 int host_fd[2];
2807
2808 buf = PARM1;
2809 RETVAL = pipe (host_fd);
2810 SW (buf, host_fd[0]);
2811 buf += sizeof(uint16);
2812 SW (buf, host_fd[1]);
8918b3a7
MM		 2813 trace_input ("<pipe>", OP_R2, OP_VOID, OP_VOID);
2814 trace_output (OP_R2);
63a91cfb
MM		 2815 }
2816 break;
8918b3a7 2817
63a91cfb
MM		 2818 case SYS_wait:
2819 {
2820 int status;
2821
2822 RETVAL = wait (&status);
8918b3a7
MM		 2823 if (PARM1)
2824 SW (PARM1, status);
2825 trace_input ("<wait>", OP_R2, OP_VOID, OP_VOID);
2826 trace_output (OP_R2);
63a91cfb
MM		 2827 }
2828 break;
57bc1a72
MM		 2829#else
2830 case SYS_getpid:
2831 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
2832 RETVAL = 1;
2833 trace_output (OP_R2);
2834 break;
2835
2836 case SYS_kill:
2837 trace_input ("<kill>", OP_REG, OP_REG, OP_VOID);
2838 trace_output (OP_VOID);
2839 State.exception = PARM2;
2840 break;
63a91cfb 2841#endif
8918b3a7 2842
63a91cfb
MM		 2843 case SYS_read:
2844 RETVAL = d10v_callback->read (d10v_callback, PARM1, MEMPTR (PARM2),
2845 PARM3);
8918b3a7
MM		 2846 trace_input ("<read>", OP_R2, OP_R3, OP_R4);
2847 trace_output (OP_R2);
63a91cfb 2848 break;
8918b3a7 2849
63a91cfb
MM		 2850 case SYS_write:
2851 if (PARM1 == 1)
2852 RETVAL = (int)d10v_callback->write_stdout (d10v_callback,
2853 MEMPTR (PARM2), PARM3);
2854 else
2855 RETVAL = (int)d10v_callback->write (d10v_callback, PARM1,
2856 MEMPTR (PARM2), PARM3);
8918b3a7
MM		 2857 trace_input ("<write>", OP_R2, OP_R3, OP_R4);
2858 trace_output (OP_R2);
63a91cfb 2859 break;
8918b3a7 2860
63a91cfb 2861 case SYS_lseek:
65c0d7de
MA		 2862 {
2863 unsigned long ret = d10v_callback->lseek (d10v_callback, PARM1,
2864 (((unsigned long)PARM2) << 16) || (unsigned long)PARM3,
2865 PARM4);
2866 RETVAL_HIGH = ret >> 16;
2867 RETVAL_LOW = ret & 0xffff;
2868 }
8918b3a7
MM		 2869 trace_input ("<lseek>", OP_R2, OP_R3, OP_R4);
2870 trace_output (OP_R2R3);
63a91cfb 2871 break;
8918b3a7 2872
63a91cfb
MM		 2873 case SYS_close:
2874 RETVAL = d10v_callback->close (d10v_callback, PARM1);
8918b3a7
MM		 2875 trace_input ("<close>", OP_R2, OP_VOID, OP_VOID);
2876 trace_output (OP_R2);
63a91cfb 2877 break;
8918b3a7 2878
63a91cfb
MM		 2879 case SYS_open:
2880 RETVAL = d10v_callback->open (d10v_callback, MEMPTR (PARM1), PARM2);
8918b3a7
MM		 2881 trace_input ("<open>", OP_R2, OP_R3, OP_R4);
2882 trace_output (OP_R2);
2883 trace_input ("<open>", OP_R2, OP_R3, OP_R4);
2884 trace_output (OP_R2);
63a91cfb 2885 break;
8918b3a7 2886
63a91cfb 2887 case SYS_exit:
a49a15ad 2888 State.exception = SIG_D10V_EXIT;
8918b3a7
MM		 2889 trace_input ("<exit>", OP_R2, OP_VOID, OP_VOID);
2890 trace_output (OP_VOID);
63a91cfb 2891 break;
63a91cfb 2892
8719be26 2893 case SYS_stat:
63a91cfb
MM		 2894 /* stat system call */
2895 {
2896 struct stat host_stat;
2897 reg_t buf;
2898
2899 RETVAL = stat (MEMPTR (PARM1), &host_stat);
2900
2901 buf = PARM2;
2902
2903 /* The hard-coded offsets and sizes were determined by using
2904 * the D10V compiler on a test program that used struct stat.
2905 */
2906 SW (buf, host_stat.st_dev);
2907 SW (buf+2, host_stat.st_ino);
2908 SW (buf+4, host_stat.st_mode);
2909 SW (buf+6, host_stat.st_nlink);
2910 SW (buf+8, host_stat.st_uid);
2911 SW (buf+10, host_stat.st_gid);
2912 SW (buf+12, host_stat.st_rdev);
2913 SLW (buf+16, host_stat.st_size);
2914 SLW (buf+20, host_stat.st_atime);
2915 SLW (buf+28, host_stat.st_mtime);
2916 SLW (buf+36, host_stat.st_ctime);
2917 }
8918b3a7
MM		 2918 trace_input ("<stat>", OP_R2, OP_R3, OP_VOID);
2919 trace_output (OP_R2);
63a91cfb 2920 break;
63a91cfb 2921
63a91cfb
MM		 2922 case SYS_chown:
2923 RETVAL = chown (MEMPTR (PARM1), PARM2, PARM3);
8918b3a7
MM		 2924 trace_input ("<chown>", OP_R2, OP_R3, OP_R4);
2925 trace_output (OP_R2);
63a91cfb 2926 break;
8918b3a7 2927
63a91cfb
MM		 2928 case SYS_chmod:
2929 RETVAL = chmod (MEMPTR (PARM1), PARM2);
8918b3a7
MM		 2930 trace_input ("<chmod>", OP_R2, OP_R3, OP_R4);
2931 trace_output (OP_R2);
63a91cfb 2932 break;
8918b3a7 2933
63a91cfb
MM		 2934 case SYS_utime:
2935 /* Cast the second argument to void *, to avoid type mismatch
2936 if a prototype is present. */
2937 RETVAL = utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2));
8918b3a7
MM		 2938 trace_input ("<utime>", OP_R2, OP_R3, OP_R4);
2939 trace_output (OP_R2);
2940 break;
2941
2942 case SYS_time:
2943 {
2944 unsigned long ret = time (PARM1 ? MEMPTR (PARM1) : NULL);
2945 RETVAL_HIGH = ret >> 16;
2946 RETVAL_LOW = ret & 0xffff;
2947 }
2948 trace_input ("<time>", OP_R2, OP_R3, OP_R4);
2949 trace_output (OP_R2R3);
63a91cfb 2950 break;
8918b3a7 2951
63a91cfb
MM		 2952 default:
2953 abort ();
2954 }
65c0d7de 2955 RETERR = d10v_callback->get_errno(d10v_callback);
63a91cfb
MM		 2956 break;
2957 }
2958
2959 case 1:
2960 /* Trap 1 prints a string */
2961 {
c422ecc7 2962 char *fstr = dmem_addr(State.regs[2]);
63a91cfb
MM		 2963 fputs (fstr, stdout);
2964 break;
2965 }
2966
2967 case 2:
2968 /* Trap 2 calls printf */
2969 {
c422ecc7 2970 char *fstr = dmem_addr(State.regs[2]);
7eebfc62
MM		 2971 (*d10v_callback->printf_filtered) (d10v_callback, fstr,
2972 (int16)State.regs[3],
2973 (int16)State.regs[4],
2974 (int16)State.regs[5]);
63a91cfb
MM		 2975 break;
2976 }
2977
2978 case 3:
2979 /* Trap 3 writes a character */
2980 putchar (State.regs[2]);
2981 break;
19d44375 2982 }
2934d1c9
MH		 2983 }
2984}
2985
2986/* tst0i */
2987void
2988OP_7000000 ()
2989{
87178dbd 2990 trace_input ("tst0i", OP_REG, OP_CONSTANT16, OP_VOID);
4c38885c 2991 State.F1 = State.F0;
4f425a32 2992 State.F0 = (State.regs[OP[0]] & OP[1]) ? 1 : 0;
87178dbd 2993 trace_output (OP_FLAG);
2934d1c9
MH		 2994}
2995
2996/* tst1i */
2997void
2998OP_F000000 ()
2999{
87178dbd 3000 trace_input ("tst1i", OP_REG, OP_CONSTANT16, OP_VOID);
4c38885c 3001 State.F1 = State.F0;
4f425a32 3002 State.F0 = (~(State.regs[OP[0]]) & OP[1]) ? 1 : 0;
87178dbd 3003 trace_output (OP_FLAG);
2934d1c9
MH		 3004}
3005
3006/* wait */
3007void
3008OP_5F80 ()
3009{
87178dbd 3010 trace_input ("wait", OP_VOID, OP_VOID, OP_VOID);
4c38885c 3011 State.IE = 1;
87178dbd 3012 trace_output (OP_VOID);
2934d1c9
MH		 3013}
3014
3015/* xor */
3016void
3017OP_A00 ()
3018{
87178dbd 3019 trace_input ("xor", OP_REG, OP_REG, OP_VOID);
4c38885c 3020 State.regs[OP[0]] ^= State.regs[OP[1]];
87178dbd 3021 trace_output (OP_REG);
2934d1c9
MH		 3022}
3023
3024/* xor3 */
3025void
3026OP_5000000 ()
3027{
87178dbd 3028 trace_input ("xor3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
4c38885c 3029 State.regs[OP[0]] = State.regs[OP[1]] ^ OP[2];
87178dbd 3030 trace_output (OP_REG);
2934d1c9
MH		 3031}
3032
GDB Binutils - Deliverables
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