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Enhance debug support
[deliverable/binutils-gdb.git] / sim / d10v / simops.c
CommitLineData
4f425a32 1#include <signal.h>
63a91cfb
MM		 2#include <errno.h>
3#include <sys/types.h>
4#include <sys/stat.h>
5#include <unistd.h>
6
2934d1c9
MH		 7#include "d10v_sim.h"
8#include "simops.h"
8719be26 9#include "sys/syscall.h"
2934d1c9 10
87178dbd
MM		 11enum op_types {
12 OP_VOID,
13 OP_REG,
14 OP_REG_OUTPUT,
15 OP_DREG,
16 OP_DREG_OUTPUT,
17 OP_ACCUM,
18 OP_ACCUM_OUTPUT,
19 OP_ACCUM_REVERSE,
20 OP_CR,
21 OP_CR_OUTPUT,
22 OP_CR_REVERSE,
23 OP_FLAG,
24 OP_CONSTANT16,
25 OP_CONSTANT3,
26 OP_CONSTANT4,
27 OP_MEMREF,
28 OP_MEMREF2,
29 OP_POSTDEC,
30 OP_POSTINC,
31 OP_PREDEC
32};
33
34#if (DEBUG & DEBUG_TRACE) != 0
35static void trace_input PARAMS ((char *name,
36 enum op_types in1,
37 enum op_types in2,
38 enum op_types in3));
39
40static void trace_output PARAMS ((enum op_types result));
41
42#ifndef SIZE_INSTRUCTION
43#define SIZE_INSTRUCTION 10
44#endif
45
46#ifndef SIZE_OPERANDS
47#define SIZE_OPERANDS 24
48#endif
49
50#ifndef SIZE_VALUES
51#define SIZE_VALUES 13
52#endif
53
54static void
55trace_input (name, in1, in2, in3)
56 char *name;
57 enum op_types in1;
58 enum op_types in2;
59 enum op_types in3;
60{
61 char *comma;
62 enum op_types in[3];
63 int i;
64 char buf[80];
65 char *p;
66 long tmp;
67 char *type;
68
69 switch (State.ins_type)
70 {
71 default:
72 case INS_UNKNOWN: type = " ?"; break;
73 case INS_LEFT: type = " L"; break;
74 case INS_RIGHT: type = " R"; break;
75 case INS_LEFT_PARALLEL: type = "*L"; break;
76 case INS_RIGHT_PARALLEL: type = "*R"; break;
77 case INS_LONG: type = " B"; break;
78 }
79
80 printf ("0x%.6x %s: %-*s", (unsigned)PC, type, SIZE_INSTRUCTION, name);
81
82 in[0] = in1;
83 in[1] = in2;
84 in[2] = in3;
85 comma = "";
86 p = buf;
87 for (i = 0; i < 3; i++)
88 {
89 switch (in[i])
90 {
91 case OP_VOID:
92 break;
93
94 case OP_REG:
95 case OP_REG_OUTPUT:
96 case OP_DREG:
97 case OP_DREG_OUTPUT:
98 sprintf (p, "%sr%d", comma, OP[i]);
99 p += strlen (p);
100 comma = ",";
101 break;
102
103 case OP_CR:
104 case OP_CR_OUTPUT:
105 case OP_CR_REVERSE:
106 sprintf (p, "%scr%d", comma, OP[i]);
107 p += strlen (p);
108 comma = ",";
109 break;
110
111 case OP_ACCUM:
112 case OP_ACCUM_OUTPUT:
113 case OP_ACCUM_REVERSE:
114 sprintf (p, "%sa%d", comma, OP[i]);
115 p += strlen (p);
116 comma = ",";
117 break;
118
119 case OP_CONSTANT16:
120 sprintf (p, "%s%d", comma, OP[i]);
121 p += strlen (p);
122 comma = ",";
123 break;
124
125 case OP_CONSTANT4:
126 sprintf (p, "%s%d", comma, SEXT4(OP[i]));
127 p += strlen (p);
128 comma = ",";
129 break;
130
131 case OP_CONSTANT3:
132 sprintf (p, "%s%d", comma, SEXT3(OP[i]));
133 p += strlen (p);
134 comma = ",";
135 break;
136
137 case OP_MEMREF:
138 sprintf (p, "%s@r%d", comma, OP[i]);
139 p += strlen (p);
140 comma = ",";
141 break;
142
143 case OP_MEMREF2:
144 sprintf (p, "%s@(%d,r%d)", comma, (int16)OP[i], OP[i+1]);
145 p += strlen (p);
146 comma = ",";
147 break;
148
149 case OP_POSTINC:
150 sprintf (p, "%s@r%d+", comma, OP[i]);
151 p += strlen (p);
152 comma = ",";
153 break;
154
155 case OP_POSTDEC:
156 sprintf (p, "%s@r%d-", comma, OP[i]);
157 p += strlen (p);
158 comma = ",";
159 break;
160
161 case OP_PREDEC:
162 sprintf (p, "%s@-r%d", comma, OP[i]);
163 p += strlen (p);
164 comma = ",";
165 break;
166
167 case OP_FLAG:
168 if (OP[i] == 0)
169 sprintf (p, "%sf0", comma);
170
171 else if (OP[i] == 1)
172 sprintf (p, "%sf1", comma);
173
174 else
175 sprintf (p, "%scarry", comma);
176
177 p += strlen (p);
178 comma = ",";
179 break;
180 }
181 }
182
183#if (DEBUG & DEBUG_VALUES) == 0
184 *p++ = '\n';
185 *p = '\0';
186 fputs (buf, stdout);
187
188#else /* DEBUG_VALUES */
189 *p = '\0';
190 printf ("%-*s", SIZE_OPERANDS, buf);
191
192 p = buf;
193 for (i = 0; i < 3; i++)
194 {
195 buf[0] = '\0';
196 switch (in[i])
197 {
198 case OP_VOID:
199 printf ("%*s", SIZE_VALUES, "");
200 break;
201
202 case OP_REG_OUTPUT:
203 case OP_DREG_OUTPUT:
204 case OP_CR_OUTPUT:
205 case OP_ACCUM_OUTPUT:
206 printf ("%*s", SIZE_VALUES, "---");
207 break;
208
209 case OP_REG:
210 case OP_MEMREF:
211 case OP_POSTDEC:
212 case OP_POSTINC:
213 case OP_PREDEC:
214 printf ("%*s0x%.4x", SIZE_VALUES-6, "", (uint16)State.regs[OP[i]]);
215 break;
216
217 case OP_DREG:
218 tmp = (long)((((uint32) State.regs[OP[i]]) << 16) | ((uint32) State.regs[OP[i]+1]));
219 printf ("%*s0x%.8lx", SIZE_VALUES-10, "", tmp);
220 break;
221
222 case OP_CR:
223 case OP_CR_REVERSE:
224 printf ("%*s0x%.4x", SIZE_VALUES-6, "", (uint16)State.cregs[OP[i]]);
225 break;
226
227 case OP_ACCUM:
228 case OP_ACCUM_REVERSE:
229 printf ("%*s0x%.2x%.8lx", SIZE_VALUES-12, "",
230 ((int)(State.a[OP[i]] >> 32) & 0xff),
231 ((unsigned long)State.a[OP[i]]) & 0xffffffff);
232 break;
233
234 case OP_CONSTANT16:
235 printf ("%*s0x%.4x", SIZE_VALUES-6, "", (uint16)OP[i]);
236 break;
237
238 case OP_CONSTANT4:
239 printf ("%*s0x%.4x", SIZE_VALUES-6, "", (uint16)SEXT4(OP[i]));
240 break;
241
242 case OP_CONSTANT3:
243 printf ("%*s0x%.4x", SIZE_VALUES-6, "", (uint16)SEXT3(OP[i]));
244 break;
245
246 case OP_FLAG:
247 if (OP[i] == 0)
248 printf ("%*sF0 = %d", SIZE_VALUES-6, "", State.F0 != 0);
249
250 else if (OP[i] == 1)
251 printf ("%*sF1 = %d", SIZE_VALUES-6, "", State.F1 != 0);
252
253 else
254 printf ("%*sC = %d", SIZE_VALUES-5, "", State.C != 0);
255
256 break;
257
258 case OP_MEMREF2:
259 printf ("%*s0x%.4x", SIZE_VALUES-6, "", (uint16)OP[i]);
260 printf ("%*s0x%.4x", SIZE_VALUES-6, "", (uint16)State.regs[OP[++i]]);
261 break;
262 }
263 }
264#endif
265}
266
267static void
268trace_output (result)
269 enum op_types result;
270{
271#if (DEBUG & DEBUG_VALUES) != 0
272 long tmp;
273
274 switch (result)
275 {
276 default:
277 putchar ('\n');
278 break;
279
280 case OP_REG:
281 case OP_REG_OUTPUT:
282 printf (" :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "", (uint16)State.regs[OP[0]],
283 State.F0 != 0, State.F1 != 0, State.C != 0);
284 break;
285
286 case OP_DREG:
287 case OP_DREG_OUTPUT:
288 tmp = (long)((((uint32) State.regs[OP[0]]) << 16) | ((uint32) State.regs[OP[0]+1]));
289 printf (" :: %*s0x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-10, "", tmp,
290 State.F0 != 0, State.F1 != 0, State.C != 0);
291 break;
292
293 case OP_CR:
294 case OP_CR_OUTPUT:
295 printf (" :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "", (uint16)State.cregs[OP[0]],
296 State.F0 != 0, State.F1 != 0, State.C != 0);
297 break;
298
299 case OP_CR_REVERSE:
300 printf (" :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "", (uint16)State.cregs[OP[1]],
301 State.F0 != 0, State.F1 != 0, State.C != 0);
302 break;
303
304 case OP_ACCUM:
305 case OP_ACCUM_OUTPUT:
306 printf (" :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-10, "",
307 ((int)(State.a[OP[0]] >> 32) & 0xff),
308 ((unsigned long)State.a[OP[0]]) & 0xffffffff,
309 State.F0 != 0, State.F1 != 0, State.C != 0);
310 break;
311
312 case OP_ACCUM_REVERSE:
313 printf (" :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-10, "",
314 ((int)(State.a[OP[1]] >> 32) & 0xff),
315 ((unsigned long)State.a[OP[1]]) & 0xffffffff,
316 State.F0 != 0, State.F1 != 0, State.C != 0);
317 break;
318
319 case OP_FLAG:
320 printf (" :: %*s F0=%d F1=%d C=%d\n", SIZE_VALUES, "",
321 State.F0 != 0, State.F1 != 0, State.C != 0);
322 break;
323 }
324
325 fflush (stdout);
326#endif
327}
328
329#else
330#define trace_input(NAME, IN1, IN2, IN3)
331#define trace_output(RESULT)
332#endif
2934d1c9
MH		 333
334/* abs */
335void
336OP_4607 ()
337{
87178dbd 338 trace_input ("abs", OP_REG, OP_VOID, OP_VOID);
2934d1c9
MH		 339 State.F1 = State.F0;
340 if ((int16)(State.regs[OP[0]]) < 0)
341 {
342 State.regs[OP[0]] = -(int16)(State.regs[OP[0]]);
343 State.F0 = 1;
344 }
345 else
346 State.F0 = 0;
87178dbd 347 trace_output (OP_REG);
2934d1c9
MH		 348}
349
350/* abs */
351void
352OP_5607 ()
353{
354 int64 tmp;
355
87178dbd 356 trace_input ("abs", OP_ACCUM, OP_VOID, OP_VOID);
4f425a32
MH		 357 State.F1 = State.F0;
358 State.a[OP[0]] = SEXT40(State.a[OP[0]]);
359
4c38885c 360 if (State.a[OP[0]] < 0 )
2934d1c9 361 {
4c38885c 362 tmp = -State.a[OP[0]];
2934d1c9
MH		 363 if (State.ST)
364 {
4c38885c 365 if (tmp > MAX32)
2934d1c9 366 State.a[OP[0]] = MAX32;
4c38885c 367 else if (tmp < MIN32)
2934d1c9
MH		 368 State.a[OP[0]] = MIN32;
369 else
4f425a32 370 State.a[OP[0]] = tmp & MASK40;
2934d1c9
MH		 371 }
372 else
4f425a32 373 State.a[OP[0]] = tmp & MASK40;
2934d1c9
MH		 374 State.F0 = 1;
375 }
376 else
377 State.F0 = 0;
87178dbd 378 trace_output (OP_ACCUM);
2934d1c9
MH		 379}
380
381/* add */
382void
383OP_200 ()
384{
385 uint16 tmp = State.regs[OP[0]];
87178dbd 386 trace_input ("add", OP_REG, OP_REG, OP_VOID);
2934d1c9
MH		 387 State.regs[OP[0]] += State.regs[OP[1]];
388 if ( tmp > State.regs[OP[0]])
389 State.C = 1;
390 else
391 State.C = 0;
87178dbd 392 trace_output (OP_REG);
2934d1c9
MH		 393}
394
395/* add */
396void
397OP_1201 ()
398{
4c38885c 399 int64 tmp;
4f425a32 400 tmp = SEXT40(State.a[OP[0]]) + (SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]);
87178dbd
MM		 401
402 trace_input ("add", OP_ACCUM, OP_REG, OP_VOID);
4c38885c
MH		 403 if (State.ST)
404 {
405 if ( tmp > MAX32)
406 State.a[OP[0]] = MAX32;
407 else if ( tmp < MIN32)
408 State.a[OP[0]] = MIN32;
409 else
4f425a32 410 State.a[OP[0]] = tmp & MASK40;
4c38885c
MH		 411 }
412 else
4f425a32 413 State.a[OP[0]] = tmp & MASK40;
87178dbd 414 trace_output (OP_ACCUM);
2934d1c9
MH		 415}
416
417/* add */
418void
419OP_1203 ()
420{
4c38885c 421 int64 tmp;
4f425a32 422 tmp = SEXT40(State.a[OP[0]]) + SEXT40(State.a[OP[1]]);
87178dbd
MM		 423
424 trace_input ("add", OP_ACCUM, OP_ACCUM, OP_VOID);
4c38885c
MH		 425 if (State.ST)
426 {
427 if (tmp > MAX32)
428 State.a[OP[0]] = MAX32;
429 else if ( tmp < MIN32)
430 State.a[OP[0]] = MIN32;
431 else
4f425a32 432 State.a[OP[0]] = tmp & MASK40;
4c38885c
MH		 433 }
434 else
4f425a32 435 State.a[OP[0]] = tmp & MASK40;
87178dbd 436 trace_output (OP_ACCUM);
2934d1c9
MH		 437}
438
439/* add2w */
440void
441OP_1200 ()
442{
443 uint32 tmp;
444 uint32 tmp1 = (State.regs[OP[0]]) << 16 | State.regs[OP[0]+1];
445 uint32 tmp2 = (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
87178dbd
MM		 446
447 trace_input ("add2w", OP_DREG, OP_DREG, OP_VOID);
2934d1c9
MH		 448 tmp = tmp1 + tmp2;
449 if ( (tmp < tmp1) || (tmp < tmp2) )
450 State.C = 1;
451 else
452 State.C = 0;
453 State.regs[OP[0]] = tmp >> 16;
454 State.regs[OP[0]+1] = tmp & 0xFFFF;
87178dbd 455 trace_output (OP_DREG);
2934d1c9
MH		 456}
457
458/* add3 */
459void
460OP_1000000 ()
461{
462 uint16 tmp = State.regs[OP[0]];
2934d1c9 463 State.regs[OP[0]] = State.regs[OP[1]] + OP[2];
87178dbd
MM		 464
465 trace_input ("add3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
2934d1c9
MH		 466 if ( tmp > State.regs[OP[0]])
467 State.C = 1;
468 else
469 State.C = 0;
87178dbd 470 trace_output (OP_REG);
2934d1c9
MH		 471}
472
473/* addac3 */
474void
475OP_17000200 ()
476{
4c38885c 477 int64 tmp;
4f425a32 478 tmp = SEXT40(State.a[OP[2]]) + SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
87178dbd
MM		 479
480 trace_input ("addac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
4c38885c
MH		 481 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
482 State.regs[OP[0]+1] = tmp & 0xffff;
87178dbd 483 trace_output (OP_DREG);
2934d1c9
MH		 484}
485
486/* addac3 */
487void
488OP_17000202 ()
489{
4c38885c 490 int64 tmp;
4f425a32 491 tmp = SEXT40(State.a[OP[1]]) + SEXT40(State.a[OP[2]]);
87178dbd
MM		 492
493 trace_input ("addac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
4c38885c
MH		 494 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
495 State.regs[OP[0]+1] = tmp & 0xffff;
87178dbd 496 trace_output (OP_DREG);
2934d1c9
MH		 497}
498
499/* addac3s */
500void
501OP_17001200 ()
502{
4c38885c 503 int64 tmp;
4c38885c 504 State.F1 = State.F0;
87178dbd
MM		 505
506 trace_input ("addac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
4f425a32 507 tmp = SEXT40(State.a[OP[2]]) + SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
4c38885c
MH		 508 if ( tmp > MAX32)
509 {
510 State.regs[OP[0]] = 0x7fff;
511 State.regs[OP[0]+1] = 0xffff;
512 State.F0 = 1;
513 }
514 else if (tmp < MIN32)
515 {
516 State.regs[OP[0]] = 0x8000;
517 State.regs[OP[0]+1] = 0;
518 State.F0 = 1;
519 }
520 else
521 {
522 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
523 State.regs[OP[0]+1] = tmp & 0xffff;
524 State.F0 = 0;
525 }
87178dbd 526 trace_output (OP_DREG);
2934d1c9
MH		 527}
528
529/* addac3s */
530void
531OP_17001202 ()
532{
4c38885c 533 int64 tmp;
4c38885c 534 State.F1 = State.F0;
87178dbd
MM		 535
536 trace_input ("addac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
4f425a32 537 tmp = SEXT40(State.a[OP[1]]) + SEXT40(State.a[OP[2]]);
4c38885c
MH		 538 if ( tmp > MAX32)
539 {
540 State.regs[OP[0]] = 0x7fff;
541 State.regs[OP[0]+1] = 0xffff;
542 State.F0 = 1;
543 }
544 else if (tmp < MIN32)
545 {
546 State.regs[OP[0]] = 0x8000;
547 State.regs[OP[0]+1] = 0;
548 State.F0 = 1;
549 }
550 else
551 {
552 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
553 State.regs[OP[0]+1] = tmp & 0xffff;
554 State.F0 = 0;
555 }
87178dbd 556 trace_output (OP_DREG);
2934d1c9
MH		 557}
558
559/* addi */
560void
561OP_201 ()
562{
4f425a32
MH		 563 if (OP[1] == 0)
564 OP[1] = 16;
87178dbd 565 trace_input ("addi", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 566 State.regs[OP[0]] += OP[1];
87178dbd 567 trace_output (OP_REG);
2934d1c9
MH		 568}
569
570/* and */
571void
572OP_C00 ()
573{
87178dbd 574 trace_input ("and", OP_REG, OP_REG, OP_VOID);
2934d1c9 575 State.regs[OP[0]] &= State.regs[OP[1]];
87178dbd 576 trace_output (OP_REG);
2934d1c9
MH		 577}
578
579/* and3 */
580void
581OP_6000000 ()
582{
87178dbd 583 trace_input ("and3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
2934d1c9 584 State.regs[OP[0]] = State.regs[OP[1]] & OP[2];
87178dbd 585 trace_output (OP_REG);
2934d1c9
MH		 586}
587
588/* bclri */
589void
590OP_C01 ()
591{
87178dbd 592 trace_input ("bclri", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 593 State.regs[OP[0]] &= ~(0x8000 >> OP[1]);
87178dbd 594 trace_output (OP_REG);
2934d1c9
MH		 595}
596
597/* bl.s */
598void
599OP_4900 ()
600{
87178dbd 601 trace_input ("bl.s", OP_CONSTANT16, OP_VOID, OP_VOID);
2934d1c9
MH		 602 State.regs[13] = PC+1;
603 PC += SEXT8 (OP[0]);
87178dbd 604 trace_output (OP_VOID);
2934d1c9
MH		 605}
606
607/* bl.l */
608void
609OP_24800000 ()
610{
87178dbd 611 trace_input ("bl.l", OP_CONSTANT16, OP_VOID, OP_VOID);
2934d1c9
MH		 612 State.regs[13] = PC+1;
613 PC += OP[0];
87178dbd 614 trace_output (OP_VOID);
2934d1c9
MH		 615}
616
617/* bnoti */
618void
619OP_A01 ()
620{
87178dbd 621 trace_input ("bnoti", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 622 State.regs[OP[0]] ^= 0x8000 >> OP[1];
87178dbd 623 trace_output (OP_REG);
2934d1c9
MH		 624}
625
626/* bra.s */
627void
628OP_4800 ()
629{
87178dbd 630 trace_input ("bra.s", OP_CONSTANT16, OP_VOID, OP_VOID);
2934d1c9 631 PC += SEXT8 (OP[0]);
87178dbd 632 trace_output (OP_VOID);
2934d1c9
MH		 633}
634
635/* bra.l */
636void
637OP_24000000 ()
638{
87178dbd 639 trace_input ("bra.l", OP_CONSTANT16, OP_VOID, OP_VOID);
2934d1c9 640 PC += OP[0];
87178dbd 641 trace_output (OP_VOID);
2934d1c9
MH		 642}
643
644/* brf0f.s */
645void
646OP_4A00 ()
647{
87178dbd 648 trace_input ("brf0f.s", OP_CONSTANT16, OP_VOID, OP_VOID);
2934d1c9
MH		 649 if (State.F0 == 0)
650 PC += SEXT8 (OP[0]);
87178dbd 651 trace_output (OP_FLAG);
2934d1c9
MH		 652}
653
654/* brf0f.l */
655void
656OP_25000000 ()
657{
87178dbd 658 trace_input ("brf0f.l", OP_CONSTANT16, OP_VOID, OP_VOID);
2934d1c9
MH		 659 if (State.F0 == 0)
660 PC += OP[0];
87178dbd 661 trace_output (OP_FLAG);
2934d1c9
MH		 662}
663
664/* brf0t.s */
665void
666OP_4B00 ()
667{
87178dbd 668 trace_input ("brf0t.s", OP_CONSTANT16, OP_VOID, OP_VOID);
2934d1c9
MH		 669 if (State.F0)
670 PC += SEXT8 (OP[0]);
87178dbd 671 trace_output (OP_FLAG);
2934d1c9
MH		 672}
673
674/* brf0t.l */
675void
676OP_25800000 ()
677{
87178dbd 678 trace_input ("brf0t.l", OP_CONSTANT16, OP_VOID, OP_VOID);
2934d1c9
MH		 679 if (State.F0)
680 PC += OP[0];
87178dbd 681 trace_output (OP_FLAG);
2934d1c9
MH		 682}
683
684/* bseti */
685void
686OP_801 ()
687{
87178dbd 688 trace_input ("bseti", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 689 State.regs[OP[0]] |= 0x8000 >> OP[1];
87178dbd 690 trace_output (OP_REG);
2934d1c9
MH		 691}
692
693/* btsti */
694void
695OP_E01 ()
696{
87178dbd 697 trace_input ("btsti", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9
MH		 698 State.F1 = State.F0;
699 State.F0 = (State.regs[OP[0]] & (0x8000 >> OP[1])) ? 1 : 0;
87178dbd 700 trace_output (OP_FLAG);
2934d1c9
MH		 701}
702
703/* clrac */
704void
705OP_5601 ()
706{
87178dbd 707 trace_input ("clrac", OP_ACCUM_OUTPUT, OP_VOID, OP_VOID);
2934d1c9 708 State.a[OP[0]] = 0;
87178dbd 709 trace_output (OP_ACCUM);
2934d1c9
MH		 710}
711
712/* cmp */
713void
714OP_600 ()
715{
87178dbd 716 trace_input ("cmp", OP_REG, OP_REG, OP_VOID);
2934d1c9
MH		 717 State.F1 = State.F0;
718 State.F0 = ((int16)(State.regs[OP[0]]) < (int16)(State.regs[OP[1]])) ? 1 : 0;
87178dbd 719 trace_output (OP_FLAG);
2934d1c9
MH		 720}
721
722/* cmp */
723void
724OP_1603 ()
725{
87178dbd 726 trace_input ("cmp", OP_ACCUM, OP_ACCUM, OP_VOID);
4c38885c 727 State.F1 = State.F0;
4f425a32 728 State.F0 = (SEXT40(State.a[OP[0]]) < SEXT40(State.a[OP[1]])) ? 1 : 0;
87178dbd 729 trace_output (OP_FLAG);
2934d1c9
MH		 730}
731
732/* cmpeq */
733void
734OP_400 ()
735{
87178dbd 736 trace_input ("cmpeq", OP_REG, OP_REG, OP_VOID);
2934d1c9
MH		 737 State.F1 = State.F0;
738 State.F0 = (State.regs[OP[0]] == State.regs[OP[1]]) ? 1 : 0;
87178dbd 739 trace_output (OP_FLAG);
2934d1c9
MH		 740}
741
742/* cmpeq */
743void
744OP_1403 ()
745{
87178dbd 746 trace_input ("cmpeq", OP_ACCUM, OP_ACCUM, OP_VOID);
4c38885c
MH		 747 State.F1 = State.F0;
748 State.F0 = (State.a[OP[0]] == State.a[OP[1]]) ? 1 : 0;
87178dbd 749 trace_output (OP_FLAG);
2934d1c9
MH		 750}
751
752/* cmpeqi.s */
753void
754OP_401 ()
755{
87178dbd 756 trace_input ("cmpeqi.s", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9
MH		 757 State.F1 = State.F0;
758 State.F0 = (State.regs[OP[0]] == SEXT4(OP[1])) ? 1 : 0;
87178dbd 759 trace_output (OP_FLAG);
2934d1c9
MH		 760}
761
762/* cmpeqi.l */
763void
764OP_2000000 ()
765{
87178dbd 766 trace_input ("cmpeqi.l", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9
MH		 767 State.F1 = State.F0;
768 State.F0 = (State.regs[OP[0]] == OP[1]) ? 1 : 0;
87178dbd 769 trace_output (OP_FLAG);
2934d1c9
MH		 770}
771
772/* cmpi.s */
773void
774OP_601 ()
775{
87178dbd 776 trace_input ("cmpi.s", OP_REG, OP_CONSTANT4, OP_VOID);
2934d1c9
MH		 777 State.F1 = State.F0;
778 State.F0 = ((int16)(State.regs[OP[0]]) < SEXT4(OP[1])) ? 1 : 0;
87178dbd 779 trace_output (OP_FLAG);
2934d1c9
MH		 780}
781
782/* cmpi.l */
783void
784OP_3000000 ()
785{
87178dbd 786 trace_input ("cmpi.l", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9
MH		 787 State.F1 = State.F0;
788 State.F0 = ((int16)(State.regs[OP[0]]) < (int16)(OP[1])) ? 1 : 0;
87178dbd 789 trace_output (OP_FLAG);
2934d1c9
MH		 790}
791
792/* cmpu */
793void
794OP_4600 ()
795{
87178dbd 796 trace_input ("cmpu", OP_REG, OP_REG, OP_VOID);
2934d1c9
MH		 797 State.F1 = State.F0;
798 State.F0 = (State.regs[OP[0]] < State.regs[OP[1]]) ? 1 : 0;
87178dbd 799 trace_output (OP_FLAG);
2934d1c9
MH		 800}
801
802/* cmpui */
803void
804OP_23000000 ()
805{
87178dbd 806 trace_input ("cmpui", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9
MH		 807 State.F1 = State.F0;
808 State.F0 = (State.regs[OP[0]] < OP[1]) ? 1 : 0;
87178dbd 809 trace_output (OP_FLAG);
2934d1c9
MH		 810}
811
812/* cpfg */
813void
814OP_4E09 ()
815{
816 uint8 *src, *dst;
2934d1c9 817
87178dbd 818 trace_input ("cpfg", OP_FLAG, OP_VOID, OP_VOID);
2934d1c9
MH		 819 if (OP[0] == 0)
820 dst = &State.F0;
821 else
822 dst = &State.F1;
823
824 if (OP[1] == 0)
825 src = &State.F0;
826 else if (OP[1] == 1)
827 src = &State.F1;
828 else
829 src = &State.C;
830
831 *dst = *src;
87178dbd 832 trace_output (OP_FLAG);
2934d1c9
MH		 833}
834
835/* dbt */
836void
837OP_5F20 ()
838{
4f425a32
MH		 839 printf("***** DBT ***** PC=%x\n",PC);
840 State.exception = SIGTRAP;
2934d1c9
MH		 841}
842
843/* divs */
844void
845OP_14002800 ()
846{
847 uint16 foo, tmp, tmpf;
87178dbd
MM		 848
849 trace_input ("divs", OP_DREG, OP_REG, OP_VOID);
2934d1c9
MH		 850 foo = (State.regs[OP[0]] << 1) | (State.regs[OP[0]+1] >> 15);
851 tmp = (int16)foo - (int16)(State.regs[OP[1]]);
852 tmpf = (foo >= State.regs[OP[1]]) ? 1 : 0;
853 State.regs[OP[0]] = (tmpf == 1) ? tmp : foo;
854 State.regs[OP[0]+1] = (State.regs[OP[0]+1] << 1) | tmpf;
87178dbd 855 trace_output (OP_DREG);
2934d1c9
MH		 856}
857
858/* exef0f */
859void
860OP_4E04 ()
861{
87178dbd 862 trace_input ("exef0f", OP_VOID, OP_VOID, OP_VOID);
2934d1c9 863 State.exe = (State.F0) ? 0 : 1;
87178dbd 864 trace_output (OP_FLAG);
2934d1c9
MH		 865}
866
867/* exef0t */
868void
869OP_4E24 ()
870{
87178dbd 871 trace_input ("exef0t", OP_VOID, OP_VOID, OP_VOID);
2934d1c9 872 State.exe = State.F0;
87178dbd 873 trace_output (OP_FLAG);
2934d1c9
MH		 874}
875
876/* exef1f */
877void
878OP_4E40 ()
879{
87178dbd 880 trace_input ("exef1f", OP_VOID, OP_VOID, OP_VOID);
2934d1c9 881 State.exe = (State.F1) ? 0 : 1;
87178dbd 882 trace_output (OP_FLAG);
2934d1c9
MH		 883}
884
885/* exef1t */
886void
887OP_4E42 ()
888{
87178dbd 889 trace_input ("exef1t", OP_VOID, OP_VOID, OP_VOID);
2934d1c9 890 State.exe = State.F1;
87178dbd 891 trace_output (OP_FLAG);
2934d1c9
MH		 892}
893
894/* exefaf */
895void
896OP_4E00 ()
897{
87178dbd 898 trace_input ("exefaf", OP_VOID, OP_VOID, OP_VOID);
2934d1c9 899 State.exe = (State.F0 | State.F1) ? 0 : 1;
87178dbd 900 trace_output (OP_FLAG);
2934d1c9
MH		 901}
902
903/* exefat */
904void
905OP_4E02 ()
906{
87178dbd 907 trace_input ("exefat", OP_VOID, OP_VOID, OP_VOID);
2934d1c9 908 State.exe = (State.F0) ? 0 : (State.F1);
87178dbd 909 trace_output (OP_FLAG);
2934d1c9
MH		 910}
911
912/* exetaf */
913void
914OP_4E20 ()
915{
87178dbd 916 trace_input ("exetaf", OP_VOID, OP_VOID, OP_VOID);
2934d1c9 917 State.exe = (State.F1) ? 0 : (State.F0);
87178dbd 918 trace_output (OP_FLAG);
2934d1c9
MH		 919}
920
921/* exetat */
922void
923OP_4E22 ()
924{
87178dbd 925 trace_input ("exetat", OP_VOID, OP_VOID, OP_VOID);
2934d1c9 926 State.exe = (State.F0) ? (State.F1) : 0;
87178dbd 927 trace_output (OP_FLAG);
2934d1c9
MH		 928}
929
930/* exp */
931void
932OP_15002A00 ()
933{
934 uint32 tmp, foo;
935 int i;
936
87178dbd 937 trace_input ("exp", OP_REG_OUTPUT, OP_DREG, OP_VOID);
4c38885c
MH		 938 if (((int16)State.regs[OP[1]]) >= 0)
939 tmp = (State.regs[OP[1]] << 16) | State.regs[OP[1]+1];
2934d1c9 940 else
4c38885c 941 tmp = ~((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
2934d1c9
MH		 942
943 foo = 0x40000000;
4c38885c 944 for (i=1;i<17;i++)
2934d1c9
MH		 945 {
946 if (tmp & foo)
947 {
948 State.regs[OP[0]] = i-1;
87178dbd 949 trace_output (OP_REG);
2934d1c9
MH		 950 return;
951 }
4c38885c 952 foo >>= 1;
2934d1c9
MH		 953 }
954 State.regs[OP[0]] = 16;
87178dbd 955 trace_output (OP_REG);
2934d1c9
MH		 956}
957
958/* exp */
959void
960OP_15002A02 ()
961{
4c38885c
MH		 962 int64 tmp, foo;
963 int i;
87178dbd
MM		 964
965 trace_input ("exp", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
4f425a32 966 if (SEXT40(State.a[OP[1]]) >= 0)
4c38885c
MH		 967 tmp = State.a[OP[1]];
968 else
969 tmp = ~(State.a[OP[1]]);
970
971 foo = 0x4000000000LL;
972 for (i=1;i<25;i++)
973 {
974 if (tmp & foo)
975 {
976 State.regs[OP[0]] = i-9;
87178dbd 977 trace_output (OP_REG);
4c38885c
MH		 978 return;
979 }
980 foo >>= 1;
981 }
982 State.regs[OP[0]] = 16;
87178dbd 983 trace_output (OP_REG);
2934d1c9
MH		 984}
985
986/* jl */
987void
988OP_4D00 ()
989{
87178dbd 990 trace_input ("jl", OP_REG, OP_VOID, OP_VOID);
2934d1c9
MH		 991 State.regs[13] = PC+1;
992 PC = State.regs[OP[0]];
87178dbd 993 trace_output (OP_VOID);
2934d1c9
MH		 994}
995
996/* jmp */
997void
998OP_4C00 ()
999{
87178dbd 1000 trace_input ("jmp", OP_REG, OP_VOID, OP_VOID);
2934d1c9 1001 PC = State.regs[OP[0]];
87178dbd 1002 trace_output (OP_VOID);
2934d1c9
MH		 1003}
1004
1005/* ld */
1006void
1007OP_30000000 ()
1008{
87178dbd 1009 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
2934d1c9 1010 State.regs[OP[0]] = RW (OP[1] + State.regs[OP[2]]);
87178dbd 1011 trace_output (OP_REG);
2934d1c9
MH		 1012}
1013
1014/* ld */
1015void
1016OP_6401 ()
1017{
87178dbd 1018 trace_input ("ld", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
4c38885c 1019 State.regs[OP[0]] = RW (State.regs[OP[1]]);
4f425a32 1020 INC_ADDR(State.regs[OP[1]],-2);
87178dbd 1021 trace_output (OP_REG);
2934d1c9
MH		 1022}
1023
1024/* ld */
1025void
1026OP_6001 ()
1027{
87178dbd 1028 trace_input ("ld", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
4c38885c 1029 State.regs[OP[0]] = RW (State.regs[OP[1]]);
4f425a32 1030 INC_ADDR(State.regs[OP[1]],2);
87178dbd 1031 trace_output (OP_REG);
2934d1c9
MH		 1032}
1033
1034/* ld */
1035void
1036OP_6000 ()
1037{
87178dbd 1038 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
2934d1c9 1039 State.regs[OP[0]] = RW (State.regs[OP[1]]);
87178dbd 1040 trace_output (OP_REG);
2934d1c9
MH		 1041}
1042
1043/* ld2w */
1044void
1045OP_31000000 ()
1046{
87178dbd 1047 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
2934d1c9
MH		 1048 State.regs[OP[0]] = RW (OP[1] + State.regs[OP[2]]);
1049 State.regs[OP[0]+1] = RW (OP[1] + State.regs[OP[2]] + 2);
87178dbd 1050 trace_output (OP_DREG);
2934d1c9
MH		 1051}
1052
1053/* ld2w */
1054void
1055OP_6601 ()
1056{
87178dbd 1057 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
4c38885c
MH		 1058 State.regs[OP[0]] = RW (State.regs[OP[1]]);
1059 State.regs[OP[0]+1] = RW (State.regs[OP[1]]+2);
4f425a32 1060 INC_ADDR(State.regs[OP[1]],-4);
87178dbd 1061 trace_output (OP_DREG);
2934d1c9
MH		 1062}
1063
1064/* ld2w */
1065void
1066OP_6201 ()
1067{
87178dbd 1068 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
4c38885c
MH		 1069 State.regs[OP[0]] = RW (State.regs[OP[1]]);
1070 State.regs[OP[0]+1] = RW (State.regs[OP[1]]+2);
4f425a32 1071 INC_ADDR(State.regs[OP[1]],4);
87178dbd 1072 trace_output (OP_REG);
2934d1c9
MH		 1073}
1074
1075/* ld2w */
1076void
1077OP_6200 ()
1078{
87178dbd 1079 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
4c38885c
MH		 1080 State.regs[OP[0]] = RW (State.regs[OP[1]]);
1081 State.regs[OP[0]+1] = RW (State.regs[OP[1]]+2);
87178dbd 1082 trace_output (OP_REG);
2934d1c9
MH		 1083}
1084
1085/* ldb */
1086void
1087OP_38000000 ()
1088{
87178dbd 1089 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
2934d1c9
MH		 1090 State.regs[OP[0]] = RB (OP[1] + State.regs[OP[2]]);
1091 SEXT8 (State.regs[OP[0]]);
87178dbd 1092 trace_output (OP_REG);
2934d1c9
MH		 1093}
1094
1095/* ldb */
1096void
1097OP_7000 ()
1098{
87178dbd 1099 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
2934d1c9
MH		 1100 State.regs[OP[0]] = RB (State.regs[OP[1]]);
1101 SEXT8 (State.regs[OP[0]]);
87178dbd 1102 trace_output (OP_REG);
2934d1c9
MH		 1103}
1104
1105/* ldi.s */
1106void
1107OP_4001 ()
1108{
87178dbd 1109 trace_input ("ldi.s", OP_REG_OUTPUT, OP_CONSTANT4, OP_VOID);
2934d1c9 1110 State.regs[OP[0]] = SEXT4(OP[1]);
87178dbd 1111 trace_output (OP_REG);
2934d1c9
MH		 1112}
1113
1114/* ldi.l */
1115void
1116OP_20000000 ()
1117{
87178dbd 1118 trace_input ("ldi.s", OP_REG_OUTPUT, OP_CONSTANT16, OP_VOID);
2934d1c9 1119 State.regs[OP[0]] = OP[1];
87178dbd 1120 trace_output (OP_REG);
2934d1c9
MH		 1121}
1122
1123/* ldub */
1124void
1125OP_39000000 ()
1126{
87178dbd 1127 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
2934d1c9 1128 State.regs[OP[0]] = RB (OP[1] + State.regs[OP[2]]);
87178dbd 1129 trace_output (OP_REG);
2934d1c9
MH		 1130}
1131
1132/* ldub */
1133void
1134OP_7200 ()
1135{
87178dbd 1136 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
2934d1c9 1137 State.regs[OP[0]] = RB (State.regs[OP[1]]);
87178dbd 1138 trace_output (OP_REG);
2934d1c9
MH		 1139}
1140
1141/* mac */
1142void
1143OP_2A00 ()
1144{
4c38885c 1145 int64 tmp;
87178dbd
MM		 1146
1147 trace_input ("mac", OP_ACCUM, OP_REG, OP_REG);
4f425a32 1148 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
4c38885c
MH		 1149
1150 if (State.FX)
4f425a32 1151 tmp = SEXT40( (tmp << 1) & MASK40);
4c38885c
MH		 1152
1153 if (State.ST && tmp > MAX32)
1154 tmp = MAX32;
1155
4f425a32 1156 tmp += SEXT40(State.a[OP[0]]);
4c38885c
MH		 1157 if (State.ST)
1158 {
1159 if (tmp > MAX32)
1160 State.a[OP[0]] = MAX32;
1161 else if (tmp < MIN32)
1162 State.a[OP[0]] = MIN32;
1163 else
4f425a32 1164 State.a[OP[0]] = tmp & MASK40;
4c38885c
MH		 1165 }
1166 else
4f425a32 1167 State.a[OP[0]] = tmp & MASK40;
87178dbd 1168 trace_output (OP_ACCUM);
2934d1c9
MH		 1169}
1170
1171/* macsu */
1172void
1173OP_1A00 ()
1174{
4f425a32 1175 int64 tmp;
87178dbd
MM		 1176
1177 trace_input ("macsu", OP_ACCUM, OP_REG, OP_REG);
4f425a32
MH		 1178 tmp = SEXT40 ((int16)State.regs[OP[1]] * State.regs[OP[2]]);
1179 if (State.FX)
1180 tmp = SEXT40( (tmp << 1) & MASK40);
1181
1182 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) + tmp) & MASK40;
87178dbd 1183 trace_output (OP_ACCUM);
2934d1c9
MH		 1184}
1185
1186/* macu */
1187void
1188OP_3A00 ()
1189{
4f425a32 1190 int64 tmp;
87178dbd
MM		 1191
1192 trace_input ("macu", OP_ACCUM, OP_REG, OP_REG);
4f425a32
MH		 1193 tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
1194 if (State.FX)
1195 tmp = SEXT40( (tmp << 1) & MASK40);
1196 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) + tmp) & MASK40;
87178dbd 1197 trace_output (OP_ACCUM);
2934d1c9
MH		 1198}
1199
1200/* max */
1201void
1202OP_2600 ()
1203{
87178dbd 1204 trace_input ("max", OP_REG, OP_REG, OP_VOID);
2934d1c9
MH		 1205 State.F1 = State.F0;
1206 if (State.regs[OP[1]] > State.regs[OP[0]])
1207 {
1208 State.regs[OP[0]] = State.regs[OP[1]];
1209 State.F0 = 1;
1210 }
1211 else
1212 State.F0 = 0;
87178dbd 1213 trace_output (OP_REG);
2934d1c9
MH		 1214}
1215
1216/* max */
1217void
1218OP_3600 ()
1219{
4f425a32 1220 int64 tmp;
87178dbd
MM		 1221
1222 trace_input ("max", OP_ACCUM, OP_DREG, OP_VOID);
4f425a32
MH		 1223 State.F1 = State.F0;
1224 tmp = SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
1225 if (tmp > SEXT40(State.a[OP[0]]))
1226 {
1227 State.a[OP[0]] = tmp & MASK40;
1228 State.F0 = 1;
1229 }
1230 else
1231 State.F0 = 0;
87178dbd 1232 trace_output (OP_ACCUM);
2934d1c9
MH		 1233}
1234
1235/* max */
1236void
1237OP_3602 ()
1238{
87178dbd 1239 trace_input ("max", OP_ACCUM, OP_ACCUM, OP_VOID);
4f425a32
MH		 1240 State.F1 = State.F0;
1241 if (SEXT40(State.a[OP[1]]) > SEXT40(State.a[OP[0]]))
1242 {
1243 State.a[OP[0]] = State.a[OP[1]];
1244 State.F0 = 1;
1245 }
1246 else
1247 State.F0 = 0;
87178dbd 1248 trace_output (OP_ACCUM);
2934d1c9
MH		 1249}
1250
4f425a32 1251
2934d1c9
MH		 1252/* min */
1253void
1254OP_2601 ()
1255{
87178dbd 1256 trace_input ("min", OP_REG, OP_REG, OP_VOID);
2934d1c9
MH		 1257 State.F1 = State.F0;
1258 if (State.regs[OP[1]] < State.regs[OP[0]])
1259 {
1260 State.regs[OP[0]] = State.regs[OP[1]];
1261 State.F0 = 1;
1262 }
1263 else
1264 State.F0 = 0;
87178dbd 1265 trace_output (OP_REG);
2934d1c9
MH		 1266}
1267
1268/* min */
1269void
1270OP_3601 ()
1271{
4f425a32 1272 int64 tmp;
87178dbd
MM		 1273
1274 trace_input ("min", OP_ACCUM, OP_DREG, OP_VOID);
4f425a32
MH		 1275 State.F1 = State.F0;
1276 tmp = SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
1277 if (tmp < SEXT40(State.a[OP[0]]))
1278 {
1279 State.a[OP[0]] = tmp & MASK40;
1280 State.F0 = 1;
1281 }
1282 else
1283 State.F0 = 0;
87178dbd 1284 trace_output (OP_ACCUM);
2934d1c9
MH		 1285}
1286
1287/* min */
1288void
1289OP_3603 ()
1290{
87178dbd 1291 trace_input ("min", OP_ACCUM, OP_ACCUM, OP_VOID);
4f425a32
MH		 1292 State.F1 = State.F0;
1293 if (SEXT40(State.a[OP[1]]) < SEXT40(State.a[OP[0]]))
1294 {
1295 State.a[OP[0]] = State.a[OP[1]];
1296 State.F0 = 1;
1297 }
1298 else
1299 State.F0 = 0;
87178dbd 1300 trace_output (OP_ACCUM);
2934d1c9
MH		 1301}
1302
1303/* msb */
1304void
1305OP_2800 ()
1306{
4f425a32 1307 int64 tmp;
87178dbd
MM		 1308
1309 trace_input ("msb", OP_ACCUM, OP_REG, OP_REG);
4f425a32
MH		 1310 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
1311
1312 if (State.FX)
1313 tmp = SEXT40 ((tmp << 1) & MASK40);
1314
1315 if (State.ST && tmp > MAX32)
1316 tmp = MAX32;
1317
1318 tmp = SEXT40(State.a[OP[0]]) - tmp;
1319 if (State.ST)
1320 {
1321 if (tmp > MAX32)
1322 State.a[OP[0]] = MAX32;
1323 else if (tmp < MIN32)
1324 State.a[OP[0]] = MIN32;
1325 else
1326 State.a[OP[0]] = tmp & MASK40;
1327 }
1328 else
1329 State.a[OP[0]] = tmp & MASK40;
87178dbd 1330 trace_output (OP_ACCUM);
2934d1c9
MH		 1331}
1332
1333/* msbsu */
1334void
1335OP_1800 ()
1336{
4f425a32 1337 int64 tmp;
87178dbd
MM		 1338
1339 trace_input ("msbsu", OP_ACCUM, OP_REG, OP_REG);
4f425a32
MH		 1340 tmp = SEXT40 ((int16)State.regs[OP[1]] * State.regs[OP[2]]);
1341 if (State.FX)
1342 tmp = SEXT40( (tmp << 1) & MASK40);
1343
1344 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) - tmp) & MASK40;
87178dbd 1345 trace_output (OP_ACCUM);
2934d1c9
MH		 1346}
1347
1348/* msbu */
1349void
1350OP_3800 ()
1351{
4f425a32 1352 int64 tmp;
87178dbd
MM		 1353
1354 trace_input ("msbu", OP_ACCUM, OP_REG, OP_REG);
4f425a32
MH		 1355 tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
1356 if (State.FX)
1357 tmp = SEXT40( (tmp << 1) & MASK40);
1358
1359 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) - tmp) & MASK40;
87178dbd 1360 trace_output (OP_ACCUM);
2934d1c9
MH		 1361}
1362
1363/* mul */
1364void
1365OP_2E00 ()
1366{
87178dbd 1367 trace_input ("mul", OP_REG, OP_REG, OP_VOID);
2934d1c9 1368 State.regs[OP[0]] *= State.regs[OP[1]];
87178dbd 1369 trace_output (OP_REG);
2934d1c9
MH		 1370}
1371
1372/* mulx */
1373void
1374OP_2C00 ()
1375{
4f425a32 1376 int64 tmp;
87178dbd
MM		 1377
1378 trace_input ("mulx", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
4f425a32
MH		 1379 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
1380
1381 if (State.FX)
1382 tmp = SEXT40 ((tmp << 1) & MASK40);
1383
1384 if (State.ST && tmp > MAX32)
1385 State.a[OP[0]] = MAX32;
1386 else
1387 State.a[OP[0]] = tmp & MASK40;
87178dbd 1388 trace_output (OP_ACCUM);
2934d1c9
MH		 1389}
1390
1391/* mulxsu */
1392void
1393OP_1C00 ()
1394{
4f425a32 1395 int64 tmp;
87178dbd
MM		 1396
1397 trace_input ("mulxsu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
4f425a32
MH		 1398 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * State.regs[OP[2]]);
1399
1400 if (State.FX)
1401 tmp <<= 1;
1402
1403 State.a[OP[0]] = tmp & MASK40;
87178dbd 1404 trace_output (OP_ACCUM);
2934d1c9
MH		 1405}
1406
1407/* mulxu */
1408void
1409OP_3C00 ()
1410{
4f425a32 1411 int64 tmp;
87178dbd
MM		 1412
1413 trace_input ("mulxu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
4f425a32
MH		 1414 tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
1415
1416 if (State.FX)
1417 tmp <<= 1;
1418
1419 State.a[OP[0]] = tmp & MASK40;
87178dbd 1420 trace_output (OP_ACCUM);
2934d1c9
MH		 1421}
1422
1423/* mv */
1424void
1425OP_4000 ()
1426{
87178dbd 1427 trace_input ("mv", OP_REG_OUTPUT, OP_REG, OP_VOID);
2934d1c9 1428 State.regs[OP[0]] = State.regs[OP[1]];
87178dbd 1429 trace_output (OP_REG);
2934d1c9
MH		 1430}
1431
1432/* mv2w */
1433void
1434OP_5000 ()
1435{
87178dbd 1436 trace_input ("mv2w", OP_DREG_OUTPUT, OP_DREG, OP_VOID);
2934d1c9
MH		 1437 State.regs[OP[0]] = State.regs[OP[1]];
1438 State.regs[OP[0]+1] = State.regs[OP[1]+1];
87178dbd 1439 trace_output (OP_DREG);
2934d1c9
MH		 1440}
1441
1442/* mv2wfac */
1443void
1444OP_3E00 ()
1445{
87178dbd 1446 trace_input ("mv2wfac", OP_DREG_OUTPUT, OP_ACCUM, OP_VOID);
2934d1c9
MH		 1447 State.regs[OP[0]] = (State.a[OP[1]] >> 16) & 0xffff;
1448 State.regs[OP[0]+1] = State.a[OP[1]] & 0xffff;
87178dbd 1449 trace_output (OP_DREG);
2934d1c9
MH		 1450}
1451
1452/* mv2wtac */
1453void
1454OP_3E01 ()
1455{
87178dbd 1456 trace_input ("mv2wtac", OP_ACCUM_OUTPUT, OP_DREG, OP_VOID);
4f425a32 1457 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]]) << 16 | State.regs[OP[0]+1]) & MASK40;
87178dbd 1458 trace_output (OP_ACCUM);
2934d1c9
MH		 1459}
1460
1461/* mvac */
1462void
1463OP_3E03 ()
1464{
87178dbd 1465 trace_input ("mvac", OP_ACCUM_OUTPUT, OP_ACCUM, OP_VOID);
2934d1c9 1466 State.a[OP[0]] = State.a[OP[1]];
87178dbd 1467 trace_output (OP_ACCUM);
2934d1c9
MH		 1468}
1469
1470/* mvb */
1471void
1472OP_5400 ()
1473{
87178dbd 1474 trace_input ("mvb", OP_REG_OUTPUT, OP_REG, OP_VOID);
2934d1c9 1475 State.regs[OP[0]] = SEXT8 (State.regs[OP[1]] & 0xff);
87178dbd 1476 trace_output (OP_REG);
2934d1c9
MH		 1477}
1478
1479/* mvf0f */
1480void
1481OP_4400 ()
1482{
87178dbd 1483 trace_input ("mf0f", OP_REG_OUTPUT, OP_REG, OP_VOID);
2934d1c9
MH		 1484 if (State.F0 == 0)
1485 State.regs[OP[0]] = State.regs[OP[1]];
87178dbd 1486 trace_output (OP_REG);
2934d1c9
MH		 1487}
1488
1489/* mvf0t */
1490void
1491OP_4401 ()
1492{
87178dbd 1493 trace_input ("mf0t", OP_REG_OUTPUT, OP_REG, OP_VOID);
2934d1c9
MH		 1494 if (State.F0)
1495 State.regs[OP[0]] = State.regs[OP[1]];
87178dbd 1496 trace_output (OP_REG);
2934d1c9
MH		 1497}
1498
1499/* mvfacg */
1500void
1501OP_1E04 ()
1502{
87178dbd 1503 trace_input ("mvfacg", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2934d1c9 1504 State.regs[OP[0]] = (State.a[OP[1]] >> 32) & 0xff;
87178dbd 1505 trace_output (OP_ACCUM);
2934d1c9
MH		 1506}
1507
1508/* mvfachi */
1509void
1510OP_1E00 ()
1511{
87178dbd 1512 trace_input ("mvfachi", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2934d1c9 1513 State.regs[OP[0]] = (State.a[OP[1]] >> 16) & 0xffff;
87178dbd 1514 trace_output (OP_REG);
2934d1c9
MH		 1515}
1516
1517/* mvfaclo */
1518void
1519OP_1E02 ()
1520{
87178dbd 1521 trace_input ("mvfaclo", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2934d1c9 1522 State.regs[OP[0]] = State.a[OP[1]] & 0xffff;
87178dbd 1523 trace_output (OP_REG);
2934d1c9
MH		 1524}
1525
1526/* mvfc */
1527void
1528OP_5200 ()
1529{
87178dbd 1530 trace_input ("mvfc", OP_REG_OUTPUT, OP_CR, OP_VOID);
2934d1c9
MH		 1531 if (OP[1] == 0)
1532 {
1533 /* PSW is treated specially */
1534 PSW = 0;
1535 if (State.SM) PSW |= 0x8000;
1536 if (State.EA) PSW |= 0x2000;
1537 if (State.DB) PSW |= 0x1000;
1538 if (State.IE) PSW |= 0x400;
1539 if (State.RP) PSW |= 0x200;
1540 if (State.MD) PSW |= 0x100;
1541 if (State.FX) PSW |= 0x80;
1542 if (State.ST) PSW |= 0x40;
1543 if (State.F0) PSW |= 8;
1544 if (State.F1) PSW |= 4;
1545 if (State.C) PSW |= 1;
1546 }
1547 State.regs[OP[0]] = State.cregs[OP[1]];
87178dbd 1548 trace_output (OP_REG);
2934d1c9
MH		 1549}
1550
1551/* mvtacg */
1552void
1553OP_1E41 ()
1554{
87178dbd 1555 trace_input ("mvtacg", OP_REG, OP_ACCUM, OP_VOID);
2934d1c9
MH		 1556 State.a[OP[1]] &= MASK32;
1557 State.a[OP[1]] |= (int64)(State.regs[OP[0]] & 0xff) << 32;
87178dbd 1558 trace_output (OP_ACCUM_REVERSE);
2934d1c9
MH		 1559}
1560
1561/* mvtachi */
1562void
1563OP_1E01 ()
1564{
1565 uint16 tmp;
87178dbd
MM		 1566
1567 trace_input ("mvtachi", OP_REG, OP_ACCUM, OP_VOID);
2934d1c9 1568 tmp = State.a[OP[1]] & 0xffff;
4f425a32 1569 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]]) << 16 | tmp) & MASK40;
87178dbd 1570 trace_output (OP_ACCUM_REVERSE);
2934d1c9
MH		 1571}
1572
1573/* mvtaclo */
1574void
1575OP_1E21 ()
1576{
87178dbd 1577 trace_input ("mvtaclo", OP_REG, OP_ACCUM, OP_VOID);
4f425a32 1578 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]])) & MASK40;
87178dbd 1579 trace_output (OP_ACCUM_REVERSE);
2934d1c9
MH		 1580}
1581
1582/* mvtc */
1583void
1584OP_5600 ()
1585{
87178dbd 1586 trace_input ("mvtc", OP_REG, OP_CR_OUTPUT, OP_VOID);
2934d1c9
MH		 1587 State.cregs[OP[1]] = State.regs[OP[0]];
1588 if (OP[1] == 0)
1589 {
1590 /* PSW is treated specially */
1591 State.SM = (PSW & 0x8000) ? 1 : 0;
1592 State.EA = (PSW & 0x2000) ? 1 : 0;
1593 State.DB = (PSW & 0x1000) ? 1 : 0;
1594 State.IE = (PSW & 0x400) ? 1 : 0;
1595 State.RP = (PSW & 0x200) ? 1 : 0;
1596 State.MD = (PSW & 0x100) ? 1 : 0;
1597 State.FX = (PSW & 0x80) ? 1 : 0;
1598 State.ST = (PSW & 0x40) ? 1 : 0;
1599 State.F0 = (PSW & 8) ? 1 : 0;
1600 State.F1 = (PSW & 4) ? 1 : 0;
1601 State.C = PSW & 1;
1602 if (State.ST && !State.FX)
1603 {
1604 fprintf (stderr,"ERROR at PC 0x%x: ST can only be set when FX is set.\n",PC<<2);
4f425a32 1605 State.exception = SIGILL;
2934d1c9
MH		 1606 }
1607 }
87178dbd 1608 trace_output (OP_CR_REVERSE);
2934d1c9
MH		 1609}
1610
1611/* mvub */
1612void
1613OP_5401 ()
1614{
87178dbd 1615 trace_input ("mvub", OP_REG_OUTPUT, OP_REG, OP_VOID);
2934d1c9 1616 State.regs[OP[0]] = State.regs[OP[1]] & 0xff;
87178dbd 1617 trace_output (OP_REG);
2934d1c9
MH		 1618}
1619
1620/* neg */
1621void
1622OP_4605 ()
1623{
87178dbd 1624 trace_input ("neg", OP_REG, OP_VOID, OP_VOID);
2934d1c9 1625 State.regs[OP[0]] = 0 - State.regs[OP[0]];
87178dbd 1626 trace_output (OP_REG);
2934d1c9
MH		 1627}
1628
1629/* neg */
1630void
1631OP_5605 ()
1632{
1633 int64 tmp;
87178dbd
MM		 1634
1635 trace_input ("neg", OP_ACCUM, OP_VOID, OP_VOID);
4f425a32 1636 tmp = -SEXT40(State.a[OP[0]]);
2934d1c9
MH		 1637 if (State.ST)
1638 {
4c38885c 1639 if ( tmp > MAX32)
2934d1c9 1640 State.a[OP[0]] = MAX32;
4c38885c 1641 else if (tmp < MIN32)
2934d1c9
MH		 1642 State.a[OP[0]] = MIN32;
1643 else
4f425a32 1644 State.a[OP[0]] = tmp & MASK40;
2934d1c9
MH		 1645 }
1646 else
4f425a32 1647 State.a[OP[0]] = tmp & MASK40;
87178dbd 1648 trace_output (OP_ACCUM);
2934d1c9
MH		 1649}
1650
1651
1652/* nop */
1653void
1654OP_5E00 ()
1655{
87178dbd
MM		 1656 trace_input ("nop", OP_VOID, OP_VOID, OP_VOID);
1657 trace_output (OP_VOID);
2934d1c9
MH		 1658}
1659
1660/* not */
1661void
1662OP_4603 ()
1663{
87178dbd 1664 trace_input ("not", OP_REG, OP_VOID, OP_VOID);
2934d1c9 1665 State.regs[OP[0]] = ~(State.regs[OP[0]]);
87178dbd 1666 trace_output (OP_REG);
2934d1c9
MH		 1667}
1668
1669/* or */
1670void
1671OP_800 ()
1672{
87178dbd 1673 trace_input ("or", OP_REG, OP_REG, OP_VOID);
2934d1c9 1674 State.regs[OP[0]] |= State.regs[OP[1]];
87178dbd 1675 trace_output (OP_REG);
2934d1c9
MH		 1676}
1677
1678/* or3 */
1679void
1680OP_4000000 ()
1681{
87178dbd 1682 trace_input ("or3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
2934d1c9 1683 State.regs[OP[0]] = State.regs[OP[1]] | OP[2];
87178dbd 1684 trace_output (OP_REG);
2934d1c9
MH		 1685}
1686
1687/* rac */
1688void
1689OP_5201 ()
1690{
1691 int64 tmp;
1692 int shift = SEXT3 (OP[2]);
87178dbd
MM		 1693
1694 trace_input ("rac", OP_DREG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
166acb9f
MH		 1695 if (OP[1] != 0)
1696 {
1697 fprintf (stderr,"ERROR at PC 0x%x: instruction only valid for A0\n",PC<<2);
1698 State.exception = SIGILL;
1699 }
1700
2934d1c9
MH		 1701 State.F1 = State.F0;
1702 if (shift >=0)
1703 tmp = ((State.a[0] << 16) | (State.a[1] & 0xffff)) << shift;
1704 else
1705 tmp = ((State.a[0] << 16) | (State.a[1] & 0xffff)) >> -shift;
166acb9f 1706 tmp = ( SEXT60(tmp) + 0x8000 ) >> 16;
4c38885c 1707 if (tmp > MAX32)
2934d1c9
MH		 1708 {
1709 State.regs[OP[0]] = 0x7fff;
1710 State.regs[OP[0]+1] = 0xffff;
1711 State.F0 = 1;
1712 }
4c38885c 1713 else if (tmp < MIN32)
2934d1c9
MH		 1714 {
1715 State.regs[OP[0]] = 0x8000;
1716 State.regs[OP[0]+1] = 0;
1717 State.F0 = 1;
1718 }
1719 else
1720 {
1721 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
1722 State.regs[OP[0]+1] = tmp & 0xffff;
1723 State.F0 = 0;
1724 }
87178dbd 1725 trace_output (OP_DREG);
2934d1c9
MH		 1726}
1727
1728/* rachi */
1729void
1730OP_4201 ()
1731{
4c38885c
MH		 1732 int64 tmp;
1733 int shift = SEXT3 (OP[2]);
87178dbd
MM		 1734
1735 trace_input ("rachi", OP_REG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
4c38885c
MH		 1736 State.F1 = State.F0;
1737 if (shift >=0)
166acb9f 1738 tmp = SEXT44 (State.a[1]) << shift;
4c38885c 1739 else
166acb9f 1740 tmp = SEXT44 (State.a[1]) >> -shift;
4c38885c 1741 tmp += 0x8000;
63a91cfb 1742
4c38885c
MH		 1743 if (tmp > MAX32)
1744 {
1745 State.regs[OP[0]] = 0x7fff;
1746 State.F0 = 1;
1747 }
1748 else if (tmp < 0xfff80000000LL)
1749 {
1750 State.regs[OP[0]] = 0x8000;
1751 State.F0 = 1;
1752 }
1753 else
1754 {
1755 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
1756 State.F0 = 0;
1757 }
87178dbd 1758 trace_output (OP_REG);
2934d1c9
MH		 1759}
1760
1761/* rep */
1762void
1763OP_27000000 ()
1764{
87178dbd 1765 trace_input ("rep", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9
MH		 1766 RPT_S = PC + 1;
1767 RPT_E = PC + OP[1];
1768 RPT_C = State.regs[OP[0]];
1769 State.RP = 1;
1770 if (RPT_C == 0)
1771 {
1772 fprintf (stderr, "ERROR: rep with count=0 is illegal.\n");
4f425a32 1773 State.exception = SIGILL;
2934d1c9 1774 }
4c38885c
MH		 1775 if (OP[1] < 4)
1776 {
1777 fprintf (stderr, "ERROR: rep must include at least 4 instructions.\n");
4f425a32 1778 State.exception = SIGILL;
4c38885c 1779 }
87178dbd 1780 trace_output (OP_VOID);
2934d1c9
MH		 1781}
1782
1783/* repi */
1784void
1785OP_2F000000 ()
1786{
87178dbd 1787 trace_input ("repi", OP_CONSTANT16, OP_CONSTANT16, OP_VOID);
2934d1c9
MH		 1788 RPT_S = PC + 1;
1789 RPT_E = PC + OP[1];
1790 RPT_C = OP[0];
1791 State.RP = 1;
1792 if (RPT_C == 0)
1793 {
4c38885c 1794 fprintf (stderr, "ERROR: repi with count=0 is illegal.\n");
4f425a32 1795 State.exception = SIGILL;
4c38885c
MH		 1796 }
1797 if (OP[1] < 4)
1798 {
1799 fprintf (stderr, "ERROR: repi must include at least 4 instructions.\n");
4f425a32 1800 State.exception = SIGILL;
2934d1c9 1801 }
87178dbd 1802 trace_output (OP_VOID);
2934d1c9
MH		 1803}
1804
1805/* rtd */
1806void
1807OP_5F60 ()
1808{
87178dbd
MM		 1809 fprintf(stderr, "ERROR: rtd - NOT IMPLEMENTED\n");
1810 State.exception = SIGILL;
2934d1c9
MH		 1811}
1812
1813/* rte */
1814void
1815OP_5F40 ()
1816{
87178dbd 1817 trace_input ("rte", OP_VOID, OP_VOID, OP_VOID);
4c38885c
MH		 1818 PC = BPC;
1819 PSW = BPSW;
87178dbd 1820 trace_output (OP_VOID);
2934d1c9
MH		 1821}
1822
1823/* sadd */
1824void
1825OP_1223 ()
1826{
4c38885c 1827 int64 tmp;
87178dbd
MM		 1828
1829 trace_input ("sadd", OP_ACCUM, OP_ACCUM, OP_VOID);
4f425a32 1830 tmp = SEXT40(State.a[OP[0]]) + (SEXT40(State.a[OP[1]]) >> 16);
4c38885c
MH		 1831 if (State.ST)
1832 {
1833 if (tmp > MAX32)
1834 State.a[OP[0]] = MAX32;
1835 else if (tmp < MIN32)
1836 State.a[OP[0]] = MIN32;
1837 else
4f425a32 1838 State.a[OP[0]] = tmp & MASK40;
4c38885c
MH		 1839 }
1840 else
4f425a32 1841 State.a[OP[0]] = tmp & MASK40;
87178dbd 1842 trace_output (OP_ACCUM);
2934d1c9
MH		 1843}
1844
1845/* setf0f */
1846void
1847OP_4611 ()
1848{
87178dbd 1849 trace_input ("setf0f", OP_REG_OUTPUT, OP_VOID, OP_VOID);
4c38885c 1850 State.regs[OP[0]] = (State.F0 == 0) ? 1 : 0;
87178dbd 1851 trace_output (OP_REG);
2934d1c9
MH		 1852}
1853
1854/* setf0t */
1855void
1856OP_4613 ()
1857{
87178dbd 1858 trace_input ("setf0t", OP_REG_OUTPUT, OP_VOID, OP_VOID);
4c38885c 1859 State.regs[OP[0]] = (State.F0 == 1) ? 1 : 0;
87178dbd 1860 trace_output (OP_REG);
2934d1c9
MH		 1861}
1862
1863/* sleep */
1864void
1865OP_5FC0 ()
1866{
87178dbd 1867 trace_input ("sleep", OP_VOID, OP_VOID, OP_VOID);
4c38885c 1868 State.IE = 1;
87178dbd 1869 trace_output (OP_VOID);
2934d1c9
MH		 1870}
1871
1872/* sll */
1873void
1874OP_2200 ()
1875{
87178dbd 1876 trace_input ("sll", OP_REG, OP_REG, OP_VOID);
2934d1c9 1877 State.regs[OP[0]] <<= (State.regs[OP[1]] & 0xf);
87178dbd 1878 trace_output (OP_REG);
2934d1c9
MH		 1879}
1880
1881/* sll */
1882void
1883OP_3200 ()
1884{
4c38885c 1885 int64 tmp;
87178dbd 1886 trace_input ("sll", OP_ACCUM, OP_REG, OP_VOID);
4c38885c
MH		 1887 if (State.regs[OP[1]] & 31 <= 16)
1888 tmp = SEXT40 (State.a[OP[0]]) << (State.regs[OP[1]] & 31);
1889
1890 if (State.ST)
1891 {
1892 if (tmp > MAX32)
1893 State.a[OP[0]] = MAX32;
1894 else if (tmp < 0xffffff80000000LL)
1895 State.a[OP[0]] = MIN32;
1896 else
1897 State.a[OP[0]] = tmp & MASK40;
1898 }
1899 else
1900 State.a[OP[0]] = tmp & MASK40;
87178dbd 1901 trace_output (OP_ACCUM);
2934d1c9
MH		 1902}
1903
1904/* slli */
1905void
1906OP_2201 ()
1907{
87178dbd 1908 trace_input ("slli", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 1909 State.regs[OP[0]] <<= OP[1];
87178dbd 1910 trace_output (OP_REG);
2934d1c9
MH		 1911}
1912
1913/* slli */
1914void
1915OP_3201 ()
1916{
4c38885c 1917 int64 tmp;
4f425a32
MH		 1918
1919 if (OP[1] == 0)
1920 OP[1] = 16;
4f425a32 1921
87178dbd 1922 trace_input ("slli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
4f425a32 1923 tmp = SEXT40(State.a[OP[0]]) << OP[1];
4c38885c
MH		 1924
1925 if (State.ST)
1926 {
1927 if (tmp > MAX32)
1928 State.a[OP[0]] = MAX32;
1929 else if (tmp < 0xffffff80000000LL)
1930 State.a[OP[0]] = MIN32;
1931 else
1932 State.a[OP[0]] = tmp & MASK40;
1933 }
1934 else
1935 State.a[OP[0]] = tmp & MASK40;
87178dbd 1936 trace_output (OP_ACCUM);
2934d1c9
MH		 1937}
1938
1939/* slx */
1940void
1941OP_460B ()
1942{
1943 uint16 tmp;
87178dbd
MM		 1944
1945 trace_input ("slx", OP_REG, OP_FLAG, OP_VOID);
2934d1c9 1946 State.regs[OP[0]] = (State.regs[OP[0]] << 1) | State.F0;
87178dbd 1947 trace_output (OP_REG);
2934d1c9
MH		 1948}
1949
1950/* sra */
1951void
1952OP_2400 ()
1953{
87178dbd 1954 trace_input ("sra", OP_REG, OP_REG, OP_VOID);
2934d1c9 1955 State.regs[OP[0]] = ((int16)(State.regs[OP[0]])) >> (State.regs[OP[1]] & 0xf);
87178dbd 1956 trace_output (OP_REG);
2934d1c9
MH		 1957}
1958
1959/* sra */
1960void
1961OP_3400 ()
1962{
87178dbd 1963 trace_input ("sra", OP_ACCUM, OP_REG, OP_VOID);
4c38885c
MH		 1964 if (State.regs[OP[1]] & 31 <= 16)
1965 State.a[OP[0]] >>= (State.regs[OP[1]] & 31);
87178dbd 1966 trace_output (OP_ACCUM);
2934d1c9
MH		 1967}
1968
1969/* srai */
1970void
1971OP_2401 ()
1972{
87178dbd 1973 trace_input ("srai", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 1974 State.regs[OP[0]] = ((int16)(State.regs[OP[0]])) >> OP[1];
87178dbd 1975 trace_output (OP_REG);
2934d1c9
MH		 1976}
1977
1978/* srai */
1979void
1980OP_3401 ()
1981{
4f425a32
MH		 1982 if (OP[1] == 0)
1983 OP[1] = 16;
87178dbd
MM		 1984
1985 trace_input ("srai", OP_ACCUM, OP_CONSTANT16, OP_VOID);
1986 State.a[OP[0]] >>= OP[1];
1987 trace_output (OP_ACCUM);
2934d1c9
MH		 1988}
1989
1990/* srl */
1991void
1992OP_2000 ()
1993{
87178dbd 1994 trace_input ("srl", OP_REG, OP_REG, OP_VOID);
2934d1c9 1995 State.regs[OP[0]] >>= (State.regs[OP[1]] & 0xf);
87178dbd 1996 trace_output (OP_REG);
2934d1c9
MH		 1997}
1998
1999/* srl */
2000void
2001OP_3000 ()
2002{
87178dbd 2003 trace_input ("srl", OP_ACCUM, OP_REG, OP_VOID);
4c38885c
MH		 2004 if (State.regs[OP[1]] & 31 <= 16)
2005 State.a[OP[0]] >>= (State.regs[OP[1]] & 31);
87178dbd 2006 trace_output (OP_ACCUM);
2934d1c9
MH		 2007}
2008
2009/* srli */
2010void
2011OP_2001 ()
2012{
87178dbd 2013 trace_input ("srli", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 2014 State.regs[OP[0]] >>= OP[1];
87178dbd 2015 trace_output (OP_REG);
2934d1c9
MH		 2016}
2017
2018/* srli */
2019void
2020OP_3001 ()
2021{
4f425a32
MH		 2022 if (OP[1] == 0)
2023 OP[1] = 16;
87178dbd
MM		 2024
2025 trace_input ("srli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2026 State.a[OP[0]] >>= OP[1];
2027 trace_output (OP_ACCUM);
2934d1c9
MH		 2028}
2029
2030/* srx */
2031void
2032OP_4609 ()
2033{
2034 uint16 tmp;
87178dbd
MM		 2035
2036 trace_input ("srx", OP_REG, OP_FLAG, OP_VOID);
2934d1c9
MH		 2037 tmp = State.F0 << 15;
2038 State.regs[OP[0]] = (State.regs[OP[0]] >> 1) | tmp;
87178dbd 2039 trace_output (OP_REG);
2934d1c9
MH		 2040}
2041
2042/* st */
2043void
2044OP_34000000 ()
2045{
87178dbd 2046 trace_input ("st", OP_REG, OP_MEMREF2, OP_VOID);
2934d1c9 2047 SW (OP[1] + State.regs[OP[2]], State.regs[OP[0]]);
87178dbd 2048 trace_output (OP_VOID);
2934d1c9
MH		 2049}
2050
2051/* st */
2052void
2053OP_6800 ()
2054{
87178dbd 2055 trace_input ("st", OP_REG, OP_MEMREF, OP_VOID);
2934d1c9 2056 SW (State.regs[OP[1]], State.regs[OP[0]]);
87178dbd 2057 trace_output (OP_VOID);
2934d1c9
MH		 2058}
2059
2060/* st */
2061void
2062OP_6C1F ()
2063{
87178dbd 2064 trace_input ("st", OP_REG, OP_PREDEC, OP_VOID);
4c38885c
MH		 2065 if ( OP[1] != 15 )
2066 {
2067 fprintf (stderr,"ERROR: cannot pre-decrement any registers but r15 (SP).\n");
4f425a32
MH		 2068 State.exception = SIGILL;
2069 return;
4c38885c
MH		 2070 }
2071 State.regs[OP[1]] -= 2;
2072 SW (State.regs[OP[1]], State.regs[OP[0]]);
87178dbd 2073 trace_output (OP_VOID);
2934d1c9
MH		 2074}
2075
2076/* st */
2077void
2078OP_6801 ()
2079{
87178dbd 2080 trace_input ("st", OP_REG, OP_POSTINC, OP_VOID);
4c38885c 2081 SW (State.regs[OP[1]], State.regs[OP[0]]);
4f425a32 2082 INC_ADDR (State.regs[OP[1]],2);
87178dbd 2083 trace_output (OP_VOID);
2934d1c9
MH		 2084}
2085
2086/* st */
2087void
2088OP_6C01 ()
2089{
87178dbd 2090 trace_input ("st", OP_REG, OP_POSTDEC, OP_VOID);
4c38885c 2091 SW (State.regs[OP[1]], State.regs[OP[0]]);
4f425a32 2092 INC_ADDR (State.regs[OP[1]],-2);
87178dbd 2093 trace_output (OP_VOID);
2934d1c9
MH		 2094}
2095
2096/* st2w */
2097void
2098OP_35000000 ()
2099{
87178dbd 2100 trace_input ("st2w", OP_DREG, OP_MEMREF2, OP_VOID);
4f425a32
MH		 2101 SW (State.regs[OP[2]]+OP[1], State.regs[OP[0]]);
2102 SW (State.regs[OP[2]]+OP[1]+2, State.regs[OP[0]+1]);
87178dbd 2103 trace_output (OP_VOID);
2934d1c9
MH		 2104}
2105
2106/* st2w */
2107void
2108OP_6A00 ()
2109{
87178dbd 2110 trace_input ("st2w", OP_REG, OP_MEMREF, OP_VOID);
4c38885c
MH		 2111 SW (State.regs[OP[1]], State.regs[OP[0]]);
2112 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
87178dbd 2113 trace_output (OP_VOID);
2934d1c9
MH		 2114}
2115
2116/* st2w */
2117void
2118OP_6E1F ()
2119{
87178dbd 2120 trace_input ("st2w", OP_REG, OP_PREDEC, OP_VOID);
4c38885c
MH		 2121 if ( OP[1] != 15 )
2122 {
2123 fprintf (stderr,"ERROR: cannot pre-decrement any registers but r15 (SP).\n");
4f425a32
MH		 2124 State.exception = SIGILL;
2125 return;
4c38885c
MH		 2126 }
2127 State.regs[OP[1]] -= 4;
2128 SW (State.regs[OP[1]], State.regs[OP[0]]);
2129 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
87178dbd 2130 trace_output (OP_VOID);
2934d1c9
MH		 2131}
2132
2133/* st2w */
2134void
2135OP_6A01 ()
2136{
87178dbd 2137 trace_input ("st2w", OP_REG, OP_POSTDEC, OP_VOID);
4c38885c
MH		 2138 SW (State.regs[OP[1]], State.regs[OP[0]]);
2139 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
4f425a32 2140 INC_ADDR (State.regs[OP[1]],4);
87178dbd 2141 trace_output (OP_VOID);
2934d1c9
MH		 2142}
2143
2144/* st2w */
2145void
2146OP_6E01 ()
2147{
87178dbd 2148 trace_input ("st2w", OP_REG, OP_POSTINC, OP_VOID);
4c38885c
MH		 2149 SW (State.regs[OP[1]], State.regs[OP[0]]);
2150 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
4f425a32 2151 INC_ADDR (State.regs[OP[1]],-4);
87178dbd 2152 trace_output (OP_VOID);
2934d1c9
MH		 2153}
2154
2155/* stb */
2156void
2157OP_3C000000 ()
2158{
87178dbd 2159 trace_input ("stb", OP_REG, OP_MEMREF2, OP_VOID);
4f425a32 2160 SB (State.regs[OP[2]]+OP[1], State.regs[OP[0]]);
87178dbd 2161 trace_output (OP_VOID);
2934d1c9
MH		 2162}
2163
2164/* stb */
2165void
2166OP_7800 ()
2167{
87178dbd 2168 trace_input ("stb", OP_REG, OP_MEMREF, OP_VOID);
4c38885c 2169 SB (State.regs[OP[1]], State.regs[OP[0]]);
87178dbd 2170 trace_output (OP_VOID);
2934d1c9
MH		 2171}
2172
2173/* stop */
2174void
2175OP_5FE0 ()
2176{
87178dbd 2177 trace_input ("stop", OP_VOID, OP_VOID, OP_VOID);
4f425a32 2178 State.exception = SIGQUIT;
87178dbd 2179 trace_output (OP_VOID);
2934d1c9
MH		 2180}
2181
2182/* sub */
2183void
2184OP_0 ()
4c38885c
MH		 2185{
2186 int32 tmp;
87178dbd
MM		 2187
2188 trace_input ("sub", OP_REG, OP_REG, OP_VOID);
4c38885c
MH		 2189 tmp = (int16)State.regs[OP[0]]- (int16)State.regs[OP[1]];
2190 State.C = (tmp & 0xffff0000) ? 1 : 0;
2191 State.regs[OP[0]] = tmp & 0xffff;
87178dbd 2192 trace_output (OP_REG);
4c38885c
MH		 2193}
2194
2195/* sub */
2196void
2197OP_1001 ()
2198{
4f425a32 2199 int64 tmp;
87178dbd
MM		 2200
2201 trace_input ("sub", OP_ACCUM, OP_DREG, OP_VOID);
4f425a32
MH		 2202 tmp = SEXT40(State.a[OP[0]]) - (SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]);
2203 if (State.ST)
2204 {
2205 if ( tmp > MAX32)
2206 State.a[OP[0]] = MAX32;
2207 else if ( tmp < MIN32)
2208 State.a[OP[0]] = MIN32;
2209 else
2210 State.a[OP[0]] = tmp & MASK40;
2211 }
2212 else
2213 State.a[OP[0]] = tmp & MASK40;
87178dbd
MM		 2214
2215 trace_output (OP_ACCUM);
4c38885c
MH		 2216}
2217
2218/* sub */
2219
2220void
2221OP_1003 ()
2934d1c9 2222{
4f425a32 2223 int64 tmp;
87178dbd
MM		 2224
2225 trace_input ("sub", OP_ACCUM, OP_ACCUM, OP_VOID);
4f425a32
MH		 2226 tmp = SEXT40(State.a[OP[0]]) - SEXT40(State.a[OP[1]]);
2227 if (State.ST)
2228 {
2229 if (tmp > MAX32)
2230 State.a[OP[0]] = MAX32;
2231 else if ( tmp < MIN32)
2232 State.a[OP[0]] = MIN32;
2233 else
2234 State.a[OP[0]] = tmp & MASK40;
2235 }
2236 else
2237 State.a[OP[0]] = tmp & MASK40;
87178dbd
MM		 2238
2239 trace_output (OP_ACCUM);
2934d1c9
MH		 2240}
2241
2242/* sub2w */
2243void
2244OP_1000 ()
2245{
4c38885c
MH		 2246 int64 tmp;
2247 int32 a,b;
4c38885c 2248
87178dbd 2249 trace_input ("sub2w", OP_DREG, OP_DREG, OP_VOID);
4c38885c
MH		 2250 a = (int32)((State.regs[OP[0]] << 16) | State.regs[OP[0]+1]);
2251 b = (int32)((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
2252 tmp = a-b;
2253 State.C = (tmp & 0xffffffff00000000LL) ? 1 : 0;
2254 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2255 State.regs[OP[0]+1] = tmp & 0xffff;
87178dbd 2256 trace_output (OP_DREG);
2934d1c9
MH		 2257}
2258
2259/* subac3 */
2260void
2261OP_17000000 ()
2262{
4f425a32 2263 int64 tmp;
87178dbd
MM		 2264
2265 trace_input ("subac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
4f425a32
MH		 2266 tmp = SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]) - SEXT40 (State.a[OP[2]]);
2267 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2268 State.regs[OP[0]+1] = tmp & 0xffff;
87178dbd 2269 trace_output (OP_DREG);
2934d1c9
MH		 2270}
2271
2272/* subac3 */
2273void
2274OP_17000002 ()
2275{
4f425a32 2276 int64 tmp;
87178dbd
MM		 2277
2278 trace_input ("subac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
4f425a32
MH		 2279 tmp = SEXT40(State.a[OP[1]]) - SEXT40(State.a[OP[2]]);
2280 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2281 State.regs[OP[0]+1] = tmp & 0xffff;
87178dbd 2282 trace_output (OP_DREG);
2934d1c9
MH		 2283}
2284
2285/* subac3s */
2286void
2287OP_17001000 ()
2288{
4f425a32 2289 int64 tmp;
87178dbd
MM		 2290
2291 trace_input ("subac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
4f425a32
MH		 2292 State.F1 = State.F0;
2293 tmp = SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]) - SEXT40(State.a[OP[2]]);
2294 if ( tmp > MAX32)
2295 {
2296 State.regs[OP[0]] = 0x7fff;
2297 State.regs[OP[0]+1] = 0xffff;
2298 State.F0 = 1;
2299 }
2300 else if (tmp < MIN32)
2301 {
2302 State.regs[OP[0]] = 0x8000;
2303 State.regs[OP[0]+1] = 0;
2304 State.F0 = 1;
2305 }
2306 else
2307 {
2308 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2309 State.regs[OP[0]+1] = tmp & 0xffff;
2310 State.F0 = 0;
2311 }
87178dbd 2312 trace_output (OP_DREG);
2934d1c9
MH		 2313}
2314
2315/* subac3s */
2316void
2317OP_17001002 ()
2318{
4f425a32 2319 int64 tmp;
87178dbd
MM		 2320
2321 trace_input ("subac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
4f425a32
MH		 2322 State.F1 = State.F0;
2323 tmp = SEXT40(State.a[OP[1]]) - SEXT40(State.a[OP[2]]);
2324 if ( tmp > MAX32)
2325 {
2326 State.regs[OP[0]] = 0x7fff;
2327 State.regs[OP[0]+1] = 0xffff;
2328 State.F0 = 1;
2329 }
2330 else if (tmp < MIN32)
2331 {
2332 State.regs[OP[0]] = 0x8000;
2333 State.regs[OP[0]+1] = 0;
2334 State.F0 = 1;
2335 }
2336 else
2337 {
2338 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2339 State.regs[OP[0]+1] = tmp & 0xffff;
2340 State.F0 = 0;
2341 }
87178dbd 2342 trace_output (OP_DREG);
2934d1c9
MH		 2343}
2344
2345/* subi */
2346void
2347OP_1 ()
2348{
4c38885c 2349 int32 tmp;
4f425a32
MH		 2350 if (OP[1] == 0)
2351 OP[1] = 16;
87178dbd
MM		 2352
2353 trace_input ("subi", OP_REG, OP_CONSTANT16, OP_VOID);
4c38885c
MH		 2354 tmp = (int16)State.regs[OP[0]] - OP[1];
2355 State.C = (tmp & 0xffff0000) ? 1 : 0;
2356 State.regs[OP[0]] = tmp & 0xffff;
87178dbd 2357 trace_output (OP_REG);
2934d1c9
MH		 2358}
2359
2360/* trap */
2361void
2362OP_5F00 ()
2363{
87178dbd
MM		 2364 trace_input ("trap", OP_CONSTANT16, OP_REG, OP_VOID);
2365 trace_output (OP_VOID);
2934d1c9 2366
63a91cfb 2367 switch (OP[0])
2934d1c9 2368 {
63a91cfb
MM		 2369 default:
2370 fprintf (stderr, "Unknown trap code %d\n", OP[0]);
2371 State.exception = SIGILL;
2372
2373 case 0:
2374 /* Trap 0 is used for simulating low-level I/O */
2375 {
2376 int save_errno = errno;
2377 errno = 0;
2378
2379/* Registers passed to trap 0 */
2380
2381#define FUNC State.regs[2] /* function number, return value */
2382#define PARM1 State.regs[3] /* optional parm 1 */
2383#define PARM2 State.regs[4] /* optional parm 2 */
2384#define PARM3 State.regs[5] /* optional parm 3 */
2385
2386/* Registers set by trap 0 */
2387
2388#define RETVAL State.regs[2] /* return value */
2389#define RETERR State.regs[3] /* return error code */
2390
2391/* Turn a pointer in a register into a pointer into real memory. */
2392
2393#define MEMPTR(x) ((char *)((x) + State.imem))
2394
2395 switch (FUNC)
2396 {
2397#if !defined(__GO32__) && !defined(_WIN32)
2398#ifdef SYS_fork
2399 case SYS_fork:
2400 RETVAL = fork ();
2401 break;
2402#endif
2403#ifdef SYS_execve
2404 case SYS_execve:
2405 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2),
2406 (char **)MEMPTR (PARM3));
2407 break;
2408#endif
2409#ifdef SYS_execv
2410 case SYS_execv:
2411 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL);
2412 break;
2413#endif
2414#ifdef SYS_pipe
2415 case SYS_pipe:
2416 {
2417 reg_t buf;
2418 int host_fd[2];
2419
2420 buf = PARM1;
2421 RETVAL = pipe (host_fd);
2422 SW (buf, host_fd[0]);
2423 buf += sizeof(uint16);
2424 SW (buf, host_fd[1]);
2425 }
2426 break;
2427#endif
2428#ifdef SYS_wait
2429 case SYS_wait:
2430 {
2431 int status;
2432
2433 RETVAL = wait (&status);
2434 SW (PARM1, status);
2435 }
2436 break;
2437#endif
2438#endif
2439
2440#ifdef SYS_read
2441 case SYS_read:
2442 RETVAL = d10v_callback->read (d10v_callback, PARM1, MEMPTR (PARM2),
2443 PARM3);
2444 break;
2445#endif
2446#ifdef SYS_write
2447 case SYS_write:
2448 if (PARM1 == 1)
2449 RETVAL = (int)d10v_callback->write_stdout (d10v_callback,
2450 MEMPTR (PARM2), PARM3);
2451 else
2452 RETVAL = (int)d10v_callback->write (d10v_callback, PARM1,
2453 MEMPTR (PARM2), PARM3);
2454 break;
2455#endif
2456#ifdef SYS_lseek
2457 case SYS_lseek:
2458 RETVAL = d10v_callback->lseek (d10v_callback, PARM1, PARM2, PARM3);
2459 break;
2460#endif
2461#ifdef SYS_close
2462 case SYS_close:
2463 RETVAL = d10v_callback->close (d10v_callback, PARM1);
2464 break;
2465#endif
2466#ifdef SYS_open
2467 case SYS_open:
2468 RETVAL = d10v_callback->open (d10v_callback, MEMPTR (PARM1), PARM2);
2469 break;
2470#endif
2471#ifdef SYS_exit
2472 case SYS_exit:
2473 /* EXIT - caller can look in PARM1 to work out the
2474 reason */
2475 State.exception = SIGQUIT;
2476 break;
2477#endif
2478
8719be26
MA		 2479#ifdef SYS_stat
2480 case SYS_stat:
63a91cfb
MM		 2481 /* stat system call */
2482 {
2483 struct stat host_stat;
2484 reg_t buf;
2485
2486 RETVAL = stat (MEMPTR (PARM1), &host_stat);
2487
2488 buf = PARM2;
2489
2490 /* The hard-coded offsets and sizes were determined by using
2491 * the D10V compiler on a test program that used struct stat.
2492 */
2493 SW (buf, host_stat.st_dev);
2494 SW (buf+2, host_stat.st_ino);
2495 SW (buf+4, host_stat.st_mode);
2496 SW (buf+6, host_stat.st_nlink);
2497 SW (buf+8, host_stat.st_uid);
2498 SW (buf+10, host_stat.st_gid);
2499 SW (buf+12, host_stat.st_rdev);
2500 SLW (buf+16, host_stat.st_size);
2501 SLW (buf+20, host_stat.st_atime);
2502 SLW (buf+28, host_stat.st_mtime);
2503 SLW (buf+36, host_stat.st_ctime);
2504 }
2505 break;
2506#endif
2507
2508#ifdef SYS_chown
2509 case SYS_chown:
2510 RETVAL = chown (MEMPTR (PARM1), PARM2, PARM3);
2511 break;
2512#endif
2513#ifdef SYS_chmod
2514 case SYS_chmod:
2515 RETVAL = chmod (MEMPTR (PARM1), PARM2);
2516 break;
2517#endif
2518#ifdef SYS_utime
2519 case SYS_utime:
2520 /* Cast the second argument to void *, to avoid type mismatch
2521 if a prototype is present. */
2522 RETVAL = utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2));
2523 break;
2524#endif
2525 default:
2526 abort ();
2527 }
2528 RETERR = errno;
2529 errno = save_errno;
2530 break;
2531 }
2532
2533 case 1:
2534 /* Trap 1 prints a string */
2535 {
2536 char *fstr = State.regs[2] + State.imem;
2537 fputs (fstr, stdout);
2538 break;
2539 }
2540
2541 case 2:
2542 /* Trap 2 calls printf */
2543 {
2544 char *fstr = State.regs[2] + State.imem;
87178dbd 2545 printf (fstr, (int16)State.regs[3], (int16)State.regs[4], (int16)State.regs[5]);
63a91cfb
MM		 2546 break;
2547 }
2548
2549 case 3:
2550 /* Trap 3 writes a character */
2551 putchar (State.regs[2]);
2552 break;
2934d1c9
MH		 2553 }
2554}
2555
2556/* tst0i */
2557void
2558OP_7000000 ()
2559{
87178dbd 2560 trace_input ("tst0i", OP_REG, OP_CONSTANT16, OP_VOID);
4c38885c 2561 State.F1 = State.F0;
4f425a32 2562 State.F0 = (State.regs[OP[0]] & OP[1]) ? 1 : 0;
87178dbd 2563 trace_output (OP_FLAG);
2934d1c9
MH		 2564}
2565
2566/* tst1i */
2567void
2568OP_F000000 ()
2569{
87178dbd 2570 trace_input ("tst1i", OP_REG, OP_CONSTANT16, OP_VOID);
4c38885c 2571 State.F1 = State.F0;
4f425a32 2572 State.F0 = (~(State.regs[OP[0]]) & OP[1]) ? 1 : 0;
87178dbd 2573 trace_output (OP_FLAG);
2934d1c9
MH		 2574}
2575
2576/* wait */
2577void
2578OP_5F80 ()
2579{
87178dbd 2580 trace_input ("wait", OP_VOID, OP_VOID, OP_VOID);
4c38885c 2581 State.IE = 1;
87178dbd 2582 trace_output (OP_VOID);
2934d1c9
MH		 2583}
2584
2585/* xor */
2586void
2587OP_A00 ()
2588{
87178dbd 2589 trace_input ("xor", OP_REG, OP_REG, OP_VOID);
4c38885c 2590 State.regs[OP[0]] ^= State.regs[OP[1]];
87178dbd 2591 trace_output (OP_REG);
2934d1c9
MH		 2592}
2593
2594/* xor3 */
2595void
2596OP_5000000 ()
2597{
87178dbd 2598 trace_input ("xor3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
4c38885c 2599 State.regs[OP[0]] = State.regs[OP[1]] ^ OP[2];
87178dbd 2600 trace_output (OP_REG);
2934d1c9
MH		 2601}
2602
GDB Binutils - Deliverables
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