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c906108c SS |
1 | #include "config.h" |
2 | ||
3 | #include <signal.h> | |
4 | #include <errno.h> | |
5 | #include <sys/types.h> | |
6 | #include <sys/stat.h> | |
7 | #ifdef HAVE_UNISTD_H | |
8 | #include <unistd.h> | |
9 | #endif | |
10 | ||
11 | #include "d10v_sim.h" | |
12 | #include "simops.h" | |
13 | #include "targ-vals.h" | |
14 | ||
15 | extern char *strrchr (); | |
16 | ||
17 | enum op_types { | |
18 | OP_VOID, | |
19 | OP_REG, | |
20 | OP_REG_OUTPUT, | |
21 | OP_DREG, | |
22 | OP_DREG_OUTPUT, | |
23 | OP_ACCUM, | |
24 | OP_ACCUM_OUTPUT, | |
25 | OP_ACCUM_REVERSE, | |
26 | OP_CR, | |
27 | OP_CR_OUTPUT, | |
28 | OP_CR_REVERSE, | |
29 | OP_FLAG, | |
30 | OP_FLAG_OUTPUT, | |
31 | OP_CONSTANT16, | |
32 | OP_CONSTANT8, | |
33 | OP_CONSTANT3, | |
34 | OP_CONSTANT4, | |
35 | OP_MEMREF, | |
36 | OP_MEMREF2, | |
cff3e48b | 37 | OP_MEMREF3, |
c906108c SS |
38 | OP_POSTDEC, |
39 | OP_POSTINC, | |
40 | OP_PREDEC, | |
41 | OP_R0, | |
42 | OP_R1, | |
43 | OP_R2, | |
44 | }; | |
45 | ||
46 | ||
47 | enum { | |
48 | PSW_MASK = (PSW_SM_BIT | |
49 | | PSW_EA_BIT | |
50 | | PSW_DB_BIT | |
c906108c SS |
51 | | PSW_IE_BIT |
52 | | PSW_RP_BIT | |
53 | | PSW_MD_BIT | |
54 | | PSW_FX_BIT | |
55 | | PSW_ST_BIT | |
56 | | PSW_F0_BIT | |
57 | | PSW_F1_BIT | |
58 | | PSW_C_BIT), | |
4ce44c66 JM |
59 | /* The following bits in the PSW _can't_ be set by instructions such |
60 | as mvtc. */ | |
61 | PSW_HW_MASK = (PSW_MASK | PSW_DM_BIT) | |
c906108c SS |
62 | }; |
63 | ||
64 | reg_t | |
4ce44c66 | 65 | move_to_cr (int cr, reg_t mask, reg_t val, int psw_hw_p) |
c906108c SS |
66 | { |
67 | /* A MASK bit is set when the corresponding bit in the CR should | |
68 | be left alone */ | |
69 | /* This assumes that (VAL & MASK) == 0 */ | |
70 | switch (cr) | |
71 | { | |
72 | case PSW_CR: | |
4ce44c66 JM |
73 | if (psw_hw_p) |
74 | val &= PSW_HW_MASK; | |
75 | else | |
76 | val &= PSW_MASK; | |
c906108c SS |
77 | if ((mask & PSW_SM_BIT) == 0) |
78 | { | |
4ce44c66 JM |
79 | int new_psw_sm = (val & PSW_SM_BIT) != 0; |
80 | /* save old SP */ | |
81 | SET_HELD_SP (PSW_SM, GPR (SP_IDX)); | |
82 | if (PSW_SM != new_psw_sm) | |
83 | /* restore new SP */ | |
84 | SET_GPR (SP_IDX, HELD_SP (new_psw_sm)); | |
c906108c SS |
85 | } |
86 | if ((mask & (PSW_ST_BIT | PSW_FX_BIT)) == 0) | |
87 | { | |
88 | if (val & PSW_ST_BIT && !(val & PSW_FX_BIT)) | |
89 | { | |
90 | (*d10v_callback->printf_filtered) | |
91 | (d10v_callback, | |
92 | "ERROR at PC 0x%x: ST can only be set when FX is set.\n", | |
93 | PC<<2); | |
94 | State.exception = SIGILL; | |
95 | } | |
96 | } | |
97 | /* keep an up-to-date psw around for tracing */ | |
98 | State.trace.psw = (State.trace.psw & mask) | val; | |
99 | break; | |
100 | case BPSW_CR: | |
101 | case DPSW_CR: | |
4ce44c66 JM |
102 | /* Just like PSW, mask things like DM out. */ |
103 | if (psw_hw_p) | |
104 | val &= PSW_HW_MASK; | |
105 | else | |
106 | val &= PSW_MASK; | |
c906108c SS |
107 | break; |
108 | case MOD_S_CR: | |
109 | case MOD_E_CR: | |
110 | val &= ~1; | |
111 | break; | |
112 | default: | |
113 | break; | |
114 | } | |
115 | /* only issue an update if the register is being changed */ | |
116 | if ((State.cregs[cr] & ~mask) != val) | |
117 | SLOT_PEND_MASK (State.cregs[cr], mask, val); | |
118 | return val; | |
119 | } | |
120 | ||
121 | #ifdef DEBUG | |
122 | static void trace_input_func PARAMS ((char *name, | |
123 | enum op_types in1, | |
124 | enum op_types in2, | |
125 | enum op_types in3)); | |
126 | ||
127 | #define trace_input(name, in1, in2, in3) do { if (d10v_debug) trace_input_func (name, in1, in2, in3); } while (0) | |
128 | ||
129 | #ifndef SIZE_INSTRUCTION | |
130 | #define SIZE_INSTRUCTION 8 | |
131 | #endif | |
132 | ||
133 | #ifndef SIZE_OPERANDS | |
134 | #define SIZE_OPERANDS 18 | |
135 | #endif | |
136 | ||
137 | #ifndef SIZE_VALUES | |
138 | #define SIZE_VALUES 13 | |
139 | #endif | |
140 | ||
141 | #ifndef SIZE_LOCATION | |
142 | #define SIZE_LOCATION 20 | |
143 | #endif | |
144 | ||
145 | #ifndef SIZE_PC | |
146 | #define SIZE_PC 6 | |
147 | #endif | |
148 | ||
149 | #ifndef SIZE_LINE_NUMBER | |
150 | #define SIZE_LINE_NUMBER 4 | |
151 | #endif | |
152 | ||
153 | static void | |
154 | trace_input_func (name, in1, in2, in3) | |
155 | char *name; | |
156 | enum op_types in1; | |
157 | enum op_types in2; | |
158 | enum op_types in3; | |
159 | { | |
160 | char *comma; | |
161 | enum op_types in[3]; | |
162 | int i; | |
163 | char buf[1024]; | |
164 | char *p; | |
165 | long tmp; | |
166 | char *type; | |
167 | const char *filename; | |
168 | const char *functionname; | |
169 | unsigned int linenumber; | |
170 | bfd_vma byte_pc; | |
171 | ||
172 | if ((d10v_debug & DEBUG_TRACE) == 0) | |
173 | return; | |
174 | ||
175 | switch (State.ins_type) | |
176 | { | |
177 | default: | |
178 | case INS_UNKNOWN: type = " ?"; break; | |
179 | case INS_LEFT: type = " L"; break; | |
180 | case INS_RIGHT: type = " R"; break; | |
181 | case INS_LEFT_PARALLEL: type = "*L"; break; | |
182 | case INS_RIGHT_PARALLEL: type = "*R"; break; | |
183 | case INS_LEFT_COND_TEST: type = "?L"; break; | |
184 | case INS_RIGHT_COND_TEST: type = "?R"; break; | |
185 | case INS_LEFT_COND_EXE: type = "&L"; break; | |
186 | case INS_RIGHT_COND_EXE: type = "&R"; break; | |
187 | case INS_LONG: type = " B"; break; | |
188 | } | |
189 | ||
190 | if ((d10v_debug & DEBUG_LINE_NUMBER) == 0) | |
191 | (*d10v_callback->printf_filtered) (d10v_callback, | |
192 | "0x%.*x %s: %-*s ", | |
193 | SIZE_PC, (unsigned)PC, | |
194 | type, | |
195 | SIZE_INSTRUCTION, name); | |
196 | ||
197 | else | |
198 | { | |
199 | buf[0] = '\0'; | |
200 | byte_pc = decode_pc (); | |
201 | if (text && byte_pc >= text_start && byte_pc < text_end) | |
202 | { | |
203 | filename = (const char *)0; | |
204 | functionname = (const char *)0; | |
205 | linenumber = 0; | |
206 | if (bfd_find_nearest_line (prog_bfd, text, (struct symbol_cache_entry **)0, byte_pc - text_start, | |
207 | &filename, &functionname, &linenumber)) | |
208 | { | |
209 | p = buf; | |
210 | if (linenumber) | |
211 | { | |
212 | sprintf (p, "#%-*d ", SIZE_LINE_NUMBER, linenumber); | |
213 | p += strlen (p); | |
214 | } | |
215 | else | |
216 | { | |
217 | sprintf (p, "%-*s ", SIZE_LINE_NUMBER+1, "---"); | |
218 | p += SIZE_LINE_NUMBER+2; | |
219 | } | |
220 | ||
221 | if (functionname) | |
222 | { | |
223 | sprintf (p, "%s ", functionname); | |
224 | p += strlen (p); | |
225 | } | |
226 | else if (filename) | |
227 | { | |
228 | char *q = strrchr (filename, '/'); | |
229 | sprintf (p, "%s ", (q) ? q+1 : filename); | |
230 | p += strlen (p); | |
231 | } | |
232 | ||
233 | if (*p == ' ') | |
234 | *p = '\0'; | |
235 | } | |
236 | } | |
237 | ||
238 | (*d10v_callback->printf_filtered) (d10v_callback, | |
239 | "0x%.*x %s: %-*.*s %-*s ", | |
240 | SIZE_PC, (unsigned)PC, | |
241 | type, | |
242 | SIZE_LOCATION, SIZE_LOCATION, buf, | |
243 | SIZE_INSTRUCTION, name); | |
244 | } | |
245 | ||
246 | in[0] = in1; | |
247 | in[1] = in2; | |
248 | in[2] = in3; | |
249 | comma = ""; | |
250 | p = buf; | |
251 | for (i = 0; i < 3; i++) | |
252 | { | |
253 | switch (in[i]) | |
254 | { | |
255 | case OP_VOID: | |
256 | case OP_R0: | |
257 | case OP_R1: | |
258 | case OP_R2: | |
259 | break; | |
260 | ||
261 | case OP_REG: | |
262 | case OP_REG_OUTPUT: | |
263 | case OP_DREG: | |
264 | case OP_DREG_OUTPUT: | |
265 | sprintf (p, "%sr%d", comma, OP[i]); | |
266 | p += strlen (p); | |
267 | comma = ","; | |
268 | break; | |
269 | ||
270 | case OP_CR: | |
271 | case OP_CR_OUTPUT: | |
272 | case OP_CR_REVERSE: | |
273 | sprintf (p, "%scr%d", comma, OP[i]); | |
274 | p += strlen (p); | |
275 | comma = ","; | |
276 | break; | |
277 | ||
278 | case OP_ACCUM: | |
279 | case OP_ACCUM_OUTPUT: | |
280 | case OP_ACCUM_REVERSE: | |
281 | sprintf (p, "%sa%d", comma, OP[i]); | |
282 | p += strlen (p); | |
283 | comma = ","; | |
284 | break; | |
285 | ||
286 | case OP_CONSTANT16: | |
287 | sprintf (p, "%s%d", comma, OP[i]); | |
288 | p += strlen (p); | |
289 | comma = ","; | |
290 | break; | |
291 | ||
292 | case OP_CONSTANT8: | |
293 | sprintf (p, "%s%d", comma, SEXT8(OP[i])); | |
294 | p += strlen (p); | |
295 | comma = ","; | |
296 | break; | |
297 | ||
298 | case OP_CONSTANT4: | |
299 | sprintf (p, "%s%d", comma, SEXT4(OP[i])); | |
300 | p += strlen (p); | |
301 | comma = ","; | |
302 | break; | |
303 | ||
304 | case OP_CONSTANT3: | |
305 | sprintf (p, "%s%d", comma, SEXT3(OP[i])); | |
306 | p += strlen (p); | |
307 | comma = ","; | |
308 | break; | |
309 | ||
310 | case OP_MEMREF: | |
311 | sprintf (p, "%s@r%d", comma, OP[i]); | |
312 | p += strlen (p); | |
313 | comma = ","; | |
314 | break; | |
315 | ||
316 | case OP_MEMREF2: | |
317 | sprintf (p, "%s@(%d,r%d)", comma, (int16)OP[i], OP[i+1]); | |
318 | p += strlen (p); | |
319 | comma = ","; | |
320 | break; | |
321 | ||
cff3e48b JM |
322 | case OP_MEMREF3: |
323 | sprintf (p, "%s@%d", comma, OP[i]); | |
324 | p += strlen (p); | |
325 | comma = ","; | |
326 | break; | |
327 | ||
c906108c SS |
328 | case OP_POSTINC: |
329 | sprintf (p, "%s@r%d+", comma, OP[i]); | |
330 | p += strlen (p); | |
331 | comma = ","; | |
332 | break; | |
333 | ||
334 | case OP_POSTDEC: | |
335 | sprintf (p, "%s@r%d-", comma, OP[i]); | |
336 | p += strlen (p); | |
337 | comma = ","; | |
338 | break; | |
339 | ||
340 | case OP_PREDEC: | |
341 | sprintf (p, "%s@-r%d", comma, OP[i]); | |
342 | p += strlen (p); | |
343 | comma = ","; | |
344 | break; | |
345 | ||
346 | case OP_FLAG: | |
347 | case OP_FLAG_OUTPUT: | |
348 | if (OP[i] == 0) | |
349 | sprintf (p, "%sf0", comma); | |
350 | ||
351 | else if (OP[i] == 1) | |
352 | sprintf (p, "%sf1", comma); | |
353 | ||
354 | else | |
355 | sprintf (p, "%sc", comma); | |
356 | ||
357 | p += strlen (p); | |
358 | comma = ","; | |
359 | break; | |
360 | } | |
361 | } | |
362 | ||
363 | if ((d10v_debug & DEBUG_VALUES) == 0) | |
364 | { | |
365 | *p++ = '\n'; | |
366 | *p = '\0'; | |
367 | (*d10v_callback->printf_filtered) (d10v_callback, "%s", buf); | |
368 | } | |
369 | else | |
370 | { | |
371 | *p = '\0'; | |
372 | (*d10v_callback->printf_filtered) (d10v_callback, "%-*s", SIZE_OPERANDS, buf); | |
373 | ||
374 | p = buf; | |
375 | for (i = 0; i < 3; i++) | |
376 | { | |
377 | buf[0] = '\0'; | |
378 | switch (in[i]) | |
379 | { | |
380 | case OP_VOID: | |
381 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, ""); | |
382 | break; | |
383 | ||
384 | case OP_REG_OUTPUT: | |
385 | case OP_DREG_OUTPUT: | |
386 | case OP_CR_OUTPUT: | |
387 | case OP_ACCUM_OUTPUT: | |
388 | case OP_FLAG_OUTPUT: | |
389 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "---"); | |
390 | break; | |
391 | ||
392 | case OP_REG: | |
393 | case OP_MEMREF: | |
394 | case OP_POSTDEC: | |
395 | case OP_POSTINC: | |
396 | case OP_PREDEC: | |
397 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", | |
398 | (uint16) GPR (OP[i])); | |
399 | break; | |
400 | ||
cff3e48b JM |
401 | case OP_MEMREF3: |
402 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", (uint16) OP[i]); | |
403 | break; | |
404 | ||
c906108c SS |
405 | case OP_DREG: |
406 | tmp = (long)((((uint32) GPR (OP[i])) << 16) | ((uint32) GPR (OP[i] + 1))); | |
407 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.8lx", SIZE_VALUES-10, "", tmp); | |
408 | break; | |
409 | ||
410 | case OP_CR: | |
411 | case OP_CR_REVERSE: | |
412 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", | |
413 | (uint16) CREG (OP[i])); | |
414 | break; | |
415 | ||
416 | case OP_ACCUM: | |
417 | case OP_ACCUM_REVERSE: | |
418 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.2x%.8lx", SIZE_VALUES-12, "", | |
419 | ((int)(ACC (OP[i]) >> 32) & 0xff), | |
420 | ((unsigned long) ACC (OP[i])) & 0xffffffff); | |
421 | break; | |
422 | ||
423 | case OP_CONSTANT16: | |
424 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", | |
425 | (uint16)OP[i]); | |
426 | break; | |
427 | ||
428 | case OP_CONSTANT4: | |
429 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", | |
430 | (uint16)SEXT4(OP[i])); | |
431 | break; | |
432 | ||
433 | case OP_CONSTANT8: | |
434 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", | |
435 | (uint16)SEXT8(OP[i])); | |
436 | break; | |
437 | ||
438 | case OP_CONSTANT3: | |
439 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", | |
440 | (uint16)SEXT3(OP[i])); | |
441 | break; | |
442 | ||
443 | case OP_FLAG: | |
444 | if (OP[i] == 0) | |
445 | (*d10v_callback->printf_filtered) (d10v_callback, "%*sF0 = %d", SIZE_VALUES-6, "", | |
446 | PSW_F0 != 0); | |
447 | ||
448 | else if (OP[i] == 1) | |
449 | (*d10v_callback->printf_filtered) (d10v_callback, "%*sF1 = %d", SIZE_VALUES-6, "", | |
450 | PSW_F1 != 0); | |
451 | ||
452 | else | |
453 | (*d10v_callback->printf_filtered) (d10v_callback, "%*sC = %d", SIZE_VALUES-5, "", | |
454 | PSW_C != 0); | |
455 | ||
456 | break; | |
457 | ||
458 | case OP_MEMREF2: | |
459 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", | |
460 | (uint16)OP[i]); | |
461 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", | |
462 | (uint16)GPR (OP[i + 1])); | |
463 | i++; | |
464 | break; | |
465 | ||
466 | case OP_R0: | |
467 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", | |
468 | (uint16) GPR (0)); | |
469 | break; | |
470 | ||
471 | case OP_R1: | |
472 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", | |
473 | (uint16) GPR (1)); | |
474 | break; | |
475 | ||
476 | case OP_R2: | |
477 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", | |
478 | (uint16) GPR (2)); | |
479 | break; | |
480 | ||
481 | } | |
482 | } | |
483 | } | |
484 | ||
485 | (*d10v_callback->flush_stdout) (d10v_callback); | |
486 | } | |
487 | ||
488 | static void | |
489 | do_trace_output_flush (void) | |
490 | { | |
491 | (*d10v_callback->flush_stdout) (d10v_callback); | |
492 | } | |
493 | ||
494 | static void | |
495 | do_trace_output_finish (void) | |
496 | { | |
497 | (*d10v_callback->printf_filtered) (d10v_callback, | |
498 | " F0=%d F1=%d C=%d\n", | |
499 | (State.trace.psw & PSW_F0_BIT) != 0, | |
500 | (State.trace.psw & PSW_F1_BIT) != 0, | |
501 | (State.trace.psw & PSW_C_BIT) != 0); | |
502 | (*d10v_callback->flush_stdout) (d10v_callback); | |
503 | } | |
504 | ||
505 | static void | |
506 | trace_output_40 (uint64 val) | |
507 | { | |
508 | if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES)) | |
509 | { | |
510 | (*d10v_callback->printf_filtered) (d10v_callback, | |
511 | " :: %*s0x%.2x%.8lx", | |
512 | SIZE_VALUES - 12, | |
513 | "", | |
514 | ((int)(val >> 32) & 0xff), | |
515 | ((unsigned long) val) & 0xffffffff); | |
516 | do_trace_output_finish (); | |
517 | } | |
518 | } | |
519 | ||
520 | static void | |
521 | trace_output_32 (uint32 val) | |
522 | { | |
523 | if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES)) | |
524 | { | |
525 | (*d10v_callback->printf_filtered) (d10v_callback, | |
526 | " :: %*s0x%.8x", | |
527 | SIZE_VALUES - 10, | |
528 | "", | |
529 | (int) val); | |
530 | do_trace_output_finish (); | |
531 | } | |
532 | } | |
533 | ||
534 | static void | |
535 | trace_output_16 (uint16 val) | |
536 | { | |
537 | if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES)) | |
538 | { | |
539 | (*d10v_callback->printf_filtered) (d10v_callback, | |
540 | " :: %*s0x%.4x", | |
541 | SIZE_VALUES - 6, | |
542 | "", | |
543 | (int) val); | |
544 | do_trace_output_finish (); | |
545 | } | |
546 | } | |
547 | ||
548 | static void | |
549 | trace_output_void () | |
550 | { | |
551 | if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES)) | |
552 | { | |
553 | (*d10v_callback->printf_filtered) (d10v_callback, "\n"); | |
554 | do_trace_output_flush (); | |
555 | } | |
556 | } | |
557 | ||
558 | static void | |
559 | trace_output_flag () | |
560 | { | |
561 | if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES)) | |
562 | { | |
563 | (*d10v_callback->printf_filtered) (d10v_callback, | |
564 | " :: %*s", | |
565 | SIZE_VALUES, | |
566 | ""); | |
567 | do_trace_output_finish (); | |
568 | } | |
569 | } | |
570 | ||
571 | ||
572 | ||
573 | ||
574 | #else | |
575 | #define trace_input(NAME, IN1, IN2, IN3) | |
576 | #define trace_output(RESULT) | |
577 | #endif | |
578 | ||
579 | /* abs */ | |
580 | void | |
581 | OP_4607 () | |
582 | { | |
583 | int16 tmp; | |
584 | trace_input ("abs", OP_REG, OP_VOID, OP_VOID); | |
585 | SET_PSW_F1 (PSW_F0); | |
586 | tmp = GPR(OP[0]); | |
587 | if (tmp < 0) | |
588 | { | |
589 | tmp = - tmp; | |
590 | SET_PSW_F0 (1); | |
591 | } | |
592 | else | |
593 | SET_PSW_F0 (0); | |
594 | SET_GPR (OP[0], tmp); | |
595 | trace_output_16 (tmp); | |
596 | } | |
597 | ||
598 | /* abs */ | |
599 | void | |
600 | OP_5607 () | |
601 | { | |
602 | int64 tmp; | |
603 | trace_input ("abs", OP_ACCUM, OP_VOID, OP_VOID); | |
604 | SET_PSW_F1 (PSW_F0); | |
605 | ||
606 | tmp = SEXT40 (ACC (OP[0])); | |
607 | if (tmp < 0 ) | |
608 | { | |
609 | tmp = - tmp; | |
610 | if (PSW_ST) | |
611 | { | |
612 | if (tmp > SEXT40(MAX32)) | |
613 | tmp = (MAX32); | |
614 | else if (tmp < SEXT40(MIN32)) | |
615 | tmp = (MIN32); | |
616 | else | |
617 | tmp = (tmp & MASK40); | |
618 | } | |
619 | else | |
620 | tmp = (tmp & MASK40); | |
621 | SET_PSW_F0 (1); | |
622 | } | |
623 | else | |
624 | { | |
625 | tmp = (tmp & MASK40); | |
626 | SET_PSW_F0 (0); | |
627 | } | |
628 | SET_ACC (OP[0], tmp); | |
629 | trace_output_40 (tmp); | |
630 | } | |
631 | ||
632 | /* add */ | |
633 | void | |
634 | OP_200 () | |
635 | { | |
636 | uint16 a = GPR (OP[0]); | |
637 | uint16 b = GPR (OP[1]); | |
638 | uint16 tmp = (a + b); | |
639 | trace_input ("add", OP_REG, OP_REG, OP_VOID); | |
640 | SET_PSW_C (a > tmp); | |
641 | SET_GPR (OP[0], tmp); | |
642 | trace_output_16 (tmp); | |
643 | } | |
644 | ||
645 | /* add */ | |
646 | void | |
647 | OP_1201 () | |
648 | { | |
649 | int64 tmp; | |
650 | tmp = SEXT40(ACC (OP[0])) + (SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1)); | |
651 | ||
652 | trace_input ("add", OP_ACCUM, OP_REG, OP_VOID); | |
653 | if (PSW_ST) | |
654 | { | |
655 | if (tmp > SEXT40(MAX32)) | |
656 | tmp = (MAX32); | |
657 | else if (tmp < SEXT40(MIN32)) | |
658 | tmp = (MIN32); | |
659 | else | |
660 | tmp = (tmp & MASK40); | |
661 | } | |
662 | else | |
663 | tmp = (tmp & MASK40); | |
664 | SET_ACC (OP[0], tmp); | |
665 | trace_output_40 (tmp); | |
666 | } | |
667 | ||
668 | /* add */ | |
669 | void | |
670 | OP_1203 () | |
671 | { | |
672 | int64 tmp; | |
673 | tmp = SEXT40(ACC (OP[0])) + SEXT40(ACC (OP[1])); | |
674 | ||
675 | trace_input ("add", OP_ACCUM, OP_ACCUM, OP_VOID); | |
676 | if (PSW_ST) | |
677 | { | |
678 | if (tmp > SEXT40(MAX32)) | |
679 | tmp = (MAX32); | |
680 | else if (tmp < SEXT40(MIN32)) | |
681 | tmp = (MIN32); | |
682 | else | |
683 | tmp = (tmp & MASK40); | |
684 | } | |
685 | else | |
686 | tmp = (tmp & MASK40); | |
687 | SET_ACC (OP[0], tmp); | |
688 | trace_output_40 (tmp); | |
689 | } | |
690 | ||
691 | /* add2w */ | |
692 | void | |
693 | OP_1200 () | |
694 | { | |
695 | uint32 tmp; | |
696 | uint32 a = (GPR (OP[0])) << 16 | GPR (OP[0] + 1); | |
697 | uint32 b = (GPR (OP[1])) << 16 | GPR (OP[1] + 1); | |
698 | trace_input ("add2w", OP_DREG, OP_DREG, OP_VOID); | |
699 | tmp = a + b; | |
700 | SET_PSW_C (tmp < a); | |
701 | SET_GPR (OP[0] + 0, (tmp >> 16)); | |
702 | SET_GPR (OP[0] + 1, (tmp & 0xFFFF)); | |
703 | trace_output_32 (tmp); | |
704 | } | |
705 | ||
706 | /* add3 */ | |
707 | void | |
708 | OP_1000000 () | |
709 | { | |
710 | uint16 a = GPR (OP[1]); | |
711 | uint16 b = OP[2]; | |
712 | uint16 tmp = (a + b); | |
713 | trace_input ("add3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16); | |
714 | SET_PSW_C (tmp < a); | |
715 | SET_GPR (OP[0], tmp); | |
716 | trace_output_16 (tmp); | |
717 | } | |
718 | ||
719 | /* addac3 */ | |
720 | void | |
721 | OP_17000200 () | |
722 | { | |
723 | int64 tmp; | |
724 | tmp = SEXT40(ACC (OP[2])) + SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1)); | |
725 | ||
726 | trace_input ("addac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM); | |
727 | SET_GPR (OP[0] + 0, ((tmp >> 16) & 0xffff)); | |
728 | SET_GPR (OP[0] + 1, (tmp & 0xffff)); | |
729 | trace_output_32 (tmp); | |
730 | } | |
731 | ||
732 | /* addac3 */ | |
733 | void | |
734 | OP_17000202 () | |
735 | { | |
736 | int64 tmp; | |
737 | tmp = SEXT40(ACC (OP[1])) + SEXT40(ACC (OP[2])); | |
738 | ||
739 | trace_input ("addac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM); | |
740 | SET_GPR (OP[0] + 0, (tmp >> 16) & 0xffff); | |
741 | SET_GPR (OP[0] + 1, tmp & 0xffff); | |
742 | trace_output_32 (tmp); | |
743 | } | |
744 | ||
745 | /* addac3s */ | |
746 | void | |
747 | OP_17001200 () | |
748 | { | |
749 | int64 tmp; | |
750 | SET_PSW_F1 (PSW_F0); | |
751 | ||
752 | trace_input ("addac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM); | |
753 | tmp = SEXT40 (ACC (OP[2])) + SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1)); | |
754 | if (tmp > SEXT40(MAX32)) | |
755 | { | |
756 | tmp = (MAX32); | |
757 | SET_PSW_F0 (1); | |
758 | } | |
759 | else if (tmp < SEXT40(MIN32)) | |
760 | { | |
761 | tmp = (MIN32); | |
762 | SET_PSW_F0 (1); | |
763 | } | |
764 | else | |
765 | { | |
766 | SET_PSW_F0 (0); | |
767 | } | |
768 | SET_GPR (OP[0] + 0, (tmp >> 16) & 0xffff); | |
769 | SET_GPR (OP[0] + 1, (tmp & 0xffff)); | |
770 | trace_output_32 (tmp); | |
771 | } | |
772 | ||
773 | /* addac3s */ | |
774 | void | |
775 | OP_17001202 () | |
776 | { | |
777 | int64 tmp; | |
778 | SET_PSW_F1 (PSW_F0); | |
779 | ||
780 | trace_input ("addac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM); | |
781 | tmp = SEXT40(ACC (OP[1])) + SEXT40(ACC (OP[2])); | |
782 | if (tmp > SEXT40(MAX32)) | |
783 | { | |
784 | tmp = (MAX32); | |
785 | SET_PSW_F0 (1); | |
786 | } | |
787 | else if (tmp < SEXT40(MIN32)) | |
788 | { | |
789 | tmp = (MIN32); | |
790 | SET_PSW_F0 (1); | |
791 | } | |
792 | else | |
793 | { | |
794 | SET_PSW_F0 (0); | |
795 | } | |
796 | SET_GPR (OP[0] + 0, (tmp >> 16) & 0xffff); | |
797 | SET_GPR (OP[0] + 1, (tmp & 0xffff)); | |
798 | trace_output_32 (tmp); | |
799 | } | |
800 | ||
801 | /* addi */ | |
802 | void | |
803 | OP_201 () | |
804 | { | |
805 | uint16 a = GPR (OP[0]); | |
806 | uint16 b; | |
807 | uint16 tmp; | |
808 | if (OP[1] == 0) | |
809 | OP[1] = 16; | |
810 | b = OP[1]; | |
811 | tmp = (a + b); | |
812 | trace_input ("addi", OP_REG, OP_CONSTANT16, OP_VOID); | |
813 | SET_PSW_C (tmp < a); | |
814 | SET_GPR (OP[0], tmp); | |
815 | trace_output_16 (tmp); | |
816 | } | |
817 | ||
818 | /* and */ | |
819 | void | |
820 | OP_C00 () | |
821 | { | |
822 | uint16 tmp = GPR (OP[0]) & GPR (OP[1]); | |
823 | trace_input ("and", OP_REG, OP_REG, OP_VOID); | |
824 | SET_GPR (OP[0], tmp); | |
825 | trace_output_16 (tmp); | |
826 | } | |
827 | ||
828 | /* and3 */ | |
829 | void | |
830 | OP_6000000 () | |
831 | { | |
832 | uint16 tmp = GPR (OP[1]) & OP[2]; | |
833 | trace_input ("and3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16); | |
834 | SET_GPR (OP[0], tmp); | |
835 | trace_output_16 (tmp); | |
836 | } | |
837 | ||
838 | /* bclri */ | |
839 | void | |
840 | OP_C01 () | |
841 | { | |
842 | int16 tmp; | |
843 | trace_input ("bclri", OP_REG, OP_CONSTANT16, OP_VOID); | |
844 | tmp = (GPR (OP[0]) &~(0x8000 >> OP[1])); | |
845 | SET_GPR (OP[0], tmp); | |
846 | trace_output_16 (tmp); | |
847 | } | |
848 | ||
849 | /* bl.s */ | |
850 | void | |
851 | OP_4900 () | |
852 | { | |
853 | trace_input ("bl.s", OP_CONSTANT8, OP_R0, OP_R1); | |
854 | SET_GPR (13, PC + 1); | |
855 | JMP( PC + SEXT8 (OP[0])); | |
856 | trace_output_void (); | |
857 | } | |
858 | ||
859 | /* bl.l */ | |
860 | void | |
861 | OP_24800000 () | |
862 | { | |
863 | trace_input ("bl.l", OP_CONSTANT16, OP_R0, OP_R1); | |
864 | SET_GPR (13, (PC + 1)); | |
865 | JMP (PC + OP[0]); | |
866 | trace_output_void (); | |
867 | } | |
868 | ||
869 | /* bnoti */ | |
870 | void | |
871 | OP_A01 () | |
872 | { | |
873 | int16 tmp; | |
874 | trace_input ("bnoti", OP_REG, OP_CONSTANT16, OP_VOID); | |
875 | tmp = (GPR (OP[0]) ^ (0x8000 >> OP[1])); | |
876 | SET_GPR (OP[0], tmp); | |
877 | trace_output_16 (tmp); | |
878 | } | |
879 | ||
880 | /* bra.s */ | |
881 | void | |
882 | OP_4800 () | |
883 | { | |
884 | trace_input ("bra.s", OP_CONSTANT8, OP_VOID, OP_VOID); | |
885 | JMP (PC + SEXT8 (OP[0])); | |
886 | trace_output_void (); | |
887 | } | |
888 | ||
889 | /* bra.l */ | |
890 | void | |
891 | OP_24000000 () | |
892 | { | |
893 | trace_input ("bra.l", OP_CONSTANT16, OP_VOID, OP_VOID); | |
894 | JMP (PC + OP[0]); | |
895 | trace_output_void (); | |
896 | } | |
897 | ||
898 | /* brf0f.s */ | |
899 | void | |
900 | OP_4A00 () | |
901 | { | |
902 | trace_input ("brf0f.s", OP_CONSTANT8, OP_VOID, OP_VOID); | |
903 | if (!PSW_F0) | |
904 | JMP (PC + SEXT8 (OP[0])); | |
905 | trace_output_flag (); | |
906 | } | |
907 | ||
908 | /* brf0f.l */ | |
909 | void | |
910 | OP_25000000 () | |
911 | { | |
912 | trace_input ("brf0f.l", OP_CONSTANT16, OP_VOID, OP_VOID); | |
913 | if (!PSW_F0) | |
914 | JMP (PC + OP[0]); | |
915 | trace_output_flag (); | |
916 | } | |
917 | ||
918 | /* brf0t.s */ | |
919 | void | |
920 | OP_4B00 () | |
921 | { | |
922 | trace_input ("brf0t.s", OP_CONSTANT8, OP_VOID, OP_VOID); | |
923 | if (PSW_F0) | |
924 | JMP (PC + SEXT8 (OP[0])); | |
925 | trace_output_flag (); | |
926 | } | |
927 | ||
928 | /* brf0t.l */ | |
929 | void | |
930 | OP_25800000 () | |
931 | { | |
932 | trace_input ("brf0t.l", OP_CONSTANT16, OP_VOID, OP_VOID); | |
933 | if (PSW_F0) | |
934 | JMP (PC + OP[0]); | |
935 | trace_output_flag (); | |
936 | } | |
937 | ||
938 | /* bseti */ | |
939 | void | |
940 | OP_801 () | |
941 | { | |
942 | int16 tmp; | |
943 | trace_input ("bseti", OP_REG, OP_CONSTANT16, OP_VOID); | |
944 | tmp = (GPR (OP[0]) | (0x8000 >> OP[1])); | |
945 | SET_GPR (OP[0], tmp); | |
946 | trace_output_16 (tmp); | |
947 | } | |
948 | ||
949 | /* btsti */ | |
950 | void | |
951 | OP_E01 () | |
952 | { | |
953 | trace_input ("btsti", OP_REG, OP_CONSTANT16, OP_VOID); | |
954 | SET_PSW_F1 (PSW_F0); | |
955 | SET_PSW_F0 ((GPR (OP[0]) & (0x8000 >> OP[1])) ? 1 : 0); | |
956 | trace_output_flag (); | |
957 | } | |
958 | ||
959 | /* clrac */ | |
960 | void | |
961 | OP_5601 () | |
962 | { | |
963 | trace_input ("clrac", OP_ACCUM_OUTPUT, OP_VOID, OP_VOID); | |
964 | SET_ACC (OP[0], 0); | |
965 | trace_output_40 (0); | |
966 | } | |
967 | ||
968 | /* cmp */ | |
969 | void | |
970 | OP_600 () | |
971 | { | |
972 | trace_input ("cmp", OP_REG, OP_REG, OP_VOID); | |
973 | SET_PSW_F1 (PSW_F0); | |
974 | SET_PSW_F0 (((int16)(GPR (OP[0])) < (int16)(GPR (OP[1]))) ? 1 : 0); | |
975 | trace_output_flag (); | |
976 | } | |
977 | ||
978 | /* cmp */ | |
979 | void | |
980 | OP_1603 () | |
981 | { | |
982 | trace_input ("cmp", OP_ACCUM, OP_ACCUM, OP_VOID); | |
983 | SET_PSW_F1 (PSW_F0); | |
984 | SET_PSW_F0 ((SEXT40(ACC (OP[0])) < SEXT40(ACC (OP[1]))) ? 1 : 0); | |
985 | trace_output_flag (); | |
986 | } | |
987 | ||
988 | /* cmpeq */ | |
989 | void | |
990 | OP_400 () | |
991 | { | |
992 | trace_input ("cmpeq", OP_REG, OP_REG, OP_VOID); | |
993 | SET_PSW_F1 (PSW_F0); | |
994 | SET_PSW_F0 ((GPR (OP[0]) == GPR (OP[1])) ? 1 : 0); | |
995 | trace_output_flag (); | |
996 | } | |
997 | ||
998 | /* cmpeq */ | |
999 | void | |
1000 | OP_1403 () | |
1001 | { | |
1002 | trace_input ("cmpeq", OP_ACCUM, OP_ACCUM, OP_VOID); | |
1003 | SET_PSW_F1 (PSW_F0); | |
1004 | SET_PSW_F0 (((ACC (OP[0]) & MASK40) == (ACC (OP[1]) & MASK40)) ? 1 : 0); | |
1005 | trace_output_flag (); | |
1006 | } | |
1007 | ||
1008 | /* cmpeqi.s */ | |
1009 | void | |
1010 | OP_401 () | |
1011 | { | |
1012 | trace_input ("cmpeqi.s", OP_REG, OP_CONSTANT4, OP_VOID); | |
1013 | SET_PSW_F1 (PSW_F0); | |
1014 | SET_PSW_F0 ((GPR (OP[0]) == (reg_t) SEXT4 (OP[1])) ? 1 : 0); | |
1015 | trace_output_flag (); | |
1016 | } | |
1017 | ||
1018 | /* cmpeqi.l */ | |
1019 | void | |
1020 | OP_2000000 () | |
1021 | { | |
1022 | trace_input ("cmpeqi.l", OP_REG, OP_CONSTANT16, OP_VOID); | |
1023 | SET_PSW_F1 (PSW_F0); | |
1024 | SET_PSW_F0 ((GPR (OP[0]) == (reg_t)OP[1]) ? 1 : 0); | |
1025 | trace_output_flag (); | |
1026 | } | |
1027 | ||
1028 | /* cmpi.s */ | |
1029 | void | |
1030 | OP_601 () | |
1031 | { | |
1032 | trace_input ("cmpi.s", OP_REG, OP_CONSTANT4, OP_VOID); | |
1033 | SET_PSW_F1 (PSW_F0); | |
1034 | SET_PSW_F0 (((int16)(GPR (OP[0])) < (int16)SEXT4(OP[1])) ? 1 : 0); | |
1035 | trace_output_flag (); | |
1036 | } | |
1037 | ||
1038 | /* cmpi.l */ | |
1039 | void | |
1040 | OP_3000000 () | |
1041 | { | |
1042 | trace_input ("cmpi.l", OP_REG, OP_CONSTANT16, OP_VOID); | |
1043 | SET_PSW_F1 (PSW_F0); | |
1044 | SET_PSW_F0 (((int16)(GPR (OP[0])) < (int16)(OP[1])) ? 1 : 0); | |
1045 | trace_output_flag (); | |
1046 | } | |
1047 | ||
1048 | /* cmpu */ | |
1049 | void | |
1050 | OP_4600 () | |
1051 | { | |
1052 | trace_input ("cmpu", OP_REG, OP_REG, OP_VOID); | |
1053 | SET_PSW_F1 (PSW_F0); | |
1054 | SET_PSW_F0 ((GPR (OP[0]) < GPR (OP[1])) ? 1 : 0); | |
1055 | trace_output_flag (); | |
1056 | } | |
1057 | ||
1058 | /* cmpui */ | |
1059 | void | |
1060 | OP_23000000 () | |
1061 | { | |
1062 | trace_input ("cmpui", OP_REG, OP_CONSTANT16, OP_VOID); | |
1063 | SET_PSW_F1 (PSW_F0); | |
1064 | SET_PSW_F0 ((GPR (OP[0]) < (reg_t)OP[1]) ? 1 : 0); | |
1065 | trace_output_flag (); | |
1066 | } | |
1067 | ||
1068 | /* cpfg */ | |
1069 | void | |
1070 | OP_4E09 () | |
1071 | { | |
1072 | uint8 val; | |
1073 | ||
1074 | trace_input ("cpfg", OP_FLAG_OUTPUT, OP_FLAG, OP_VOID); | |
1075 | ||
1076 | if (OP[1] == 0) | |
1077 | val = PSW_F0; | |
1078 | else if (OP[1] == 1) | |
1079 | val = PSW_F1; | |
1080 | else | |
1081 | val = PSW_C; | |
1082 | if (OP[0] == 0) | |
1083 | SET_PSW_F0 (val); | |
1084 | else | |
1085 | SET_PSW_F1 (val); | |
1086 | ||
1087 | trace_output_flag (); | |
1088 | } | |
1089 | ||
c2d11a7d JM |
1090 | /* cpfg */ |
1091 | void | |
1092 | OP_4E0F () | |
1093 | { | |
1094 | uint8 val; | |
1095 | ||
1096 | trace_input ("cpfg", OP_FLAG_OUTPUT, OP_FLAG, OP_VOID); | |
1097 | ||
1098 | if (OP[1] == 0) | |
1099 | val = PSW_F0; | |
1100 | else if (OP[1] == 1) | |
1101 | val = PSW_F1; | |
1102 | else | |
1103 | val = PSW_C; | |
1104 | if (OP[0] == 0) | |
1105 | SET_PSW_F0 (val); | |
1106 | else | |
1107 | SET_PSW_F1 (val); | |
1108 | ||
1109 | trace_output_flag (); | |
1110 | } | |
1111 | ||
c906108c SS |
1112 | /* dbt */ |
1113 | void | |
1114 | OP_5F20 () | |
1115 | { | |
1116 | /* d10v_callback->printf_filtered(d10v_callback, "***** DBT ***** PC=%x\n",PC); */ | |
1117 | ||
1118 | /* GDB uses the instruction pair ``dbt || nop'' as a break-point. | |
1119 | The conditional below is for either of the instruction pairs | |
1120 | ``dbt -> XXX'' or ``dbt <- XXX'' and treats them as as cases | |
1121 | where the dbt instruction should be interpreted. | |
1122 | ||
1123 | The module `sim-break' provides a more effective mechanism for | |
1124 | detecting GDB planted breakpoints. The code below may, | |
1125 | eventually, be changed to use that mechanism. */ | |
1126 | ||
1127 | if (State.ins_type == INS_LEFT | |
1128 | || State.ins_type == INS_RIGHT) | |
1129 | { | |
1130 | trace_input ("dbt", OP_VOID, OP_VOID, OP_VOID); | |
1131 | SET_DPC (PC + 1); | |
1132 | SET_DPSW (PSW); | |
4ce44c66 | 1133 | SET_HW_PSW (PSW_DM_BIT | (PSW & (PSW_F0_BIT | PSW_F1_BIT | PSW_C_BIT))); |
c906108c SS |
1134 | JMP (DBT_VECTOR_START); |
1135 | trace_output_void (); | |
1136 | } | |
1137 | else | |
1138 | { | |
1139 | State.exception = SIGTRAP; | |
1140 | } | |
1141 | } | |
1142 | ||
1143 | /* divs */ | |
1144 | void | |
1145 | OP_14002800 () | |
1146 | { | |
1147 | uint16 foo, tmp, tmpf; | |
1148 | uint16 hi; | |
1149 | uint16 lo; | |
1150 | ||
1151 | trace_input ("divs", OP_DREG, OP_REG, OP_VOID); | |
1152 | foo = (GPR (OP[0]) << 1) | (GPR (OP[0] + 1) >> 15); | |
1153 | tmp = (int16)foo - (int16)(GPR (OP[1])); | |
1154 | tmpf = (foo >= GPR (OP[1])) ? 1 : 0; | |
1155 | hi = ((tmpf == 1) ? tmp : foo); | |
1156 | lo = ((GPR (OP[0] + 1) << 1) | tmpf); | |
1157 | SET_GPR (OP[0] + 0, hi); | |
1158 | SET_GPR (OP[0] + 1, lo); | |
1159 | trace_output_32 (((uint32) hi << 16) | lo); | |
1160 | } | |
1161 | ||
1162 | /* exef0f */ | |
1163 | void | |
1164 | OP_4E04 () | |
1165 | { | |
1166 | trace_input ("exef0f", OP_VOID, OP_VOID, OP_VOID); | |
1167 | State.exe = (PSW_F0 == 0); | |
1168 | trace_output_flag (); | |
1169 | } | |
1170 | ||
1171 | /* exef0t */ | |
1172 | void | |
1173 | OP_4E24 () | |
1174 | { | |
1175 | trace_input ("exef0t", OP_VOID, OP_VOID, OP_VOID); | |
1176 | State.exe = (PSW_F0 != 0); | |
1177 | trace_output_flag (); | |
1178 | } | |
1179 | ||
1180 | /* exef1f */ | |
1181 | void | |
1182 | OP_4E40 () | |
1183 | { | |
1184 | trace_input ("exef1f", OP_VOID, OP_VOID, OP_VOID); | |
1185 | State.exe = (PSW_F1 == 0); | |
1186 | trace_output_flag (); | |
1187 | } | |
1188 | ||
1189 | /* exef1t */ | |
1190 | void | |
1191 | OP_4E42 () | |
1192 | { | |
1193 | trace_input ("exef1t", OP_VOID, OP_VOID, OP_VOID); | |
1194 | State.exe = (PSW_F1 != 0); | |
1195 | trace_output_flag (); | |
1196 | } | |
1197 | ||
1198 | /* exefaf */ | |
1199 | void | |
1200 | OP_4E00 () | |
1201 | { | |
1202 | trace_input ("exefaf", OP_VOID, OP_VOID, OP_VOID); | |
1203 | State.exe = (PSW_F0 == 0) & (PSW_F1 == 0); | |
1204 | trace_output_flag (); | |
1205 | } | |
1206 | ||
1207 | /* exefat */ | |
1208 | void | |
1209 | OP_4E02 () | |
1210 | { | |
1211 | trace_input ("exefat", OP_VOID, OP_VOID, OP_VOID); | |
1212 | State.exe = (PSW_F0 == 0) & (PSW_F1 != 0); | |
1213 | trace_output_flag (); | |
1214 | } | |
1215 | ||
1216 | /* exetaf */ | |
1217 | void | |
1218 | OP_4E20 () | |
1219 | { | |
1220 | trace_input ("exetaf", OP_VOID, OP_VOID, OP_VOID); | |
1221 | State.exe = (PSW_F0 != 0) & (PSW_F1 == 0); | |
1222 | trace_output_flag (); | |
1223 | } | |
1224 | ||
1225 | /* exetat */ | |
1226 | void | |
1227 | OP_4E22 () | |
1228 | { | |
1229 | trace_input ("exetat", OP_VOID, OP_VOID, OP_VOID); | |
1230 | State.exe = (PSW_F0 != 0) & (PSW_F1 != 0); | |
1231 | trace_output_flag (); | |
1232 | } | |
1233 | ||
1234 | /* exp */ | |
1235 | void | |
1236 | OP_15002A00 () | |
1237 | { | |
1238 | uint32 tmp, foo; | |
1239 | int i; | |
1240 | ||
1241 | trace_input ("exp", OP_REG_OUTPUT, OP_DREG, OP_VOID); | |
1242 | if (((int16)GPR (OP[1])) >= 0) | |
1243 | tmp = (GPR (OP[1]) << 16) | GPR (OP[1] + 1); | |
1244 | else | |
1245 | tmp = ~((GPR (OP[1]) << 16) | GPR (OP[1] + 1)); | |
1246 | ||
1247 | foo = 0x40000000; | |
1248 | for (i=1;i<17;i++) | |
1249 | { | |
1250 | if (tmp & foo) | |
1251 | { | |
1252 | SET_GPR (OP[0], (i - 1)); | |
1253 | trace_output_16 (i - 1); | |
1254 | return; | |
1255 | } | |
1256 | foo >>= 1; | |
1257 | } | |
1258 | SET_GPR (OP[0], 16); | |
1259 | trace_output_16 (16); | |
1260 | } | |
1261 | ||
1262 | /* exp */ | |
1263 | void | |
1264 | OP_15002A02 () | |
1265 | { | |
1266 | int64 tmp, foo; | |
1267 | int i; | |
1268 | ||
1269 | trace_input ("exp", OP_REG_OUTPUT, OP_ACCUM, OP_VOID); | |
1270 | tmp = SEXT40(ACC (OP[1])); | |
1271 | if (tmp < 0) | |
1272 | tmp = ~tmp & MASK40; | |
1273 | ||
1274 | foo = 0x4000000000LL; | |
1275 | for (i=1;i<25;i++) | |
1276 | { | |
1277 | if (tmp & foo) | |
1278 | { | |
1279 | SET_GPR (OP[0], i - 9); | |
1280 | trace_output_16 (i - 9); | |
1281 | return; | |
1282 | } | |
1283 | foo >>= 1; | |
1284 | } | |
1285 | SET_GPR (OP[0], 16); | |
1286 | trace_output_16 (16); | |
1287 | } | |
1288 | ||
1289 | /* jl */ | |
1290 | void | |
1291 | OP_4D00 () | |
1292 | { | |
1293 | trace_input ("jl", OP_REG, OP_R0, OP_R1); | |
1294 | SET_GPR (13, PC + 1); | |
1295 | JMP (GPR (OP[0])); | |
1296 | trace_output_void (); | |
1297 | } | |
1298 | ||
1299 | /* jmp */ | |
1300 | void | |
1301 | OP_4C00 () | |
1302 | { | |
1303 | trace_input ("jmp", OP_REG, | |
1304 | (OP[0] == 13) ? OP_R0 : OP_VOID, | |
1305 | (OP[0] == 13) ? OP_R1 : OP_VOID); | |
1306 | ||
1307 | JMP (GPR (OP[0])); | |
1308 | trace_output_void (); | |
1309 | } | |
1310 | ||
1311 | /* ld */ | |
1312 | void | |
1313 | OP_30000000 () | |
1314 | { | |
1315 | uint16 tmp; | |
c3f6f71d | 1316 | uint16 addr = OP[1] + GPR (OP[2]); |
c906108c | 1317 | trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID); |
c3f6f71d JM |
1318 | if ((addr & 1)) |
1319 | { | |
7fc5b5ad AC |
1320 | State.exception = SIG_D10V_BUS; |
1321 | State.pc_changed = 1; /* Don't increment the PC. */ | |
c3f6f71d JM |
1322 | trace_output_void (); |
1323 | return; | |
1324 | } | |
1325 | tmp = RW (addr); | |
c906108c SS |
1326 | SET_GPR (OP[0], tmp); |
1327 | trace_output_16 (tmp); | |
1328 | } | |
1329 | ||
1330 | /* ld */ | |
1331 | void | |
1332 | OP_6401 () | |
1333 | { | |
1334 | uint16 tmp; | |
c3f6f71d | 1335 | uint16 addr = GPR (OP[1]); |
c906108c | 1336 | trace_input ("ld", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID); |
c3f6f71d JM |
1337 | if ((addr & 1)) |
1338 | { | |
7fc5b5ad AC |
1339 | State.exception = SIG_D10V_BUS; |
1340 | State.pc_changed = 1; /* Don't increment the PC. */ | |
c3f6f71d JM |
1341 | trace_output_void (); |
1342 | return; | |
1343 | } | |
1344 | tmp = RW (addr); | |
c906108c SS |
1345 | SET_GPR (OP[0], tmp); |
1346 | if (OP[0] != OP[1]) | |
1347 | INC_ADDR (OP[1], -2); | |
1348 | trace_output_16 (tmp); | |
1349 | } | |
1350 | ||
1351 | /* ld */ | |
1352 | void | |
1353 | OP_6001 () | |
1354 | { | |
1355 | uint16 tmp; | |
c3f6f71d | 1356 | uint16 addr = GPR (OP[1]); |
c906108c | 1357 | trace_input ("ld", OP_REG_OUTPUT, OP_POSTINC, OP_VOID); |
c3f6f71d JM |
1358 | if ((addr & 1)) |
1359 | { | |
7fc5b5ad AC |
1360 | State.exception = SIG_D10V_BUS; |
1361 | State.pc_changed = 1; /* Don't increment the PC. */ | |
c3f6f71d JM |
1362 | trace_output_void (); |
1363 | return; | |
1364 | } | |
1365 | tmp = RW (addr); | |
c906108c SS |
1366 | SET_GPR (OP[0], tmp); |
1367 | if (OP[0] != OP[1]) | |
1368 | INC_ADDR (OP[1], 2); | |
1369 | trace_output_16 (tmp); | |
1370 | } | |
1371 | ||
1372 | /* ld */ | |
1373 | void | |
1374 | OP_6000 () | |
1375 | { | |
1376 | uint16 tmp; | |
c3f6f71d | 1377 | uint16 addr = GPR (OP[1]); |
c906108c | 1378 | trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF, OP_VOID); |
c3f6f71d JM |
1379 | if ((addr & 1)) |
1380 | { | |
7fc5b5ad AC |
1381 | State.exception = SIG_D10V_BUS; |
1382 | State.pc_changed = 1; /* Don't increment the PC. */ | |
c3f6f71d JM |
1383 | trace_output_void (); |
1384 | return; | |
1385 | } | |
1386 | tmp = RW (addr); | |
c906108c SS |
1387 | SET_GPR (OP[0], tmp); |
1388 | trace_output_16 (tmp); | |
1389 | } | |
1390 | ||
cff3e48b JM |
1391 | /* ld */ |
1392 | void | |
1393 | OP_32010000 () | |
1394 | { | |
1395 | uint16 tmp; | |
c3f6f71d | 1396 | uint16 addr = OP[1]; |
cff3e48b | 1397 | trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF3, OP_VOID); |
c3f6f71d JM |
1398 | if ((addr & 1)) |
1399 | { | |
7fc5b5ad AC |
1400 | State.exception = SIG_D10V_BUS; |
1401 | State.pc_changed = 1; /* Don't increment the PC. */ | |
c3f6f71d JM |
1402 | trace_output_void (); |
1403 | return; | |
1404 | } | |
1405 | tmp = RW (addr); | |
cff3e48b JM |
1406 | SET_GPR (OP[0], tmp); |
1407 | trace_output_16 (tmp); | |
1408 | } | |
1409 | ||
c906108c SS |
1410 | /* ld2w */ |
1411 | void | |
1412 | OP_31000000 () | |
1413 | { | |
1414 | int32 tmp; | |
c3f6f71d | 1415 | uint16 addr = OP[1] + GPR (OP[2]); |
c906108c | 1416 | trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID); |
c3f6f71d JM |
1417 | if ((addr & 1)) |
1418 | { | |
7fc5b5ad AC |
1419 | State.exception = SIG_D10V_BUS; |
1420 | State.pc_changed = 1; /* Don't increment the PC. */ | |
c3f6f71d JM |
1421 | trace_output_void (); |
1422 | return; | |
1423 | } | |
1424 | tmp = RLW (addr); | |
c906108c SS |
1425 | SET_GPR32 (OP[0], tmp); |
1426 | trace_output_32 (tmp); | |
1427 | } | |
1428 | ||
1429 | /* ld2w */ | |
1430 | void | |
1431 | OP_6601 () | |
1432 | { | |
1433 | uint16 addr = GPR (OP[1]); | |
1434 | int32 tmp; | |
1435 | trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID); | |
c3f6f71d JM |
1436 | if ((addr & 1)) |
1437 | { | |
7fc5b5ad AC |
1438 | State.exception = SIG_D10V_BUS; |
1439 | State.pc_changed = 1; /* Don't increment the PC. */ | |
c3f6f71d JM |
1440 | trace_output_void (); |
1441 | return; | |
1442 | } | |
c906108c SS |
1443 | tmp = RLW (addr); |
1444 | SET_GPR32 (OP[0], tmp); | |
d4f3574e | 1445 | if (OP[0] != OP[1] && ((OP[0] + 1) != OP[1])) |
7a292a7a | 1446 | INC_ADDR (OP[1], -4); |
c906108c SS |
1447 | trace_output_32 (tmp); |
1448 | } | |
1449 | ||
1450 | /* ld2w */ | |
1451 | void | |
1452 | OP_6201 () | |
1453 | { | |
1454 | int32 tmp; | |
1455 | uint16 addr = GPR (OP[1]); | |
1456 | trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTINC, OP_VOID); | |
c3f6f71d JM |
1457 | if ((addr & 1)) |
1458 | { | |
7fc5b5ad AC |
1459 | State.exception = SIG_D10V_BUS; |
1460 | State.pc_changed = 1; /* Don't increment the PC. */ | |
c3f6f71d JM |
1461 | trace_output_void (); |
1462 | return; | |
1463 | } | |
c906108c SS |
1464 | tmp = RLW (addr); |
1465 | SET_GPR32 (OP[0], tmp); | |
d4f3574e | 1466 | if (OP[0] != OP[1] && ((OP[0] + 1) != OP[1])) |
7a292a7a | 1467 | INC_ADDR (OP[1], 4); |
c906108c SS |
1468 | trace_output_32 (tmp); |
1469 | } | |
1470 | ||
1471 | /* ld2w */ | |
1472 | void | |
1473 | OP_6200 () | |
1474 | { | |
1475 | uint16 addr = GPR (OP[1]); | |
1476 | int32 tmp; | |
1477 | trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF, OP_VOID); | |
c3f6f71d JM |
1478 | if ((addr & 1)) |
1479 | { | |
7fc5b5ad AC |
1480 | State.exception = SIG_D10V_BUS; |
1481 | State.pc_changed = 1; /* Don't increment the PC. */ | |
c3f6f71d JM |
1482 | trace_output_void (); |
1483 | return; | |
1484 | } | |
1485 | tmp = RLW (addr); | |
c906108c SS |
1486 | SET_GPR32 (OP[0], tmp); |
1487 | trace_output_32 (tmp); | |
1488 | } | |
1489 | ||
cff3e48b JM |
1490 | /* ld2w */ |
1491 | void | |
1492 | OP_33010000 () | |
1493 | { | |
1494 | int32 tmp; | |
c3f6f71d | 1495 | uint16 addr = OP[1]; |
cff3e48b | 1496 | trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF3, OP_VOID); |
c3f6f71d JM |
1497 | if ((addr & 1)) |
1498 | { | |
7fc5b5ad AC |
1499 | State.exception = SIG_D10V_BUS; |
1500 | State.pc_changed = 1; /* Don't increment the PC. */ | |
c3f6f71d JM |
1501 | trace_output_void (); |
1502 | return; | |
1503 | } | |
1504 | tmp = RLW (addr); | |
cff3e48b JM |
1505 | SET_GPR32 (OP[0], tmp); |
1506 | trace_output_32 (tmp); | |
1507 | } | |
1508 | ||
c906108c SS |
1509 | /* ldb */ |
1510 | void | |
1511 | OP_38000000 () | |
1512 | { | |
1513 | int16 tmp; | |
1514 | trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID); | |
1515 | tmp = SEXT8 (RB (OP[1] + GPR (OP[2]))); | |
1516 | SET_GPR (OP[0], tmp); | |
1517 | trace_output_16 (tmp); | |
1518 | } | |
1519 | ||
1520 | /* ldb */ | |
1521 | void | |
1522 | OP_7000 () | |
1523 | { | |
1524 | int16 tmp; | |
1525 | trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF, OP_VOID); | |
1526 | tmp = SEXT8 (RB (GPR (OP[1]))); | |
1527 | SET_GPR (OP[0], tmp); | |
1528 | trace_output_16 (tmp); | |
1529 | } | |
1530 | ||
1531 | /* ldi.s */ | |
1532 | void | |
1533 | OP_4001 () | |
1534 | { | |
1535 | int16 tmp; | |
1536 | trace_input ("ldi.s", OP_REG_OUTPUT, OP_CONSTANT4, OP_VOID); | |
1537 | tmp = SEXT4 (OP[1]); | |
1538 | SET_GPR (OP[0], tmp); | |
1539 | trace_output_16 (tmp); | |
1540 | } | |
1541 | ||
1542 | /* ldi.l */ | |
1543 | void | |
1544 | OP_20000000 () | |
1545 | { | |
1546 | int16 tmp; | |
1547 | trace_input ("ldi.l", OP_REG_OUTPUT, OP_CONSTANT16, OP_VOID); | |
1548 | tmp = OP[1]; | |
1549 | SET_GPR (OP[0], tmp); | |
1550 | trace_output_16 (tmp); | |
1551 | } | |
1552 | ||
1553 | /* ldub */ | |
1554 | void | |
1555 | OP_39000000 () | |
1556 | { | |
1557 | int16 tmp; | |
1558 | trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID); | |
1559 | tmp = RB (OP[1] + GPR (OP[2])); | |
1560 | SET_GPR (OP[0], tmp); | |
1561 | trace_output_16 (tmp); | |
1562 | } | |
1563 | ||
1564 | /* ldub */ | |
1565 | void | |
1566 | OP_7200 () | |
1567 | { | |
1568 | int16 tmp; | |
1569 | trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF, OP_VOID); | |
1570 | tmp = RB (GPR (OP[1])); | |
1571 | SET_GPR (OP[0], tmp); | |
1572 | trace_output_16 (tmp); | |
1573 | } | |
1574 | ||
1575 | /* mac */ | |
1576 | void | |
1577 | OP_2A00 () | |
1578 | { | |
1579 | int64 tmp; | |
1580 | ||
1581 | trace_input ("mac", OP_ACCUM, OP_REG, OP_REG); | |
1582 | tmp = SEXT40 ((int16)(GPR (OP[1])) * (int16)(GPR (OP[2]))); | |
1583 | ||
1584 | if (PSW_FX) | |
1585 | tmp = SEXT40( (tmp << 1) & MASK40); | |
1586 | ||
1587 | if (PSW_ST && tmp > SEXT40(MAX32)) | |
1588 | tmp = (MAX32); | |
1589 | ||
1590 | tmp += SEXT40 (ACC (OP[0])); | |
1591 | if (PSW_ST) | |
1592 | { | |
1593 | if (tmp > SEXT40(MAX32)) | |
1594 | tmp = (MAX32); | |
1595 | else if (tmp < SEXT40(MIN32)) | |
1596 | tmp = (MIN32); | |
1597 | else | |
1598 | tmp = (tmp & MASK40); | |
1599 | } | |
1600 | else | |
1601 | tmp = (tmp & MASK40); | |
1602 | SET_ACC (OP[0], tmp); | |
1603 | trace_output_40 (tmp); | |
1604 | } | |
1605 | ||
1606 | /* macsu */ | |
1607 | void | |
1608 | OP_1A00 () | |
1609 | { | |
1610 | int64 tmp; | |
1611 | ||
1612 | trace_input ("macsu", OP_ACCUM, OP_REG, OP_REG); | |
1613 | tmp = SEXT40 ((int16) GPR (OP[1]) * GPR (OP[2])); | |
1614 | if (PSW_FX) | |
1615 | tmp = SEXT40 ((tmp << 1) & MASK40); | |
1616 | tmp = ((SEXT40 (ACC (OP[0])) + tmp) & MASK40); | |
1617 | SET_ACC (OP[0], tmp); | |
1618 | trace_output_40 (tmp); | |
1619 | } | |
1620 | ||
1621 | /* macu */ | |
1622 | void | |
1623 | OP_3A00 () | |
1624 | { | |
1625 | uint64 tmp; | |
1626 | uint32 src1; | |
1627 | uint32 src2; | |
1628 | ||
1629 | trace_input ("macu", OP_ACCUM, OP_REG, OP_REG); | |
1630 | src1 = (uint16) GPR (OP[1]); | |
1631 | src2 = (uint16) GPR (OP[2]); | |
1632 | tmp = src1 * src2; | |
1633 | if (PSW_FX) | |
1634 | tmp = (tmp << 1); | |
1635 | tmp = ((ACC (OP[0]) + tmp) & MASK40); | |
1636 | SET_ACC (OP[0], tmp); | |
1637 | trace_output_40 (tmp); | |
1638 | } | |
1639 | ||
1640 | /* max */ | |
1641 | void | |
1642 | OP_2600 () | |
1643 | { | |
1644 | int16 tmp; | |
1645 | trace_input ("max", OP_REG, OP_REG, OP_VOID); | |
1646 | SET_PSW_F1 (PSW_F0); | |
1647 | if ((int16) GPR (OP[1]) > (int16)GPR (OP[0])) | |
1648 | { | |
1649 | tmp = GPR (OP[1]); | |
1650 | SET_PSW_F0 (1); | |
1651 | } | |
1652 | else | |
1653 | { | |
1654 | tmp = GPR (OP[0]); | |
1655 | SET_PSW_F0 (0); | |
1656 | } | |
1657 | SET_GPR (OP[0], tmp); | |
1658 | trace_output_16 (tmp); | |
1659 | } | |
1660 | ||
1661 | /* max */ | |
1662 | void | |
1663 | OP_3600 () | |
1664 | { | |
1665 | int64 tmp; | |
1666 | ||
1667 | trace_input ("max", OP_ACCUM, OP_DREG, OP_VOID); | |
1668 | SET_PSW_F1 (PSW_F0); | |
1669 | tmp = SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1); | |
1670 | if (tmp > SEXT40 (ACC (OP[0]))) | |
1671 | { | |
1672 | tmp = (tmp & MASK40); | |
1673 | SET_PSW_F0 (1); | |
1674 | } | |
1675 | else | |
1676 | { | |
1677 | tmp = ACC (OP[0]); | |
1678 | SET_PSW_F0 (0); | |
1679 | } | |
1680 | SET_ACC (OP[0], tmp); | |
1681 | trace_output_40 (tmp); | |
1682 | } | |
1683 | ||
1684 | /* max */ | |
1685 | void | |
1686 | OP_3602 () | |
1687 | { | |
1688 | int64 tmp; | |
1689 | trace_input ("max", OP_ACCUM, OP_ACCUM, OP_VOID); | |
1690 | SET_PSW_F1 (PSW_F0); | |
1691 | if (SEXT40 (ACC (OP[1])) > SEXT40 (ACC (OP[0]))) | |
1692 | { | |
1693 | tmp = ACC (OP[1]); | |
1694 | SET_PSW_F0 (1); | |
1695 | } | |
1696 | else | |
1697 | { | |
1698 | tmp = ACC (OP[0]); | |
1699 | SET_PSW_F0 (0); | |
1700 | } | |
1701 | SET_ACC (OP[0], tmp); | |
1702 | trace_output_40 (tmp); | |
1703 | } | |
1704 | ||
1705 | ||
1706 | /* min */ | |
1707 | void | |
1708 | OP_2601 () | |
1709 | { | |
1710 | int16 tmp; | |
1711 | trace_input ("min", OP_REG, OP_REG, OP_VOID); | |
1712 | SET_PSW_F1 (PSW_F0); | |
1713 | if ((int16)GPR (OP[1]) < (int16)GPR (OP[0])) | |
1714 | { | |
1715 | tmp = GPR (OP[1]); | |
1716 | SET_PSW_F0 (1); | |
1717 | } | |
1718 | else | |
1719 | { | |
1720 | tmp = GPR (OP[0]); | |
1721 | SET_PSW_F0 (0); | |
1722 | } | |
1723 | SET_GPR (OP[0], tmp); | |
1724 | trace_output_16 (tmp); | |
1725 | } | |
1726 | ||
1727 | /* min */ | |
1728 | void | |
1729 | OP_3601 () | |
1730 | { | |
1731 | int64 tmp; | |
1732 | ||
1733 | trace_input ("min", OP_ACCUM, OP_DREG, OP_VOID); | |
1734 | SET_PSW_F1 (PSW_F0); | |
1735 | tmp = SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1); | |
1736 | if (tmp < SEXT40(ACC (OP[0]))) | |
1737 | { | |
1738 | tmp = (tmp & MASK40); | |
1739 | SET_PSW_F0 (1); | |
1740 | } | |
1741 | else | |
1742 | { | |
1743 | tmp = ACC (OP[0]); | |
1744 | SET_PSW_F0 (0); | |
1745 | } | |
1746 | SET_ACC (OP[0], tmp); | |
1747 | trace_output_40 (tmp); | |
1748 | } | |
1749 | ||
1750 | /* min */ | |
1751 | void | |
1752 | OP_3603 () | |
1753 | { | |
1754 | int64 tmp; | |
1755 | trace_input ("min", OP_ACCUM, OP_ACCUM, OP_VOID); | |
1756 | SET_PSW_F1 (PSW_F0); | |
1757 | if (SEXT40(ACC (OP[1])) < SEXT40(ACC (OP[0]))) | |
1758 | { | |
1759 | tmp = ACC (OP[1]); | |
1760 | SET_PSW_F0 (1); | |
1761 | } | |
1762 | else | |
1763 | { | |
1764 | tmp = ACC (OP[0]); | |
1765 | SET_PSW_F0 (0); | |
1766 | } | |
1767 | SET_ACC (OP[0], tmp); | |
1768 | trace_output_40 (tmp); | |
1769 | } | |
1770 | ||
1771 | /* msb */ | |
1772 | void | |
1773 | OP_2800 () | |
1774 | { | |
1775 | int64 tmp; | |
1776 | ||
1777 | trace_input ("msb", OP_ACCUM, OP_REG, OP_REG); | |
1778 | tmp = SEXT40 ((int16)(GPR (OP[1])) * (int16)(GPR (OP[2]))); | |
1779 | ||
1780 | if (PSW_FX) | |
1781 | tmp = SEXT40 ((tmp << 1) & MASK40); | |
1782 | ||
1783 | if (PSW_ST && tmp > SEXT40(MAX32)) | |
1784 | tmp = (MAX32); | |
1785 | ||
1786 | tmp = SEXT40(ACC (OP[0])) - tmp; | |
1787 | if (PSW_ST) | |
1788 | { | |
1789 | if (tmp > SEXT40(MAX32)) | |
1790 | tmp = (MAX32); | |
1791 | else if (tmp < SEXT40(MIN32)) | |
1792 | tmp = (MIN32); | |
1793 | else | |
1794 | tmp = (tmp & MASK40); | |
1795 | } | |
1796 | else | |
1797 | { | |
1798 | tmp = (tmp & MASK40); | |
1799 | } | |
1800 | SET_ACC (OP[0], tmp); | |
1801 | trace_output_40 (tmp); | |
1802 | } | |
1803 | ||
1804 | /* msbsu */ | |
1805 | void | |
1806 | OP_1800 () | |
1807 | { | |
1808 | int64 tmp; | |
1809 | ||
1810 | trace_input ("msbsu", OP_ACCUM, OP_REG, OP_REG); | |
1811 | tmp = SEXT40 ((int16)GPR (OP[1]) * GPR (OP[2])); | |
1812 | if (PSW_FX) | |
1813 | tmp = SEXT40( (tmp << 1) & MASK40); | |
1814 | tmp = ((SEXT40 (ACC (OP[0])) - tmp) & MASK40); | |
1815 | SET_ACC (OP[0], tmp); | |
1816 | trace_output_40 (tmp); | |
1817 | } | |
1818 | ||
1819 | /* msbu */ | |
1820 | void | |
1821 | OP_3800 () | |
1822 | { | |
1823 | uint64 tmp; | |
1824 | uint32 src1; | |
1825 | uint32 src2; | |
1826 | ||
1827 | trace_input ("msbu", OP_ACCUM, OP_REG, OP_REG); | |
1828 | src1 = (uint16) GPR (OP[1]); | |
1829 | src2 = (uint16) GPR (OP[2]); | |
1830 | tmp = src1 * src2; | |
1831 | if (PSW_FX) | |
1832 | tmp = (tmp << 1); | |
1833 | tmp = ((ACC (OP[0]) - tmp) & MASK40); | |
1834 | SET_ACC (OP[0], tmp); | |
1835 | trace_output_40 (tmp); | |
1836 | } | |
1837 | ||
1838 | /* mul */ | |
1839 | void | |
1840 | OP_2E00 () | |
1841 | { | |
1842 | int16 tmp; | |
1843 | trace_input ("mul", OP_REG, OP_REG, OP_VOID); | |
1844 | tmp = GPR (OP[0]) * GPR (OP[1]); | |
1845 | SET_GPR (OP[0], tmp); | |
1846 | trace_output_16 (tmp); | |
1847 | } | |
1848 | ||
1849 | /* mulx */ | |
1850 | void | |
1851 | OP_2C00 () | |
1852 | { | |
1853 | int64 tmp; | |
1854 | ||
1855 | trace_input ("mulx", OP_ACCUM_OUTPUT, OP_REG, OP_REG); | |
1856 | tmp = SEXT40 ((int16)(GPR (OP[1])) * (int16)(GPR (OP[2]))); | |
1857 | ||
1858 | if (PSW_FX) | |
1859 | tmp = SEXT40 ((tmp << 1) & MASK40); | |
1860 | ||
1861 | if (PSW_ST && tmp > SEXT40(MAX32)) | |
1862 | tmp = (MAX32); | |
1863 | else | |
1864 | tmp = (tmp & MASK40); | |
1865 | SET_ACC (OP[0], tmp); | |
1866 | trace_output_40 (tmp); | |
1867 | } | |
1868 | ||
1869 | /* mulxsu */ | |
1870 | void | |
1871 | OP_1C00 () | |
1872 | { | |
1873 | int64 tmp; | |
1874 | ||
1875 | trace_input ("mulxsu", OP_ACCUM_OUTPUT, OP_REG, OP_REG); | |
1876 | tmp = SEXT40 ((int16)(GPR (OP[1])) * GPR (OP[2])); | |
1877 | ||
1878 | if (PSW_FX) | |
1879 | tmp <<= 1; | |
1880 | tmp = (tmp & MASK40); | |
1881 | SET_ACC (OP[0], tmp); | |
1882 | trace_output_40 (tmp); | |
1883 | } | |
1884 | ||
1885 | /* mulxu */ | |
1886 | void | |
1887 | OP_3C00 () | |
1888 | { | |
1889 | uint64 tmp; | |
1890 | uint32 src1; | |
1891 | uint32 src2; | |
1892 | ||
1893 | trace_input ("mulxu", OP_ACCUM_OUTPUT, OP_REG, OP_REG); | |
1894 | src1 = (uint16) GPR (OP[1]); | |
1895 | src2 = (uint16) GPR (OP[2]); | |
1896 | tmp = src1 * src2; | |
1897 | if (PSW_FX) | |
1898 | tmp <<= 1; | |
1899 | tmp = (tmp & MASK40); | |
1900 | SET_ACC (OP[0], tmp); | |
1901 | trace_output_40 (tmp); | |
1902 | } | |
1903 | ||
1904 | /* mv */ | |
1905 | void | |
1906 | OP_4000 () | |
1907 | { | |
1908 | int16 tmp; | |
1909 | trace_input ("mv", OP_REG_OUTPUT, OP_REG, OP_VOID); | |
1910 | tmp = GPR (OP[1]); | |
1911 | SET_GPR (OP[0], tmp); | |
1912 | trace_output_16 (tmp); | |
1913 | } | |
1914 | ||
1915 | /* mv2w */ | |
1916 | void | |
1917 | OP_5000 () | |
1918 | { | |
1919 | int32 tmp; | |
1920 | trace_input ("mv2w", OP_DREG_OUTPUT, OP_DREG, OP_VOID); | |
1921 | tmp = GPR32 (OP[1]); | |
1922 | SET_GPR32 (OP[0], tmp); | |
1923 | trace_output_32 (tmp); | |
1924 | } | |
1925 | ||
1926 | /* mv2wfac */ | |
1927 | void | |
1928 | OP_3E00 () | |
1929 | { | |
1930 | int32 tmp; | |
1931 | trace_input ("mv2wfac", OP_DREG_OUTPUT, OP_ACCUM, OP_VOID); | |
1932 | tmp = ACC (OP[1]); | |
1933 | SET_GPR32 (OP[0], tmp); | |
1934 | trace_output_32 (tmp); | |
1935 | } | |
1936 | ||
1937 | /* mv2wtac */ | |
1938 | void | |
1939 | OP_3E01 () | |
1940 | { | |
1941 | int64 tmp; | |
1942 | trace_input ("mv2wtac", OP_DREG, OP_ACCUM_OUTPUT, OP_VOID); | |
1943 | tmp = ((SEXT16 (GPR (OP[0])) << 16 | GPR (OP[0] + 1)) & MASK40); | |
1944 | SET_ACC (OP[1], tmp); | |
1945 | trace_output_40 (tmp); | |
1946 | } | |
1947 | ||
1948 | /* mvac */ | |
1949 | void | |
1950 | OP_3E03 () | |
1951 | { | |
1952 | int64 tmp; | |
1953 | trace_input ("mvac", OP_ACCUM_OUTPUT, OP_ACCUM, OP_VOID); | |
1954 | tmp = ACC (OP[1]); | |
1955 | SET_ACC (OP[0], tmp); | |
1956 | trace_output_40 (tmp); | |
1957 | } | |
1958 | ||
1959 | /* mvb */ | |
1960 | void | |
1961 | OP_5400 () | |
1962 | { | |
1963 | int16 tmp; | |
1964 | trace_input ("mvb", OP_REG_OUTPUT, OP_REG, OP_VOID); | |
1965 | tmp = SEXT8 (GPR (OP[1]) & 0xff); | |
1966 | SET_GPR (OP[0], tmp); | |
1967 | trace_output_16 (tmp); | |
1968 | } | |
1969 | ||
1970 | /* mvf0f */ | |
1971 | void | |
1972 | OP_4400 () | |
1973 | { | |
1974 | int16 tmp; | |
1975 | trace_input ("mf0f", OP_REG_OUTPUT, OP_REG, OP_VOID); | |
1976 | if (PSW_F0 == 0) | |
1977 | { | |
1978 | tmp = GPR (OP[1]); | |
1979 | SET_GPR (OP[0], tmp); | |
1980 | } | |
1981 | else | |
1982 | tmp = GPR (OP[0]); | |
1983 | trace_output_16 (tmp); | |
1984 | } | |
1985 | ||
1986 | /* mvf0t */ | |
1987 | void | |
1988 | OP_4401 () | |
1989 | { | |
1990 | int16 tmp; | |
1991 | trace_input ("mf0t", OP_REG_OUTPUT, OP_REG, OP_VOID); | |
1992 | if (PSW_F0) | |
1993 | { | |
1994 | tmp = GPR (OP[1]); | |
1995 | SET_GPR (OP[0], tmp); | |
1996 | } | |
1997 | else | |
1998 | tmp = GPR (OP[0]); | |
1999 | trace_output_16 (tmp); | |
2000 | } | |
2001 | ||
2002 | /* mvfacg */ | |
2003 | void | |
2004 | OP_1E04 () | |
2005 | { | |
2006 | int16 tmp; | |
2007 | trace_input ("mvfacg", OP_REG_OUTPUT, OP_ACCUM, OP_VOID); | |
2008 | tmp = ((ACC (OP[1]) >> 32) & 0xff); | |
2009 | SET_GPR (OP[0], tmp); | |
2010 | trace_output_16 (tmp); | |
2011 | } | |
2012 | ||
2013 | /* mvfachi */ | |
2014 | void | |
2015 | OP_1E00 () | |
2016 | { | |
2017 | int16 tmp; | |
2018 | trace_input ("mvfachi", OP_REG_OUTPUT, OP_ACCUM, OP_VOID); | |
2019 | tmp = (ACC (OP[1]) >> 16); | |
2020 | SET_GPR (OP[0], tmp); | |
2021 | trace_output_16 (tmp); | |
2022 | } | |
2023 | ||
2024 | /* mvfaclo */ | |
2025 | void | |
2026 | OP_1E02 () | |
2027 | { | |
2028 | int16 tmp; | |
2029 | trace_input ("mvfaclo", OP_REG_OUTPUT, OP_ACCUM, OP_VOID); | |
2030 | tmp = ACC (OP[1]); | |
2031 | SET_GPR (OP[0], tmp); | |
2032 | trace_output_16 (tmp); | |
2033 | } | |
2034 | ||
2035 | /* mvfc */ | |
2036 | void | |
2037 | OP_5200 () | |
2038 | { | |
2039 | int16 tmp; | |
2040 | trace_input ("mvfc", OP_REG_OUTPUT, OP_CR, OP_VOID); | |
2041 | tmp = CREG (OP[1]); | |
2042 | SET_GPR (OP[0], tmp); | |
2043 | trace_output_16 (tmp); | |
2044 | } | |
2045 | ||
2046 | /* mvtacg */ | |
2047 | void | |
2048 | OP_1E41 () | |
2049 | { | |
2050 | int64 tmp; | |
2051 | trace_input ("mvtacg", OP_REG, OP_ACCUM, OP_VOID); | |
2052 | tmp = ((ACC (OP[1]) & MASK32) | |
2053 | | ((int64)(GPR (OP[0]) & 0xff) << 32)); | |
2054 | SET_ACC (OP[1], tmp); | |
2055 | trace_output_40 (tmp); | |
2056 | } | |
2057 | ||
2058 | /* mvtachi */ | |
2059 | void | |
2060 | OP_1E01 () | |
2061 | { | |
2062 | uint64 tmp; | |
2063 | trace_input ("mvtachi", OP_REG, OP_ACCUM, OP_VOID); | |
2064 | tmp = ACC (OP[1]) & 0xffff; | |
2065 | tmp = ((SEXT16 (GPR (OP[0])) << 16 | tmp) & MASK40); | |
2066 | SET_ACC (OP[1], tmp); | |
2067 | trace_output_40 (tmp); | |
2068 | } | |
2069 | ||
2070 | /* mvtaclo */ | |
2071 | void | |
2072 | OP_1E21 () | |
2073 | { | |
2074 | int64 tmp; | |
2075 | trace_input ("mvtaclo", OP_REG, OP_ACCUM, OP_VOID); | |
2076 | tmp = ((SEXT16 (GPR (OP[0]))) & MASK40); | |
2077 | SET_ACC (OP[1], tmp); | |
2078 | trace_output_40 (tmp); | |
2079 | } | |
2080 | ||
2081 | /* mvtc */ | |
2082 | void | |
2083 | OP_5600 () | |
2084 | { | |
2085 | int16 tmp; | |
2086 | trace_input ("mvtc", OP_REG, OP_CR_OUTPUT, OP_VOID); | |
2087 | tmp = GPR (OP[0]); | |
2088 | tmp = SET_CREG (OP[1], tmp); | |
2089 | trace_output_16 (tmp); | |
2090 | } | |
2091 | ||
2092 | /* mvub */ | |
2093 | void | |
2094 | OP_5401 () | |
2095 | { | |
2096 | int16 tmp; | |
2097 | trace_input ("mvub", OP_REG_OUTPUT, OP_REG, OP_VOID); | |
2098 | tmp = (GPR (OP[1]) & 0xff); | |
2099 | SET_GPR (OP[0], tmp); | |
2100 | trace_output_16 (tmp); | |
2101 | } | |
2102 | ||
2103 | /* neg */ | |
2104 | void | |
2105 | OP_4605 () | |
2106 | { | |
2107 | int16 tmp; | |
2108 | trace_input ("neg", OP_REG, OP_VOID, OP_VOID); | |
2109 | tmp = - GPR (OP[0]); | |
2110 | SET_GPR (OP[0], tmp); | |
2111 | trace_output_16 (tmp); | |
2112 | } | |
2113 | ||
2114 | /* neg */ | |
2115 | void | |
2116 | OP_5605 () | |
2117 | { | |
2118 | int64 tmp; | |
2119 | ||
2120 | trace_input ("neg", OP_ACCUM, OP_VOID, OP_VOID); | |
2121 | tmp = -SEXT40(ACC (OP[0])); | |
2122 | if (PSW_ST) | |
2123 | { | |
2124 | if (tmp > SEXT40(MAX32)) | |
2125 | tmp = (MAX32); | |
2126 | else if (tmp < SEXT40(MIN32)) | |
2127 | tmp = (MIN32); | |
2128 | else | |
2129 | tmp = (tmp & MASK40); | |
2130 | } | |
2131 | else | |
2132 | tmp = (tmp & MASK40); | |
2133 | SET_ACC (OP[0], tmp); | |
2134 | trace_output_40 (tmp); | |
2135 | } | |
2136 | ||
2137 | ||
2138 | /* nop */ | |
2139 | void | |
2140 | OP_5E00 () | |
2141 | { | |
2142 | trace_input ("nop", OP_VOID, OP_VOID, OP_VOID); | |
2143 | ||
2144 | ins_type_counters[ (int)State.ins_type ]--; /* don't count nops as normal instructions */ | |
2145 | switch (State.ins_type) | |
2146 | { | |
2147 | default: | |
2148 | ins_type_counters[ (int)INS_UNKNOWN ]++; | |
2149 | break; | |
2150 | ||
2151 | case INS_LEFT_PARALLEL: | |
2152 | /* Don't count a parallel op that includes a NOP as a true parallel op */ | |
2153 | ins_type_counters[ (int)INS_RIGHT_PARALLEL ]--; | |
2154 | ins_type_counters[ (int)INS_RIGHT ]++; | |
2155 | ins_type_counters[ (int)INS_LEFT_NOPS ]++; | |
2156 | break; | |
2157 | ||
2158 | case INS_LEFT: | |
2159 | case INS_LEFT_COND_EXE: | |
2160 | ins_type_counters[ (int)INS_LEFT_NOPS ]++; | |
2161 | break; | |
2162 | ||
2163 | case INS_RIGHT_PARALLEL: | |
2164 | /* Don't count a parallel op that includes a NOP as a true parallel op */ | |
2165 | ins_type_counters[ (int)INS_LEFT_PARALLEL ]--; | |
2166 | ins_type_counters[ (int)INS_LEFT ]++; | |
2167 | ins_type_counters[ (int)INS_RIGHT_NOPS ]++; | |
2168 | break; | |
2169 | ||
2170 | case INS_RIGHT: | |
2171 | case INS_RIGHT_COND_EXE: | |
2172 | ins_type_counters[ (int)INS_RIGHT_NOPS ]++; | |
2173 | break; | |
2174 | } | |
2175 | ||
2176 | trace_output_void (); | |
2177 | } | |
2178 | ||
2179 | /* not */ | |
2180 | void | |
2181 | OP_4603 () | |
2182 | { | |
2183 | int16 tmp; | |
2184 | trace_input ("not", OP_REG, OP_VOID, OP_VOID); | |
2185 | tmp = ~GPR (OP[0]); | |
2186 | SET_GPR (OP[0], tmp); | |
2187 | trace_output_16 (tmp); | |
2188 | } | |
2189 | ||
2190 | /* or */ | |
2191 | void | |
2192 | OP_800 () | |
2193 | { | |
2194 | int16 tmp; | |
2195 | trace_input ("or", OP_REG, OP_REG, OP_VOID); | |
2196 | tmp = (GPR (OP[0]) | GPR (OP[1])); | |
2197 | SET_GPR (OP[0], tmp); | |
2198 | trace_output_16 (tmp); | |
2199 | } | |
2200 | ||
2201 | /* or3 */ | |
2202 | void | |
2203 | OP_4000000 () | |
2204 | { | |
2205 | int16 tmp; | |
2206 | trace_input ("or3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16); | |
2207 | tmp = (GPR (OP[1]) | OP[2]); | |
2208 | SET_GPR (OP[0], tmp); | |
2209 | trace_output_16 (tmp); | |
2210 | } | |
2211 | ||
2212 | /* rac */ | |
2213 | void | |
2214 | OP_5201 () | |
2215 | { | |
2216 | int64 tmp; | |
2217 | int shift = SEXT3 (OP[2]); | |
2218 | ||
2219 | trace_input ("rac", OP_DREG_OUTPUT, OP_ACCUM, OP_CONSTANT3); | |
2220 | if (OP[1] != 0) | |
2221 | { | |
2222 | (*d10v_callback->printf_filtered) (d10v_callback, | |
2223 | "ERROR at PC 0x%x: instruction only valid for A0\n", | |
2224 | PC<<2); | |
2225 | State.exception = SIGILL; | |
2226 | } | |
2227 | ||
2228 | SET_PSW_F1 (PSW_F0); | |
2229 | tmp = SEXT56 ((ACC (0) << 16) | (ACC (1) & 0xffff)); | |
2230 | if (shift >=0) | |
2231 | tmp <<= shift; | |
2232 | else | |
2233 | tmp >>= -shift; | |
2234 | tmp += 0x8000; | |
2235 | tmp >>= 16; /* look at bits 0:43 */ | |
2236 | if (tmp > SEXT44 (SIGNED64 (0x0007fffffff))) | |
2237 | { | |
2238 | tmp = 0x7fffffff; | |
2239 | SET_PSW_F0 (1); | |
2240 | } | |
2241 | else if (tmp < SEXT44 (SIGNED64 (0xfff80000000))) | |
2242 | { | |
2243 | tmp = 0x80000000; | |
2244 | SET_PSW_F0 (1); | |
2245 | } | |
2246 | else | |
2247 | { | |
2248 | SET_PSW_F0 (0); | |
2249 | } | |
2250 | SET_GPR32 (OP[0], tmp); | |
2251 | trace_output_32 (tmp); | |
2252 | } | |
2253 | ||
2254 | /* rachi */ | |
2255 | void | |
2256 | OP_4201 () | |
2257 | { | |
2258 | signed64 tmp; | |
2259 | int shift = SEXT3 (OP[2]); | |
2260 | ||
2261 | trace_input ("rachi", OP_REG_OUTPUT, OP_ACCUM, OP_CONSTANT3); | |
2262 | SET_PSW_F1 (PSW_F0); | |
2263 | if (shift >=0) | |
2264 | tmp = SEXT40 (ACC (OP[1])) << shift; | |
2265 | else | |
2266 | tmp = SEXT40 (ACC (OP[1])) >> -shift; | |
2267 | tmp += 0x8000; | |
2268 | ||
2269 | if (tmp > SEXT44 (SIGNED64 (0x0007fffffff))) | |
2270 | { | |
2271 | tmp = 0x7fff; | |
2272 | SET_PSW_F0 (1); | |
2273 | } | |
2274 | else if (tmp < SEXT44 (SIGNED64 (0xfff80000000))) | |
2275 | { | |
2276 | tmp = 0x8000; | |
2277 | SET_PSW_F0 (1); | |
2278 | } | |
2279 | else | |
2280 | { | |
2281 | tmp = (tmp >> 16); | |
2282 | SET_PSW_F0 (0); | |
2283 | } | |
2284 | SET_GPR (OP[0], tmp); | |
2285 | trace_output_16 (tmp); | |
2286 | } | |
2287 | ||
2288 | /* rep */ | |
2289 | void | |
2290 | OP_27000000 () | |
2291 | { | |
2292 | trace_input ("rep", OP_REG, OP_CONSTANT16, OP_VOID); | |
2293 | SET_RPT_S (PC + 1); | |
2294 | SET_RPT_E (PC + OP[1]); | |
2295 | SET_RPT_C (GPR (OP[0])); | |
2296 | SET_PSW_RP (1); | |
2297 | if (GPR (OP[0]) == 0) | |
2298 | { | |
2299 | (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep with count=0 is illegal.\n"); | |
2300 | State.exception = SIGILL; | |
2301 | } | |
2302 | if (OP[1] < 4) | |
2303 | { | |
2304 | (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep must include at least 4 instructions.\n"); | |
2305 | State.exception = SIGILL; | |
2306 | } | |
2307 | trace_output_void (); | |
2308 | } | |
2309 | ||
2310 | /* repi */ | |
2311 | void | |
2312 | OP_2F000000 () | |
2313 | { | |
2314 | trace_input ("repi", OP_CONSTANT16, OP_CONSTANT16, OP_VOID); | |
2315 | SET_RPT_S (PC + 1); | |
2316 | SET_RPT_E (PC + OP[1]); | |
2317 | SET_RPT_C (OP[0]); | |
2318 | SET_PSW_RP (1); | |
2319 | if (OP[0] == 0) | |
2320 | { | |
2321 | (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi with count=0 is illegal.\n"); | |
2322 | State.exception = SIGILL; | |
2323 | } | |
2324 | if (OP[1] < 4) | |
2325 | { | |
2326 | (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi must include at least 4 instructions.\n"); | |
2327 | State.exception = SIGILL; | |
2328 | } | |
2329 | trace_output_void (); | |
2330 | } | |
2331 | ||
2332 | /* rtd */ | |
2333 | void | |
2334 | OP_5F60 () | |
2335 | { | |
2336 | trace_input ("rtd", OP_VOID, OP_VOID, OP_VOID); | |
2337 | SET_CREG (PSW_CR, DPSW); | |
2338 | JMP(DPC); | |
2339 | trace_output_void (); | |
2340 | } | |
2341 | ||
2342 | /* rte */ | |
2343 | void | |
2344 | OP_5F40 () | |
2345 | { | |
2346 | trace_input ("rte", OP_VOID, OP_VOID, OP_VOID); | |
2347 | SET_CREG (PSW_CR, BPSW); | |
2348 | JMP(BPC); | |
2349 | trace_output_void (); | |
2350 | } | |
2351 | ||
cff3e48b JM |
2352 | /* sac */ |
2353 | void OP_5209 () | |
2354 | { | |
2355 | int64 tmp; | |
2356 | ||
2357 | trace_input ("sac", OP_REG_OUTPUT, OP_ACCUM, OP_VOID); | |
2358 | ||
2359 | tmp = SEXT40(ACC (OP[1])); | |
2360 | ||
2361 | SET_PSW_F1 (PSW_F0); | |
2362 | ||
2363 | if (tmp > SEXT40(MAX32)) | |
2364 | { | |
2365 | tmp = (MAX32); | |
2366 | SET_PSW_F0 (1); | |
2367 | } | |
2368 | else if (tmp < SEXT40(MIN32)) | |
2369 | { | |
2370 | tmp = 0x80000000; | |
2371 | SET_PSW_F0 (1); | |
2372 | } | |
2373 | else | |
2374 | { | |
2375 | tmp = (tmp & MASK32); | |
2376 | SET_PSW_F0 (0); | |
2377 | } | |
2378 | ||
2379 | SET_GPR32 (OP[0], tmp); | |
2380 | ||
2381 | trace_output_40 (tmp); | |
2382 | } | |
2383 | ||
cff3e48b JM |
2384 | /* sachi */ |
2385 | void | |
2386 | OP_4209 () | |
2387 | { | |
2388 | int64 tmp; | |
2389 | ||
2390 | trace_input ("sachi", OP_REG_OUTPUT, OP_ACCUM, OP_VOID); | |
2391 | ||
2392 | tmp = SEXT40(ACC (OP[1])); | |
2393 | ||
2394 | SET_PSW_F1 (PSW_F0); | |
2395 | ||
2396 | if (tmp > SEXT40(MAX32)) | |
2397 | { | |
2398 | tmp = 0x7fff; | |
2399 | SET_PSW_F0 (1); | |
2400 | } | |
2401 | else if (tmp < SEXT40(MIN32)) | |
2402 | { | |
2403 | tmp = 0x8000; | |
2404 | SET_PSW_F0 (1); | |
2405 | } | |
2406 | else | |
2407 | { | |
2408 | tmp >>= 16; | |
2409 | SET_PSW_F0 (0); | |
2410 | } | |
2411 | ||
2412 | SET_GPR (OP[0], tmp); | |
2413 | ||
2414 | trace_output_16 (OP[0]); | |
2415 | } | |
2416 | ||
c906108c SS |
2417 | /* sadd */ |
2418 | void | |
2419 | OP_1223 () | |
2420 | { | |
2421 | int64 tmp; | |
2422 | ||
2423 | trace_input ("sadd", OP_ACCUM, OP_ACCUM, OP_VOID); | |
2424 | tmp = SEXT40(ACC (OP[0])) + (SEXT40(ACC (OP[1])) >> 16); | |
2425 | if (PSW_ST) | |
2426 | { | |
2427 | if (tmp > SEXT40(MAX32)) | |
2428 | tmp = (MAX32); | |
2429 | else if (tmp < SEXT40(MIN32)) | |
2430 | tmp = (MIN32); | |
2431 | else | |
2432 | tmp = (tmp & MASK40); | |
2433 | } | |
2434 | else | |
2435 | tmp = (tmp & MASK40); | |
2436 | SET_ACC (OP[0], tmp); | |
2437 | trace_output_40 (tmp); | |
2438 | } | |
2439 | ||
2440 | /* setf0f */ | |
2441 | void | |
2442 | OP_4611 () | |
2443 | { | |
2444 | int16 tmp; | |
2445 | trace_input ("setf0f", OP_REG_OUTPUT, OP_VOID, OP_VOID); | |
2446 | tmp = ((PSW_F0 == 0) ? 1 : 0); | |
2447 | SET_GPR (OP[0], tmp); | |
2448 | trace_output_16 (tmp); | |
2449 | } | |
2450 | ||
2451 | /* setf0t */ | |
2452 | void | |
2453 | OP_4613 () | |
2454 | { | |
2455 | int16 tmp; | |
2456 | trace_input ("setf0t", OP_REG_OUTPUT, OP_VOID, OP_VOID); | |
2457 | tmp = ((PSW_F0 == 1) ? 1 : 0); | |
2458 | SET_GPR (OP[0], tmp); | |
2459 | trace_output_16 (tmp); | |
2460 | } | |
2461 | ||
cff3e48b JM |
2462 | /* slae */ |
2463 | void | |
2464 | OP_3220 () | |
2465 | { | |
2466 | int64 tmp; | |
2467 | int16 reg; | |
2468 | ||
2469 | trace_input ("slae", OP_ACCUM, OP_REG, OP_VOID); | |
2470 | ||
5c44784c | 2471 | reg = SEXT16 (GPR (OP[1])); |
cff3e48b JM |
2472 | |
2473 | if (reg >= 17 || reg <= -17) | |
2474 | { | |
2475 | (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", reg); | |
2476 | State.exception = SIGILL; | |
2477 | return; | |
2478 | } | |
2479 | ||
2480 | tmp = SEXT40 (ACC (OP[0])); | |
2481 | ||
2482 | if (PSW_ST && (tmp < SEXT40 (MIN32) || tmp > SEXT40 (MAX32))) | |
2483 | { | |
5c44784c | 2484 | (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: accumulator value 0x%.2x%.8lx out of range\n", ((int)(tmp >> 32) & 0xff), ((unsigned long) tmp) & 0xffffffff); |
cff3e48b JM |
2485 | State.exception = SIGILL; |
2486 | return; | |
2487 | } | |
2488 | ||
2489 | if (reg >= 0 && reg <= 16) | |
2490 | { | |
2491 | tmp = SEXT56 ((SEXT56 (tmp)) << (GPR (OP[1]))); | |
2492 | if (PSW_ST) | |
2493 | { | |
2494 | if (tmp > SEXT40(MAX32)) | |
2495 | tmp = (MAX32); | |
2496 | else if (tmp < SEXT40(MIN32)) | |
2497 | tmp = (MIN32); | |
2498 | else | |
2499 | tmp = (tmp & MASK40); | |
2500 | } | |
2501 | else | |
2502 | tmp = (tmp & MASK40); | |
2503 | } | |
2504 | else | |
2505 | { | |
2506 | tmp = (SEXT40 (ACC (OP[0]))) >> (-GPR (OP[1])); | |
2507 | } | |
2508 | ||
2509 | SET_ACC(OP[0], tmp); | |
2510 | ||
2511 | trace_output_40(tmp); | |
2512 | } | |
2513 | ||
c906108c SS |
2514 | /* sleep */ |
2515 | void | |
2516 | OP_5FC0 () | |
2517 | { | |
2518 | trace_input ("sleep", OP_VOID, OP_VOID, OP_VOID); | |
2519 | SET_PSW_IE (1); | |
2520 | trace_output_void (); | |
2521 | } | |
2522 | ||
2523 | /* sll */ | |
2524 | void | |
2525 | OP_2200 () | |
2526 | { | |
2527 | int16 tmp; | |
2528 | trace_input ("sll", OP_REG, OP_REG, OP_VOID); | |
2529 | tmp = (GPR (OP[0]) << (GPR (OP[1]) & 0xf)); | |
2530 | SET_GPR (OP[0], tmp); | |
2531 | trace_output_16 (tmp); | |
2532 | } | |
2533 | ||
2534 | /* sll */ | |
2535 | void | |
2536 | OP_3200 () | |
2537 | { | |
2538 | int64 tmp; | |
2539 | trace_input ("sll", OP_ACCUM, OP_REG, OP_VOID); | |
2540 | if ((GPR (OP[1]) & 31) <= 16) | |
2541 | tmp = SEXT40 (ACC (OP[0])) << (GPR (OP[1]) & 31); | |
2542 | else | |
2543 | { | |
2544 | (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", GPR (OP[1]) & 31); | |
2545 | State.exception = SIGILL; | |
2546 | return; | |
2547 | } | |
2548 | ||
2549 | if (PSW_ST) | |
2550 | { | |
2551 | if (tmp > SEXT40(MAX32)) | |
2552 | tmp = (MAX32); | |
2553 | else if (tmp < SEXT40(MIN32)) | |
2554 | tmp = (MIN32); | |
2555 | else | |
2556 | tmp = (tmp & MASK40); | |
2557 | } | |
2558 | else | |
2559 | tmp = (tmp & MASK40); | |
2560 | SET_ACC (OP[0], tmp); | |
2561 | trace_output_40 (tmp); | |
2562 | } | |
2563 | ||
2564 | /* slli */ | |
2565 | void | |
2566 | OP_2201 () | |
2567 | { | |
2568 | int16 tmp; | |
2569 | trace_input ("slli", OP_REG, OP_CONSTANT16, OP_VOID); | |
2570 | tmp = (GPR (OP[0]) << OP[1]); | |
2571 | SET_GPR (OP[0], tmp); | |
2572 | trace_output_16 (tmp); | |
2573 | } | |
2574 | ||
2575 | /* slli */ | |
2576 | void | |
2577 | OP_3201 () | |
2578 | { | |
2579 | int64 tmp; | |
2580 | ||
2581 | if (OP[1] == 0) | |
2582 | OP[1] = 16; | |
2583 | ||
2584 | trace_input ("slli", OP_ACCUM, OP_CONSTANT16, OP_VOID); | |
2585 | tmp = SEXT40(ACC (OP[0])) << OP[1]; | |
2586 | ||
2587 | if (PSW_ST) | |
2588 | { | |
2589 | if (tmp > SEXT40(MAX32)) | |
2590 | tmp = (MAX32); | |
2591 | else if (tmp < SEXT40(MIN32)) | |
2592 | tmp = (MIN32); | |
2593 | else | |
2594 | tmp = (tmp & MASK40); | |
2595 | } | |
2596 | else | |
2597 | tmp = (tmp & MASK40); | |
2598 | SET_ACC (OP[0], tmp); | |
2599 | trace_output_40 (tmp); | |
2600 | } | |
2601 | ||
2602 | /* slx */ | |
2603 | void | |
2604 | OP_460B () | |
2605 | { | |
2606 | int16 tmp; | |
2607 | trace_input ("slx", OP_REG, OP_FLAG, OP_VOID); | |
2608 | tmp = ((GPR (OP[0]) << 1) | PSW_F0); | |
2609 | SET_GPR (OP[0], tmp); | |
2610 | trace_output_16 (tmp); | |
2611 | } | |
2612 | ||
2613 | /* sra */ | |
2614 | void | |
2615 | OP_2400 () | |
2616 | { | |
2617 | int16 tmp; | |
2618 | trace_input ("sra", OP_REG, OP_REG, OP_VOID); | |
2619 | tmp = (((int16)(GPR (OP[0]))) >> (GPR (OP[1]) & 0xf)); | |
2620 | SET_GPR (OP[0], tmp); | |
2621 | trace_output_16 (tmp); | |
2622 | } | |
2623 | ||
2624 | /* sra */ | |
2625 | void | |
2626 | OP_3400 () | |
2627 | { | |
2628 | trace_input ("sra", OP_ACCUM, OP_REG, OP_VOID); | |
2629 | if ((GPR (OP[1]) & 31) <= 16) | |
2630 | { | |
2631 | int64 tmp = ((SEXT40(ACC (OP[0])) >> (GPR (OP[1]) & 31)) & MASK40); | |
2632 | SET_ACC (OP[0], tmp); | |
2633 | trace_output_40 (tmp); | |
2634 | } | |
2635 | else | |
2636 | { | |
2637 | (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", GPR (OP[1]) & 31); | |
2638 | State.exception = SIGILL; | |
2639 | return; | |
2640 | } | |
2641 | } | |
2642 | ||
2643 | /* srai */ | |
2644 | void | |
2645 | OP_2401 () | |
2646 | { | |
2647 | int16 tmp; | |
2648 | trace_input ("srai", OP_REG, OP_CONSTANT16, OP_VOID); | |
2649 | tmp = (((int16)(GPR (OP[0]))) >> OP[1]); | |
2650 | SET_GPR (OP[0], tmp); | |
2651 | trace_output_16 (tmp); | |
2652 | } | |
2653 | ||
2654 | /* srai */ | |
2655 | void | |
2656 | OP_3401 () | |
2657 | { | |
2658 | int64 tmp; | |
2659 | if (OP[1] == 0) | |
2660 | OP[1] = 16; | |
2661 | ||
2662 | trace_input ("srai", OP_ACCUM, OP_CONSTANT16, OP_VOID); | |
2663 | tmp = ((SEXT40(ACC (OP[0])) >> OP[1]) & MASK40); | |
2664 | SET_ACC (OP[0], tmp); | |
2665 | trace_output_40 (tmp); | |
2666 | } | |
2667 | ||
2668 | /* srl */ | |
2669 | void | |
2670 | OP_2000 () | |
2671 | { | |
2672 | int16 tmp; | |
2673 | trace_input ("srl", OP_REG, OP_REG, OP_VOID); | |
2674 | tmp = (GPR (OP[0]) >> (GPR (OP[1]) & 0xf)); | |
2675 | SET_GPR (OP[0], tmp); | |
2676 | trace_output_16 (tmp); | |
2677 | } | |
2678 | ||
2679 | /* srl */ | |
2680 | void | |
2681 | OP_3000 () | |
2682 | { | |
2683 | trace_input ("srl", OP_ACCUM, OP_REG, OP_VOID); | |
2684 | if ((GPR (OP[1]) & 31) <= 16) | |
2685 | { | |
2686 | int64 tmp = ((uint64)((ACC (OP[0]) & MASK40) >> (GPR (OP[1]) & 31))); | |
2687 | SET_ACC (OP[0], tmp); | |
2688 | trace_output_40 (tmp); | |
2689 | } | |
2690 | else | |
2691 | { | |
2692 | (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", GPR (OP[1]) & 31); | |
2693 | State.exception = SIGILL; | |
2694 | return; | |
2695 | } | |
2696 | ||
2697 | } | |
2698 | ||
2699 | /* srli */ | |
2700 | void | |
2701 | OP_2001 () | |
2702 | { | |
2703 | int16 tmp; | |
2704 | trace_input ("srli", OP_REG, OP_CONSTANT16, OP_VOID); | |
2705 | tmp = (GPR (OP[0]) >> OP[1]); | |
2706 | SET_GPR (OP[0], tmp); | |
2707 | trace_output_16 (tmp); | |
2708 | } | |
2709 | ||
2710 | /* srli */ | |
2711 | void | |
2712 | OP_3001 () | |
2713 | { | |
2714 | int64 tmp; | |
2715 | if (OP[1] == 0) | |
2716 | OP[1] = 16; | |
2717 | ||
2718 | trace_input ("srli", OP_ACCUM, OP_CONSTANT16, OP_VOID); | |
2719 | tmp = ((uint64)(ACC (OP[0]) & MASK40) >> OP[1]); | |
2720 | SET_ACC (OP[0], tmp); | |
2721 | trace_output_40 (tmp); | |
2722 | } | |
2723 | ||
2724 | /* srx */ | |
2725 | void | |
2726 | OP_4609 () | |
2727 | { | |
2728 | uint16 tmp; | |
2729 | trace_input ("srx", OP_REG, OP_FLAG, OP_VOID); | |
2730 | tmp = PSW_F0 << 15; | |
2731 | tmp = ((GPR (OP[0]) >> 1) | tmp); | |
2732 | SET_GPR (OP[0], tmp); | |
2733 | trace_output_16 (tmp); | |
2734 | } | |
2735 | ||
2736 | /* st */ | |
2737 | void | |
2738 | OP_34000000 () | |
2739 | { | |
c3f6f71d | 2740 | uint16 addr = OP[1] + GPR (OP[2]); |
c906108c | 2741 | trace_input ("st", OP_REG, OP_MEMREF2, OP_VOID); |
c3f6f71d JM |
2742 | if ((addr & 1)) |
2743 | { | |
7fc5b5ad AC |
2744 | State.exception = SIG_D10V_BUS; |
2745 | State.pc_changed = 1; /* Don't increment the PC. */ | |
c3f6f71d JM |
2746 | trace_output_void (); |
2747 | return; | |
2748 | } | |
2749 | SW (addr, GPR (OP[0])); | |
c906108c SS |
2750 | trace_output_void (); |
2751 | } | |
2752 | ||
2753 | /* st */ | |
2754 | void | |
2755 | OP_6800 () | |
2756 | { | |
c3f6f71d | 2757 | uint16 addr = GPR (OP[1]); |
c906108c | 2758 | trace_input ("st", OP_REG, OP_MEMREF, OP_VOID); |
c3f6f71d JM |
2759 | if ((addr & 1)) |
2760 | { | |
7fc5b5ad AC |
2761 | State.exception = SIG_D10V_BUS; |
2762 | State.pc_changed = 1; /* Don't increment the PC. */ | |
c3f6f71d JM |
2763 | trace_output_void (); |
2764 | return; | |
2765 | } | |
2766 | SW (addr, GPR (OP[0])); | |
c906108c SS |
2767 | trace_output_void (); |
2768 | } | |
2769 | ||
2770 | /* st */ | |
c3f6f71d | 2771 | /* st Rsrc1,@-SP */ |
c906108c SS |
2772 | void |
2773 | OP_6C1F () | |
2774 | { | |
2775 | uint16 addr = GPR (OP[1]) - 2; | |
2776 | trace_input ("st", OP_REG, OP_PREDEC, OP_VOID); | |
2777 | if (OP[1] != 15) | |
2778 | { | |
2779 | (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n"); | |
2780 | State.exception = SIGILL; | |
2781 | return; | |
2782 | } | |
c3f6f71d JM |
2783 | if ((addr & 1)) |
2784 | { | |
7fc5b5ad AC |
2785 | State.exception = SIG_D10V_BUS; |
2786 | State.pc_changed = 1; /* Don't increment the PC. */ | |
c3f6f71d JM |
2787 | trace_output_void (); |
2788 | return; | |
2789 | } | |
c906108c SS |
2790 | SW (addr, GPR (OP[0])); |
2791 | SET_GPR (OP[1], addr); | |
2792 | trace_output_void (); | |
2793 | } | |
2794 | ||
2795 | /* st */ | |
2796 | void | |
2797 | OP_6801 () | |
2798 | { | |
c3f6f71d | 2799 | uint16 addr = GPR (OP[1]); |
c906108c | 2800 | trace_input ("st", OP_REG, OP_POSTINC, OP_VOID); |
c3f6f71d JM |
2801 | if ((addr & 1)) |
2802 | { | |
7fc5b5ad AC |
2803 | State.exception = SIG_D10V_BUS; |
2804 | State.pc_changed = 1; /* Don't increment the PC. */ | |
c3f6f71d JM |
2805 | trace_output_void (); |
2806 | return; | |
2807 | } | |
2808 | SW (addr, GPR (OP[0])); | |
c906108c SS |
2809 | INC_ADDR (OP[1], 2); |
2810 | trace_output_void (); | |
2811 | } | |
2812 | ||
2813 | /* st */ | |
2814 | void | |
2815 | OP_6C01 () | |
2816 | { | |
c3f6f71d | 2817 | uint16 addr = GPR (OP[1]); |
c906108c SS |
2818 | trace_input ("st", OP_REG, OP_POSTDEC, OP_VOID); |
2819 | if ( OP[1] == 15 ) | |
2820 | { | |
2821 | (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot post-decrement register r15 (SP).\n"); | |
2822 | State.exception = SIGILL; | |
2823 | return; | |
2824 | } | |
c3f6f71d JM |
2825 | if ((addr & 1)) |
2826 | { | |
7fc5b5ad AC |
2827 | State.exception = SIG_D10V_BUS; |
2828 | State.pc_changed = 1; /* Don't increment the PC. */ | |
c3f6f71d JM |
2829 | trace_output_void (); |
2830 | return; | |
2831 | } | |
2832 | SW (addr, GPR (OP[0])); | |
c906108c SS |
2833 | INC_ADDR (OP[1], -2); |
2834 | trace_output_void (); | |
2835 | } | |
2836 | ||
cff3e48b JM |
2837 | /* st */ |
2838 | void | |
2839 | OP_36010000 () | |
2840 | { | |
c3f6f71d | 2841 | uint16 addr = OP[1]; |
cff3e48b | 2842 | trace_input ("st", OP_REG, OP_MEMREF3, OP_VOID); |
c3f6f71d JM |
2843 | if ((addr & 1)) |
2844 | { | |
7fc5b5ad AC |
2845 | State.exception = SIG_D10V_BUS; |
2846 | State.pc_changed = 1; /* Don't increment the PC. */ | |
c3f6f71d JM |
2847 | trace_output_void (); |
2848 | return; | |
2849 | } | |
2850 | SW (addr, GPR (OP[0])); | |
cff3e48b JM |
2851 | trace_output_void (); |
2852 | } | |
2853 | ||
c906108c SS |
2854 | /* st2w */ |
2855 | void | |
2856 | OP_35000000 () | |
2857 | { | |
c3f6f71d | 2858 | uint16 addr = GPR (OP[2])+ OP[1]; |
c906108c | 2859 | trace_input ("st2w", OP_DREG, OP_MEMREF2, OP_VOID); |
c3f6f71d JM |
2860 | if ((addr & 1)) |
2861 | { | |
7fc5b5ad AC |
2862 | State.exception = SIG_D10V_BUS; |
2863 | State.pc_changed = 1; /* Don't increment the PC. */ | |
c3f6f71d JM |
2864 | trace_output_void (); |
2865 | return; | |
2866 | } | |
2867 | SW (addr + 0, GPR (OP[0] + 0)); | |
2868 | SW (addr + 2, GPR (OP[0] + 1)); | |
c906108c SS |
2869 | trace_output_void (); |
2870 | } | |
2871 | ||
2872 | /* st2w */ | |
2873 | void | |
2874 | OP_6A00 () | |
2875 | { | |
c3f6f71d | 2876 | uint16 addr = GPR (OP[1]); |
c906108c | 2877 | trace_input ("st2w", OP_DREG, OP_MEMREF, OP_VOID); |
c3f6f71d JM |
2878 | if ((addr & 1)) |
2879 | { | |
7fc5b5ad AC |
2880 | State.exception = SIG_D10V_BUS; |
2881 | State.pc_changed = 1; /* Don't increment the PC. */ | |
c3f6f71d JM |
2882 | trace_output_void (); |
2883 | return; | |
2884 | } | |
2885 | SW (addr + 0, GPR (OP[0] + 0)); | |
2886 | SW (addr + 2, GPR (OP[0] + 1)); | |
c906108c SS |
2887 | trace_output_void (); |
2888 | } | |
2889 | ||
2890 | /* st2w */ | |
2891 | void | |
2892 | OP_6E1F () | |
2893 | { | |
2894 | uint16 addr = GPR (OP[1]) - 4; | |
2895 | trace_input ("st2w", OP_DREG, OP_PREDEC, OP_VOID); | |
2896 | if ( OP[1] != 15 ) | |
2897 | { | |
2898 | (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n"); | |
2899 | State.exception = SIGILL; | |
2900 | return; | |
2901 | } | |
c3f6f71d JM |
2902 | if ((addr & 1)) |
2903 | { | |
7fc5b5ad AC |
2904 | State.exception = SIG_D10V_BUS; |
2905 | State.pc_changed = 1; /* Don't increment the PC. */ | |
c3f6f71d JM |
2906 | trace_output_void (); |
2907 | return; | |
2908 | } | |
c906108c SS |
2909 | SW (addr + 0, GPR (OP[0] + 0)); |
2910 | SW (addr + 2, GPR (OP[0] + 1)); | |
2911 | SET_GPR (OP[1], addr); | |
2912 | trace_output_void (); | |
2913 | } | |
2914 | ||
2915 | /* st2w */ | |
2916 | void | |
2917 | OP_6A01 () | |
2918 | { | |
c3f6f71d | 2919 | uint16 addr = GPR (OP[1]); |
c906108c | 2920 | trace_input ("st2w", OP_DREG, OP_POSTINC, OP_VOID); |
c3f6f71d JM |
2921 | if ((addr & 1)) |
2922 | { | |
7fc5b5ad AC |
2923 | State.exception = SIG_D10V_BUS; |
2924 | State.pc_changed = 1; /* Don't increment the PC. */ | |
c3f6f71d JM |
2925 | trace_output_void (); |
2926 | return; | |
2927 | } | |
2928 | SW (addr + 0, GPR (OP[0] + 0)); | |
2929 | SW (addr + 2, GPR (OP[0] + 1)); | |
c906108c SS |
2930 | INC_ADDR (OP[1], 4); |
2931 | trace_output_void (); | |
2932 | } | |
2933 | ||
2934 | /* st2w */ | |
2935 | void | |
2936 | OP_6E01 () | |
2937 | { | |
c3f6f71d | 2938 | uint16 addr = GPR (OP[1]); |
c906108c SS |
2939 | trace_input ("st2w", OP_DREG, OP_POSTDEC, OP_VOID); |
2940 | if ( OP[1] == 15 ) | |
2941 | { | |
2942 | (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot post-decrement register r15 (SP).\n"); | |
2943 | State.exception = SIGILL; | |
2944 | return; | |
2945 | } | |
c3f6f71d JM |
2946 | if ((addr & 1)) |
2947 | { | |
7fc5b5ad AC |
2948 | State.exception = SIG_D10V_BUS; |
2949 | State.pc_changed = 1; /* Don't increment the PC. */ | |
c3f6f71d JM |
2950 | trace_output_void (); |
2951 | return; | |
2952 | } | |
2953 | SW (addr + 0, GPR (OP[0] + 0)); | |
2954 | SW (addr + 2, GPR (OP[0] + 1)); | |
c906108c SS |
2955 | INC_ADDR (OP[1], -4); |
2956 | trace_output_void (); | |
2957 | } | |
2958 | ||
cff3e48b JM |
2959 | /* st2w */ |
2960 | void | |
2961 | OP_37010000 () | |
2962 | { | |
c3f6f71d | 2963 | uint16 addr = OP[1]; |
cff3e48b | 2964 | trace_input ("st2w", OP_DREG, OP_MEMREF3, OP_VOID); |
c3f6f71d JM |
2965 | if ((addr & 1)) |
2966 | { | |
7fc5b5ad AC |
2967 | State.exception = SIG_D10V_BUS; |
2968 | State.pc_changed = 1; /* Don't increment the PC. */ | |
c3f6f71d JM |
2969 | trace_output_void (); |
2970 | return; | |
2971 | } | |
2972 | SW (addr + 0, GPR (OP[0] + 0)); | |
2973 | SW (addr + 2, GPR (OP[0] + 1)); | |
cff3e48b JM |
2974 | trace_output_void (); |
2975 | } | |
2976 | ||
c906108c SS |
2977 | /* stb */ |
2978 | void | |
2979 | OP_3C000000 () | |
2980 | { | |
2981 | trace_input ("stb", OP_REG, OP_MEMREF2, OP_VOID); | |
2982 | SB (GPR (OP[2]) + OP[1], GPR (OP[0])); | |
2983 | trace_output_void (); | |
2984 | } | |
2985 | ||
2986 | /* stb */ | |
2987 | void | |
2988 | OP_7800 () | |
2989 | { | |
2990 | trace_input ("stb", OP_REG, OP_MEMREF, OP_VOID); | |
2991 | SB (GPR (OP[1]), GPR (OP[0])); | |
2992 | trace_output_void (); | |
2993 | } | |
2994 | ||
2995 | /* stop */ | |
2996 | void | |
2997 | OP_5FE0 () | |
2998 | { | |
2999 | trace_input ("stop", OP_VOID, OP_VOID, OP_VOID); | |
3000 | State.exception = SIG_D10V_STOP; | |
3001 | trace_output_void (); | |
3002 | } | |
3003 | ||
3004 | /* sub */ | |
3005 | void | |
3006 | OP_0 () | |
3007 | { | |
3008 | uint16 a = GPR (OP[0]); | |
3009 | uint16 b = GPR (OP[1]); | |
3010 | uint16 tmp = (a - b); | |
3011 | trace_input ("sub", OP_REG, OP_REG, OP_VOID); | |
3012 | /* see ../common/sim-alu.h for a more extensive discussion on how to | |
3013 | compute the carry/overflow bits. */ | |
3014 | SET_PSW_C (a >= b); | |
3015 | SET_GPR (OP[0], tmp); | |
3016 | trace_output_16 (tmp); | |
3017 | } | |
3018 | ||
3019 | /* sub */ | |
3020 | void | |
3021 | OP_1001 () | |
3022 | { | |
3023 | int64 tmp; | |
3024 | ||
3025 | trace_input ("sub", OP_ACCUM, OP_DREG, OP_VOID); | |
3026 | tmp = SEXT40(ACC (OP[0])) - (SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1)); | |
3027 | if (PSW_ST) | |
3028 | { | |
3029 | if (tmp > SEXT40(MAX32)) | |
3030 | tmp = (MAX32); | |
3031 | else if (tmp < SEXT40(MIN32)) | |
3032 | tmp = (MIN32); | |
3033 | else | |
3034 | tmp = (tmp & MASK40); | |
3035 | } | |
3036 | else | |
3037 | tmp = (tmp & MASK40); | |
3038 | SET_ACC (OP[0], tmp); | |
3039 | ||
3040 | trace_output_40 (tmp); | |
3041 | } | |
3042 | ||
3043 | /* sub */ | |
3044 | ||
3045 | void | |
3046 | OP_1003 () | |
3047 | { | |
3048 | int64 tmp; | |
3049 | ||
3050 | trace_input ("sub", OP_ACCUM, OP_ACCUM, OP_VOID); | |
3051 | tmp = SEXT40(ACC (OP[0])) - SEXT40(ACC (OP[1])); | |
3052 | if (PSW_ST) | |
3053 | { | |
3054 | if (tmp > SEXT40(MAX32)) | |
3055 | tmp = (MAX32); | |
3056 | else if (tmp < SEXT40(MIN32)) | |
3057 | tmp = (MIN32); | |
3058 | else | |
3059 | tmp = (tmp & MASK40); | |
3060 | } | |
3061 | else | |
3062 | tmp = (tmp & MASK40); | |
3063 | SET_ACC (OP[0], tmp); | |
3064 | ||
3065 | trace_output_40 (tmp); | |
3066 | } | |
3067 | ||
3068 | /* sub2w */ | |
3069 | void | |
3070 | OP_1000 () | |
3071 | { | |
3072 | uint32 tmp, a, b; | |
3073 | ||
3074 | trace_input ("sub2w", OP_DREG, OP_DREG, OP_VOID); | |
3075 | a = (uint32)((GPR (OP[0]) << 16) | GPR (OP[0] + 1)); | |
3076 | b = (uint32)((GPR (OP[1]) << 16) | GPR (OP[1] + 1)); | |
3077 | /* see ../common/sim-alu.h for a more extensive discussion on how to | |
3078 | compute the carry/overflow bits */ | |
3079 | tmp = a - b; | |
3080 | SET_PSW_C (a >= b); | |
3081 | SET_GPR32 (OP[0], tmp); | |
3082 | trace_output_32 (tmp); | |
3083 | } | |
3084 | ||
3085 | /* subac3 */ | |
3086 | void | |
3087 | OP_17000000 () | |
3088 | { | |
3089 | int64 tmp; | |
3090 | ||
3091 | trace_input ("subac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM); | |
3092 | tmp = SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1)) - SEXT40 (ACC (OP[2])); | |
3093 | SET_GPR32 (OP[0], tmp); | |
3094 | trace_output_32 (tmp); | |
3095 | } | |
3096 | ||
3097 | /* subac3 */ | |
3098 | void | |
3099 | OP_17000002 () | |
3100 | { | |
3101 | int64 tmp; | |
3102 | ||
3103 | trace_input ("subac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM); | |
3104 | tmp = SEXT40 (ACC (OP[1])) - SEXT40(ACC (OP[2])); | |
3105 | SET_GPR32 (OP[0], tmp); | |
3106 | trace_output_32 (tmp); | |
3107 | } | |
3108 | ||
3109 | /* subac3s */ | |
3110 | void | |
3111 | OP_17001000 () | |
3112 | { | |
3113 | int64 tmp; | |
3114 | ||
3115 | trace_input ("subac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM); | |
3116 | SET_PSW_F1 (PSW_F0); | |
3117 | tmp = SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1)) - SEXT40(ACC (OP[2])); | |
3118 | if (tmp > SEXT40(MAX32)) | |
3119 | { | |
3120 | tmp = (MAX32); | |
3121 | SET_PSW_F0 (1); | |
3122 | } | |
3123 | else if (tmp < SEXT40(MIN32)) | |
3124 | { | |
3125 | tmp = (MIN32); | |
3126 | SET_PSW_F0 (1); | |
3127 | } | |
3128 | else | |
3129 | { | |
3130 | SET_PSW_F0 (0); | |
3131 | } | |
3132 | SET_GPR32 (OP[0], tmp); | |
3133 | trace_output_32 (tmp); | |
3134 | } | |
3135 | ||
3136 | /* subac3s */ | |
3137 | void | |
3138 | OP_17001002 () | |
3139 | { | |
3140 | int64 tmp; | |
3141 | ||
3142 | trace_input ("subac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM); | |
3143 | SET_PSW_F1 (PSW_F0); | |
3144 | tmp = SEXT40(ACC (OP[1])) - SEXT40(ACC (OP[2])); | |
3145 | if (tmp > SEXT40(MAX32)) | |
3146 | { | |
3147 | tmp = (MAX32); | |
3148 | SET_PSW_F0 (1); | |
3149 | } | |
3150 | else if (tmp < SEXT40(MIN32)) | |
3151 | { | |
3152 | tmp = (MIN32); | |
3153 | SET_PSW_F0 (1); | |
3154 | } | |
3155 | else | |
3156 | { | |
3157 | SET_PSW_F0 (0); | |
3158 | } | |
3159 | SET_GPR32 (OP[0], tmp); | |
3160 | trace_output_32 (tmp); | |
3161 | } | |
3162 | ||
3163 | /* subi */ | |
3164 | void | |
3165 | OP_1 () | |
3166 | { | |
3167 | unsigned tmp; | |
3168 | if (OP[1] == 0) | |
3169 | OP[1] = 16; | |
3170 | ||
3171 | trace_input ("subi", OP_REG, OP_CONSTANT16, OP_VOID); | |
3172 | /* see ../common/sim-alu.h for a more extensive discussion on how to | |
3173 | compute the carry/overflow bits. */ | |
3174 | /* since OP[1] is never <= 0, -OP[1] == ~OP[1]+1 can never overflow */ | |
3175 | tmp = ((unsigned)(unsigned16) GPR (OP[0]) | |
3176 | + (unsigned)(unsigned16) ( - OP[1])); | |
3177 | SET_PSW_C (tmp >= (1 << 16)); | |
3178 | SET_GPR (OP[0], tmp); | |
3179 | trace_output_16 (tmp); | |
3180 | } | |
3181 | ||
3182 | /* trap */ | |
3183 | void | |
3184 | OP_5F00 () | |
3185 | { | |
3186 | trace_input ("trap", OP_CONSTANT4, OP_VOID, OP_VOID); | |
3187 | trace_output_void (); | |
3188 | ||
3189 | switch (OP[0]) | |
3190 | { | |
3191 | default: | |
3192 | #if (DEBUG & DEBUG_TRAP) == 0 | |
3193 | { | |
3194 | uint16 vec = OP[0] + TRAP_VECTOR_START; | |
3195 | SET_BPC (PC + 1); | |
3196 | SET_BPSW (PSW); | |
3197 | SET_PSW (PSW & PSW_SM_BIT); | |
3198 | JMP (vec); | |
3199 | break; | |
3200 | } | |
3201 | #else /* if debugging use trap to print registers */ | |
3202 | { | |
3203 | int i; | |
3204 | static int first_time = 1; | |
3205 | ||
3206 | if (first_time) | |
3207 | { | |
3208 | first_time = 0; | |
3209 | (*d10v_callback->printf_filtered) (d10v_callback, "Trap # PC "); | |
3210 | for (i = 0; i < 16; i++) | |
3211 | (*d10v_callback->printf_filtered) (d10v_callback, " %sr%d", (i > 9) ? "" : " ", i); | |
3212 | (*d10v_callback->printf_filtered) (d10v_callback, " a0 a1 f0 f1 c\n"); | |
3213 | } | |
3214 | ||
3215 | (*d10v_callback->printf_filtered) (d10v_callback, "Trap %2d 0x%.4x:", (int)OP[0], (int)PC); | |
3216 | ||
3217 | for (i = 0; i < 16; i++) | |
3218 | (*d10v_callback->printf_filtered) (d10v_callback, " %.4x", (int) GPR (i)); | |
3219 | ||
3220 | for (i = 0; i < 2; i++) | |
3221 | (*d10v_callback->printf_filtered) (d10v_callback, " %.2x%.8lx", | |
3222 | ((int)(ACC (i) >> 32) & 0xff), | |
3223 | ((unsigned long) ACC (i)) & 0xffffffff); | |
3224 | ||
3225 | (*d10v_callback->printf_filtered) (d10v_callback, " %d %d %d\n", | |
3226 | PSW_F0 != 0, PSW_F1 != 0, PSW_C != 0); | |
3227 | (*d10v_callback->flush_stdout) (d10v_callback); | |
3228 | break; | |
3229 | } | |
3230 | #endif | |
3231 | case 15: /* new system call trap */ | |
3232 | /* Trap 15 is used for simulating low-level I/O */ | |
3233 | { | |
3234 | unsigned32 result = 0; | |
3235 | errno = 0; | |
3236 | ||
3237 | /* Registers passed to trap 0 */ | |
3238 | ||
3239 | #define FUNC GPR (4) /* function number */ | |
3240 | #define PARM1 GPR (0) /* optional parm 1 */ | |
3241 | #define PARM2 GPR (1) /* optional parm 2 */ | |
3242 | #define PARM3 GPR (2) /* optional parm 3 */ | |
3243 | #define PARM4 GPR (3) /* optional parm 3 */ | |
3244 | ||
3245 | /* Registers set by trap 0 */ | |
3246 | ||
3247 | #define RETVAL(X) do { result = (X); SET_GPR (0, result); } while (0) | |
3248 | #define RETVAL32(X) do { result = (X); SET_GPR (0, result >> 16); SET_GPR (1, result); } while (0) | |
3249 | #define RETERR(X) SET_GPR (4, (X)) /* return error code */ | |
3250 | ||
3251 | /* Turn a pointer in a register into a pointer into real memory. */ | |
3252 | ||
3253 | #define MEMPTR(x) ((char *)(dmem_addr(x))) | |
3254 | ||
3255 | switch (FUNC) | |
3256 | { | |
3257 | #if !defined(__GO32__) && !defined(_WIN32) | |
3258 | case TARGET_SYS_fork: | |
3259 | trace_input ("<fork>", OP_VOID, OP_VOID, OP_VOID); | |
3260 | RETVAL (fork ()); | |
3261 | trace_output_16 (result); | |
3262 | break; | |
3263 | ||
3264 | #define getpid() 47 | |
3265 | case TARGET_SYS_getpid: | |
3266 | trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID); | |
3267 | RETVAL (getpid ()); | |
3268 | trace_output_16 (result); | |
3269 | break; | |
3270 | ||
3271 | case TARGET_SYS_kill: | |
3272 | trace_input ("<kill>", OP_R0, OP_R1, OP_VOID); | |
3273 | if (PARM1 == getpid ()) | |
3274 | { | |
3275 | trace_output_void (); | |
3276 | State.exception = PARM2; | |
3277 | } | |
3278 | else | |
3279 | { | |
3280 | int os_sig = -1; | |
3281 | switch (PARM2) | |
3282 | { | |
3283 | #ifdef SIGHUP | |
3284 | case 1: os_sig = SIGHUP; break; | |
3285 | #endif | |
3286 | #ifdef SIGINT | |
3287 | case 2: os_sig = SIGINT; break; | |
3288 | #endif | |
3289 | #ifdef SIGQUIT | |
3290 | case 3: os_sig = SIGQUIT; break; | |
3291 | #endif | |
3292 | #ifdef SIGILL | |
3293 | case 4: os_sig = SIGILL; break; | |
3294 | #endif | |
3295 | #ifdef SIGTRAP | |
3296 | case 5: os_sig = SIGTRAP; break; | |
3297 | #endif | |
3298 | #ifdef SIGABRT | |
3299 | case 6: os_sig = SIGABRT; break; | |
3300 | #elif defined(SIGIOT) | |
3301 | case 6: os_sig = SIGIOT; break; | |
3302 | #endif | |
3303 | #ifdef SIGEMT | |
3304 | case 7: os_sig = SIGEMT; break; | |
3305 | #endif | |
3306 | #ifdef SIGFPE | |
3307 | case 8: os_sig = SIGFPE; break; | |
3308 | #endif | |
3309 | #ifdef SIGKILL | |
3310 | case 9: os_sig = SIGKILL; break; | |
3311 | #endif | |
3312 | #ifdef SIGBUS | |
3313 | case 10: os_sig = SIGBUS; break; | |
3314 | #endif | |
3315 | #ifdef SIGSEGV | |
3316 | case 11: os_sig = SIGSEGV; break; | |
3317 | #endif | |
3318 | #ifdef SIGSYS | |
3319 | case 12: os_sig = SIGSYS; break; | |
3320 | #endif | |
3321 | #ifdef SIGPIPE | |
3322 | case 13: os_sig = SIGPIPE; break; | |
3323 | #endif | |
3324 | #ifdef SIGALRM | |
3325 | case 14: os_sig = SIGALRM; break; | |
3326 | #endif | |
3327 | #ifdef SIGTERM | |
3328 | case 15: os_sig = SIGTERM; break; | |
3329 | #endif | |
3330 | #ifdef SIGURG | |
3331 | case 16: os_sig = SIGURG; break; | |
3332 | #endif | |
3333 | #ifdef SIGSTOP | |
3334 | case 17: os_sig = SIGSTOP; break; | |
3335 | #endif | |
3336 | #ifdef SIGTSTP | |
3337 | case 18: os_sig = SIGTSTP; break; | |
3338 | #endif | |
3339 | #ifdef SIGCONT | |
3340 | case 19: os_sig = SIGCONT; break; | |
3341 | #endif | |
3342 | #ifdef SIGCHLD | |
3343 | case 20: os_sig = SIGCHLD; break; | |
3344 | #elif defined(SIGCLD) | |
3345 | case 20: os_sig = SIGCLD; break; | |
3346 | #endif | |
3347 | #ifdef SIGTTIN | |
3348 | case 21: os_sig = SIGTTIN; break; | |
3349 | #endif | |
3350 | #ifdef SIGTTOU | |
3351 | case 22: os_sig = SIGTTOU; break; | |
3352 | #endif | |
3353 | #ifdef SIGIO | |
3354 | case 23: os_sig = SIGIO; break; | |
3355 | #elif defined (SIGPOLL) | |
3356 | case 23: os_sig = SIGPOLL; break; | |
3357 | #endif | |
3358 | #ifdef SIGXCPU | |
3359 | case 24: os_sig = SIGXCPU; break; | |
3360 | #endif | |
3361 | #ifdef SIGXFSZ | |
3362 | case 25: os_sig = SIGXFSZ; break; | |
3363 | #endif | |
3364 | #ifdef SIGVTALRM | |
3365 | case 26: os_sig = SIGVTALRM; break; | |
3366 | #endif | |
3367 | #ifdef SIGPROF | |
3368 | case 27: os_sig = SIGPROF; break; | |
3369 | #endif | |
3370 | #ifdef SIGWINCH | |
3371 | case 28: os_sig = SIGWINCH; break; | |
3372 | #endif | |
3373 | #ifdef SIGLOST | |
3374 | case 29: os_sig = SIGLOST; break; | |
3375 | #endif | |
3376 | #ifdef SIGUSR1 | |
3377 | case 30: os_sig = SIGUSR1; break; | |
3378 | #endif | |
3379 | #ifdef SIGUSR2 | |
3380 | case 31: os_sig = SIGUSR2; break; | |
3381 | #endif | |
3382 | } | |
3383 | ||
3384 | if (os_sig == -1) | |
3385 | { | |
3386 | trace_output_void (); | |
3387 | (*d10v_callback->printf_filtered) (d10v_callback, "Unknown signal %d\n", PARM2); | |
3388 | (*d10v_callback->flush_stdout) (d10v_callback); | |
3389 | State.exception = SIGILL; | |
3390 | } | |
3391 | else | |
3392 | { | |
3393 | RETVAL (kill (PARM1, PARM2)); | |
3394 | trace_output_16 (result); | |
3395 | } | |
3396 | } | |
3397 | break; | |
3398 | ||
3399 | case TARGET_SYS_execve: | |
3400 | trace_input ("<execve>", OP_R0, OP_R1, OP_R2); | |
3401 | RETVAL (execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), | |
3402 | (char **)MEMPTR (PARM3))); | |
3403 | trace_output_16 (result); | |
3404 | break; | |
3405 | ||
3406 | #ifdef TARGET_SYS_execv | |
3407 | case TARGET_SYS_execv: | |
3408 | trace_input ("<execv>", OP_R0, OP_R1, OP_VOID); | |
3409 | RETVAL (execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL)); | |
3410 | trace_output_16 (result); | |
3411 | break; | |
3412 | #endif | |
3413 | ||
3414 | case TARGET_SYS_pipe: | |
3415 | { | |
3416 | reg_t buf; | |
3417 | int host_fd[2]; | |
3418 | ||
3419 | trace_input ("<pipe>", OP_R0, OP_VOID, OP_VOID); | |
3420 | buf = PARM1; | |
3421 | RETVAL (pipe (host_fd)); | |
3422 | SW (buf, host_fd[0]); | |
3423 | buf += sizeof(uint16); | |
3424 | SW (buf, host_fd[1]); | |
3425 | trace_output_16 (result); | |
3426 | } | |
3427 | break; | |
3428 | ||
3429 | #if 0 | |
3430 | #ifdef TARGET_SYS_wait | |
3431 | case TARGET_SYS_wait: | |
3432 | { | |
3433 | int status; | |
3434 | trace_input ("<wait>", OP_R0, OP_VOID, OP_VOID); | |
3435 | RETVAL (wait (&status)); | |
3436 | if (PARM1) | |
3437 | SW (PARM1, status); | |
3438 | trace_output_16 (result); | |
3439 | } | |
3440 | break; | |
3441 | #endif | |
3442 | #endif | |
3443 | #else | |
3444 | case TARGET_SYS_getpid: | |
3445 | trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID); | |
3446 | RETVAL (1); | |
3447 | trace_output_16 (result); | |
3448 | break; | |
3449 | ||
3450 | case TARGET_SYS_kill: | |
3451 | trace_input ("<kill>", OP_REG, OP_REG, OP_VOID); | |
3452 | trace_output_void (); | |
3453 | State.exception = PARM2; | |
3454 | break; | |
3455 | #endif | |
3456 | ||
3457 | case TARGET_SYS_read: | |
3458 | trace_input ("<read>", OP_R0, OP_R1, OP_R2); | |
3459 | RETVAL (d10v_callback->read (d10v_callback, PARM1, MEMPTR (PARM2), | |
3460 | PARM3)); | |
3461 | trace_output_16 (result); | |
3462 | break; | |
3463 | ||
3464 | case TARGET_SYS_write: | |
3465 | trace_input ("<write>", OP_R0, OP_R1, OP_R2); | |
3466 | if (PARM1 == 1) | |
3467 | RETVAL ((int)d10v_callback->write_stdout (d10v_callback, | |
3468 | MEMPTR (PARM2), PARM3)); | |
3469 | else | |
3470 | RETVAL ((int)d10v_callback->write (d10v_callback, PARM1, | |
3471 | MEMPTR (PARM2), PARM3)); | |
3472 | trace_output_16 (result); | |
3473 | break; | |
3474 | ||
3475 | case TARGET_SYS_lseek: | |
3476 | trace_input ("<lseek>", OP_R0, OP_R1, OP_R2); | |
3477 | RETVAL32 (d10v_callback->lseek (d10v_callback, PARM1, | |
3478 | ((((unsigned long) PARM2) << 16) | |
3479 | || (unsigned long) PARM3), | |
3480 | PARM4)); | |
3481 | trace_output_32 (result); | |
3482 | break; | |
3483 | ||
3484 | case TARGET_SYS_close: | |
3485 | trace_input ("<close>", OP_R0, OP_VOID, OP_VOID); | |
3486 | RETVAL (d10v_callback->close (d10v_callback, PARM1)); | |
3487 | trace_output_16 (result); | |
3488 | break; | |
3489 | ||
3490 | case TARGET_SYS_open: | |
3491 | trace_input ("<open>", OP_R0, OP_R1, OP_R2); | |
3492 | RETVAL (d10v_callback->open (d10v_callback, MEMPTR (PARM1), PARM2)); | |
3493 | trace_output_16 (result); | |
3494 | break; | |
3495 | ||
3496 | case TARGET_SYS_exit: | |
3497 | trace_input ("<exit>", OP_R0, OP_VOID, OP_VOID); | |
3498 | State.exception = SIG_D10V_EXIT; | |
3499 | trace_output_void (); | |
3500 | break; | |
3501 | ||
7a292a7a | 3502 | #ifdef TARGET_SYS_stat |
c906108c SS |
3503 | case TARGET_SYS_stat: |
3504 | trace_input ("<stat>", OP_R0, OP_R1, OP_VOID); | |
3505 | /* stat system call */ | |
3506 | { | |
3507 | struct stat host_stat; | |
3508 | reg_t buf; | |
3509 | ||
3510 | RETVAL (stat (MEMPTR (PARM1), &host_stat)); | |
3511 | ||
3512 | buf = PARM2; | |
3513 | ||
3514 | /* The hard-coded offsets and sizes were determined by using | |
3515 | * the D10V compiler on a test program that used struct stat. | |
3516 | */ | |
3517 | SW (buf, host_stat.st_dev); | |
3518 | SW (buf+2, host_stat.st_ino); | |
3519 | SW (buf+4, host_stat.st_mode); | |
3520 | SW (buf+6, host_stat.st_nlink); | |
3521 | SW (buf+8, host_stat.st_uid); | |
3522 | SW (buf+10, host_stat.st_gid); | |
3523 | SW (buf+12, host_stat.st_rdev); | |
3524 | SLW (buf+16, host_stat.st_size); | |
3525 | SLW (buf+20, host_stat.st_atime); | |
3526 | SLW (buf+28, host_stat.st_mtime); | |
3527 | SLW (buf+36, host_stat.st_ctime); | |
3528 | } | |
3529 | trace_output_16 (result); | |
3530 | break; | |
7a292a7a | 3531 | #endif |
c906108c SS |
3532 | |
3533 | case TARGET_SYS_chown: | |
3534 | trace_input ("<chown>", OP_R0, OP_R1, OP_R2); | |
3535 | RETVAL (chown (MEMPTR (PARM1), PARM2, PARM3)); | |
3536 | trace_output_16 (result); | |
3537 | break; | |
3538 | ||
3539 | case TARGET_SYS_chmod: | |
3540 | trace_input ("<chmod>", OP_R0, OP_R1, OP_R2); | |
3541 | RETVAL (chmod (MEMPTR (PARM1), PARM2)); | |
3542 | trace_output_16 (result); | |
3543 | break; | |
3544 | ||
3545 | #if 0 | |
3546 | #ifdef TARGET_SYS_utime | |
3547 | case TARGET_SYS_utime: | |
3548 | trace_input ("<utime>", OP_R0, OP_R1, OP_R2); | |
3549 | /* Cast the second argument to void *, to avoid type mismatch | |
3550 | if a prototype is present. */ | |
3551 | RETVAL (utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2))); | |
3552 | trace_output_16 (result); | |
3553 | break; | |
3554 | #endif | |
3555 | #endif | |
3556 | ||
3557 | #if 0 | |
3558 | #ifdef TARGET_SYS_time | |
3559 | case TARGET_SYS_time: | |
3560 | trace_input ("<time>", OP_R0, OP_R1, OP_R2); | |
3561 | RETVAL32 (time (PARM1 ? MEMPTR (PARM1) : NULL)); | |
3562 | trace_output_32 (result); | |
3563 | break; | |
3564 | #endif | |
3565 | #endif | |
3566 | ||
3567 | default: | |
3568 | d10v_callback->error (d10v_callback, "Unknown syscall %d", FUNC); | |
3569 | } | |
3570 | if ((uint16) result == (uint16) -1) | |
3571 | RETERR (d10v_callback->get_errno(d10v_callback)); | |
3572 | else | |
3573 | RETERR (0); | |
3574 | break; | |
3575 | } | |
3576 | } | |
3577 | } | |
3578 | ||
3579 | /* tst0i */ | |
3580 | void | |
3581 | OP_7000000 () | |
3582 | { | |
3583 | trace_input ("tst0i", OP_REG, OP_CONSTANT16, OP_VOID); | |
3584 | SET_PSW_F1 (PSW_F0);; | |
3585 | SET_PSW_F0 ((GPR (OP[0]) & OP[1]) ? 1 : 0); | |
3586 | trace_output_flag (); | |
3587 | } | |
3588 | ||
3589 | /* tst1i */ | |
3590 | void | |
3591 | OP_F000000 () | |
3592 | { | |
3593 | trace_input ("tst1i", OP_REG, OP_CONSTANT16, OP_VOID); | |
3594 | SET_PSW_F1 (PSW_F0); | |
3595 | SET_PSW_F0 ((~(GPR (OP[0])) & OP[1]) ? 1 : 0); | |
3596 | trace_output_flag (); | |
3597 | } | |
3598 | ||
3599 | /* wait */ | |
3600 | void | |
3601 | OP_5F80 () | |
3602 | { | |
3603 | trace_input ("wait", OP_VOID, OP_VOID, OP_VOID); | |
3604 | SET_PSW_IE (1); | |
3605 | trace_output_void (); | |
3606 | } | |
3607 | ||
3608 | /* xor */ | |
3609 | void | |
3610 | OP_A00 () | |
3611 | { | |
3612 | int16 tmp; | |
3613 | trace_input ("xor", OP_REG, OP_REG, OP_VOID); | |
3614 | tmp = (GPR (OP[0]) ^ GPR (OP[1])); | |
3615 | SET_GPR (OP[0], tmp); | |
3616 | trace_output_16 (tmp); | |
3617 | } | |
3618 | ||
3619 | /* xor3 */ | |
3620 | void | |
3621 | OP_5000000 () | |
3622 | { | |
3623 | int16 tmp; | |
3624 | trace_input ("xor3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16); | |
3625 | tmp = (GPR (OP[1]) ^ OP[2]); | |
3626 | SET_GPR (OP[0], tmp); | |
3627 | trace_output_16 (tmp); | |
3628 | } |