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Don't abort() when system call is unknown.
[deliverable/binutils-gdb.git] / sim / d10v / simops.c
CommitLineData
fd435e9f
MM		 1#include "config.h"
2
4f425a32 3#include <signal.h>
63a91cfb
MM		 4#include <errno.h>
5#include <sys/types.h>
6#include <sys/stat.h>
fd435e9f 7#ifdef HAVE_UNISTD_H
63a91cfb 8#include <unistd.h>
fd435e9f 9#endif
63a91cfb 10
2934d1c9
MH		 11#include "d10v_sim.h"
12#include "simops.h"
8719be26 13#include "sys/syscall.h"
2934d1c9 14
c422ecc7
MH		 15extern char *strrchr ();
16
87178dbd
MM		 17enum op_types {
18 OP_VOID,
19 OP_REG,
20 OP_REG_OUTPUT,
21 OP_DREG,
22 OP_DREG_OUTPUT,
23 OP_ACCUM,
24 OP_ACCUM_OUTPUT,
25 OP_ACCUM_REVERSE,
26 OP_CR,
27 OP_CR_OUTPUT,
28 OP_CR_REVERSE,
29 OP_FLAG,
60fc5b72 30 OP_FLAG_OUTPUT,
87178dbd 31 OP_CONSTANT16,
a18cb100 32 OP_CONSTANT8,
87178dbd
MM		 33 OP_CONSTANT3,
34 OP_CONSTANT4,
35 OP_MEMREF,
36 OP_MEMREF2,
37 OP_POSTDEC,
38 OP_POSTINC,
a18cb100 39 OP_PREDEC,
8831cb01
MM		 40 OP_R0,
41 OP_R1,
a18cb100 42 OP_R2,
8831cb01 43 OP_R0R1
87178dbd
MM		 44};
45
bc6df23d
AC		 46
47void
48move_to_cr (int cr, reg_t val)
49{
50 switch (cr)
51 {
52 case PSW_CR:
53 State.SM = (val & PSW_SM_BIT) != 0;
54 State.EA = (val & PSW_EA_BIT) != 0;
55 State.DB = (val & PSW_DB_BIT) != 0;
56 State.DM = (val & PSW_DM_BIT) != 0;
57 State.IE = (val & PSW_IE_BIT) != 0;
58 State.RP = (val & PSW_RP_BIT) != 0;
59 State.MD = (val & PSW_MD_BIT) != 0;
60 State.FX = (val & PSW_FX_BIT) != 0;
61 State.ST = (val & PSW_ST_BIT) != 0;
62 State.F0 = (val & PSW_F0_BIT) != 0;
63 State.F1 = (val & PSW_F1_BIT) != 0;
64 State.C = (val & PSW_C_BIT) != 0;
65 if (State.ST && !State.FX)
66 {
67 (*d10v_callback->printf_filtered)
68 (d10v_callback,
69 "ERROR at PC 0x%x: ST can only be set when FX is set.\n",
70 PC<<2);
71 State.exception = SIGILL;
72 }
19431a02 73 State.cregs[cr] = (val & ~0x4032);
bc6df23d
AC		 74 break;
75 case BPSW_CR:
19431a02
AC		 76 case DPSW_CR:
77 State.cregs[cr] = (val & ~0x4032);
bc6df23d
AC		 78 break;
79 case MOD_S_CR:
80 case MOD_E_CR:
81 State.cregs[cr] = (val & ~0x1);
82 break;
83 default:
84 State.cregs[cr] = val;
85 break;
86 }
87}
88
89reg_t
90move_from_cr (int cr)
91{
92 reg_t val = 0;
93 switch (cr)
94 {
95 case PSW_CR:
96 if (State.SM) val |= PSW_SM_BIT;
97 if (State.EA) val |= PSW_EA_BIT;
98 if (State.DB) val |= PSW_DB_BIT;
99 if (State.DM) val |= PSW_DM_BIT;
100 if (State.IE) val |= PSW_IE_BIT;
101 if (State.RP) val |= PSW_RP_BIT;
102 if (State.MD) val |= PSW_MD_BIT;
103 if (State.FX) val |= PSW_FX_BIT;
104 if (State.ST) val |= PSW_ST_BIT;
105 if (State.F0) val |= PSW_F0_BIT;
106 if (State.F1) val |= PSW_F1_BIT;
107 if (State.C) val |= PSW_C_BIT;
108 break;
109 default:
110 val = State.cregs[cr];
111 break;
112 }
113 return val;
114}
115
116
7eebfc62 117#ifdef DEBUG
a49a15ad
MM		 118static void trace_input_func PARAMS ((char *name,
119 enum op_types in1,
120 enum op_types in2,
121 enum op_types in3));
87178dbd 122
a49a15ad
MM		 123#define trace_input(name, in1, in2, in3) do { if (d10v_debug) trace_input_func (name, in1, in2, in3); } while (0)
124
125static void trace_output_func PARAMS ((enum op_types result));
126
127#define trace_output(result) do { if (d10v_debug) trace_output_func (result); } while (0)
128
87178dbd 129#ifndef SIZE_INSTRUCTION
a49a15ad 130#define SIZE_INSTRUCTION 8
87178dbd
MM		 131#endif
132
133#ifndef SIZE_OPERANDS
a49a15ad 134#define SIZE_OPERANDS 18
87178dbd
MM		 135#endif
136
137#ifndef SIZE_VALUES
138#define SIZE_VALUES 13
139#endif
140
a49a15ad
MM		 141#ifndef SIZE_LOCATION
142#define SIZE_LOCATION 20
143#endif
144
891513ee
MM		 145#ifndef SIZE_PC
146#define SIZE_PC 6
147#endif
148
149#ifndef SIZE_LINE_NUMBER
150#define SIZE_LINE_NUMBER 4
151#endif
152
87178dbd 153static void
a49a15ad 154trace_input_func (name, in1, in2, in3)
87178dbd
MM		 155 char *name;
156 enum op_types in1;
157 enum op_types in2;
158 enum op_types in3;
159{
160 char *comma;
161 enum op_types in[3];
162 int i;
a49a15ad 163 char buf[1024];
87178dbd
MM		 164 char *p;
165 long tmp;
166 char *type;
a49a15ad
MM		 167 const char *filename;
168 const char *functionname;
169 unsigned int linenumber;
170 bfd_vma byte_pc;
87178dbd 171
7eebfc62
MM		 172 if ((d10v_debug & DEBUG_TRACE) == 0)
173 return;
174
87178dbd
MM		 175 switch (State.ins_type)
176 {
177 default:
178 case INS_UNKNOWN: type = " ?"; break;
179 case INS_LEFT: type = " L"; break;
180 case INS_RIGHT: type = " R"; break;
181 case INS_LEFT_PARALLEL: type = "*L"; break;
182 case INS_RIGHT_PARALLEL: type = "*R"; break;
c422ecc7
MH		 183 case INS_LEFT_COND_TEST: type = "?L"; break;
184 case INS_RIGHT_COND_TEST: type = "?R"; break;
185 case INS_LEFT_COND_EXE: type = "&L"; break;
186 case INS_RIGHT_COND_EXE: type = "&R"; break;
87178dbd
MM		 187 case INS_LONG: type = " B"; break;
188 }
189
a49a15ad
MM		 190 if ((d10v_debug & DEBUG_LINE_NUMBER) == 0)
191 (*d10v_callback->printf_filtered) (d10v_callback,
f061ddf6 192 "0x%.*x %s: %-*s ",
891513ee
MM		 193 SIZE_PC, (unsigned)PC,
194 type,
a49a15ad
MM		 195 SIZE_INSTRUCTION, name);
196
197 else
198 {
891513ee 199 buf[0] = '\0';
b30cdd35 200 byte_pc = decode_pc ();
a49a15ad
MM		 201 if (text && byte_pc >= text_start && byte_pc < text_end)
202 {
203 filename = (const char *)0;
204 functionname = (const char *)0;
205 linenumber = 0;
b83093ff 206 if (bfd_find_nearest_line (prog_bfd, text, (struct symbol_cache_entry **)0, byte_pc - text_start,
a49a15ad
MM		 207 &filename, &functionname, &linenumber))
208 {
209 p = buf;
210 if (linenumber)
211 {
891513ee 212 sprintf (p, "#%-*d ", SIZE_LINE_NUMBER, linenumber);
a49a15ad
MM		 213 p += strlen (p);
214 }
891513ee
MM		 215 else
216 {
217 sprintf (p, "%-*s ", SIZE_LINE_NUMBER+1, "---");
218 p += SIZE_LINE_NUMBER+2;
219 }
a49a15ad
MM		 220
221 if (functionname)
222 {
223 sprintf (p, "%s ", functionname);
224 p += strlen (p);
225 }
226 else if (filename)
227 {
c422ecc7 228 char *q = strrchr (filename, '/');
a49a15ad
MM		 229 sprintf (p, "%s ", (q) ? q+1 : filename);
230 p += strlen (p);
231 }
232
233 if (*p == ' ')
234 *p = '\0';
235 }
236 }
237
238 (*d10v_callback->printf_filtered) (d10v_callback,
f061ddf6 239 "0x%.*x %s: %-*.*s %-*s ",
891513ee
MM		 240 SIZE_PC, (unsigned)PC,
241 type,
a49a15ad
MM		 242 SIZE_LOCATION, SIZE_LOCATION, buf,
243 SIZE_INSTRUCTION, name);
244 }
87178dbd
MM		 245
246 in[0] = in1;
247 in[1] = in2;
248 in[2] = in3;
249 comma = "";
250 p = buf;
251 for (i = 0; i < 3; i++)
252 {
253 switch (in[i])
254 {
255 case OP_VOID:
8831cb01
MM		 256 case OP_R0:
257 case OP_R1:
a18cb100 258 case OP_R2:
8831cb01 259 case OP_R0R1:
87178dbd
MM		 260 break;
261
262 case OP_REG:
263 case OP_REG_OUTPUT:
264 case OP_DREG:
265 case OP_DREG_OUTPUT:
266 sprintf (p, "%sr%d", comma, OP[i]);
267 p += strlen (p);
268 comma = ",";
269 break;
270
271 case OP_CR:
272 case OP_CR_OUTPUT:
273 case OP_CR_REVERSE:
274 sprintf (p, "%scr%d", comma, OP[i]);
275 p += strlen (p);
276 comma = ",";
277 break;
278
279 case OP_ACCUM:
280 case OP_ACCUM_OUTPUT:
281 case OP_ACCUM_REVERSE:
282 sprintf (p, "%sa%d", comma, OP[i]);
283 p += strlen (p);
284 comma = ",";
285 break;
286
287 case OP_CONSTANT16:
288 sprintf (p, "%s%d", comma, OP[i]);
289 p += strlen (p);
290 comma = ",";
291 break;
292
a18cb100
MM		 293 case OP_CONSTANT8:
294 sprintf (p, "%s%d", comma, SEXT8(OP[i]));
295 p += strlen (p);
296 comma = ",";
297 break;
298
87178dbd
MM		 299 case OP_CONSTANT4:
300 sprintf (p, "%s%d", comma, SEXT4(OP[i]));
301 p += strlen (p);
302 comma = ",";
303 break;
304
305 case OP_CONSTANT3:
306 sprintf (p, "%s%d", comma, SEXT3(OP[i]));
307 p += strlen (p);
308 comma = ",";
309 break;
310
311 case OP_MEMREF:
312 sprintf (p, "%s@r%d", comma, OP[i]);
313 p += strlen (p);
314 comma = ",";
315 break;
316
317 case OP_MEMREF2:
318 sprintf (p, "%s@(%d,r%d)", comma, (int16)OP[i], OP[i+1]);
319 p += strlen (p);
320 comma = ",";
321 break;
322
323 case OP_POSTINC:
324 sprintf (p, "%s@r%d+", comma, OP[i]);
325 p += strlen (p);
326 comma = ",";
327 break;
328
329 case OP_POSTDEC:
330 sprintf (p, "%s@r%d-", comma, OP[i]);
331 p += strlen (p);
332 comma = ",";
333 break;
334
335 case OP_PREDEC:
336 sprintf (p, "%s@-r%d", comma, OP[i]);
337 p += strlen (p);
338 comma = ",";
339 break;
340
341 case OP_FLAG:
60fc5b72 342 case OP_FLAG_OUTPUT:
87178dbd
MM		 343 if (OP[i] == 0)
344 sprintf (p, "%sf0", comma);
345
346 else if (OP[i] == 1)
347 sprintf (p, "%sf1", comma);
348
349 else
60fc5b72 350 sprintf (p, "%sc", comma);
87178dbd
MM		 351
352 p += strlen (p);
353 comma = ",";
354 break;
355 }
356 }
357
7eebfc62
MM		 358 if ((d10v_debug & DEBUG_VALUES) == 0)
359 {
360 *p++ = '\n';
361 *p = '\0';
362 (*d10v_callback->printf_filtered) (d10v_callback, "%s", buf);
363 }
364 else
365 {
366 *p = '\0';
367 (*d10v_callback->printf_filtered) (d10v_callback, "%-*s", SIZE_OPERANDS, buf);
87178dbd 368
7eebfc62
MM		 369 p = buf;
370 for (i = 0; i < 3; i++)
371 {
372 buf[0] = '\0';
373 switch (in[i])
374 {
375 case OP_VOID:
376 (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "");
377 break;
378
379 case OP_REG_OUTPUT:
380 case OP_DREG_OUTPUT:
381 case OP_CR_OUTPUT:
382 case OP_ACCUM_OUTPUT:
60fc5b72 383 case OP_FLAG_OUTPUT:
7eebfc62
MM		 384 (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "---");
385 break;
386
387 case OP_REG:
388 case OP_MEMREF:
389 case OP_POSTDEC:
390 case OP_POSTINC:
391 case OP_PREDEC:
392 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
393 (uint16)State.regs[OP[i]]);
394 break;
395
396 case OP_DREG:
397 tmp = (long)((((uint32) State.regs[OP[i]]) << 16) | ((uint32) State.regs[OP[i]+1]));
398 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.8lx", SIZE_VALUES-10, "", tmp);
399 break;
400
401 case OP_CR:
402 case OP_CR_REVERSE:
403 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
404 (uint16)State.cregs[OP[i]]);
405 break;
406
407 case OP_ACCUM:
408 case OP_ACCUM_REVERSE:
409 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.2x%.8lx", SIZE_VALUES-12, "",
410 ((int)(State.a[OP[i]] >> 32) & 0xff),
411 ((unsigned long)State.a[OP[i]]) & 0xffffffff);
412 break;
413
414 case OP_CONSTANT16:
415 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
416 (uint16)OP[i]);
417 break;
418
419 case OP_CONSTANT4:
420 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
421 (uint16)SEXT4(OP[i]));
422 break;
423
a18cb100
MM		 424 case OP_CONSTANT8:
425 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
426 (uint16)SEXT8(OP[i]));
427 break;
428
7eebfc62
MM		 429 case OP_CONSTANT3:
430 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
431 (uint16)SEXT3(OP[i]));
432 break;
433
434 case OP_FLAG:
435 if (OP[i] == 0)
436 (*d10v_callback->printf_filtered) (d10v_callback, "%*sF0 = %d", SIZE_VALUES-6, "",
437 State.F0 != 0);
438
439 else if (OP[i] == 1)
440 (*d10v_callback->printf_filtered) (d10v_callback, "%*sF1 = %d", SIZE_VALUES-6, "",
441 State.F1 != 0);
442
443 else
444 (*d10v_callback->printf_filtered) (d10v_callback, "%*sC = %d", SIZE_VALUES-5, "",
445 State.C != 0);
446
447 break;
448
449 case OP_MEMREF2:
450 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
451 (uint16)OP[i]);
452 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
453 (uint16)State.regs[OP[++i]]);
454 break;
a18cb100 455
8831cb01 456 case OP_R0:
a18cb100 457 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
8831cb01 458 (uint16)State.regs[0]);
a18cb100
MM		 459 break;
460
8831cb01 461 case OP_R1:
a18cb100 462 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
8831cb01 463 (uint16)State.regs[1]);
a18cb100 464 break;
8918b3a7 465
8831cb01 466 case OP_R2:
8918b3a7 467 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
8831cb01 468 (uint16)State.regs[2]);
8918b3a7 469 break;
c422ecc7 470
8831cb01 471 case OP_R0R1:
c422ecc7 472 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
8831cb01 473 (uint16)State.regs[0]);
c422ecc7 474 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
8831cb01 475 (uint16)State.regs[1]);
c422ecc7
MH		 476 i++;
477 break;
7eebfc62
MM		 478 }
479 }
480 }
fd435e9f
MM		 481
482 (*d10v_callback->flush_stdout) (d10v_callback);
7eebfc62 483}
87178dbd 484
7eebfc62 485static void
a49a15ad 486trace_output_func (result)
7eebfc62
MM		 487 enum op_types result;
488{
489 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
87178dbd 490 {
7eebfc62 491 long tmp;
87178dbd 492
7eebfc62
MM		 493 switch (result)
494 {
495 default:
496 putchar ('\n');
87178dbd
MM		 497 break;
498
499 case OP_REG:
7eebfc62
MM		 500 case OP_REG_OUTPUT:
501 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
502 (uint16)State.regs[OP[0]],
503 State.F0 != 0, State.F1 != 0, State.C != 0);
87178dbd
MM		 504 break;
505
506 case OP_DREG:
7eebfc62
MM		 507 case OP_DREG_OUTPUT:
508 tmp = (long)((((uint32) State.regs[OP[0]]) << 16) | ((uint32) State.regs[OP[0]+1]));
509 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-10, "", tmp,
510 State.F0 != 0, State.F1 != 0, State.C != 0);
87178dbd
MM		 511 break;
512
513 case OP_CR:
7eebfc62
MM		 514 case OP_CR_OUTPUT:
515 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
516 (uint16)State.cregs[OP[0]],
517 State.F0 != 0, State.F1 != 0, State.C != 0);
87178dbd
MM		 518 break;
519
7eebfc62
MM		 520 case OP_CR_REVERSE:
521 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
522 (uint16)State.cregs[OP[1]],
523 State.F0 != 0, State.F1 != 0, State.C != 0);
87178dbd
MM		 524 break;
525
7eebfc62
MM		 526 case OP_ACCUM:
527 case OP_ACCUM_OUTPUT:
069398aa 528 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-12, "",
7eebfc62
MM		 529 ((int)(State.a[OP[0]] >> 32) & 0xff),
530 ((unsigned long)State.a[OP[0]]) & 0xffffffff,
531 State.F0 != 0, State.F1 != 0, State.C != 0);
87178dbd
MM		 532 break;
533
7eebfc62 534 case OP_ACCUM_REVERSE:
069398aa 535 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-12, "",
7eebfc62
MM		 536 ((int)(State.a[OP[1]] >> 32) & 0xff),
537 ((unsigned long)State.a[OP[1]]) & 0xffffffff,
538 State.F0 != 0, State.F1 != 0, State.C != 0);
87178dbd
MM		 539 break;
540
541 case OP_FLAG:
60fc5b72 542 case OP_FLAG_OUTPUT:
7eebfc62
MM		 543 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s F0=%d F1=%d C=%d\n", SIZE_VALUES, "",
544 State.F0 != 0, State.F1 != 0, State.C != 0);
87178dbd 545 break;
8918b3a7 546
8831cb01 547 case OP_R0:
8918b3a7 548 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
8831cb01 549 (uint16)State.regs[0],
8918b3a7
MM		 550 State.F0 != 0, State.F1 != 0, State.C != 0);
551 break;
552
8831cb01 553 case OP_R0R1:
8918b3a7 554 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-10, "",
8831cb01 555 (uint16)State.regs[0], (uint16)State.regs[1],
8918b3a7
MM		 556 State.F0 != 0, State.F1 != 0, State.C != 0);
557 break;
87178dbd
MM		 558 }
559 }
fd435e9f
MM		 560
561 (*d10v_callback->flush_stdout) (d10v_callback);
87178dbd
MM		 562}
563
564#else
565#define trace_input(NAME, IN1, IN2, IN3)
566#define trace_output(RESULT)
567#endif
2934d1c9
MH		 568
569/* abs */
570void
571OP_4607 ()
572{
87178dbd 573 trace_input ("abs", OP_REG, OP_VOID, OP_VOID);
2934d1c9
MH		 574 State.F1 = State.F0;
575 if ((int16)(State.regs[OP[0]]) < 0)
576 {
577 State.regs[OP[0]] = -(int16)(State.regs[OP[0]]);
578 State.F0 = 1;
579 }
580 else
581 State.F0 = 0;
87178dbd 582 trace_output (OP_REG);
2934d1c9
MH		 583}
584
585/* abs */
586void
587OP_5607 ()
588{
589 int64 tmp;
590
87178dbd 591 trace_input ("abs", OP_ACCUM, OP_VOID, OP_VOID);
4f425a32
MH		 592 State.F1 = State.F0;
593 State.a[OP[0]] = SEXT40(State.a[OP[0]]);
594
4c38885c 595 if (State.a[OP[0]] < 0 )
2934d1c9 596 {
4c38885c 597 tmp = -State.a[OP[0]];
2934d1c9
MH		 598 if (State.ST)
599 {
4c38885c 600 if (tmp > MAX32)
2934d1c9 601 State.a[OP[0]] = MAX32;
4c38885c 602 else if (tmp < MIN32)
2934d1c9
MH		 603 State.a[OP[0]] = MIN32;
604 else
4f425a32 605 State.a[OP[0]] = tmp & MASK40;
2934d1c9
MH		 606 }
607 else
4f425a32 608 State.a[OP[0]] = tmp & MASK40;
2934d1c9
MH		 609 State.F0 = 1;
610 }
611 else
612 State.F0 = 0;
87178dbd 613 trace_output (OP_ACCUM);
2934d1c9
MH		 614}
615
616/* add */
617void
618OP_200 ()
619{
620 uint16 tmp = State.regs[OP[0]];
87178dbd 621 trace_input ("add", OP_REG, OP_REG, OP_VOID);
2934d1c9
MH		 622 State.regs[OP[0]] += State.regs[OP[1]];
623 if ( tmp > State.regs[OP[0]])
624 State.C = 1;
625 else
626 State.C = 0;
87178dbd 627 trace_output (OP_REG);
2934d1c9
MH		 628}
629
630/* add */
631void
632OP_1201 ()
633{
4c38885c 634 int64 tmp;
4f425a32 635 tmp = SEXT40(State.a[OP[0]]) + (SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]);
87178dbd
MM		 636
637 trace_input ("add", OP_ACCUM, OP_REG, OP_VOID);
4c38885c
MH		 638 if (State.ST)
639 {
640 if ( tmp > MAX32)
641 State.a[OP[0]] = MAX32;
642 else if ( tmp < MIN32)
643 State.a[OP[0]] = MIN32;
644 else
4f425a32 645 State.a[OP[0]] = tmp & MASK40;
4c38885c
MH		 646 }
647 else
4f425a32 648 State.a[OP[0]] = tmp & MASK40;
87178dbd 649 trace_output (OP_ACCUM);
2934d1c9
MH		 650}
651
652/* add */
653void
654OP_1203 ()
655{
4c38885c 656 int64 tmp;
4f425a32 657 tmp = SEXT40(State.a[OP[0]]) + SEXT40(State.a[OP[1]]);
87178dbd
MM		 658
659 trace_input ("add", OP_ACCUM, OP_ACCUM, OP_VOID);
4c38885c
MH		 660 if (State.ST)
661 {
662 if (tmp > MAX32)
663 State.a[OP[0]] = MAX32;
664 else if ( tmp < MIN32)
665 State.a[OP[0]] = MIN32;
666 else
4f425a32 667 State.a[OP[0]] = tmp & MASK40;
4c38885c
MH		 668 }
669 else
4f425a32 670 State.a[OP[0]] = tmp & MASK40;
87178dbd 671 trace_output (OP_ACCUM);
2934d1c9
MH		 672}
673
674/* add2w */
675void
676OP_1200 ()
677{
678 uint32 tmp;
f4b022d3
MM		 679 uint32 a = (State.regs[OP[0]]) << 16 | State.regs[OP[0]+1];
680 uint32 b = (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
87178dbd
MM		 681
682 trace_input ("add2w", OP_DREG, OP_DREG, OP_VOID);
f4b022d3
MM		 683 tmp = a + b;
684 State.C = (tmp < a);
2934d1c9
MH		 685 State.regs[OP[0]] = tmp >> 16;
686 State.regs[OP[0]+1] = tmp & 0xFFFF;
87178dbd 687 trace_output (OP_DREG);
2934d1c9
MH		 688}
689
690/* add3 */
691void
692OP_1000000 ()
693{
f4b022d3
MM		 694 uint16 tmp = State.regs[OP[1]];
695 State.regs[OP[0]] = tmp + OP[2];
87178dbd
MM		 696
697 trace_input ("add3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
f4b022d3 698 State.C = (State.regs[OP[0]] < tmp);
87178dbd 699 trace_output (OP_REG);
2934d1c9
MH		 700}
701
702/* addac3 */
703void
704OP_17000200 ()
705{
4c38885c 706 int64 tmp;
4f425a32 707 tmp = SEXT40(State.a[OP[2]]) + SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
87178dbd
MM		 708
709 trace_input ("addac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
4c38885c
MH		 710 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
711 State.regs[OP[0]+1] = tmp & 0xffff;
87178dbd 712 trace_output (OP_DREG);
2934d1c9
MH		 713}
714
715/* addac3 */
716void
717OP_17000202 ()
718{
4c38885c 719 int64 tmp;
4f425a32 720 tmp = SEXT40(State.a[OP[1]]) + SEXT40(State.a[OP[2]]);
87178dbd
MM		 721
722 trace_input ("addac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
4c38885c
MH		 723 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
724 State.regs[OP[0]+1] = tmp & 0xffff;
87178dbd 725 trace_output (OP_DREG);
2934d1c9
MH		 726}
727
728/* addac3s */
729void
730OP_17001200 ()
731{
4c38885c 732 int64 tmp;
4c38885c 733 State.F1 = State.F0;
87178dbd
MM		 734
735 trace_input ("addac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
4f425a32 736 tmp = SEXT40(State.a[OP[2]]) + SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
4c38885c
MH		 737 if ( tmp > MAX32)
738 {
739 State.regs[OP[0]] = 0x7fff;
740 State.regs[OP[0]+1] = 0xffff;
741 State.F0 = 1;
742 }
743 else if (tmp < MIN32)
744 {
745 State.regs[OP[0]] = 0x8000;
746 State.regs[OP[0]+1] = 0;
747 State.F0 = 1;
748 }
749 else
750 {
751 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
752 State.regs[OP[0]+1] = tmp & 0xffff;
753 State.F0 = 0;
754 }
87178dbd 755 trace_output (OP_DREG);
2934d1c9
MH		 756}
757
758/* addac3s */
759void
760OP_17001202 ()
761{
4c38885c 762 int64 tmp;
4c38885c 763 State.F1 = State.F0;
87178dbd
MM		 764
765 trace_input ("addac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
4f425a32 766 tmp = SEXT40(State.a[OP[1]]) + SEXT40(State.a[OP[2]]);
4c38885c
MH		 767 if ( tmp > MAX32)
768 {
769 State.regs[OP[0]] = 0x7fff;
770 State.regs[OP[0]+1] = 0xffff;
771 State.F0 = 1;
772 }
773 else if (tmp < MIN32)
774 {
775 State.regs[OP[0]] = 0x8000;
776 State.regs[OP[0]+1] = 0;
777 State.F0 = 1;
778 }
779 else
780 {
781 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
782 State.regs[OP[0]+1] = tmp & 0xffff;
783 State.F0 = 0;
784 }
87178dbd 785 trace_output (OP_DREG);
2934d1c9
MH		 786}
787
788/* addi */
789void
790OP_201 ()
791{
2254cd90 792 uint tmp = State.regs[OP[0]];
4f425a32
MH		 793 if (OP[1] == 0)
794 OP[1] = 16;
f4b022d3 795
87178dbd 796 trace_input ("addi", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 797 State.regs[OP[0]] += OP[1];
f4b022d3 798 State.C = (State.regs[OP[0]] < tmp);
87178dbd 799 trace_output (OP_REG);
2934d1c9
MH		 800}
801
802/* and */
803void
804OP_C00 ()
805{
87178dbd 806 trace_input ("and", OP_REG, OP_REG, OP_VOID);
2934d1c9 807 State.regs[OP[0]] &= State.regs[OP[1]];
87178dbd 808 trace_output (OP_REG);
2934d1c9
MH		 809}
810
811/* and3 */
812void
813OP_6000000 ()
814{
87178dbd 815 trace_input ("and3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
2934d1c9 816 State.regs[OP[0]] = State.regs[OP[1]] & OP[2];
87178dbd 817 trace_output (OP_REG);
2934d1c9
MH		 818}
819
820/* bclri */
821void
822OP_C01 ()
823{
87178dbd 824 trace_input ("bclri", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 825 State.regs[OP[0]] &= ~(0x8000 >> OP[1]);
87178dbd 826 trace_output (OP_REG);
2934d1c9
MH		 827}
828
829/* bl.s */
830void
831OP_4900 ()
832{
8831cb01 833 trace_input ("bl.s", OP_CONSTANT8, OP_R0, OP_R1);
2934d1c9 834 State.regs[13] = PC+1;
fd435e9f 835 JMP( PC + SEXT8 (OP[0]));
87178dbd 836 trace_output (OP_VOID);
2934d1c9
MH		 837}
838
839/* bl.l */
840void
841OP_24800000 ()
842{
8831cb01 843 trace_input ("bl.l", OP_CONSTANT16, OP_R0, OP_R1);
2934d1c9 844 State.regs[13] = PC+1;
fd435e9f 845 JMP (PC + OP[0]);
87178dbd 846 trace_output (OP_VOID);
2934d1c9
MH		 847}
848
849/* bnoti */
850void
851OP_A01 ()
852{
87178dbd 853 trace_input ("bnoti", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 854 State.regs[OP[0]] ^= 0x8000 >> OP[1];
87178dbd 855 trace_output (OP_REG);
2934d1c9
MH		 856}
857
858/* bra.s */
859void
860OP_4800 ()
861{
a18cb100 862 trace_input ("bra.s", OP_CONSTANT8, OP_VOID, OP_VOID);
fd435e9f 863 JMP (PC + SEXT8 (OP[0]));
87178dbd 864 trace_output (OP_VOID);
2934d1c9
MH		 865}
866
867/* bra.l */
868void
869OP_24000000 ()
870{
87178dbd 871 trace_input ("bra.l", OP_CONSTANT16, OP_VOID, OP_VOID);
fd435e9f 872 JMP (PC + OP[0]);
87178dbd 873 trace_output (OP_VOID);
2934d1c9
MH		 874}
875
876/* brf0f.s */
877void
878OP_4A00 ()
879{
a18cb100 880 trace_input ("brf0f.s", OP_CONSTANT8, OP_VOID, OP_VOID);
2934d1c9 881 if (State.F0 == 0)
fd435e9f 882 JMP (PC + SEXT8 (OP[0]));
87178dbd 883 trace_output (OP_FLAG);
2934d1c9
MH		 884}
885
886/* brf0f.l */
887void
888OP_25000000 ()
889{
87178dbd 890 trace_input ("brf0f.l", OP_CONSTANT16, OP_VOID, OP_VOID);
2934d1c9 891 if (State.F0 == 0)
fd435e9f 892 JMP (PC + OP[0]);
87178dbd 893 trace_output (OP_FLAG);
2934d1c9
MH		 894}
895
896/* brf0t.s */
897void
898OP_4B00 ()
899{
a18cb100 900 trace_input ("brf0t.s", OP_CONSTANT8, OP_VOID, OP_VOID);
2934d1c9 901 if (State.F0)
fd435e9f 902 JMP (PC + SEXT8 (OP[0]));
87178dbd 903 trace_output (OP_FLAG);
2934d1c9
MH		 904}
905
906/* brf0t.l */
907void
908OP_25800000 ()
909{
87178dbd 910 trace_input ("brf0t.l", OP_CONSTANT16, OP_VOID, OP_VOID);
2934d1c9 911 if (State.F0)
fd435e9f 912 JMP (PC + OP[0]);
87178dbd 913 trace_output (OP_FLAG);
2934d1c9
MH		 914}
915
916/* bseti */
917void
918OP_801 ()
919{
87178dbd 920 trace_input ("bseti", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 921 State.regs[OP[0]] |= 0x8000 >> OP[1];
87178dbd 922 trace_output (OP_REG);
2934d1c9
MH		 923}
924
925/* btsti */
926void
927OP_E01 ()
928{
87178dbd 929 trace_input ("btsti", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9
MH		 930 State.F1 = State.F0;
931 State.F0 = (State.regs[OP[0]] & (0x8000 >> OP[1])) ? 1 : 0;
87178dbd 932 trace_output (OP_FLAG);
2934d1c9
MH		 933}
934
935/* clrac */
936void
937OP_5601 ()
938{
87178dbd 939 trace_input ("clrac", OP_ACCUM_OUTPUT, OP_VOID, OP_VOID);
2934d1c9 940 State.a[OP[0]] = 0;
87178dbd 941 trace_output (OP_ACCUM);
2934d1c9
MH		 942}
943
944/* cmp */
945void
946OP_600 ()
947{
87178dbd 948 trace_input ("cmp", OP_REG, OP_REG, OP_VOID);
2934d1c9
MH		 949 State.F1 = State.F0;
950 State.F0 = ((int16)(State.regs[OP[0]]) < (int16)(State.regs[OP[1]])) ? 1 : 0;
87178dbd 951 trace_output (OP_FLAG);
2934d1c9
MH		 952}
953
954/* cmp */
955void
956OP_1603 ()
957{
87178dbd 958 trace_input ("cmp", OP_ACCUM, OP_ACCUM, OP_VOID);
4c38885c 959 State.F1 = State.F0;
4f425a32 960 State.F0 = (SEXT40(State.a[OP[0]]) < SEXT40(State.a[OP[1]])) ? 1 : 0;
87178dbd 961 trace_output (OP_FLAG);
2934d1c9
MH		 962}
963
964/* cmpeq */
965void
966OP_400 ()
967{
87178dbd 968 trace_input ("cmpeq", OP_REG, OP_REG, OP_VOID);
2934d1c9
MH		 969 State.F1 = State.F0;
970 State.F0 = (State.regs[OP[0]] == State.regs[OP[1]]) ? 1 : 0;
87178dbd 971 trace_output (OP_FLAG);
2934d1c9
MH		 972}
973
974/* cmpeq */
975void
976OP_1403 ()
977{
87178dbd 978 trace_input ("cmpeq", OP_ACCUM, OP_ACCUM, OP_VOID);
4c38885c 979 State.F1 = State.F0;
fd435e9f 980 State.F0 = ((State.a[OP[0]] & MASK40) == (State.a[OP[1]] & MASK40)) ? 1 : 0;
87178dbd 981 trace_output (OP_FLAG);
2934d1c9
MH		 982}
983
984/* cmpeqi.s */
985void
986OP_401 ()
987{
c12f5c67 988 trace_input ("cmpeqi.s", OP_REG, OP_CONSTANT4, OP_VOID);
2934d1c9 989 State.F1 = State.F0;
c12f5c67 990 State.F0 = (State.regs[OP[0]] == (reg_t)SEXT4(OP[1])) ? 1 : 0;
87178dbd 991 trace_output (OP_FLAG);
2934d1c9
MH		 992}
993
994/* cmpeqi.l */
995void
996OP_2000000 ()
997{
87178dbd 998 trace_input ("cmpeqi.l", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 999 State.F1 = State.F0;
c12f5c67 1000 State.F0 = (State.regs[OP[0]] == (reg_t)OP[1]) ? 1 : 0;
87178dbd 1001 trace_output (OP_FLAG);
2934d1c9
MH		 1002}
1003
1004/* cmpi.s */
1005void
1006OP_601 ()
1007{
87178dbd 1008 trace_input ("cmpi.s", OP_REG, OP_CONSTANT4, OP_VOID);
2934d1c9 1009 State.F1 = State.F0;
c12f5c67 1010 State.F0 = ((int16)(State.regs[OP[0]]) < (int16)SEXT4(OP[1])) ? 1 : 0;
87178dbd 1011 trace_output (OP_FLAG);
2934d1c9
MH		 1012}
1013
1014/* cmpi.l */
1015void
1016OP_3000000 ()
1017{
87178dbd 1018 trace_input ("cmpi.l", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9
MH		 1019 State.F1 = State.F0;
1020 State.F0 = ((int16)(State.regs[OP[0]]) < (int16)(OP[1])) ? 1 : 0;
87178dbd 1021 trace_output (OP_FLAG);
2934d1c9
MH		 1022}
1023
1024/* cmpu */
1025void
1026OP_4600 ()
1027{
87178dbd 1028 trace_input ("cmpu", OP_REG, OP_REG, OP_VOID);
2934d1c9
MH		 1029 State.F1 = State.F0;
1030 State.F0 = (State.regs[OP[0]] < State.regs[OP[1]]) ? 1 : 0;
87178dbd 1031 trace_output (OP_FLAG);
2934d1c9
MH		 1032}
1033
1034/* cmpui */
1035void
1036OP_23000000 ()
1037{
87178dbd 1038 trace_input ("cmpui", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 1039 State.F1 = State.F0;
c12f5c67 1040 State.F0 = (State.regs[OP[0]] < (reg_t)OP[1]) ? 1 : 0;
87178dbd 1041 trace_output (OP_FLAG);
2934d1c9
MH		 1042}
1043
1044/* cpfg */
1045void
1046OP_4E09 ()
1047{
1048 uint8 *src, *dst;
2934d1c9 1049
60fc5b72 1050 trace_input ("cpfg", OP_FLAG_OUTPUT, OP_FLAG, OP_VOID);
2934d1c9
MH		 1051 if (OP[0] == 0)
1052 dst = &State.F0;
1053 else
1054 dst = &State.F1;
1055
1056 if (OP[1] == 0)
1057 src = &State.F0;
1058 else if (OP[1] == 1)
1059 src = &State.F1;
1060 else
1061 src = &State.C;
1062
1063 *dst = *src;
87178dbd 1064 trace_output (OP_FLAG);
2934d1c9
MH		 1065}
1066
1067/* dbt */
1068void
1069OP_5F20 ()
1070{
a49a15ad 1071 /* d10v_callback->printf_filtered(d10v_callback, "***** DBT ***** PC=%x\n",PC); */
4f425a32 1072 State.exception = SIGTRAP;
2934d1c9
MH		 1073}
1074
1075/* divs */
1076void
1077OP_14002800 ()
1078{
1079 uint16 foo, tmp, tmpf;
87178dbd
MM		 1080
1081 trace_input ("divs", OP_DREG, OP_REG, OP_VOID);
2934d1c9
MH		 1082 foo = (State.regs[OP[0]] << 1) | (State.regs[OP[0]+1] >> 15);
1083 tmp = (int16)foo - (int16)(State.regs[OP[1]]);
1084 tmpf = (foo >= State.regs[OP[1]]) ? 1 : 0;
1085 State.regs[OP[0]] = (tmpf == 1) ? tmp : foo;
1086 State.regs[OP[0]+1] = (State.regs[OP[0]+1] << 1) | tmpf;
87178dbd 1087 trace_output (OP_DREG);
2934d1c9
MH		 1088}
1089
1090/* exef0f */
1091void
1092OP_4E04 ()
1093{
87178dbd 1094 trace_input ("exef0f", OP_VOID, OP_VOID, OP_VOID);
293c76a3 1095 State.exe = (State.F0 == 0);
87178dbd 1096 trace_output (OP_FLAG);
2934d1c9
MH		 1097}
1098
1099/* exef0t */
1100void
1101OP_4E24 ()
1102{
87178dbd 1103 trace_input ("exef0t", OP_VOID, OP_VOID, OP_VOID);
293c76a3 1104 State.exe = (State.F0 != 0);
87178dbd 1105 trace_output (OP_FLAG);
2934d1c9
MH		 1106}
1107
1108/* exef1f */
1109void
1110OP_4E40 ()
1111{
87178dbd 1112 trace_input ("exef1f", OP_VOID, OP_VOID, OP_VOID);
293c76a3 1113 State.exe = (State.F1 == 0);
87178dbd 1114 trace_output (OP_FLAG);
2934d1c9
MH		 1115}
1116
1117/* exef1t */
1118void
1119OP_4E42 ()
1120{
87178dbd 1121 trace_input ("exef1t", OP_VOID, OP_VOID, OP_VOID);
293c76a3 1122 State.exe = (State.F1 != 0);
87178dbd 1123 trace_output (OP_FLAG);
2934d1c9
MH		 1124}
1125
1126/* exefaf */
1127void
1128OP_4E00 ()
1129{
87178dbd 1130 trace_input ("exefaf", OP_VOID, OP_VOID, OP_VOID);
293c76a3 1131 State.exe = (State.F0 == 0) & (State.F1 == 0);
87178dbd 1132 trace_output (OP_FLAG);
2934d1c9
MH		 1133}
1134
1135/* exefat */
1136void
1137OP_4E02 ()
1138{
87178dbd 1139 trace_input ("exefat", OP_VOID, OP_VOID, OP_VOID);
293c76a3 1140 State.exe = (State.F0 == 0) & (State.F1 != 0);
87178dbd 1141 trace_output (OP_FLAG);
2934d1c9
MH		 1142}
1143
1144/* exetaf */
1145void
1146OP_4E20 ()
1147{
87178dbd 1148 trace_input ("exetaf", OP_VOID, OP_VOID, OP_VOID);
293c76a3 1149 State.exe = (State.F0 != 0) & (State.F1 == 0);
87178dbd 1150 trace_output (OP_FLAG);
2934d1c9
MH		 1151}
1152
1153/* exetat */
1154void
1155OP_4E22 ()
1156{
87178dbd 1157 trace_input ("exetat", OP_VOID, OP_VOID, OP_VOID);
293c76a3 1158 State.exe = (State.F0 != 0) & (State.F1 != 0);
87178dbd 1159 trace_output (OP_FLAG);
2934d1c9
MH		 1160}
1161
1162/* exp */
1163void
1164OP_15002A00 ()
1165{
1166 uint32 tmp, foo;
1167 int i;
1168
87178dbd 1169 trace_input ("exp", OP_REG_OUTPUT, OP_DREG, OP_VOID);
4c38885c
MH		 1170 if (((int16)State.regs[OP[1]]) >= 0)
1171 tmp = (State.regs[OP[1]] << 16) | State.regs[OP[1]+1];
2934d1c9 1172 else
4c38885c 1173 tmp = ~((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
2934d1c9
MH		 1174
1175 foo = 0x40000000;
4c38885c 1176 for (i=1;i<17;i++)
2934d1c9
MH		 1177 {
1178 if (tmp & foo)
1179 {
1180 State.regs[OP[0]] = i-1;
87178dbd 1181 trace_output (OP_REG);
2934d1c9
MH		 1182 return;
1183 }
4c38885c 1184 foo >>= 1;
2934d1c9
MH		 1185 }
1186 State.regs[OP[0]] = 16;
87178dbd 1187 trace_output (OP_REG);
2934d1c9
MH		 1188}
1189
1190/* exp */
1191void
1192OP_15002A02 ()
1193{
4c38885c
MH		 1194 int64 tmp, foo;
1195 int i;
87178dbd
MM		 1196
1197 trace_input ("exp", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
fd435e9f
MM		 1198 tmp = SEXT40(State.a[OP[1]]);
1199 if (tmp < 0)
1200 tmp = ~tmp & MASK40;
4c38885c
MH		 1201
1202 foo = 0x4000000000LL;
1203 for (i=1;i<25;i++)
1204 {
1205 if (tmp & foo)
1206 {
1207 State.regs[OP[0]] = i-9;
87178dbd 1208 trace_output (OP_REG);
4c38885c
MH		 1209 return;
1210 }
1211 foo >>= 1;
1212 }
1213 State.regs[OP[0]] = 16;
87178dbd 1214 trace_output (OP_REG);
2934d1c9
MH		 1215}
1216
1217/* jl */
1218void
1219OP_4D00 ()
1220{
8831cb01 1221 trace_input ("jl", OP_REG, OP_R0, OP_R1);
2934d1c9 1222 State.regs[13] = PC+1;
fd435e9f 1223 JMP (State.regs[OP[0]]);
87178dbd 1224 trace_output (OP_VOID);
2934d1c9
MH		 1225}
1226
1227/* jmp */
1228void
1229OP_4C00 ()
1230{
a18cb100 1231 trace_input ("jmp", OP_REG,
8831cb01
MM		 1232 (OP[0] == 13) ? OP_R0 : OP_VOID,
1233 (OP[0] == 13) ? OP_R1 : OP_VOID);
a18cb100 1234
fd435e9f 1235 JMP (State.regs[OP[0]]);
87178dbd 1236 trace_output (OP_VOID);
2934d1c9
MH		 1237}
1238
1239/* ld */
1240void
1241OP_30000000 ()
1242{
87178dbd 1243 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
2934d1c9 1244 State.regs[OP[0]] = RW (OP[1] + State.regs[OP[2]]);
87178dbd 1245 trace_output (OP_REG);
2934d1c9
MH		 1246}
1247
1248/* ld */
1249void
1250OP_6401 ()
1251{
87178dbd 1252 trace_input ("ld", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
4c38885c 1253 State.regs[OP[0]] = RW (State.regs[OP[1]]);
4f425a32 1254 INC_ADDR(State.regs[OP[1]],-2);
87178dbd 1255 trace_output (OP_REG);
2934d1c9
MH		 1256}
1257
1258/* ld */
1259void
1260OP_6001 ()
1261{
87178dbd 1262 trace_input ("ld", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
4c38885c 1263 State.regs[OP[0]] = RW (State.regs[OP[1]]);
4f425a32 1264 INC_ADDR(State.regs[OP[1]],2);
87178dbd 1265 trace_output (OP_REG);
2934d1c9
MH		 1266}
1267
1268/* ld */
1269void
1270OP_6000 ()
1271{
87178dbd 1272 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
2934d1c9 1273 State.regs[OP[0]] = RW (State.regs[OP[1]]);
87178dbd 1274 trace_output (OP_REG);
2934d1c9
MH		 1275}
1276
1277/* ld2w */
1278void
1279OP_31000000 ()
1280{
8918b3a7 1281 uint16 addr = State.regs[OP[2]];
308f64d3 1282 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
8918b3a7
MM		 1283 State.regs[OP[0]] = RW (OP[1] + addr);
1284 State.regs[OP[0]+1] = RW (OP[1] + addr + 2);
87178dbd 1285 trace_output (OP_DREG);
2934d1c9
MH		 1286}
1287
1288/* ld2w */
1289void
1290OP_6601 ()
1291{
8918b3a7 1292 uint16 addr = State.regs[OP[1]];
87178dbd 1293 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
8918b3a7
MM		 1294 State.regs[OP[0]] = RW (addr);
1295 State.regs[OP[0]+1] = RW (addr+2);
4f425a32 1296 INC_ADDR(State.regs[OP[1]],-4);
87178dbd 1297 trace_output (OP_DREG);
2934d1c9
MH		 1298}
1299
1300/* ld2w */
1301void
1302OP_6201 ()
1303{
8918b3a7 1304 uint16 addr = State.regs[OP[1]];
87178dbd 1305 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
8918b3a7
MM		 1306 State.regs[OP[0]] = RW (addr);
1307 State.regs[OP[0]+1] = RW (addr+2);
4f425a32 1308 INC_ADDR(State.regs[OP[1]],4);
8918b3a7 1309 trace_output (OP_DREG);
2934d1c9
MH		 1310}
1311
1312/* ld2w */
1313void
1314OP_6200 ()
1315{
8918b3a7 1316 uint16 addr = State.regs[OP[1]];
addb61a5 1317 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
8918b3a7
MM		 1318 State.regs[OP[0]] = RW (addr);
1319 State.regs[OP[0]+1] = RW (addr+2);
1320 trace_output (OP_DREG);
2934d1c9
MH		 1321}
1322
1323/* ldb */
1324void
1325OP_38000000 ()
1326{
87178dbd 1327 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
c422ecc7 1328 State.regs[OP[0]] = SEXT8 (RB (OP[1] + State.regs[OP[2]]));
87178dbd 1329 trace_output (OP_REG);
2934d1c9
MH		 1330}
1331
1332/* ldb */
1333void
1334OP_7000 ()
1335{
87178dbd 1336 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
c422ecc7 1337 State.regs[OP[0]] = SEXT8 (RB (State.regs[OP[1]]));
87178dbd 1338 trace_output (OP_REG);
2934d1c9
MH		 1339}
1340
1341/* ldi.s */
1342void
1343OP_4001 ()
1344{
87178dbd 1345 trace_input ("ldi.s", OP_REG_OUTPUT, OP_CONSTANT4, OP_VOID);
2934d1c9 1346 State.regs[OP[0]] = SEXT4(OP[1]);
87178dbd 1347 trace_output (OP_REG);
2934d1c9
MH		 1348}
1349
1350/* ldi.l */
1351void
1352OP_20000000 ()
1353{
fd435e9f 1354 trace_input ("ldi.l", OP_REG_OUTPUT, OP_CONSTANT16, OP_VOID);
2934d1c9 1355 State.regs[OP[0]] = OP[1];
87178dbd 1356 trace_output (OP_REG);
2934d1c9
MH		 1357}
1358
1359/* ldub */
1360void
1361OP_39000000 ()
1362{
87178dbd 1363 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
2934d1c9 1364 State.regs[OP[0]] = RB (OP[1] + State.regs[OP[2]]);
87178dbd 1365 trace_output (OP_REG);
2934d1c9
MH		 1366}
1367
1368/* ldub */
1369void
1370OP_7200 ()
1371{
87178dbd 1372 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
2934d1c9 1373 State.regs[OP[0]] = RB (State.regs[OP[1]]);
87178dbd 1374 trace_output (OP_REG);
2934d1c9
MH		 1375}
1376
1377/* mac */
1378void
1379OP_2A00 ()
1380{
4c38885c 1381 int64 tmp;
87178dbd
MM		 1382
1383 trace_input ("mac", OP_ACCUM, OP_REG, OP_REG);
4f425a32 1384 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
4c38885c
MH		 1385
1386 if (State.FX)
4f425a32 1387 tmp = SEXT40( (tmp << 1) & MASK40);
4c38885c
MH		 1388
1389 if (State.ST && tmp > MAX32)
1390 tmp = MAX32;
1391
4f425a32 1392 tmp += SEXT40(State.a[OP[0]]);
4c38885c
MH		 1393 if (State.ST)
1394 {
1395 if (tmp > MAX32)
1396 State.a[OP[0]] = MAX32;
1397 else if (tmp < MIN32)
1398 State.a[OP[0]] = MIN32;
1399 else
4f425a32 1400 State.a[OP[0]] = tmp & MASK40;
4c38885c
MH		 1401 }
1402 else
4f425a32 1403 State.a[OP[0]] = tmp & MASK40;
87178dbd 1404 trace_output (OP_ACCUM);
2934d1c9
MH		 1405}
1406
1407/* macsu */
1408void
1409OP_1A00 ()
1410{
4f425a32 1411 int64 tmp;
87178dbd
MM		 1412
1413 trace_input ("macsu", OP_ACCUM, OP_REG, OP_REG);
4f425a32
MH		 1414 tmp = SEXT40 ((int16)State.regs[OP[1]] * State.regs[OP[2]]);
1415 if (State.FX)
1416 tmp = SEXT40( (tmp << 1) & MASK40);
1417
1418 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) + tmp) & MASK40;
87178dbd 1419 trace_output (OP_ACCUM);
2934d1c9
MH		 1420}
1421
1422/* macu */
1423void
1424OP_3A00 ()
1425{
ae558075
AC		 1426 uint64 tmp;
1427 uint32 src1;
1428 uint32 src2;
87178dbd
MM		 1429
1430 trace_input ("macu", OP_ACCUM, OP_REG, OP_REG);
ae558075
AC		 1431 src1 = (uint16) State.regs[OP[1]];
1432 src2 = (uint16) State.regs[OP[2]];
1433 tmp = src1 * src2;
4f425a32 1434 if (State.FX)
ae558075
AC		 1435 tmp = (tmp << 1);
1436 State.a[OP[0]] = (State.a[OP[0]] + tmp) & MASK40;
87178dbd 1437 trace_output (OP_ACCUM);
2934d1c9
MH		 1438}
1439
1440/* max */
1441void
1442OP_2600 ()
1443{
87178dbd 1444 trace_input ("max", OP_REG, OP_REG, OP_VOID);
2934d1c9 1445 State.F1 = State.F0;
ea2155e8 1446 if ((int16)State.regs[OP[1]] > (int16)State.regs[OP[0]])
2934d1c9
MH		 1447 {
1448 State.regs[OP[0]] = State.regs[OP[1]];
1449 State.F0 = 1;
1450 }
1451 else
1452 State.F0 = 0;
87178dbd 1453 trace_output (OP_REG);
2934d1c9
MH		 1454}
1455
1456/* max */
1457void
1458OP_3600 ()
1459{
4f425a32 1460 int64 tmp;
87178dbd
MM		 1461
1462 trace_input ("max", OP_ACCUM, OP_DREG, OP_VOID);
4f425a32
MH		 1463 State.F1 = State.F0;
1464 tmp = SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
1465 if (tmp > SEXT40(State.a[OP[0]]))
1466 {
1467 State.a[OP[0]] = tmp & MASK40;
1468 State.F0 = 1;
1469 }
1470 else
1471 State.F0 = 0;
87178dbd 1472 trace_output (OP_ACCUM);
2934d1c9
MH		 1473}
1474
1475/* max */
1476void
1477OP_3602 ()
1478{
87178dbd 1479 trace_input ("max", OP_ACCUM, OP_ACCUM, OP_VOID);
4f425a32
MH		 1480 State.F1 = State.F0;
1481 if (SEXT40(State.a[OP[1]]) > SEXT40(State.a[OP[0]]))
1482 {
1483 State.a[OP[0]] = State.a[OP[1]];
1484 State.F0 = 1;
1485 }
1486 else
1487 State.F0 = 0;
87178dbd 1488 trace_output (OP_ACCUM);
2934d1c9
MH		 1489}
1490
4f425a32 1491
2934d1c9
MH		 1492/* min */
1493void
1494OP_2601 ()
1495{
87178dbd 1496 trace_input ("min", OP_REG, OP_REG, OP_VOID);
2934d1c9 1497 State.F1 = State.F0;
ea2155e8 1498 if ((int16)State.regs[OP[1]] < (int16)State.regs[OP[0]])
2934d1c9
MH		 1499 {
1500 State.regs[OP[0]] = State.regs[OP[1]];
1501 State.F0 = 1;
1502 }
1503 else
1504 State.F0 = 0;
87178dbd 1505 trace_output (OP_REG);
2934d1c9
MH		 1506}
1507
1508/* min */
1509void
1510OP_3601 ()
1511{
4f425a32 1512 int64 tmp;
87178dbd
MM		 1513
1514 trace_input ("min", OP_ACCUM, OP_DREG, OP_VOID);
4f425a32
MH		 1515 State.F1 = State.F0;
1516 tmp = SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
1517 if (tmp < SEXT40(State.a[OP[0]]))
1518 {
1519 State.a[OP[0]] = tmp & MASK40;
1520 State.F0 = 1;
1521 }
1522 else
1523 State.F0 = 0;
87178dbd 1524 trace_output (OP_ACCUM);
2934d1c9
MH		 1525}
1526
1527/* min */
1528void
1529OP_3603 ()
1530{
87178dbd 1531 trace_input ("min", OP_ACCUM, OP_ACCUM, OP_VOID);
4f425a32
MH		 1532 State.F1 = State.F0;
1533 if (SEXT40(State.a[OP[1]]) < SEXT40(State.a[OP[0]]))
1534 {
1535 State.a[OP[0]] = State.a[OP[1]];
1536 State.F0 = 1;
1537 }
1538 else
1539 State.F0 = 0;
87178dbd 1540 trace_output (OP_ACCUM);
2934d1c9
MH		 1541}
1542
1543/* msb */
1544void
1545OP_2800 ()
1546{
4f425a32 1547 int64 tmp;
87178dbd
MM		 1548
1549 trace_input ("msb", OP_ACCUM, OP_REG, OP_REG);
4f425a32
MH		 1550 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
1551
1552 if (State.FX)
1553 tmp = SEXT40 ((tmp << 1) & MASK40);
1554
1555 if (State.ST && tmp > MAX32)
1556 tmp = MAX32;
1557
1558 tmp = SEXT40(State.a[OP[0]]) - tmp;
1559 if (State.ST)
1560 {
1561 if (tmp > MAX32)
1562 State.a[OP[0]] = MAX32;
1563 else if (tmp < MIN32)
1564 State.a[OP[0]] = MIN32;
1565 else
1566 State.a[OP[0]] = tmp & MASK40;
1567 }
1568 else
1569 State.a[OP[0]] = tmp & MASK40;
87178dbd 1570 trace_output (OP_ACCUM);
2934d1c9
MH		 1571}
1572
1573/* msbsu */
1574void
1575OP_1800 ()
1576{
4f425a32 1577 int64 tmp;
87178dbd
MM		 1578
1579 trace_input ("msbsu", OP_ACCUM, OP_REG, OP_REG);
4f425a32
MH		 1580 tmp = SEXT40 ((int16)State.regs[OP[1]] * State.regs[OP[2]]);
1581 if (State.FX)
1582 tmp = SEXT40( (tmp << 1) & MASK40);
1583
1584 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) - tmp) & MASK40;
87178dbd 1585 trace_output (OP_ACCUM);
2934d1c9
MH		 1586}
1587
1588/* msbu */
1589void
1590OP_3800 ()
1591{
d294a657
AC		 1592 uint64 tmp;
1593 uint32 src1;
1594 uint32 src2;
87178dbd
MM		 1595
1596 trace_input ("msbu", OP_ACCUM, OP_REG, OP_REG);
d294a657
AC		 1597 src1 = (uint16) State.regs[OP[1]];
1598 src2 = (uint16) State.regs[OP[2]];
1599 tmp = src1 * src2;
4f425a32 1600 if (State.FX)
d294a657 1601 tmp = (tmp << 1);
4f425a32 1602
d294a657 1603 State.a[OP[0]] = (State.a[OP[0]] - tmp) & MASK40;
87178dbd 1604 trace_output (OP_ACCUM);
2934d1c9
MH		 1605}
1606
1607/* mul */
1608void
1609OP_2E00 ()
1610{
87178dbd 1611 trace_input ("mul", OP_REG, OP_REG, OP_VOID);
2934d1c9 1612 State.regs[OP[0]] *= State.regs[OP[1]];
87178dbd 1613 trace_output (OP_REG);
2934d1c9
MH		 1614}
1615
1616/* mulx */
1617void
1618OP_2C00 ()
1619{
4f425a32 1620 int64 tmp;
87178dbd
MM		 1621
1622 trace_input ("mulx", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
4f425a32
MH		 1623 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
1624
1625 if (State.FX)
1626 tmp = SEXT40 ((tmp << 1) & MASK40);
1627
1628 if (State.ST && tmp > MAX32)
1629 State.a[OP[0]] = MAX32;
1630 else
1631 State.a[OP[0]] = tmp & MASK40;
87178dbd 1632 trace_output (OP_ACCUM);
2934d1c9
MH		 1633}
1634
1635/* mulxsu */
1636void
1637OP_1C00 ()
1638{
4f425a32 1639 int64 tmp;
87178dbd
MM		 1640
1641 trace_input ("mulxsu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
4f425a32
MH		 1642 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * State.regs[OP[2]]);
1643
1644 if (State.FX)
1645 tmp <<= 1;
1646
1647 State.a[OP[0]] = tmp & MASK40;
87178dbd 1648 trace_output (OP_ACCUM);
2934d1c9
MH		 1649}
1650
1651/* mulxu */
1652void
1653OP_3C00 ()
1654{
9420287e
AC		 1655 uint64 tmp;
1656 uint32 src1;
1657 uint32 src2;
87178dbd
MM		 1658
1659 trace_input ("mulxu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
9420287e
AC		 1660 src1 = (uint16) State.regs[OP[1]];
1661 src2 = (uint16) State.regs[OP[2]];
1662 tmp = src1 * src2;
4f425a32
MH		 1663 if (State.FX)
1664 tmp <<= 1;
1665
1666 State.a[OP[0]] = tmp & MASK40;
87178dbd 1667 trace_output (OP_ACCUM);
2934d1c9
MH		 1668}
1669
1670/* mv */
1671void
1672OP_4000 ()
1673{
87178dbd 1674 trace_input ("mv", OP_REG_OUTPUT, OP_REG, OP_VOID);
2934d1c9 1675 State.regs[OP[0]] = State.regs[OP[1]];
87178dbd 1676 trace_output (OP_REG);
2934d1c9
MH		 1677}
1678
1679/* mv2w */
1680void
1681OP_5000 ()
1682{
87178dbd 1683 trace_input ("mv2w", OP_DREG_OUTPUT, OP_DREG, OP_VOID);
2934d1c9
MH		 1684 State.regs[OP[0]] = State.regs[OP[1]];
1685 State.regs[OP[0]+1] = State.regs[OP[1]+1];
87178dbd 1686 trace_output (OP_DREG);
2934d1c9
MH		 1687}
1688
1689/* mv2wfac */
1690void
1691OP_3E00 ()
1692{
87178dbd 1693 trace_input ("mv2wfac", OP_DREG_OUTPUT, OP_ACCUM, OP_VOID);
2934d1c9
MH		 1694 State.regs[OP[0]] = (State.a[OP[1]] >> 16) & 0xffff;
1695 State.regs[OP[0]+1] = State.a[OP[1]] & 0xffff;
87178dbd 1696 trace_output (OP_DREG);
2934d1c9
MH		 1697}
1698
1699/* mv2wtac */
1700void
1701OP_3E01 ()
1702{
fd435e9f 1703 trace_input ("mv2wtac", OP_DREG, OP_ACCUM_OUTPUT, OP_VOID);
4f425a32 1704 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]]) << 16 | State.regs[OP[0]+1]) & MASK40;
fd435e9f 1705 trace_output (OP_ACCUM_REVERSE);
2934d1c9
MH		 1706}
1707
1708/* mvac */
1709void
1710OP_3E03 ()
1711{
87178dbd 1712 trace_input ("mvac", OP_ACCUM_OUTPUT, OP_ACCUM, OP_VOID);
2934d1c9 1713 State.a[OP[0]] = State.a[OP[1]];
87178dbd 1714 trace_output (OP_ACCUM);
2934d1c9
MH		 1715}
1716
1717/* mvb */
1718void
1719OP_5400 ()
1720{
87178dbd 1721 trace_input ("mvb", OP_REG_OUTPUT, OP_REG, OP_VOID);
2934d1c9 1722 State.regs[OP[0]] = SEXT8 (State.regs[OP[1]] & 0xff);
87178dbd 1723 trace_output (OP_REG);
2934d1c9
MH		 1724}
1725
1726/* mvf0f */
1727void
1728OP_4400 ()
1729{
87178dbd 1730 trace_input ("mf0f", OP_REG_OUTPUT, OP_REG, OP_VOID);
2934d1c9
MH		 1731 if (State.F0 == 0)
1732 State.regs[OP[0]] = State.regs[OP[1]];
87178dbd 1733 trace_output (OP_REG);
2934d1c9
MH		 1734}
1735
1736/* mvf0t */
1737void
1738OP_4401 ()
1739{
87178dbd 1740 trace_input ("mf0t", OP_REG_OUTPUT, OP_REG, OP_VOID);
2934d1c9
MH		 1741 if (State.F0)
1742 State.regs[OP[0]] = State.regs[OP[1]];
87178dbd 1743 trace_output (OP_REG);
2934d1c9
MH		 1744}
1745
1746/* mvfacg */
1747void
1748OP_1E04 ()
1749{
87178dbd 1750 trace_input ("mvfacg", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2934d1c9 1751 State.regs[OP[0]] = (State.a[OP[1]] >> 32) & 0xff;
87178dbd 1752 trace_output (OP_ACCUM);
2934d1c9
MH		 1753}
1754
1755/* mvfachi */
1756void
1757OP_1E00 ()
1758{
87178dbd 1759 trace_input ("mvfachi", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2934d1c9 1760 State.regs[OP[0]] = (State.a[OP[1]] >> 16) & 0xffff;
87178dbd 1761 trace_output (OP_REG);
2934d1c9
MH		 1762}
1763
1764/* mvfaclo */
1765void
1766OP_1E02 ()
1767{
87178dbd 1768 trace_input ("mvfaclo", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2934d1c9 1769 State.regs[OP[0]] = State.a[OP[1]] & 0xffff;
87178dbd 1770 trace_output (OP_REG);
2934d1c9
MH		 1771}
1772
1773/* mvfc */
1774void
1775OP_5200 ()
1776{
87178dbd 1777 trace_input ("mvfc", OP_REG_OUTPUT, OP_CR, OP_VOID);
bc6df23d 1778 State.regs[OP[0]] = move_from_cr (OP[1]);
87178dbd 1779 trace_output (OP_REG);
2934d1c9
MH		 1780}
1781
1782/* mvtacg */
1783void
1784OP_1E41 ()
1785{
87178dbd 1786 trace_input ("mvtacg", OP_REG, OP_ACCUM, OP_VOID);
2934d1c9
MH		 1787 State.a[OP[1]] &= MASK32;
1788 State.a[OP[1]] |= (int64)(State.regs[OP[0]] & 0xff) << 32;
87178dbd 1789 trace_output (OP_ACCUM_REVERSE);
2934d1c9
MH		 1790}
1791
1792/* mvtachi */
1793void
1794OP_1E01 ()
1795{
1796 uint16 tmp;
87178dbd
MM		 1797
1798 trace_input ("mvtachi", OP_REG, OP_ACCUM, OP_VOID);
2934d1c9 1799 tmp = State.a[OP[1]] & 0xffff;
4f425a32 1800 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]]) << 16 | tmp) & MASK40;
87178dbd 1801 trace_output (OP_ACCUM_REVERSE);
2934d1c9
MH		 1802}
1803
1804/* mvtaclo */
1805void
1806OP_1E21 ()
1807{
87178dbd 1808 trace_input ("mvtaclo", OP_REG, OP_ACCUM, OP_VOID);
4f425a32 1809 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]])) & MASK40;
87178dbd 1810 trace_output (OP_ACCUM_REVERSE);
2934d1c9
MH		 1811}
1812
1813/* mvtc */
1814void
1815OP_5600 ()
1816{
87178dbd 1817 trace_input ("mvtc", OP_REG, OP_CR_OUTPUT, OP_VOID);
bc6df23d 1818 move_to_cr (OP[1], State.regs[OP[0]]);
87178dbd 1819 trace_output (OP_CR_REVERSE);
2934d1c9
MH		 1820}
1821
1822/* mvub */
1823void
1824OP_5401 ()
1825{
87178dbd 1826 trace_input ("mvub", OP_REG_OUTPUT, OP_REG, OP_VOID);
2934d1c9 1827 State.regs[OP[0]] = State.regs[OP[1]] & 0xff;
87178dbd 1828 trace_output (OP_REG);
2934d1c9
MH		 1829}
1830
1831/* neg */
1832void
1833OP_4605 ()
1834{
87178dbd 1835 trace_input ("neg", OP_REG, OP_VOID, OP_VOID);
2934d1c9 1836 State.regs[OP[0]] = 0 - State.regs[OP[0]];
87178dbd 1837 trace_output (OP_REG);
2934d1c9
MH		 1838}
1839
1840/* neg */
1841void
1842OP_5605 ()
1843{
1844 int64 tmp;
87178dbd
MM		 1845
1846 trace_input ("neg", OP_ACCUM, OP_VOID, OP_VOID);
4f425a32 1847 tmp = -SEXT40(State.a[OP[0]]);
2934d1c9
MH		 1848 if (State.ST)
1849 {
4c38885c 1850 if ( tmp > MAX32)
2934d1c9 1851 State.a[OP[0]] = MAX32;
4c38885c 1852 else if (tmp < MIN32)
2934d1c9
MH		 1853 State.a[OP[0]] = MIN32;
1854 else
4f425a32 1855 State.a[OP[0]] = tmp & MASK40;
2934d1c9
MH		 1856 }
1857 else
4f425a32 1858 State.a[OP[0]] = tmp & MASK40;
87178dbd 1859 trace_output (OP_ACCUM);
2934d1c9
MH		 1860}
1861
1862
1863/* nop */
1864void
1865OP_5E00 ()
1866{
87178dbd 1867 trace_input ("nop", OP_VOID, OP_VOID, OP_VOID);
7eebfc62 1868
c422ecc7
MH		 1869 ins_type_counters[ (int)State.ins_type ]--; /* don't count nops as normal instructions */
1870 switch (State.ins_type)
1871 {
1872 default:
1873 ins_type_counters[ (int)INS_UNKNOWN ]++;
1874 break;
1875
1876 case INS_LEFT_PARALLEL:
1877 /* Don't count a parallel op that includes a NOP as a true parallel op */
1878 ins_type_counters[ (int)INS_RIGHT_PARALLEL ]--;
1879 ins_type_counters[ (int)INS_RIGHT ]++;
1880 ins_type_counters[ (int)INS_LEFT_NOPS ]++;
1881 break;
1882
1883 case INS_LEFT:
1884 case INS_LEFT_COND_EXE:
1885 ins_type_counters[ (int)INS_LEFT_NOPS ]++;
1886 break;
1887
1888 case INS_RIGHT_PARALLEL:
1889 /* Don't count a parallel op that includes a NOP as a true parallel op */
1890 ins_type_counters[ (int)INS_LEFT_PARALLEL ]--;
1891 ins_type_counters[ (int)INS_LEFT ]++;
1892 ins_type_counters[ (int)INS_RIGHT_NOPS ]++;
1893 break;
1894
1895 case INS_RIGHT:
1896 case INS_RIGHT_COND_EXE:
1897 ins_type_counters[ (int)INS_RIGHT_NOPS ]++;
1898 break;
1899 }
1900
1901 trace_output (OP_VOID);
2934d1c9
MH		 1902}
1903
1904/* not */
1905void
1906OP_4603 ()
1907{
87178dbd 1908 trace_input ("not", OP_REG, OP_VOID, OP_VOID);
2934d1c9 1909 State.regs[OP[0]] = ~(State.regs[OP[0]]);
87178dbd 1910 trace_output (OP_REG);
2934d1c9
MH		 1911}
1912
1913/* or */
1914void
1915OP_800 ()
1916{
87178dbd 1917 trace_input ("or", OP_REG, OP_REG, OP_VOID);
2934d1c9 1918 State.regs[OP[0]] |= State.regs[OP[1]];
87178dbd 1919 trace_output (OP_REG);
2934d1c9
MH		 1920}
1921
1922/* or3 */
1923void
1924OP_4000000 ()
1925{
87178dbd 1926 trace_input ("or3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
2934d1c9 1927 State.regs[OP[0]] = State.regs[OP[1]] | OP[2];
87178dbd 1928 trace_output (OP_REG);
2934d1c9
MH		 1929}
1930
1931/* rac */
1932void
1933OP_5201 ()
1934{
1935 int64 tmp;
1936 int shift = SEXT3 (OP[2]);
87178dbd
MM		 1937
1938 trace_input ("rac", OP_DREG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
166acb9f
MH		 1939 if (OP[1] != 0)
1940 {
7eebfc62
MM		 1941 (*d10v_callback->printf_filtered) (d10v_callback,
1942 "ERROR at PC 0x%x: instruction only valid for A0\n",
1943 PC<<2);
166acb9f
MH		 1944 State.exception = SIGILL;
1945 }
1946
2934d1c9 1947 State.F1 = State.F0;
aa49c64f 1948 tmp = SEXT56 ((State.a[0] << 16) | (State.a[1] & 0xffff));
2934d1c9 1949 if (shift >=0)
aa49c64f 1950 tmp <<= shift;
2934d1c9 1951 else
aa49c64f
AC		 1952 tmp >>= -shift;
1953 tmp += 0x8000;
1954 tmp >>= 16; /* look at bits 0:43 */
1955 if (tmp > SEXT44 (SIGNED64 (0x0007fffffff)))
2934d1c9
MH		 1956 {
1957 State.regs[OP[0]] = 0x7fff;
1958 State.regs[OP[0]+1] = 0xffff;
1959 State.F0 = 1;
1960 }
aa49c64f 1961 else if (tmp < SEXT44 (SIGNED64 (0xfff80000000)))
2934d1c9
MH		 1962 {
1963 State.regs[OP[0]] = 0x8000;
1964 State.regs[OP[0]+1] = 0;
1965 State.F0 = 1;
1966 }
1967 else
1968 {
1969 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
1970 State.regs[OP[0]+1] = tmp & 0xffff;
1971 State.F0 = 0;
1972 }
87178dbd 1973 trace_output (OP_DREG);
2934d1c9
MH		 1974}
1975
1976/* rachi */
1977void
1978OP_4201 ()
1979{
70ee56c5 1980 signed64 tmp;
4c38885c 1981 int shift = SEXT3 (OP[2]);
87178dbd
MM		 1982
1983 trace_input ("rachi", OP_REG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
4c38885c
MH		 1984 State.F1 = State.F0;
1985 if (shift >=0)
70ee56c5 1986 tmp = SEXT40 (State.a[OP[1]]) << shift;
4c38885c 1987 else
70ee56c5 1988 tmp = SEXT40 (State.a[OP[1]]) >> -shift;
4c38885c 1989 tmp += 0x8000;
63a91cfb 1990
70ee56c5 1991 if (tmp > SEXT44 (SIGNED64 (0x0007fffffff)))
4c38885c
MH		 1992 {
1993 State.regs[OP[0]] = 0x7fff;
1994 State.F0 = 1;
1995 }
70ee56c5 1996 else if (tmp < SEXT44 (SIGNED64 (0xfff80000000)))
4c38885c
MH		 1997 {
1998 State.regs[OP[0]] = 0x8000;
1999 State.F0 = 1;
2000 }
2001 else
2002 {
2003 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2004 State.F0 = 0;
2005 }
87178dbd 2006 trace_output (OP_REG);
2934d1c9
MH		 2007}
2008
2009/* rep */
2010void
2011OP_27000000 ()
2012{
87178dbd 2013 trace_input ("rep", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9
MH		 2014 RPT_S = PC + 1;
2015 RPT_E = PC + OP[1];
2016 RPT_C = State.regs[OP[0]];
2017 State.RP = 1;
2018 if (RPT_C == 0)
2019 {
7eebfc62 2020 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep with count=0 is illegal.\n");
4f425a32 2021 State.exception = SIGILL;
2934d1c9 2022 }
4c38885c
MH		 2023 if (OP[1] < 4)
2024 {
7eebfc62 2025 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep must include at least 4 instructions.\n");
4f425a32 2026 State.exception = SIGILL;
4c38885c 2027 }
87178dbd 2028 trace_output (OP_VOID);
2934d1c9
MH		 2029}
2030
2031/* repi */
2032void
2033OP_2F000000 ()
2034{
87178dbd 2035 trace_input ("repi", OP_CONSTANT16, OP_CONSTANT16, OP_VOID);
2934d1c9
MH		 2036 RPT_S = PC + 1;
2037 RPT_E = PC + OP[1];
2038 RPT_C = OP[0];
2039 State.RP = 1;
2040 if (RPT_C == 0)
2041 {
7eebfc62 2042 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi with count=0 is illegal.\n");
4f425a32 2043 State.exception = SIGILL;
4c38885c
MH		 2044 }
2045 if (OP[1] < 4)
2046 {
7eebfc62 2047 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi must include at least 4 instructions.\n");
4f425a32 2048 State.exception = SIGILL;
2934d1c9 2049 }
87178dbd 2050 trace_output (OP_VOID);
2934d1c9
MH		 2051}
2052
2053/* rtd */
2054void
2055OP_5F60 ()
2056{
7eebfc62 2057 d10v_callback->printf_filtered(d10v_callback, "ERROR: rtd - NOT IMPLEMENTED\n");
87178dbd 2058 State.exception = SIGILL;
2934d1c9
MH		 2059}
2060
2061/* rte */
2062void
2063OP_5F40 ()
2064{
87178dbd 2065 trace_input ("rte", OP_VOID, OP_VOID, OP_VOID);
bc6df23d 2066 move_to_cr (PSW_CR, BPSW);
8831cb01 2067 JMP(BPC);
87178dbd 2068 trace_output (OP_VOID);
2934d1c9
MH		 2069}
2070
2071/* sadd */
2072void
2073OP_1223 ()
2074{
4c38885c 2075 int64 tmp;
87178dbd
MM		 2076
2077 trace_input ("sadd", OP_ACCUM, OP_ACCUM, OP_VOID);
4f425a32 2078 tmp = SEXT40(State.a[OP[0]]) + (SEXT40(State.a[OP[1]]) >> 16);
4c38885c
MH		 2079 if (State.ST)
2080 {
2081 if (tmp > MAX32)
2082 State.a[OP[0]] = MAX32;
2083 else if (tmp < MIN32)
2084 State.a[OP[0]] = MIN32;
2085 else
4f425a32 2086 State.a[OP[0]] = tmp & MASK40;
4c38885c
MH		 2087 }
2088 else
4f425a32 2089 State.a[OP[0]] = tmp & MASK40;
87178dbd 2090 trace_output (OP_ACCUM);
2934d1c9
MH		 2091}
2092
2093/* setf0f */
2094void
2095OP_4611 ()
2096{
87178dbd 2097 trace_input ("setf0f", OP_REG_OUTPUT, OP_VOID, OP_VOID);
4c38885c 2098 State.regs[OP[0]] = (State.F0 == 0) ? 1 : 0;
87178dbd 2099 trace_output (OP_REG);
2934d1c9
MH		 2100}
2101
2102/* setf0t */
2103void
2104OP_4613 ()
2105{
87178dbd 2106 trace_input ("setf0t", OP_REG_OUTPUT, OP_VOID, OP_VOID);
4c38885c 2107 State.regs[OP[0]] = (State.F0 == 1) ? 1 : 0;
87178dbd 2108 trace_output (OP_REG);
2934d1c9
MH		 2109}
2110
2111/* sleep */
2112void
2113OP_5FC0 ()
2114{
87178dbd 2115 trace_input ("sleep", OP_VOID, OP_VOID, OP_VOID);
4c38885c 2116 State.IE = 1;
87178dbd 2117 trace_output (OP_VOID);
2934d1c9
MH		 2118}
2119
2120/* sll */
2121void
2122OP_2200 ()
2123{
87178dbd 2124 trace_input ("sll", OP_REG, OP_REG, OP_VOID);
2934d1c9 2125 State.regs[OP[0]] <<= (State.regs[OP[1]] & 0xf);
87178dbd 2126 trace_output (OP_REG);
2934d1c9
MH		 2127}
2128
2129/* sll */
2130void
2131OP_3200 ()
2132{
4c38885c 2133 int64 tmp;
87178dbd 2134 trace_input ("sll", OP_ACCUM, OP_REG, OP_VOID);
069398aa 2135 if ((State.regs[OP[1]] & 31) <= 16)
4c38885c 2136 tmp = SEXT40 (State.a[OP[0]]) << (State.regs[OP[1]] & 31);
069398aa
MM		 2137 else
2138 {
2139 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31);
2140 State.exception = SIGILL;
2141 return;
2142 }
4c38885c
MH		 2143
2144 if (State.ST)
2145 {
2146 if (tmp > MAX32)
2147 State.a[OP[0]] = MAX32;
2148 else if (tmp < 0xffffff80000000LL)
2149 State.a[OP[0]] = MIN32;
2150 else
2151 State.a[OP[0]] = tmp & MASK40;
2152 }
2153 else
2154 State.a[OP[0]] = tmp & MASK40;
87178dbd 2155 trace_output (OP_ACCUM);
2934d1c9
MH		 2156}
2157
2158/* slli */
2159void
2160OP_2201 ()
2161{
87178dbd 2162 trace_input ("slli", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 2163 State.regs[OP[0]] <<= OP[1];
87178dbd 2164 trace_output (OP_REG);
2934d1c9
MH		 2165}
2166
2167/* slli */
2168void
2169OP_3201 ()
2170{
4c38885c 2171 int64 tmp;
4f425a32
MH		 2172
2173 if (OP[1] == 0)
2174 OP[1] = 16;
4f425a32 2175
87178dbd 2176 trace_input ("slli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
4f425a32 2177 tmp = SEXT40(State.a[OP[0]]) << OP[1];
4c38885c
MH		 2178
2179 if (State.ST)
2180 {
2181 if (tmp > MAX32)
2182 State.a[OP[0]] = MAX32;
2183 else if (tmp < 0xffffff80000000LL)
2184 State.a[OP[0]] = MIN32;
2185 else
2186 State.a[OP[0]] = tmp & MASK40;
2187 }
2188 else
2189 State.a[OP[0]] = tmp & MASK40;
87178dbd 2190 trace_output (OP_ACCUM);
2934d1c9
MH		 2191}
2192
2193/* slx */
2194void
2195OP_460B ()
2196{
87178dbd 2197 trace_input ("slx", OP_REG, OP_FLAG, OP_VOID);
2934d1c9 2198 State.regs[OP[0]] = (State.regs[OP[0]] << 1) | State.F0;
87178dbd 2199 trace_output (OP_REG);
2934d1c9
MH		 2200}
2201
2202/* sra */
2203void
2204OP_2400 ()
2205{
87178dbd 2206 trace_input ("sra", OP_REG, OP_REG, OP_VOID);
2934d1c9 2207 State.regs[OP[0]] = ((int16)(State.regs[OP[0]])) >> (State.regs[OP[1]] & 0xf);
87178dbd 2208 trace_output (OP_REG);
2934d1c9
MH		 2209}
2210
2211/* sra */
2212void
2213OP_3400 ()
2214{
87178dbd 2215 trace_input ("sra", OP_ACCUM, OP_REG, OP_VOID);
069398aa 2216 if ((State.regs[OP[1]] & 31) <= 16)
fd435e9f 2217 State.a[OP[0]] = (SEXT40(State.a[OP[0]]) >> (State.regs[OP[1]] & 31)) & MASK40;
069398aa
MM		 2218 else
2219 {
2220 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31);
2221 State.exception = SIGILL;
2222 return;
2223 }
2224
87178dbd 2225 trace_output (OP_ACCUM);
2934d1c9
MH		 2226}
2227
2228/* srai */
2229void
2230OP_2401 ()
2231{
87178dbd 2232 trace_input ("srai", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 2233 State.regs[OP[0]] = ((int16)(State.regs[OP[0]])) >> OP[1];
87178dbd 2234 trace_output (OP_REG);
2934d1c9
MH		 2235}
2236
2237/* srai */
2238void
2239OP_3401 ()
2240{
4f425a32
MH		 2241 if (OP[1] == 0)
2242 OP[1] = 16;
87178dbd
MM		 2243
2244 trace_input ("srai", OP_ACCUM, OP_CONSTANT16, OP_VOID);
fd435e9f 2245 State.a[OP[0]] = (SEXT40(State.a[OP[0]]) >> OP[1]) & MASK40;
87178dbd 2246 trace_output (OP_ACCUM);
2934d1c9
MH		 2247}
2248
2249/* srl */
2250void
2251OP_2000 ()
2252{
87178dbd 2253 trace_input ("srl", OP_REG, OP_REG, OP_VOID);
2934d1c9 2254 State.regs[OP[0]] >>= (State.regs[OP[1]] & 0xf);
87178dbd 2255 trace_output (OP_REG);
2934d1c9
MH		 2256}
2257
2258/* srl */
2259void
2260OP_3000 ()
2261{
87178dbd 2262 trace_input ("srl", OP_ACCUM, OP_REG, OP_VOID);
069398aa 2263 if ((State.regs[OP[1]] & 31) <= 16)
fd435e9f 2264 State.a[OP[0]] = (uint64)((State.a[OP[0]] & MASK40) >> (State.regs[OP[1]] & 31));
069398aa
MM		 2265 else
2266 {
2267 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31);
2268 State.exception = SIGILL;
2269 return;
2270 }
2271
87178dbd 2272 trace_output (OP_ACCUM);
2934d1c9
MH		 2273}
2274
2275/* srli */
2276void
2277OP_2001 ()
2278{
87178dbd 2279 trace_input ("srli", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 2280 State.regs[OP[0]] >>= OP[1];
87178dbd 2281 trace_output (OP_REG);
2934d1c9
MH		 2282}
2283
2284/* srli */
2285void
2286OP_3001 ()
2287{
4f425a32
MH		 2288 if (OP[1] == 0)
2289 OP[1] = 16;
87178dbd
MM		 2290
2291 trace_input ("srli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
fd435e9f 2292 State.a[OP[0]] = (uint64)(State.a[OP[0]] & MASK40) >> OP[1];
87178dbd 2293 trace_output (OP_ACCUM);
2934d1c9
MH		 2294}
2295
2296/* srx */
2297void
2298OP_4609 ()
2299{
2300 uint16 tmp;
87178dbd
MM		 2301
2302 trace_input ("srx", OP_REG, OP_FLAG, OP_VOID);
2934d1c9
MH		 2303 tmp = State.F0 << 15;
2304 State.regs[OP[0]] = (State.regs[OP[0]] >> 1) | tmp;
87178dbd 2305 trace_output (OP_REG);
2934d1c9
MH		 2306}
2307
2308/* st */
2309void
2310OP_34000000 ()
2311{
87178dbd 2312 trace_input ("st", OP_REG, OP_MEMREF2, OP_VOID);
2934d1c9 2313 SW (OP[1] + State.regs[OP[2]], State.regs[OP[0]]);
87178dbd 2314 trace_output (OP_VOID);
2934d1c9
MH		 2315}
2316
2317/* st */
2318void
2319OP_6800 ()
2320{
87178dbd 2321 trace_input ("st", OP_REG, OP_MEMREF, OP_VOID);
2934d1c9 2322 SW (State.regs[OP[1]], State.regs[OP[0]]);
87178dbd 2323 trace_output (OP_VOID);
2934d1c9
MH		 2324}
2325
2326/* st */
2327void
2328OP_6C1F ()
2329{
87178dbd 2330 trace_input ("st", OP_REG, OP_PREDEC, OP_VOID);
4c38885c
MH		 2331 if ( OP[1] != 15 )
2332 {
7eebfc62 2333 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
4f425a32
MH		 2334 State.exception = SIGILL;
2335 return;
4c38885c
MH		 2336 }
2337 State.regs[OP[1]] -= 2;
2338 SW (State.regs[OP[1]], State.regs[OP[0]]);
87178dbd 2339 trace_output (OP_VOID);
2934d1c9
MH		 2340}
2341
2342/* st */
2343void
2344OP_6801 ()
2345{
87178dbd 2346 trace_input ("st", OP_REG, OP_POSTINC, OP_VOID);
4c38885c 2347 SW (State.regs[OP[1]], State.regs[OP[0]]);
4f425a32 2348 INC_ADDR (State.regs[OP[1]],2);
87178dbd 2349 trace_output (OP_VOID);
2934d1c9
MH		 2350}
2351
2352/* st */
2353void
2354OP_6C01 ()
2355{
87178dbd 2356 trace_input ("st", OP_REG, OP_POSTDEC, OP_VOID);
fd435e9f
MM		 2357 if ( OP[1] == 15 )
2358 {
2359 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot post-decrement register r15 (SP).\n");
2360 State.exception = SIGILL;
2361 return;
2362 }
4c38885c 2363 SW (State.regs[OP[1]], State.regs[OP[0]]);
4f425a32 2364 INC_ADDR (State.regs[OP[1]],-2);
87178dbd 2365 trace_output (OP_VOID);
2934d1c9
MH		 2366}
2367
2368/* st2w */
2369void
2370OP_35000000 ()
2371{
87178dbd 2372 trace_input ("st2w", OP_DREG, OP_MEMREF2, OP_VOID);
4f425a32
MH		 2373 SW (State.regs[OP[2]]+OP[1], State.regs[OP[0]]);
2374 SW (State.regs[OP[2]]+OP[1]+2, State.regs[OP[0]+1]);
87178dbd 2375 trace_output (OP_VOID);
2934d1c9
MH		 2376}
2377
2378/* st2w */
2379void
2380OP_6A00 ()
2381{
a18cb100 2382 trace_input ("st2w", OP_DREG, OP_MEMREF, OP_VOID);
4c38885c
MH		 2383 SW (State.regs[OP[1]], State.regs[OP[0]]);
2384 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
87178dbd 2385 trace_output (OP_VOID);
2934d1c9
MH		 2386}
2387
2388/* st2w */
2389void
2390OP_6E1F ()
2391{
a18cb100 2392 trace_input ("st2w", OP_DREG, OP_PREDEC, OP_VOID);
4c38885c
MH		 2393 if ( OP[1] != 15 )
2394 {
7eebfc62 2395 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
4f425a32
MH		 2396 State.exception = SIGILL;
2397 return;
4c38885c
MH		 2398 }
2399 State.regs[OP[1]] -= 4;
2400 SW (State.regs[OP[1]], State.regs[OP[0]]);
2401 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
87178dbd 2402 trace_output (OP_VOID);
2934d1c9
MH		 2403}
2404
2405/* st2w */
2406void
2407OP_6A01 ()
2408{
1155e06e 2409 trace_input ("st2w", OP_DREG, OP_POSTINC, OP_VOID);
4c38885c
MH		 2410 SW (State.regs[OP[1]], State.regs[OP[0]]);
2411 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
4f425a32 2412 INC_ADDR (State.regs[OP[1]],4);
87178dbd 2413 trace_output (OP_VOID);
2934d1c9
MH		 2414}
2415
2416/* st2w */
2417void
2418OP_6E01 ()
2419{
1155e06e
FF		 2420 trace_input ("st2w", OP_DREG, OP_POSTDEC, OP_VOID);
2421 if ( OP[1] == 15 )
2422 {
2423 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot post-decrement register r15 (SP).\n");
2424 State.exception = SIGILL;
2425 return;
2426 }
4c38885c
MH		 2427 SW (State.regs[OP[1]], State.regs[OP[0]]);
2428 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
4f425a32 2429 INC_ADDR (State.regs[OP[1]],-4);
87178dbd 2430 trace_output (OP_VOID);
2934d1c9
MH		 2431}
2432
2433/* stb */
2434void
2435OP_3C000000 ()
2436{
87178dbd 2437 trace_input ("stb", OP_REG, OP_MEMREF2, OP_VOID);
4f425a32 2438 SB (State.regs[OP[2]]+OP[1], State.regs[OP[0]]);
87178dbd 2439 trace_output (OP_VOID);
2934d1c9
MH		 2440}
2441
2442/* stb */
2443void
2444OP_7800 ()
2445{
87178dbd 2446 trace_input ("stb", OP_REG, OP_MEMREF, OP_VOID);
4c38885c 2447 SB (State.regs[OP[1]], State.regs[OP[0]]);
87178dbd 2448 trace_output (OP_VOID);
2934d1c9
MH		 2449}
2450
2451/* stop */
2452void
2453OP_5FE0 ()
2454{
87178dbd 2455 trace_input ("stop", OP_VOID, OP_VOID, OP_VOID);
a49a15ad 2456 State.exception = SIG_D10V_STOP;
87178dbd 2457 trace_output (OP_VOID);
2934d1c9
MH		 2458}
2459
2460/* sub */
2461void
2462OP_0 ()
4c38885c 2463{
f4b022d3 2464 uint16 tmp;
87178dbd
MM		 2465
2466 trace_input ("sub", OP_REG, OP_REG, OP_VOID);
aa49c64f
AC		 2467 /* see ../common/sim-alu.h for a more extensive discussion on how to
2468 compute the carry/overflow bits. */
f4b022d3 2469 tmp = State.regs[OP[0]] - State.regs[OP[1]];
aa49c64f 2470 State.C = ((uint16) State.regs[OP[0]] >= (uint16) State.regs[OP[1]]);
f4b022d3 2471 State.regs[OP[0]] = tmp;
87178dbd 2472 trace_output (OP_REG);
4c38885c
MH		 2473}
2474
2475/* sub */
2476void
2477OP_1001 ()
2478{
4f425a32 2479 int64 tmp;
87178dbd
MM		 2480
2481 trace_input ("sub", OP_ACCUM, OP_DREG, OP_VOID);
4f425a32
MH		 2482 tmp = SEXT40(State.a[OP[0]]) - (SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]);
2483 if (State.ST)
2484 {
2485 if ( tmp > MAX32)
2486 State.a[OP[0]] = MAX32;
2487 else if ( tmp < MIN32)
2488 State.a[OP[0]] = MIN32;
2489 else
2490 State.a[OP[0]] = tmp & MASK40;
2491 }
2492 else
2493 State.a[OP[0]] = tmp & MASK40;
87178dbd
MM		 2494
2495 trace_output (OP_ACCUM);
4c38885c
MH		 2496}
2497
2498/* sub */
2499
2500void
2501OP_1003 ()
2934d1c9 2502{
4f425a32 2503 int64 tmp;
87178dbd
MM		 2504
2505 trace_input ("sub", OP_ACCUM, OP_ACCUM, OP_VOID);
4f425a32
MH		 2506 tmp = SEXT40(State.a[OP[0]]) - SEXT40(State.a[OP[1]]);
2507 if (State.ST)
2508 {
2509 if (tmp > MAX32)
2510 State.a[OP[0]] = MAX32;
2511 else if ( tmp < MIN32)
2512 State.a[OP[0]] = MIN32;
2513 else
2514 State.a[OP[0]] = tmp & MASK40;
2515 }
2516 else
2517 State.a[OP[0]] = tmp & MASK40;
87178dbd
MM		 2518
2519 trace_output (OP_ACCUM);
2934d1c9
MH		 2520}
2521
2522/* sub2w */
2523void
2524OP_1000 ()
2525{
f4b022d3 2526 uint32 tmp,a,b;
4c38885c 2527
87178dbd 2528 trace_input ("sub2w", OP_DREG, OP_DREG, OP_VOID);
f4b022d3
MM		 2529 a = (uint32)((State.regs[OP[0]] << 16) | State.regs[OP[0]+1]);
2530 b = (uint32)((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
70ee56c5
AC		 2531 /* see ../common/sim-alu.h for a more extensive discussion on how to
2532 compute the carry/overflow bits */
2533 tmp = a - b;
51b057f2 2534 State.C = (a >= b);
4c38885c
MH		 2535 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2536 State.regs[OP[0]+1] = tmp & 0xffff;
87178dbd 2537 trace_output (OP_DREG);
2934d1c9
MH		 2538}
2539
2540/* subac3 */
2541void
2542OP_17000000 ()
2543{
4f425a32 2544 int64 tmp;
87178dbd
MM		 2545
2546 trace_input ("subac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
4f425a32
MH		 2547 tmp = SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]) - SEXT40 (State.a[OP[2]]);
2548 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2549 State.regs[OP[0]+1] = tmp & 0xffff;
87178dbd 2550 trace_output (OP_DREG);
2934d1c9
MH		 2551}
2552
2553/* subac3 */
2554void
2555OP_17000002 ()
2556{
4f425a32 2557 int64 tmp;
87178dbd
MM		 2558
2559 trace_input ("subac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
4f425a32
MH		 2560 tmp = SEXT40(State.a[OP[1]]) - SEXT40(State.a[OP[2]]);
2561 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2562 State.regs[OP[0]+1] = tmp & 0xffff;
87178dbd 2563 trace_output (OP_DREG);
2934d1c9
MH		 2564}
2565
2566/* subac3s */
2567void
2568OP_17001000 ()
2569{
4f425a32 2570 int64 tmp;
87178dbd
MM		 2571
2572 trace_input ("subac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
4f425a32
MH		 2573 State.F1 = State.F0;
2574 tmp = SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]) - SEXT40(State.a[OP[2]]);
2575 if ( tmp > MAX32)
2576 {
2577 State.regs[OP[0]] = 0x7fff;
2578 State.regs[OP[0]+1] = 0xffff;
2579 State.F0 = 1;
2580 }
2581 else if (tmp < MIN32)
2582 {
2583 State.regs[OP[0]] = 0x8000;
2584 State.regs[OP[0]+1] = 0;
2585 State.F0 = 1;
2586 }
2587 else
2588 {
2589 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2590 State.regs[OP[0]+1] = tmp & 0xffff;
2591 State.F0 = 0;
2592 }
87178dbd 2593 trace_output (OP_DREG);
2934d1c9
MH		 2594}
2595
2596/* subac3s */
2597void
2598OP_17001002 ()
2599{
4f425a32 2600 int64 tmp;
87178dbd
MM		 2601
2602 trace_input ("subac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
4f425a32
MH		 2603 State.F1 = State.F0;
2604 tmp = SEXT40(State.a[OP[1]]) - SEXT40(State.a[OP[2]]);
2605 if ( tmp > MAX32)
2606 {
2607 State.regs[OP[0]] = 0x7fff;
2608 State.regs[OP[0]+1] = 0xffff;
2609 State.F0 = 1;
2610 }
2611 else if (tmp < MIN32)
2612 {
2613 State.regs[OP[0]] = 0x8000;
2614 State.regs[OP[0]+1] = 0;
2615 State.F0 = 1;
2616 }
2617 else
2618 {
2619 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2620 State.regs[OP[0]+1] = tmp & 0xffff;
2621 State.F0 = 0;
2622 }
87178dbd 2623 trace_output (OP_DREG);
2934d1c9
MH		 2624}
2625
2626/* subi */
2627void
2628OP_1 ()
2629{
70ee56c5 2630 unsigned tmp;
4f425a32
MH		 2631 if (OP[1] == 0)
2632 OP[1] = 16;
87178dbd
MM		 2633
2634 trace_input ("subi", OP_REG, OP_CONSTANT16, OP_VOID);
70ee56c5 2635 /* see ../common/sim-alu.h for a more extensive discussion on how to
51b057f2
AC		 2636 compute the carry/overflow bits. */
2637 /* since OP[1] is never <= 0, -OP[1] == ~OP[1]+1 can never overflow */
70ee56c5
AC		 2638 tmp = ((unsigned)(unsigned16) State.regs[OP[0]]
2639 + (unsigned)(unsigned16) ( - OP[1]));
2640 State.C = (tmp >= (1 << 16));
2641 State.regs[OP[0]] = tmp;
87178dbd 2642 trace_output (OP_REG);
2934d1c9
MH		 2643}
2644
2645/* trap */
2646void
2647OP_5F00 ()
2648{
a5719092 2649 trace_input ("trap", OP_CONSTANT4, OP_VOID, OP_VOID);
87178dbd 2650 trace_output (OP_VOID);
8918b3a7 2651
63a91cfb 2652 switch (OP[0])
2934d1c9 2653 {
63a91cfb 2654 default:
19431a02 2655#if (DEBUG & DEBUG_TRAP) == 0
19d44375 2656 {
bc6df23d
AC		 2657 uint16 vec = OP[0] + TRAP_VECTOR_START;
2658 BPC = PC + 1;
2659 move_to_cr (BPSW_CR, PSW);
2660 move_to_cr (PSW_CR, PSW & PSW_SM_BIT);
2661 JMP (vec);
19431a02 2662 break;
87e43259 2663 }
19431a02
AC		 2664#else /* if debugging use trap to print registers */
2665 {
2666 int i;
2667 static int first_time = 1;
2668
2669 if (first_time)
2670 {
2671 first_time = 0;
2672 (*d10v_callback->printf_filtered) (d10v_callback, "Trap # PC ");
2673 for (i = 0; i < 16; i++)
2674 (*d10v_callback->printf_filtered) (d10v_callback, " %sr%d", (i > 9) ? "" : " ", i);
2675 (*d10v_callback->printf_filtered) (d10v_callback, " a0 a1 f0 f1 c\n");
2676 }
2677
2678 (*d10v_callback->printf_filtered) (d10v_callback, "Trap %2d 0x%.4x:", (int)OP[0], (int)PC);
2679
2680 for (i = 0; i < 16; i++)
2681 (*d10v_callback->printf_filtered) (d10v_callback, " %.4x", (int) State.regs[i]);
2682
2683 for (i = 0; i < 2; i++)
2684 (*d10v_callback->printf_filtered) (d10v_callback, " %.2x%.8lx",
2685 ((int)(State.a[i] >> 32) & 0xff),
2686 ((unsigned long)State.a[i]) & 0xffffffff);
2687
2688 (*d10v_callback->printf_filtered) (d10v_callback, " %d %d %d\n",
2689 State.F0 != 0, State.F1 != 0, State.C != 0);
2690 (*d10v_callback->flush_stdout) (d10v_callback);
2691 break;
2692 }
2693#endif
87e43259
AC		 2694 case 15: /* new system call trap */
2695 /* Trap 15 is used for simulating low-level I/O */
63a91cfb 2696 {
63a91cfb
MM		 2697 errno = 0;
2698
2699/* Registers passed to trap 0 */
2700
8831cb01
MM		 2701#define FUNC State.regs[4] /* function number */
2702#define PARM1 State.regs[0] /* optional parm 1 */
2703#define PARM2 State.regs[1] /* optional parm 2 */
2704#define PARM3 State.regs[2] /* optional parm 3 */
2705#define PARM4 State.regs[3] /* optional parm 3 */
63a91cfb
MM		 2706
2707/* Registers set by trap 0 */
2708
8831cb01
MM		 2709#define RETVAL State.regs[0] /* return value */
2710#define RETVAL_HIGH State.regs[0] /* return value */
2711#define RETVAL_LOW State.regs[1] /* return value */
65c0d7de 2712#define RETERR State.regs[4] /* return error code */
63a91cfb
MM		 2713
2714/* Turn a pointer in a register into a pointer into real memory. */
2715
c422ecc7 2716#define MEMPTR(x) ((char *)(dmem_addr(x)))
63a91cfb
MM		 2717
2718 switch (FUNC)
2719 {
2720#if !defined(__GO32__) && !defined(_WIN32)
63a91cfb
MM		 2721 case SYS_fork:
2722 RETVAL = fork ();
8918b3a7 2723 trace_input ("<fork>", OP_VOID, OP_VOID, OP_VOID);
8831cb01 2724 trace_output (OP_R0);
63a91cfb 2725 break;
8918b3a7 2726
57bc1a72
MM		 2727 case SYS_getpid:
2728 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
2729 RETVAL = getpid ();
8831cb01 2730 trace_output (OP_R0);
57bc1a72
MM		 2731 break;
2732
2733 case SYS_kill:
2734 trace_input ("<kill>", OP_REG, OP_REG, OP_VOID);
2735 if (PARM1 == getpid ())
2736 {
2737 trace_output (OP_VOID);
2738 State.exception = PARM2;
2739 }
2740 else
2741 {
2742 int os_sig = -1;
2743 switch (PARM2)
2744 {
2745#ifdef SIGHUP
2746 case 1: os_sig = SIGHUP; break;
2747#endif
2748#ifdef SIGINT
2749 case 2: os_sig = SIGINT; break;
2750#endif
2751#ifdef SIGQUIT
2752 case 3: os_sig = SIGQUIT; break;
2753#endif
2754#ifdef SIGILL
2755 case 4: os_sig = SIGILL; break;
2756#endif
2757#ifdef SIGTRAP
2758 case 5: os_sig = SIGTRAP; break;
2759#endif
2760#ifdef SIGABRT
2761 case 6: os_sig = SIGABRT; break;
2762#elif defined(SIGIOT)
2763 case 6: os_sig = SIGIOT; break;
2764#endif
2765#ifdef SIGEMT
2766 case 7: os_sig = SIGEMT; break;
2767#endif
2768#ifdef SIGFPE
2769 case 8: os_sig = SIGFPE; break;
2770#endif
2771#ifdef SIGKILL
2772 case 9: os_sig = SIGKILL; break;
2773#endif
2774#ifdef SIGBUS
2775 case 10: os_sig = SIGBUS; break;
2776#endif
2777#ifdef SIGSEGV
2778 case 11: os_sig = SIGSEGV; break;
2779#endif
2780#ifdef SIGSYS
2781 case 12: os_sig = SIGSYS; break;
2782#endif
2783#ifdef SIGPIPE
2784 case 13: os_sig = SIGPIPE; break;
2785#endif
2786#ifdef SIGALRM
2787 case 14: os_sig = SIGALRM; break;
2788#endif
2789#ifdef SIGTERM
2790 case 15: os_sig = SIGTERM; break;
2791#endif
2792#ifdef SIGURG
2793 case 16: os_sig = SIGURG; break;
2794#endif
2795#ifdef SIGSTOP
2796 case 17: os_sig = SIGSTOP; break;
2797#endif
2798#ifdef SIGTSTP
2799 case 18: os_sig = SIGTSTP; break;
2800#endif
2801#ifdef SIGCONT
2802 case 19: os_sig = SIGCONT; break;
2803#endif
2804#ifdef SIGCHLD
2805 case 20: os_sig = SIGCHLD; break;
2806#elif defined(SIGCLD)
2807 case 20: os_sig = SIGCLD; break;
2808#endif
2809#ifdef SIGTTIN
2810 case 21: os_sig = SIGTTIN; break;
2811#endif
2812#ifdef SIGTTOU
2813 case 22: os_sig = SIGTTOU; break;
2814#endif
2815#ifdef SIGIO
2816 case 23: os_sig = SIGIO; break;
2817#elif defined (SIGPOLL)
2818 case 23: os_sig = SIGPOLL; break;
2819#endif
2820#ifdef SIGXCPU
2821 case 24: os_sig = SIGXCPU; break;
2822#endif
2823#ifdef SIGXFSZ
2824 case 25: os_sig = SIGXFSZ; break;
2825#endif
2826#ifdef SIGVTALRM
2827 case 26: os_sig = SIGVTALRM; break;
2828#endif
2829#ifdef SIGPROF
2830 case 27: os_sig = SIGPROF; break;
2831#endif
2832#ifdef SIGWINCH
2833 case 28: os_sig = SIGWINCH; break;
2834#endif
2835#ifdef SIGLOST
2836 case 29: os_sig = SIGLOST; break;
2837#endif
2838#ifdef SIGUSR1
2839 case 30: os_sig = SIGUSR1; break;
2840#endif
2841#ifdef SIGUSR2
2842 case 31: os_sig = SIGUSR2; break;
2843#endif
2844 }
2845
2846 if (os_sig == -1)
2847 {
2848 trace_output (OP_VOID);
2849 (*d10v_callback->printf_filtered) (d10v_callback, "Unknown signal %d\n", PARM2);
fd435e9f 2850 (*d10v_callback->flush_stdout) (d10v_callback);
57bc1a72
MM		 2851 State.exception = SIGILL;
2852 }
2853 else
2854 {
2855 RETVAL = kill (PARM1, PARM2);
8831cb01 2856 trace_output (OP_R0);
57bc1a72
MM		 2857 }
2858 }
2859 break;
2860
63a91cfb
MM		 2861 case SYS_execve:
2862 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2),
2863 (char **)MEMPTR (PARM3));
8831cb01
MM		 2864 trace_input ("<execve>", OP_R0, OP_R1, OP_R2);
2865 trace_output (OP_R0);
63a91cfb 2866 break;
8918b3a7 2867
87e43259 2868#ifdef SYS_execv
63a91cfb
MM		 2869 case SYS_execv:
2870 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL);
8831cb01
MM		 2871 trace_input ("<execv>", OP_R0, OP_R1, OP_VOID);
2872 trace_output (OP_R0);
63a91cfb 2873 break;
87e43259 2874#endif
8918b3a7 2875
63a91cfb
MM		 2876 case SYS_pipe:
2877 {
2878 reg_t buf;
2879 int host_fd[2];
2880
2881 buf = PARM1;
2882 RETVAL = pipe (host_fd);
2883 SW (buf, host_fd[0]);
2884 buf += sizeof(uint16);
2885 SW (buf, host_fd[1]);
8831cb01
MM		 2886 trace_input ("<pipe>", OP_R0, OP_VOID, OP_VOID);
2887 trace_output (OP_R0);
63a91cfb
MM		 2888 }
2889 break;
8918b3a7 2890
87e43259 2891#ifdef SYS_wait
63a91cfb
MM		 2892 case SYS_wait:
2893 {
2894 int status;
2895
2896 RETVAL = wait (&status);
8918b3a7
MM		 2897 if (PARM1)
2898 SW (PARM1, status);
8831cb01
MM		 2899 trace_input ("<wait>", OP_R0, OP_VOID, OP_VOID);
2900 trace_output (OP_R0);
63a91cfb
MM		 2901 }
2902 break;
87e43259 2903#endif
57bc1a72
MM		 2904#else
2905 case SYS_getpid:
2906 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
2907 RETVAL = 1;
8831cb01 2908 trace_output (OP_R0);
57bc1a72
MM		 2909 break;
2910
2911 case SYS_kill:
2912 trace_input ("<kill>", OP_REG, OP_REG, OP_VOID);
2913 trace_output (OP_VOID);
2914 State.exception = PARM2;
2915 break;
63a91cfb 2916#endif
8918b3a7 2917
63a91cfb
MM		 2918 case SYS_read:
2919 RETVAL = d10v_callback->read (d10v_callback, PARM1, MEMPTR (PARM2),
2920 PARM3);
8831cb01
MM		 2921 trace_input ("<read>", OP_R0, OP_R1, OP_R2);
2922 trace_output (OP_R0);
63a91cfb 2923 break;
8918b3a7 2924
63a91cfb
MM		 2925 case SYS_write:
2926 if (PARM1 == 1)
2927 RETVAL = (int)d10v_callback->write_stdout (d10v_callback,
2928 MEMPTR (PARM2), PARM3);
2929 else
2930 RETVAL = (int)d10v_callback->write (d10v_callback, PARM1,
2931 MEMPTR (PARM2), PARM3);
8831cb01
MM		 2932 trace_input ("<write>", OP_R0, OP_R1, OP_R2);
2933 trace_output (OP_R0);
63a91cfb 2934 break;
8918b3a7 2935
63a91cfb 2936 case SYS_lseek:
65c0d7de
MA		 2937 {
2938 unsigned long ret = d10v_callback->lseek (d10v_callback, PARM1,
2939 (((unsigned long)PARM2) << 16) || (unsigned long)PARM3,
2940 PARM4);
2941 RETVAL_HIGH = ret >> 16;
2942 RETVAL_LOW = ret & 0xffff;
2943 }
8831cb01
MM		 2944 trace_input ("<lseek>", OP_R0, OP_R1, OP_R2);
2945 trace_output (OP_R0R1);
63a91cfb 2946 break;
8918b3a7 2947
63a91cfb
MM		 2948 case SYS_close:
2949 RETVAL = d10v_callback->close (d10v_callback, PARM1);
8831cb01
MM		 2950 trace_input ("<close>", OP_R0, OP_VOID, OP_VOID);
2951 trace_output (OP_R0);
63a91cfb 2952 break;
8918b3a7 2953
63a91cfb
MM		 2954 case SYS_open:
2955 RETVAL = d10v_callback->open (d10v_callback, MEMPTR (PARM1), PARM2);
8831cb01
MM		 2956 trace_input ("<open>", OP_R0, OP_R1, OP_R2);
2957 trace_output (OP_R0);
2958 trace_input ("<open>", OP_R0, OP_R1, OP_R2);
2959 trace_output (OP_R0);
63a91cfb 2960 break;
8918b3a7 2961
63a91cfb 2962 case SYS_exit:
a49a15ad 2963 State.exception = SIG_D10V_EXIT;
8831cb01 2964 trace_input ("<exit>", OP_R0, OP_VOID, OP_VOID);
8918b3a7 2965 trace_output (OP_VOID);
63a91cfb 2966 break;
63a91cfb 2967
8719be26 2968 case SYS_stat:
63a91cfb
MM		 2969 /* stat system call */
2970 {
2971 struct stat host_stat;
2972 reg_t buf;
2973
2974 RETVAL = stat (MEMPTR (PARM1), &host_stat);
2975
2976 buf = PARM2;
2977
2978 /* The hard-coded offsets and sizes were determined by using
2979 * the D10V compiler on a test program that used struct stat.
2980 */
2981 SW (buf, host_stat.st_dev);
2982 SW (buf+2, host_stat.st_ino);
2983 SW (buf+4, host_stat.st_mode);
2984 SW (buf+6, host_stat.st_nlink);
2985 SW (buf+8, host_stat.st_uid);
2986 SW (buf+10, host_stat.st_gid);
2987 SW (buf+12, host_stat.st_rdev);
2988 SLW (buf+16, host_stat.st_size);
2989 SLW (buf+20, host_stat.st_atime);
2990 SLW (buf+28, host_stat.st_mtime);
2991 SLW (buf+36, host_stat.st_ctime);
2992 }
8831cb01
MM		 2993 trace_input ("<stat>", OP_R0, OP_R1, OP_VOID);
2994 trace_output (OP_R0);
63a91cfb 2995 break;
63a91cfb 2996
63a91cfb
MM		 2997 case SYS_chown:
2998 RETVAL = chown (MEMPTR (PARM1), PARM2, PARM3);
8831cb01
MM		 2999 trace_input ("<chown>", OP_R0, OP_R1, OP_R2);
3000 trace_output (OP_R0);
63a91cfb 3001 break;
8918b3a7 3002
63a91cfb
MM		 3003 case SYS_chmod:
3004 RETVAL = chmod (MEMPTR (PARM1), PARM2);
8831cb01
MM		 3005 trace_input ("<chmod>", OP_R0, OP_R1, OP_R2);
3006 trace_output (OP_R0);
63a91cfb 3007 break;
8918b3a7 3008
87e43259 3009#ifdef SYS_utime
63a91cfb
MM		 3010 case SYS_utime:
3011 /* Cast the second argument to void *, to avoid type mismatch
3012 if a prototype is present. */
3013 RETVAL = utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2));
8831cb01
MM		 3014 trace_input ("<utime>", OP_R0, OP_R1, OP_R2);
3015 trace_output (OP_R0);
8918b3a7 3016 break;
87e43259 3017#endif
8918b3a7 3018
87e43259 3019#ifdef SYS_time
8918b3a7
MM		 3020 case SYS_time:
3021 {
3022 unsigned long ret = time (PARM1 ? MEMPTR (PARM1) : NULL);
3023 RETVAL_HIGH = ret >> 16;
3024 RETVAL_LOW = ret & 0xffff;
3025 }
8831cb01
MM		 3026 trace_input ("<time>", OP_R0, OP_R1, OP_R2);
3027 trace_output (OP_R0R1);
63a91cfb 3028 break;
87e43259 3029#endif
8918b3a7 3030
63a91cfb 3031 default:
b41dff6b 3032 d10v_callback->error (d10v_callback, "Unknown syscall %d", FUNC);
63a91cfb 3033 }
87e43259 3034 RETERR = (RETVAL == (uint16) -1) ? d10v_callback->get_errno(d10v_callback) : 0;
63a91cfb
MM		 3035 break;
3036 }
2934d1c9
MH		 3037 }
3038}
3039
3040/* tst0i */
3041void
3042OP_7000000 ()
3043{
87178dbd 3044 trace_input ("tst0i", OP_REG, OP_CONSTANT16, OP_VOID);
4c38885c 3045 State.F1 = State.F0;
4f425a32 3046 State.F0 = (State.regs[OP[0]] & OP[1]) ? 1 : 0;
87178dbd 3047 trace_output (OP_FLAG);
2934d1c9
MH		 3048}
3049
3050/* tst1i */
3051void
3052OP_F000000 ()
3053{
87178dbd 3054 trace_input ("tst1i", OP_REG, OP_CONSTANT16, OP_VOID);
4c38885c 3055 State.F1 = State.F0;
4f425a32 3056 State.F0 = (~(State.regs[OP[0]]) & OP[1]) ? 1 : 0;
87178dbd 3057 trace_output (OP_FLAG);
2934d1c9
MH		 3058}
3059
3060/* wait */
3061void
3062OP_5F80 ()
3063{
87178dbd 3064 trace_input ("wait", OP_VOID, OP_VOID, OP_VOID);
4c38885c 3065 State.IE = 1;
87178dbd 3066 trace_output (OP_VOID);
2934d1c9
MH		 3067}
3068
3069/* xor */
3070void
3071OP_A00 ()
3072{
87178dbd 3073 trace_input ("xor", OP_REG, OP_REG, OP_VOID);
4c38885c 3074 State.regs[OP[0]] ^= State.regs[OP[1]];
87178dbd 3075 trace_output (OP_REG);
2934d1c9
MH		 3076}
3077
3078/* xor3 */
3079void
3080OP_5000000 ()
3081{
87178dbd 3082 trace_input ("xor3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
4c38885c 3083 State.regs[OP[0]] = State.regs[OP[1]] ^ OP[2];
87178dbd 3084 trace_output (OP_REG);
2934d1c9
MH		 3085}
3086
GDB Binutils - Deliverables
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