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* config/vx-gdb.exp (gdb_start): Fix syntax of `$shell_id < 0'.
[deliverable/binutils-gdb.git] / sim / d10v / simops.c
CommitLineData
2934d1c9
MH		 1#include "d10v_sim.h"
2#include "simops.h"
3
4/* #define DEBUG 1 */
5
6/* abs */
7void
8OP_4607 ()
9{
10#ifdef DEBUG
11 printf(" abs\tr%d\n",OP[0]);
12#endif
13 State.F1 = State.F0;
14 if ((int16)(State.regs[OP[0]]) < 0)
15 {
16 State.regs[OP[0]] = -(int16)(State.regs[OP[0]]);
17 State.F0 = 1;
18 }
19 else
20 State.F0 = 0;
21}
22
23/* abs */
24void
25OP_5607 ()
26{
27 int64 tmp;
28
29#ifdef DEBUG
30 printf(" abs\ta%d\n",OP[0]);
31#endif
32 State.F1 = State.F0;
33 if (State.a[OP[0]] & BIT40 )
34 {
35 tmp = -State.a[OP[0]] & MASK40;
36 if (State.ST)
37 {
38 if ( !(tmp & BIT40) && (tmp > MAX32))
39 State.a[OP[0]] = MAX32;
40 else if ( (tmp & BIT40) && (tmp < MIN32))
41 State.a[OP[0]] = MIN32;
42 else
43 State.a[OP[0]] = tmp;
44 }
45 else
46 State.a[OP[0]] = tmp;
47 State.F0 = 1;
48 }
49 else
50 State.F0 = 0;
51}
52
53/* add */
54void
55OP_200 ()
56{
57 uint16 tmp = State.regs[OP[0]];
58#ifdef DEBUG
59 printf(" add\tr%d,r%d\n",OP[0],OP[1]);
60#endif
61 State.regs[OP[0]] += State.regs[OP[1]];
62 if ( tmp > State.regs[OP[0]])
63 State.C = 1;
64 else
65 State.C = 0;
66}
67
68/* add */
69void
70OP_1201 ()
71{
72#ifdef DEBUG
73 printf(" add\ta%d,r%d\n",OP[0],OP[1]);
74#endif
75}
76
77/* add */
78void
79OP_1203 ()
80{
81#ifdef DEBUG
82printf(" add\t%x,%x\n",OP[0],OP[1]);
83#endif
84}
85
86/* add2w */
87void
88OP_1200 ()
89{
90 uint32 tmp;
91 uint32 tmp1 = (State.regs[OP[0]]) << 16 | State.regs[OP[0]+1];
92 uint32 tmp2 = (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
93#ifdef DEBUG
94 printf(" add2w\tr%d,r%d\n",OP[0],OP[1]);
95#endif
96 tmp = tmp1 + tmp2;
97 if ( (tmp < tmp1) || (tmp < tmp2) )
98 State.C = 1;
99 else
100 State.C = 0;
101 State.regs[OP[0]] = tmp >> 16;
102 State.regs[OP[0]+1] = tmp & 0xFFFF;
103}
104
105/* add3 */
106void
107OP_1000000 ()
108{
109 uint16 tmp = State.regs[OP[0]];
110#ifdef DEBUG
111 printf(" add3\tr%d,r%d,0x%x\n",OP[0],OP[1],OP[2]);
112#endif
113 State.regs[OP[0]] = State.regs[OP[1]] + OP[2];
114 if ( tmp > State.regs[OP[0]])
115 State.C = 1;
116 else
117 State.C = 0;
118}
119
120/* addac3 */
121void
122OP_17000200 ()
123{
124#ifdef DEBUG
125printf(" addac3\t%x,%x,%x\n",OP[0],OP[1],OP[2]);
126#endif
127}
128
129/* addac3 */
130void
131OP_17000202 ()
132{
133#ifdef DEBUG
134printf(" addac3\t%x,%x,%x\n",OP[0],OP[1],OP[2]);
135#endif
136}
137
138/* addac3s */
139void
140OP_17001200 ()
141{
142#ifdef DEBUG
143printf(" addac3s\t%x,%x,%x\n",OP[0],OP[1],OP[2]);
144#endif
145}
146
147/* addac3s */
148void
149OP_17001202 ()
150{
151#ifdef DEBUG
152printf(" addac3s\t%x,%x,%x\n",OP[0],OP[1],OP[2]);
153#endif
154}
155
156/* addi */
157void
158OP_201 ()
159{
160#ifdef DEBUG
161 printf(" addi\tr%d,0x%x\n",OP[0],OP[1]);
162#endif
163 State.regs[OP[0]] += OP[1];
164}
165
166/* and */
167void
168OP_C00 ()
169{
170#ifdef DEBUG
171 printf(" and\tr%d,r%d\n",OP[0],OP[1]);
172#endif
173 State.regs[OP[0]] &= State.regs[OP[1]];
174}
175
176/* and3 */
177void
178OP_6000000 ()
179{
180#ifdef DEBUG
181 printf(" and3\tr%d,r%d,0x%x\n",OP[0],OP[1],OP[2]);
182#endif
183 State.regs[OP[0]] = State.regs[OP[1]] & OP[2];
184}
185
186/* bclri */
187void
188OP_C01 ()
189{
190#ifdef DEBUG
191 printf(" bclri\tr%d,%d\n",OP[0],OP[1]);
192#endif
193 State.regs[OP[0]] &= ~(0x8000 >> OP[1]);
194}
195
196/* bl.s */
197void
198OP_4900 ()
199{
200#ifdef DEBUG
201 printf(" bl.s\t0x%x\n",OP[0]);
202#endif
203 State.regs[13] = PC+1;
204 PC += SEXT8 (OP[0]);
205}
206
207/* bl.l */
208void
209OP_24800000 ()
210{
211#ifdef DEBUG
212 printf(" bl.l\t0x%x\n",OP[0]);
213#endif
214 State.regs[13] = PC+1;
215 PC += OP[0];
216}
217
218/* bnoti */
219void
220OP_A01 ()
221{
222#ifdef DEBUG
223 printf(" bnoti\tr%d,%d\n",OP[0],OP[1]);
224#endif
225 State.regs[OP[0]] ^= 0x8000 >> OP[1];
226}
227
228/* bra.s */
229void
230OP_4800 ()
231{
232#ifdef DEBUG
233 printf(" bra.s\t0x%x\n",OP[0]);
234#endif
235 PC += SEXT8 (OP[0]);
236}
237
238/* bra.l */
239void
240OP_24000000 ()
241{
242#ifdef DEBUG
243 printf(" bra.l\t0x%x\n",OP[0]);
244#endif
245 PC += OP[0];
246}
247
248/* brf0f.s */
249void
250OP_4A00 ()
251{
252#ifdef DEBUG
253 printf(" brf0f.s\t0x%x\n",OP[0]);
254#endif
255 if (State.F0 == 0)
256 PC += SEXT8 (OP[0]);
257}
258
259/* brf0f.l */
260void
261OP_25000000 ()
262{
263#ifdef DEBUG
264 printf(" brf0f.l\t0x%x\n",OP[0]);
265#endif
266 if (State.F0 == 0)
267 PC += OP[0];
268}
269
270/* brf0t.s */
271void
272OP_4B00 ()
273{
274#ifdef DEBUG
275 printf(" brf0t.s\t0x%x\n",OP[0]);
276#endif
277 if (State.F0)
278 PC += SEXT8 (OP[0]);
279}
280
281/* brf0t.l */
282void
283OP_25800000 ()
284{
285#ifdef DEBUG
286 printf(" brf0t.l\t0x%x\n",OP[0]);
287#endif
288 if (State.F0)
289 PC += OP[0];
290}
291
292/* bseti */
293void
294OP_801 ()
295{
296#ifdef DEBUG
297 printf(" bseti\tr%d,%d\n",OP[0],OP[1]);
298#endif
299 State.regs[OP[0]] |= 0x8000 >> OP[1];
300}
301
302/* btsti */
303void
304OP_E01 ()
305{
306#ifdef DEBUG
307 printf(" btsti\tr%d,%d\n",OP[0],OP[1]);
308#endif
309 State.F1 = State.F0;
310 State.F0 = (State.regs[OP[0]] & (0x8000 >> OP[1])) ? 1 : 0;
311}
312
313/* clrac */
314void
315OP_5601 ()
316{
317#ifdef DEBUG
318 printf(" clrac\ta%d\n",OP[0]);
319#endif
320 State.a[OP[0]] = 0;
321}
322
323/* cmp */
324void
325OP_600 ()
326{
327#ifdef DEBUG
328 printf(" cmp\tr%d,r%d\n",OP[0],OP[1]);
329#endif
330 State.F1 = State.F0;
331 State.F0 = ((int16)(State.regs[OP[0]]) < (int16)(State.regs[OP[1]])) ? 1 : 0;
332}
333
334/* cmp */
335void
336OP_1603 ()
337{
338#ifdef DEBUG
339printf(" cmp\t%x,%x\n",OP[0],OP[1]);
340#endif
341}
342
343/* cmpeq */
344void
345OP_400 ()
346{
347#ifdef DEBUG
348 printf(" cmpeq\tr%d,r%d\n",OP[0],OP[1]);
349#endif
350 State.F1 = State.F0;
351 State.F0 = (State.regs[OP[0]] == State.regs[OP[1]]) ? 1 : 0;
352}
353
354/* cmpeq */
355void
356OP_1403 ()
357{
358#ifdef DEBUG
359printf(" cmpeq\t%x,%x\n",OP[0],OP[1]);
360#endif
361}
362
363/* cmpeqi.s */
364void
365OP_401 ()
366{
367#ifdef DEBUG
368 printf(" cmpeqi.s\tr%d,0x%x\n",OP[0],OP[1]);
369#endif
370 State.F1 = State.F0;
371 State.F0 = (State.regs[OP[0]] == SEXT4(OP[1])) ? 1 : 0;
372}
373
374/* cmpeqi.l */
375void
376OP_2000000 ()
377{
378#ifdef DEBUG
379 printf(" cmpeqi.l\tr%d,0x%x\n",OP[0],OP[1]);
380#endif
381 State.F1 = State.F0;
382 State.F0 = (State.regs[OP[0]] == OP[1]) ? 1 : 0;
383}
384
385/* cmpi.s */
386void
387OP_601 ()
388{
389#ifdef DEBUG
390 printf(" cmpi.s\tr%d,0x%x\n",OP[0],OP[1]);
391#endif
392 State.F1 = State.F0;
393 State.F0 = ((int16)(State.regs[OP[0]]) < SEXT4(OP[1])) ? 1 : 0;
394}
395
396/* cmpi.l */
397void
398OP_3000000 ()
399{
400#ifdef DEBUG
401 printf(" cmpi.l\tr%d,0x%x\n",OP[0],OP[1]);
402#endif
403 State.F1 = State.F0;
404 State.F0 = ((int16)(State.regs[OP[0]]) < (int16)(OP[1])) ? 1 : 0;
405}
406
407/* cmpu */
408void
409OP_4600 ()
410{
411#ifdef DEBUG
412 printf(" cmpu\tr%d,r%d\n",OP[0],OP[1]);
413#endif
414 State.F1 = State.F0;
415 State.F0 = (State.regs[OP[0]] < State.regs[OP[1]]) ? 1 : 0;
416}
417
418/* cmpui */
419void
420OP_23000000 ()
421{
422#ifdef DEBUG
423 printf(" cmpui\tr%d,0x%x\n",OP[0],OP[1]);
424#endif
425 State.F1 = State.F0;
426 State.F0 = (State.regs[OP[0]] < OP[1]) ? 1 : 0;
427}
428
429/* cpfg */
430void
431OP_4E09 ()
432{
433 uint8 *src, *dst;
434#ifdef DEBUG
435 printf(" cpfg\t%x,%x\n",OP[0],OP[1]);
436#endif
437
438 if (OP[0] == 0)
439 dst = &State.F0;
440 else
441 dst = &State.F1;
442
443 if (OP[1] == 0)
444 src = &State.F0;
445 else if (OP[1] == 1)
446 src = &State.F1;
447 else
448 src = &State.C;
449
450 *dst = *src;
451}
452
453/* dbt */
454void
455OP_5F20 ()
456{
457#ifdef DEBUG
458 printf(" dbt\n");
459#endif
460}
461
462/* divs */
463void
464OP_14002800 ()
465{
466 uint16 foo, tmp, tmpf;
467#ifdef DEBUG
468 printf(" divs\tr%d,r%d\n",OP[0],OP[1]);
469#endif
470 foo = (State.regs[OP[0]] << 1) | (State.regs[OP[0]+1] >> 15);
471 tmp = (int16)foo - (int16)(State.regs[OP[1]]);
472 tmpf = (foo >= State.regs[OP[1]]) ? 1 : 0;
473 State.regs[OP[0]] = (tmpf == 1) ? tmp : foo;
474 State.regs[OP[0]+1] = (State.regs[OP[0]+1] << 1) | tmpf;
475}
476
477/* exef0f */
478void
479OP_4E04 ()
480{
481#ifdef DEBUG
482 printf(" exef0f\n");
483#endif
484 State.exe = (State.F0) ? 0 : 1;
485}
486
487/* exef0t */
488void
489OP_4E24 ()
490{
491#ifdef DEBUG
492 printf(" exef0t\n");
493#endif
494 State.exe = State.F0;
495}
496
497/* exef1f */
498void
499OP_4E40 ()
500{
501#ifdef DEBUG
502 printf(" exef1f\n");
503#endif
504 State.exe = (State.F1) ? 0 : 1;
505}
506
507/* exef1t */
508void
509OP_4E42 ()
510{
511#ifdef DEBUG
512 printf(" exef1t\n");
513#endif
514 State.exe = State.F1;
515}
516
517/* exefaf */
518void
519OP_4E00 ()
520{
521#ifdef DEBUG
522 printf(" exefaf\n");
523#endif
524 State.exe = (State.F0 | State.F1) ? 0 : 1;
525}
526
527/* exefat */
528void
529OP_4E02 ()
530{
531#ifdef DEBUG
532 printf(" exefat\n");
533#endif
534 State.exe = (State.F0) ? 0 : (State.F1);
535}
536
537/* exetaf */
538void
539OP_4E20 ()
540{
541#ifdef DEBUG
542 printf(" exetaf\n");
543#endif
544 State.exe = (State.F1) ? 0 : (State.F0);
545}
546
547/* exetat */
548void
549OP_4E22 ()
550{
551#ifdef DEBUG
552 printf(" exetat\n");
553#endif
554 State.exe = (State.F0) ? (State.F1) : 0;
555}
556
557/* exp */
558void
559OP_15002A00 ()
560{
561 uint32 tmp, foo;
562 int i;
563
564#ifdef DEBUG
565 printf(" exp\tr%d,r%d\n",OP[0],OP[1]);
566#endif
567 if (((int16)State.regs[OP[0]]) >= 0)
568 tmp = (State.regs[OP[0]] << 16) | State.regs[OP[0]+1];
569 else
570 tmp = ~((State.regs[OP[0]] << 16) | State.regs[OP[0]+1]);
571
572 foo = 0x40000000;
573 for (i=1;i<16;i++)
574 {
575 if (tmp & foo)
576 {
577 State.regs[OP[0]] = i-1;
578 return;
579 }
580 }
581 State.regs[OP[0]] = 16;
582}
583
584/* exp */
585void
586OP_15002A02 ()
587{
588#ifdef DEBUG
589printf(" exp\t%x,%x\n",OP[0],OP[1]);
590#endif
591}
592
593/* jl */
594void
595OP_4D00 ()
596{
597#ifdef DEBUG
598 printf(" jl\t%x\n",OP[0]);
599#endif
600 State.regs[13] = PC+1;
601 PC = State.regs[OP[0]];
602}
603
604/* jmp */
605void
606OP_4C00 ()
607{
608#ifdef DEBUG
609 printf(" jmp\tr%d\n",OP[0]);
610#endif
611 PC = State.regs[OP[0]];
612}
613
614/* ld */
615void
616OP_30000000 ()
617{
618#ifdef DEBUG
619 printf(" ld\tr%d,@(0x%x,r%d)\n",OP[0],OP[1],OP[2]);
620#endif
621 State.regs[OP[0]] = RW (OP[1] + State.regs[OP[2]]);
622}
623
624/* ld */
625void
626OP_6401 ()
627{
628#ifdef DEBUG
629 printf(" ld\tr%d,@r%d-\n",OP[0],OP[1]);
630#endif
631 State.regs[OP[0]] = RW (State.regs[OP[2]]);
632 State.regs[OP[1]] -= 2;
633}
634
635/* ld */
636void
637OP_6001 ()
638{
639#ifdef DEBUG
640 printf(" ld\tr%d,@r%d+\n",OP[0],OP[1]);
641#endif
642 State.regs[OP[0]] = RW (State.regs[OP[2]]);
643 State.regs[OP[1]] += 2;
644}
645
646/* ld */
647void
648OP_6000 ()
649{
650#ifdef DEBUG
651 printf(" ld\tr%d,@r%d\n",OP[0],OP[1]);
652#endif
653 State.regs[OP[0]] = RW (State.regs[OP[1]]);
654}
655
656/* ld2w */
657void
658OP_31000000 ()
659{
660#ifdef DEBUG
661 printf(" ld2w\tr%d,@(0x%x,r%d)\n",OP[0],OP[1],OP[2]);
662#endif
663 State.regs[OP[0]] = RW (OP[1] + State.regs[OP[2]]);
664 State.regs[OP[0]+1] = RW (OP[1] + State.regs[OP[2]] + 2);
665}
666
667/* ld2w */
668void
669OP_6601 ()
670{
671#ifdef DEBUG
672 printf(" ld2w\tr%d,@r%d-\n",OP[0],OP[1]);
673#endif
674 State.regs[OP[0]] = RW (State.regs[OP[2]]);
675 State.regs[OP[0]+1] = RW (State.regs[OP[2]]+2);
676 State.regs[OP[1]] -= 4;
677}
678
679/* ld2w */
680void
681OP_6201 ()
682{
683#ifdef DEBUG
684 printf(" ld2w\tr%d,@r%d+\n",OP[0],OP[1]);
685#endif
686 State.regs[OP[0]] = RW (State.regs[OP[2]]);
687 State.regs[OP[0]+1] = RW (State.regs[OP[2]]+2);
688 State.regs[OP[1]] += 4;
689}
690
691/* ld2w */
692void
693OP_6200 ()
694{
695#ifdef DEBUG
696 printf(" ld2w\tr%d,@r%d\n",OP[0],OP[1]);
697#endif
698 State.regs[OP[0]] = RW (State.regs[OP[2]]);
699 State.regs[OP[0]+1] = RW (State.regs[OP[2]]+2);
700}
701
702/* ldb */
703void
704OP_38000000 ()
705{
706#ifdef DEBUG
707 printf(" ldb\tr%d,@(0x%x,r%d)\n",OP[0],OP[1],OP[2]);
708#endif
709 State.regs[OP[0]] = RB (OP[1] + State.regs[OP[2]]);
710 SEXT8 (State.regs[OP[0]]);
711}
712
713/* ldb */
714void
715OP_7000 ()
716{
717#ifdef DEBUG
718 printf(" ldb\tr%d,@r%d\n",OP[0],OP[1]);
719#endif
720 State.regs[OP[0]] = RB (State.regs[OP[1]]);
721 SEXT8 (State.regs[OP[0]]);
722}
723
724/* ldi.s */
725void
726OP_4001 ()
727{
728#ifdef DEBUG
729 printf(" ldi.s\tr%d,%x\n",OP[0],SEXT4(OP[1]));
730#endif
731 State.regs[OP[0]] = SEXT4(OP[1]);
732}
733
734/* ldi.l */
735void
736OP_20000000 ()
737{
738#ifdef DEBUG
739 printf(" ldi.l\tr%d,%d\t;0x%x\n",OP[0],OP[1],OP[1]);
740#endif
741 State.regs[OP[0]] = OP[1];
742}
743
744/* ldub */
745void
746OP_39000000 ()
747{
748#ifdef DEBUG
749 printf(" ldub\tr%d,@(0x%x,r%d)\n",OP[0],OP[1],OP[2]);
750#endif
751 State.regs[OP[0]] = RB (OP[1] + State.regs[OP[2]]);
752}
753
754/* ldub */
755void
756OP_7200 ()
757{
758#ifdef DEBUG
759 printf(" ldub\tr%d,@r%d\n",OP[0],OP[1]);
760#endif
761 State.regs[OP[0]] = RB (State.regs[OP[1]]);
762}
763
764/* mac */
765void
766OP_2A00 ()
767{
768#ifdef DEBUG
769printf(" mac\t%x,%x,%x\n",OP[0],OP[1],OP[2]);
770#endif
771}
772
773/* macsu */
774void
775OP_1A00 ()
776{
777#ifdef DEBUG
778printf(" macsu\t%x,%x,%x\n",OP[0],OP[1],OP[2]);
779#endif
780}
781
782/* macu */
783void
784OP_3A00 ()
785{
786#ifdef DEBUG
787printf(" macu\t%x,%x,%x\n",OP[0],OP[1],OP[2]);
788#endif
789}
790
791/* max */
792void
793OP_2600 ()
794{
795#ifdef DEBUG
796 printf(" max\tr%d,r%d\n",OP[0],OP[1]);
797#endif
798 State.F1 = State.F0;
799 if (State.regs[OP[1]] > State.regs[OP[0]])
800 {
801 State.regs[OP[0]] = State.regs[OP[1]];
802 State.F0 = 1;
803 }
804 else
805 State.F0 = 0;
806}
807
808/* max */
809void
810OP_3600 ()
811{
812#ifdef DEBUG
813printf(" max\t%x,%x\n",OP[0],OP[1]);
814#endif
815}
816
817/* max */
818void
819OP_3602 ()
820{
821#ifdef DEBUG
822printf(" max\t%x,%x\n",OP[0],OP[1]);
823#endif
824}
825
826/* min */
827void
828OP_2601 ()
829{
830#ifdef DEBUG
831 printf(" min\tr%d,r%d\n",OP[0],OP[1]);
832#endif
833 State.F1 = State.F0;
834 if (State.regs[OP[1]] < State.regs[OP[0]])
835 {
836 State.regs[OP[0]] = State.regs[OP[1]];
837 State.F0 = 1;
838 }
839 else
840 State.F0 = 0;
841}
842
843/* min */
844void
845OP_3601 ()
846{
847#ifdef DEBUG
848printf(" min\t%x,%x\n",OP[0],OP[1]);
849#endif
850}
851
852/* min */
853void
854OP_3603 ()
855{
856#ifdef DEBUG
857printf(" min\t%x,%x\n",OP[0],OP[1]);
858#endif
859}
860
861/* msb */
862void
863OP_2800 ()
864{
865#ifdef DEBUG
866printf(" msb\t%x,%x,%x\n",OP[0],OP[1],OP[2]);
867#endif
868}
869
870/* msbsu */
871void
872OP_1800 ()
873{
874#ifdef DEBUG
875printf(" msbsu\t%x,%x,%x\n",OP[0],OP[1],OP[2]);
876#endif
877}
878
879/* msbu */
880void
881OP_3800 ()
882{
883#ifdef DEBUG
884printf(" msbu\t%x,%x,%x\n",OP[0],OP[1],OP[2]);
885#endif
886}
887
888/* mul */
889void
890OP_2E00 ()
891{
892#ifdef DEBUG
893 printf(" mul\tr%d,r%d\n",OP[0],OP[1]);
894#endif
895 State.regs[OP[0]] *= State.regs[OP[1]];
896}
897
898/* mulx */
899void
900OP_2C00 ()
901{
902#ifdef DEBUG
903printf(" mulx\t%x,%x,%x\n",OP[0],OP[1],OP[2]);
904#endif
905}
906
907/* mulxsu */
908void
909OP_1C00 ()
910{
911#ifdef DEBUG
912printf(" mulxsu\t%x,%x,%x\n",OP[0],OP[1],OP[2]);
913#endif
914}
915
916/* mulxu */
917void
918OP_3C00 ()
919{
920#ifdef DEBUG
921printf(" mulxu\t%x,%x,%x\n",OP[0],OP[1],OP[2]);
922#endif
923}
924
925/* mv */
926void
927OP_4000 ()
928{
929#ifdef DEBUG
930 printf(" mv\tr%d,r%d\n",OP[0],OP[1]);
931#endif
932 State.regs[OP[0]] = State.regs[OP[1]];
933}
934
935/* mv2w */
936void
937OP_5000 ()
938{
939#ifdef DEBUG
940 printf(" mv2w\tr%d,r%d\n",OP[0],OP[1]);
941#endif
942 State.regs[OP[0]] = State.regs[OP[1]];
943 State.regs[OP[0]+1] = State.regs[OP[1]+1];
944}
945
946/* mv2wfac */
947void
948OP_3E00 ()
949{
950#ifdef DEBUG
951 printf(" mv2wfac\tr%d,a%d\n",OP[0],OP[1]);
952#endif
953 State.regs[OP[0]] = (State.a[OP[1]] >> 16) & 0xffff;
954 State.regs[OP[0]+1] = State.a[OP[1]] & 0xffff;
955}
956
957/* mv2wtac */
958void
959OP_3E01 ()
960{
961#ifdef DEBUG
962 printf(" mv2wtac\tr%d,a%d\n",OP[0],OP[1]);
963#endif
964 State.a[OP[1]] = SEXT16 (State.regs[OP[0]]) << 16 | State.regs[OP[0]+1];
965}
966
967/* mvac */
968void
969OP_3E03 ()
970{
971#ifdef DEBUG
972 printf(" mvac\ta%d,a%d\n",OP[0],OP[1]);
973#endif
974 State.a[OP[0]] = State.a[OP[1]];
975}
976
977/* mvb */
978void
979OP_5400 ()
980{
981#ifdef DEBUG
982 printf(" mvb\tr%d,r%d\n",OP[0],OP[1]);
983#endif
984 State.regs[OP[0]] = SEXT8 (State.regs[OP[1]] & 0xff);
985}
986
987/* mvf0f */
988void
989OP_4400 ()
990{
991#ifdef DEBUG
992 printf(" mvf0f\tr%d,r%d\n",OP[0],OP[1]);
993#endif
994 if (State.F0 == 0)
995 State.regs[OP[0]] = State.regs[OP[1]];
996}
997
998/* mvf0t */
999void
1000OP_4401 ()
1001{
1002#ifdef DEBUG
1003 printf(" mvf0t\tr%d,r%d\n",OP[0],OP[1]);
1004#endif
1005 if (State.F0)
1006 State.regs[OP[0]] = State.regs[OP[1]];
1007}
1008
1009/* mvfacg */
1010void
1011OP_1E04 ()
1012{
1013#ifdef DEBUG
1014 printf(" mvfacg\tr%d,a%d\n",OP[0],OP[1]);
1015#endif
1016 State.regs[OP[0]] = (State.a[OP[1]] >> 32) & 0xff;
1017}
1018
1019/* mvfachi */
1020void
1021OP_1E00 ()
1022{
1023#ifdef DEBUG
1024 printf(" mvfachi\tr%d,a%d\n",OP[0],OP[1]);
1025#endif
1026 State.regs[OP[0]] = (State.a[OP[1]] >> 16) & 0xffff;
1027}
1028
1029/* mvfaclo */
1030void
1031OP_1E02 ()
1032{
1033#ifdef DEBUG
1034 printf(" mvfaclo\tr%d,a%d\n",OP[0],OP[1]);
1035#endif
1036 State.regs[OP[0]] = State.a[OP[1]] & 0xffff;
1037}
1038
1039/* mvfc */
1040void
1041OP_5200 ()
1042{
1043#ifdef DEBUG
1044 printf(" mvfc\tr%d,cr%d\n",OP[0],OP[1]);
1045#endif
1046 if (OP[1] == 0)
1047 {
1048 /* PSW is treated specially */
1049 PSW = 0;
1050 if (State.SM) PSW |= 0x8000;
1051 if (State.EA) PSW |= 0x2000;
1052 if (State.DB) PSW |= 0x1000;
1053 if (State.IE) PSW |= 0x400;
1054 if (State.RP) PSW |= 0x200;
1055 if (State.MD) PSW |= 0x100;
1056 if (State.FX) PSW |= 0x80;
1057 if (State.ST) PSW |= 0x40;
1058 if (State.F0) PSW |= 8;
1059 if (State.F1) PSW |= 4;
1060 if (State.C) PSW |= 1;
1061 }
1062 State.regs[OP[0]] = State.cregs[OP[1]];
1063}
1064
1065/* mvtacg */
1066void
1067OP_1E41 ()
1068{
1069#ifdef DEBUG
1070 printf(" mvtacg\tr%d,a%d\n",OP[0],OP[1]);
1071#endif
1072 State.a[OP[1]] &= MASK32;
1073 State.a[OP[1]] |= (int64)(State.regs[OP[0]] & 0xff) << 32;
1074}
1075
1076/* mvtachi */
1077void
1078OP_1E01 ()
1079{
1080 uint16 tmp;
1081#ifdef DEBUG
1082 printf(" mvtachi\tr%d,a%d\n",OP[0],OP[1]);
1083#endif
1084 tmp = State.a[OP[1]] & 0xffff;
1085 State.a[OP[1]] = SEXT16 (State.regs[OP[0]]) << 16 | tmp;
1086 printf("put 0x%llx\n",State.a[OP[1]]);
1087}
1088
1089/* mvtaclo */
1090void
1091OP_1E21 ()
1092{
1093#ifdef DEBUG
1094 printf(" mvtaclo\tr%d,a%d\n",OP[0],OP[1]);
1095#endif
1096 State.a[OP[1]] = SEXT16 (State.regs[OP[0]]);
1097}
1098
1099/* mvtc */
1100void
1101OP_5600 ()
1102{
1103#ifdef DEBUG
1104 printf(" mvtc\tr%d,cr%d\n",OP[0],OP[1]);
1105#endif
1106 State.cregs[OP[1]] = State.regs[OP[0]];
1107 if (OP[1] == 0)
1108 {
1109 /* PSW is treated specially */
1110 State.SM = (PSW & 0x8000) ? 1 : 0;
1111 State.EA = (PSW & 0x2000) ? 1 : 0;
1112 State.DB = (PSW & 0x1000) ? 1 : 0;
1113 State.IE = (PSW & 0x400) ? 1 : 0;
1114 State.RP = (PSW & 0x200) ? 1 : 0;
1115 State.MD = (PSW & 0x100) ? 1 : 0;
1116 State.FX = (PSW & 0x80) ? 1 : 0;
1117 State.ST = (PSW & 0x40) ? 1 : 0;
1118 State.F0 = (PSW & 8) ? 1 : 0;
1119 State.F1 = (PSW & 4) ? 1 : 0;
1120 State.C = PSW & 1;
1121 if (State.ST && !State.FX)
1122 {
1123 fprintf (stderr,"ERROR at PC 0x%x: ST can only be set when FX is set.\n",PC<<2);
1124 exit (1);
1125 }
1126 }
1127}
1128
1129/* mvub */
1130void
1131OP_5401 ()
1132{
1133#ifdef DEBUG
1134 printf(" mvub\tr%d,r%d\n",OP[0],OP[1]);
1135#endif
1136 State.regs[OP[0]] = State.regs[OP[1]] & 0xff;
1137}
1138
1139/* neg */
1140void
1141OP_4605 ()
1142{
1143#ifdef DEBUG
1144 printf(" neg\tr%d\n",OP[0]);
1145#endif
1146 State.regs[OP[0]] = 0 - State.regs[OP[0]];
1147}
1148
1149/* neg */
1150void
1151OP_5605 ()
1152{
1153 int64 tmp;
1154#ifdef DEBUG
1155 printf(" neg\ta%d\n",OP[0]);
1156#endif
1157 tmp = -State.a[OP[0]] & MASK40;
1158 if (State.ST)
1159 {
1160 if ( !(tmp & BIT40) && (tmp > MAX32))
1161 State.a[OP[0]] = MAX32;
1162 else if ( (tmp & BIT40) && (tmp < MIN32))
1163 State.a[OP[0]] = MIN32;
1164 else
1165 State.a[OP[0]] = tmp;
1166 }
1167 else
1168 State.a[OP[0]] = tmp;
1169}
1170
1171
1172/* nop */
1173void
1174OP_5E00 ()
1175{
1176}
1177
1178/* not */
1179void
1180OP_4603 ()
1181{
1182#ifdef DEBUG
1183 printf(" not\tr%d\n",OP[0]);
1184#endif
1185 State.regs[OP[0]] = ~(State.regs[OP[0]]);
1186}
1187
1188/* or */
1189void
1190OP_800 ()
1191{
1192#ifdef DEBUG
1193 printf(" or\tr%d,r%d\n",OP[0],OP[1]);
1194#endif
1195 State.regs[OP[0]] |= State.regs[OP[1]];
1196}
1197
1198/* or3 */
1199void
1200OP_4000000 ()
1201{
1202#ifdef DEBUG
1203 printf(" or3\tr%d,r%d,0x%x\n",OP[0],OP[1],OP[2]);
1204#endif
1205 State.regs[OP[0]] = State.regs[OP[1]] | OP[2];
1206}
1207
1208/* rac */
1209void
1210OP_5201 ()
1211{
1212 int64 tmp;
1213 int shift = SEXT3 (OP[2]);
1214#ifdef DEBUG
1215 printf(" rac\tr%d,a%d,%d\n",OP[0],OP[1],shift);
1216#endif
1217 State.F1 = State.F0;
1218 if (shift >=0)
1219 tmp = ((State.a[0] << 16) | (State.a[1] & 0xffff)) << shift;
1220 else
1221 tmp = ((State.a[0] << 16) | (State.a[1] & 0xffff)) >> -shift;
1222 tmp = (tmp + 0x8000) & MASK44;
1223 if ( !(tmp & BIT44) && (tmp > MAX32))
1224 {
1225 State.regs[OP[0]] = 0x7fff;
1226 State.regs[OP[0]+1] = 0xffff;
1227 State.F0 = 1;
1228 }
1229 else if ((tmp & BIT44) && (tmp < 0xfff80000000LL))
1230 {
1231 State.regs[OP[0]] = 0x8000;
1232 State.regs[OP[0]+1] = 0;
1233 State.F0 = 1;
1234 }
1235 else
1236 {
1237 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
1238 State.regs[OP[0]+1] = tmp & 0xffff;
1239 State.F0 = 0;
1240 }
1241}
1242
1243/* rachi */
1244void
1245OP_4201 ()
1246{
1247#ifdef DEBUG
1248printf(" rachi\t%x,%x,%x\n",OP[0],OP[1],OP[2]);
1249#endif
1250}
1251
1252/* rep */
1253void
1254OP_27000000 ()
1255{
1256#ifdef DEBUG
1257 printf(" rep\tr%d,0x%x\n",OP[0],OP[1]);
1258#endif
1259 RPT_S = PC + 1;
1260 RPT_E = PC + OP[1];
1261 RPT_C = State.regs[OP[0]];
1262 State.RP = 1;
1263 if (RPT_C == 0)
1264 {
1265 fprintf (stderr, "ERROR: rep with count=0 is illegal.\n");
1266 exit(1);
1267 }
1268}
1269
1270/* repi */
1271void
1272OP_2F000000 ()
1273{
1274#ifdef DEBUG
1275 printf(" repi\t%d,0x%x\n",OP[0],OP[1]);
1276#endif
1277 RPT_S = PC + 1;
1278 RPT_E = PC + OP[1];
1279 RPT_C = OP[0];
1280 State.RP = 1;
1281 if (RPT_C == 0)
1282 {
1283 fprintf (stderr, "ERROR: rep with count=0 is illegal.\n");
1284 exit(1);
1285 }
1286}
1287
1288/* rtd */
1289void
1290OP_5F60 ()
1291{
1292#ifdef DEBUG
1293printf(" rtd\n");
1294#endif
1295}
1296
1297/* rte */
1298void
1299OP_5F40 ()
1300{
1301#ifdef DEBUG
1302printf(" rte\n");
1303#endif
1304}
1305
1306/* sadd */
1307void
1308OP_1223 ()
1309{
1310#ifdef DEBUG
1311printf(" sadd\t%x,%x\n",OP[0],OP[1]);
1312#endif
1313}
1314
1315/* setf0f */
1316void
1317OP_4611 ()
1318{
1319#ifdef DEBUG
1320printf(" setf0f\t%x\n",OP[0]);
1321#endif
1322}
1323
1324/* setf0t */
1325void
1326OP_4613 ()
1327{
1328#ifdef DEBUG
1329printf(" setf0t\t%x\n",OP[0]);
1330#endif
1331}
1332
1333/* sleep */
1334void
1335OP_5FC0 ()
1336{
1337#ifdef DEBUG
1338printf(" sleep\n");
1339#endif
1340}
1341
1342/* sll */
1343void
1344OP_2200 ()
1345{
1346#ifdef DEBUG
1347 printf(" sll\tr%d,r%d\n",OP[0],OP[1]);
1348#endif
1349 State.regs[OP[0]] <<= (State.regs[OP[1]] & 0xf);
1350}
1351
1352/* sll */
1353void
1354OP_3200 ()
1355{
1356#ifdef DEBUG
1357printf(" sll\t%x,%x\n",OP[0],OP[1]);
1358#endif
1359}
1360
1361/* slli */
1362void
1363OP_2201 ()
1364{
1365#ifdef DEBUG
1366 printf(" slli\tr%d,%d\n",OP[0],OP[1]);
1367#endif
1368 State.regs[OP[0]] <<= OP[1];
1369}
1370
1371/* slli */
1372void
1373OP_3201 ()
1374{
1375#ifdef DEBUG
1376printf(" slli\t%x,%x\n",OP[0],OP[1]);
1377#endif
1378}
1379
1380/* slx */
1381void
1382OP_460B ()
1383{
1384 uint16 tmp;
1385#ifdef DEBUG
1386 printf(" slx\tr%d\n",OP[0]);
1387#endif
1388 State.regs[OP[0]] = (State.regs[OP[0]] << 1) | State.F0;
1389}
1390
1391/* sra */
1392void
1393OP_2400 ()
1394{
1395#ifdef DEBUG
1396 printf(" sra\tr%d,r%d\n",OP[0],OP[1]);
1397#endif
1398 State.regs[OP[0]] = ((int16)(State.regs[OP[0]])) >> (State.regs[OP[1]] & 0xf);
1399}
1400
1401/* sra */
1402void
1403OP_3400 ()
1404{
1405#ifdef DEBUG
1406printf(" sra\t%x,%x\n",OP[0],OP[1]);
1407#endif
1408}
1409
1410/* srai */
1411void
1412OP_2401 ()
1413{
1414#ifdef DEBUG
1415 printf(" srai\tr%d,%d\n",OP[0],OP[1]);
1416#endif
1417 State.regs[OP[0]] = ((int16)(State.regs[OP[0]])) >> OP[1];
1418}
1419
1420/* srai */
1421void
1422OP_3401 ()
1423{
1424#ifdef DEBUG
1425printf(" srai\t%x,%x\n",OP[0],OP[1]);
1426#endif
1427}
1428
1429/* srl */
1430void
1431OP_2000 ()
1432{
1433#ifdef DEBUG
1434 printf(" srl\tr%d,r%d\n",OP[0],OP[1]);
1435#endif
1436 State.regs[OP[0]] >>= (State.regs[OP[1]] & 0xf);
1437}
1438
1439/* srl */
1440void
1441OP_3000 ()
1442{
1443#ifdef DEBUG
1444printf(" srl\t%x,%x\n",OP[0],OP[1]);
1445#endif
1446}
1447
1448/* srli */
1449void
1450OP_2001 ()
1451{
1452#ifdef DEBUG
1453printf(" srli\tr%d,%d\n",OP[0],OP[1]);
1454#endif
1455 State.regs[OP[0]] >>= OP[1];
1456}
1457
1458/* srli */
1459void
1460OP_3001 ()
1461{
1462#ifdef DEBUG
1463printf(" srli\t%x,%x\n",OP[0],OP[1]);
1464#endif
1465}
1466
1467/* srx */
1468void
1469OP_4609 ()
1470{
1471 uint16 tmp;
1472#ifdef DEBUG
1473 printf(" srx\tr%d\n",OP[0]);
1474#endif
1475 tmp = State.F0 << 15;
1476 State.regs[OP[0]] = (State.regs[OP[0]] >> 1) | tmp;
1477}
1478
1479/* st */
1480void
1481OP_34000000 ()
1482{
1483#ifdef DEBUG
1484 printf(" st\tr%d,@(0x%x,r%d)\n",OP[0],OP[1],OP[2]);
1485#endif
1486 SW (OP[1] + State.regs[OP[2]], State.regs[OP[0]]);
1487}
1488
1489/* st */
1490void
1491OP_6800 ()
1492{
1493#ifdef DEBUG
1494 printf(" st\tr%d,@r%d\n",OP[0],OP[1]);
1495#endif
1496 SW (State.regs[OP[1]], State.regs[OP[0]]);
1497}
1498
1499/* st */
1500void
1501OP_6C1F ()
1502{
1503#ifdef DEBUG
1504printf(" st\t%x,%x\n",OP[0],OP[1]);
1505#endif
1506}
1507
1508/* st */
1509void
1510OP_6801 ()
1511{
1512#ifdef DEBUG
1513printf(" st\t%x,%x\n",OP[0],OP[1]);
1514#endif
1515}
1516
1517/* st */
1518void
1519OP_6C01 ()
1520{
1521#ifdef DEBUG
1522printf(" st\t%x,%x\n",OP[0],OP[1]);
1523#endif
1524}
1525
1526/* st2w */
1527void
1528OP_35000000 ()
1529{
1530#ifdef DEBUG
1531printf(" st2w\t%x,%x,%x\n",OP[0],OP[1],OP[2]);
1532#endif
1533}
1534
1535/* st2w */
1536void
1537OP_6A00 ()
1538{
1539#ifdef DEBUG
1540printf(" st2w\t%x,%x\n",OP[0],OP[1]);
1541#endif
1542}
1543
1544/* st2w */
1545void
1546OP_6E1F ()
1547{
1548#ifdef DEBUG
1549printf(" st2w\t%x,%x\n",OP[0],OP[1]);
1550#endif
1551}
1552
1553/* st2w */
1554void
1555OP_6A01 ()
1556{
1557#ifdef DEBUG
1558printf(" st2w\t%x,%x\n",OP[0],OP[1]);
1559#endif
1560}
1561
1562/* st2w */
1563void
1564OP_6E01 ()
1565{
1566#ifdef DEBUG
1567printf(" st2w\t%x,%x\n",OP[0],OP[1]);
1568#endif
1569}
1570
1571/* stb */
1572void
1573OP_3C000000 ()
1574{
1575#ifdef DEBUG
1576printf(" stb\t%x,%x,%x\n",OP[0],OP[1],OP[2]);
1577#endif
1578}
1579
1580/* stb */
1581void
1582OP_7800 ()
1583{
1584#ifdef DEBUG
1585printf(" stb\t%x,%x\n",OP[0],OP[1]);
1586#endif
1587}
1588
1589/* stop */
1590void
1591OP_5FE0 ()
1592{
1593#ifdef DEBUG
1594 printf(" stop\n");
1595#endif
1596 exit(1);
1597}
1598
1599/* sub */
1600void
1601OP_0 ()
1602{
1603#ifdef DEBUG
1604printf(" sub\t%x,%x\n",OP[0],OP[1]);
1605#endif
1606}
1607
1608/* sub2w */
1609void
1610OP_1000 ()
1611{
1612#ifdef DEBUG
1613printf(" sub2w\t%x,%x\n",OP[0],OP[1]);
1614#endif
1615}
1616
1617/* subac3 */
1618void
1619OP_17000000 ()
1620{
1621#ifdef DEBUG
1622printf(" subac3\t%x,%x,%x\n",OP[0],OP[1],OP[2]);
1623#endif
1624}
1625
1626/* subac3 */
1627void
1628OP_17000002 ()
1629{
1630#ifdef DEBUG
1631printf(" subac3\t%x,%x,%x\n",OP[0],OP[1],OP[2]);
1632#endif
1633}
1634
1635/* subac3s */
1636void
1637OP_17001000 ()
1638{
1639#ifdef DEBUG
1640printf(" subac3s\t%x,%x,%x\n",OP[0],OP[1],OP[2]);
1641#endif
1642}
1643
1644/* subac3s */
1645void
1646OP_17001002 ()
1647{
1648#ifdef DEBUG
1649printf(" subac3s\t%x,%x,%x\n",OP[0],OP[1],OP[2]);
1650#endif
1651}
1652
1653/* subi */
1654void
1655OP_1 ()
1656{
1657#ifdef DEBUG
1658printf(" subi\t%x,%x\n",OP[0],OP[1]);
1659#endif
1660}
1661
1662/* trap */
1663void
1664OP_5F00 ()
1665{
1666#ifdef DEBUG
1667 printf(" trap\t%d\n",OP[0]);
1668#endif
1669
1670 /* for now, trap 0 is used for simulating IO */
1671
1672 if (OP[0] == 0)
1673 {
1674 char *fstr = State.regs[2] + State.imem;
1675 printf (fstr,State.regs[3],State.regs[4],State.regs[5]);
1676 }
1677 else if (OP[0] == 1 )
1678 {
1679 char *fstr = State.regs[2] + State.imem;
1680 puts (fstr);
1681 }
1682}
1683
1684/* tst0i */
1685void
1686OP_7000000 ()
1687{
1688#ifdef DEBUG
1689printf(" tst0i\t%x,%x\n",OP[0],OP[1]);
1690#endif
1691}
1692
1693/* tst1i */
1694void
1695OP_F000000 ()
1696{
1697#ifdef DEBUG
1698printf(" tst1i\t%x,%x\n",OP[0],OP[1]);
1699#endif
1700}
1701
1702/* wait */
1703void
1704OP_5F80 ()
1705{
1706#ifdef DEBUG
1707printf(" wait\n");
1708#endif
1709}
1710
1711/* xor */
1712void
1713OP_A00 ()
1714{
1715#ifdef DEBUG
1716printf(" xor\t%x,%x\n",OP[0],OP[1]);
1717#endif
1718}
1719
1720/* xor3 */
1721void
1722OP_5000000 ()
1723{
1724#ifdef DEBUG
1725printf(" xor3\t%x,%x,%x\n",OP[0],OP[1],OP[2]);
1726#endif
1727}
1728
GDB Binutils - Deliverables
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