Commit | Line | Data |
---|---|---|
4f425a32 | 1 | #include <signal.h> |
63a91cfb MM |
2 | #include <errno.h> |
3 | #include <sys/types.h> | |
4 | #include <sys/stat.h> | |
5 | #include <unistd.h> | |
6 | ||
2934d1c9 MH |
7 | #include "d10v_sim.h" |
8 | #include "simops.h" | |
8719be26 | 9 | #include "sys/syscall.h" |
2934d1c9 | 10 | |
87178dbd MM |
11 | enum op_types { |
12 | OP_VOID, | |
13 | OP_REG, | |
14 | OP_REG_OUTPUT, | |
15 | OP_DREG, | |
16 | OP_DREG_OUTPUT, | |
17 | OP_ACCUM, | |
18 | OP_ACCUM_OUTPUT, | |
19 | OP_ACCUM_REVERSE, | |
20 | OP_CR, | |
21 | OP_CR_OUTPUT, | |
22 | OP_CR_REVERSE, | |
23 | OP_FLAG, | |
24 | OP_CONSTANT16, | |
25 | OP_CONSTANT3, | |
26 | OP_CONSTANT4, | |
27 | OP_MEMREF, | |
28 | OP_MEMREF2, | |
29 | OP_POSTDEC, | |
30 | OP_POSTINC, | |
31 | OP_PREDEC | |
32 | }; | |
33 | ||
7eebfc62 | 34 | #ifdef DEBUG |
87178dbd MM |
35 | static void trace_input PARAMS ((char *name, |
36 | enum op_types in1, | |
37 | enum op_types in2, | |
38 | enum op_types in3)); | |
39 | ||
40 | static void trace_output PARAMS ((enum op_types result)); | |
41 | ||
42 | #ifndef SIZE_INSTRUCTION | |
43 | #define SIZE_INSTRUCTION 10 | |
44 | #endif | |
45 | ||
46 | #ifndef SIZE_OPERANDS | |
47 | #define SIZE_OPERANDS 24 | |
48 | #endif | |
49 | ||
50 | #ifndef SIZE_VALUES | |
51 | #define SIZE_VALUES 13 | |
52 | #endif | |
53 | ||
54 | static void | |
55 | trace_input (name, in1, in2, in3) | |
56 | char *name; | |
57 | enum op_types in1; | |
58 | enum op_types in2; | |
59 | enum op_types in3; | |
60 | { | |
61 | char *comma; | |
62 | enum op_types in[3]; | |
63 | int i; | |
64 | char buf[80]; | |
65 | char *p; | |
66 | long tmp; | |
67 | char *type; | |
68 | ||
7eebfc62 MM |
69 | if ((d10v_debug & DEBUG_TRACE) == 0) |
70 | return; | |
71 | ||
87178dbd MM |
72 | switch (State.ins_type) |
73 | { | |
74 | default: | |
75 | case INS_UNKNOWN: type = " ?"; break; | |
76 | case INS_LEFT: type = " L"; break; | |
77 | case INS_RIGHT: type = " R"; break; | |
78 | case INS_LEFT_PARALLEL: type = "*L"; break; | |
79 | case INS_RIGHT_PARALLEL: type = "*R"; break; | |
80 | case INS_LONG: type = " B"; break; | |
81 | } | |
82 | ||
7eebfc62 MM |
83 | (*d10v_callback->printf_filtered) (d10v_callback, |
84 | "0x%.6x %s: %-*s", | |
85 | (unsigned)PC, type, | |
86 | SIZE_INSTRUCTION, name); | |
87178dbd MM |
87 | |
88 | in[0] = in1; | |
89 | in[1] = in2; | |
90 | in[2] = in3; | |
91 | comma = ""; | |
92 | p = buf; | |
93 | for (i = 0; i < 3; i++) | |
94 | { | |
95 | switch (in[i]) | |
96 | { | |
97 | case OP_VOID: | |
98 | break; | |
99 | ||
100 | case OP_REG: | |
101 | case OP_REG_OUTPUT: | |
102 | case OP_DREG: | |
103 | case OP_DREG_OUTPUT: | |
104 | sprintf (p, "%sr%d", comma, OP[i]); | |
105 | p += strlen (p); | |
106 | comma = ","; | |
107 | break; | |
108 | ||
109 | case OP_CR: | |
110 | case OP_CR_OUTPUT: | |
111 | case OP_CR_REVERSE: | |
112 | sprintf (p, "%scr%d", comma, OP[i]); | |
113 | p += strlen (p); | |
114 | comma = ","; | |
115 | break; | |
116 | ||
117 | case OP_ACCUM: | |
118 | case OP_ACCUM_OUTPUT: | |
119 | case OP_ACCUM_REVERSE: | |
120 | sprintf (p, "%sa%d", comma, OP[i]); | |
121 | p += strlen (p); | |
122 | comma = ","; | |
123 | break; | |
124 | ||
125 | case OP_CONSTANT16: | |
126 | sprintf (p, "%s%d", comma, OP[i]); | |
127 | p += strlen (p); | |
128 | comma = ","; | |
129 | break; | |
130 | ||
131 | case OP_CONSTANT4: | |
132 | sprintf (p, "%s%d", comma, SEXT4(OP[i])); | |
133 | p += strlen (p); | |
134 | comma = ","; | |
135 | break; | |
136 | ||
137 | case OP_CONSTANT3: | |
138 | sprintf (p, "%s%d", comma, SEXT3(OP[i])); | |
139 | p += strlen (p); | |
140 | comma = ","; | |
141 | break; | |
142 | ||
143 | case OP_MEMREF: | |
144 | sprintf (p, "%s@r%d", comma, OP[i]); | |
145 | p += strlen (p); | |
146 | comma = ","; | |
147 | break; | |
148 | ||
149 | case OP_MEMREF2: | |
150 | sprintf (p, "%s@(%d,r%d)", comma, (int16)OP[i], OP[i+1]); | |
151 | p += strlen (p); | |
152 | comma = ","; | |
153 | break; | |
154 | ||
155 | case OP_POSTINC: | |
156 | sprintf (p, "%s@r%d+", comma, OP[i]); | |
157 | p += strlen (p); | |
158 | comma = ","; | |
159 | break; | |
160 | ||
161 | case OP_POSTDEC: | |
162 | sprintf (p, "%s@r%d-", comma, OP[i]); | |
163 | p += strlen (p); | |
164 | comma = ","; | |
165 | break; | |
166 | ||
167 | case OP_PREDEC: | |
168 | sprintf (p, "%s@-r%d", comma, OP[i]); | |
169 | p += strlen (p); | |
170 | comma = ","; | |
171 | break; | |
172 | ||
173 | case OP_FLAG: | |
174 | if (OP[i] == 0) | |
175 | sprintf (p, "%sf0", comma); | |
176 | ||
177 | else if (OP[i] == 1) | |
178 | sprintf (p, "%sf1", comma); | |
179 | ||
180 | else | |
181 | sprintf (p, "%scarry", comma); | |
182 | ||
183 | p += strlen (p); | |
184 | comma = ","; | |
185 | break; | |
186 | } | |
187 | } | |
188 | ||
7eebfc62 MM |
189 | if ((d10v_debug & DEBUG_VALUES) == 0) |
190 | { | |
191 | *p++ = '\n'; | |
192 | *p = '\0'; | |
193 | (*d10v_callback->printf_filtered) (d10v_callback, "%s", buf); | |
194 | } | |
195 | else | |
196 | { | |
197 | *p = '\0'; | |
198 | (*d10v_callback->printf_filtered) (d10v_callback, "%-*s", SIZE_OPERANDS, buf); | |
87178dbd | 199 | |
7eebfc62 MM |
200 | p = buf; |
201 | for (i = 0; i < 3; i++) | |
202 | { | |
203 | buf[0] = '\0'; | |
204 | switch (in[i]) | |
205 | { | |
206 | case OP_VOID: | |
207 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, ""); | |
208 | break; | |
209 | ||
210 | case OP_REG_OUTPUT: | |
211 | case OP_DREG_OUTPUT: | |
212 | case OP_CR_OUTPUT: | |
213 | case OP_ACCUM_OUTPUT: | |
214 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "---"); | |
215 | break; | |
216 | ||
217 | case OP_REG: | |
218 | case OP_MEMREF: | |
219 | case OP_POSTDEC: | |
220 | case OP_POSTINC: | |
221 | case OP_PREDEC: | |
222 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", | |
223 | (uint16)State.regs[OP[i]]); | |
224 | break; | |
225 | ||
226 | case OP_DREG: | |
227 | tmp = (long)((((uint32) State.regs[OP[i]]) << 16) | ((uint32) State.regs[OP[i]+1])); | |
228 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.8lx", SIZE_VALUES-10, "", tmp); | |
229 | break; | |
230 | ||
231 | case OP_CR: | |
232 | case OP_CR_REVERSE: | |
233 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", | |
234 | (uint16)State.cregs[OP[i]]); | |
235 | break; | |
236 | ||
237 | case OP_ACCUM: | |
238 | case OP_ACCUM_REVERSE: | |
239 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.2x%.8lx", SIZE_VALUES-12, "", | |
240 | ((int)(State.a[OP[i]] >> 32) & 0xff), | |
241 | ((unsigned long)State.a[OP[i]]) & 0xffffffff); | |
242 | break; | |
243 | ||
244 | case OP_CONSTANT16: | |
245 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", | |
246 | (uint16)OP[i]); | |
247 | break; | |
248 | ||
249 | case OP_CONSTANT4: | |
250 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", | |
251 | (uint16)SEXT4(OP[i])); | |
252 | break; | |
253 | ||
254 | case OP_CONSTANT3: | |
255 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", | |
256 | (uint16)SEXT3(OP[i])); | |
257 | break; | |
258 | ||
259 | case OP_FLAG: | |
260 | if (OP[i] == 0) | |
261 | (*d10v_callback->printf_filtered) (d10v_callback, "%*sF0 = %d", SIZE_VALUES-6, "", | |
262 | State.F0 != 0); | |
263 | ||
264 | else if (OP[i] == 1) | |
265 | (*d10v_callback->printf_filtered) (d10v_callback, "%*sF1 = %d", SIZE_VALUES-6, "", | |
266 | State.F1 != 0); | |
267 | ||
268 | else | |
269 | (*d10v_callback->printf_filtered) (d10v_callback, "%*sC = %d", SIZE_VALUES-5, "", | |
270 | State.C != 0); | |
271 | ||
272 | break; | |
273 | ||
274 | case OP_MEMREF2: | |
275 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", | |
276 | (uint16)OP[i]); | |
277 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", | |
278 | (uint16)State.regs[OP[++i]]); | |
279 | break; | |
280 | } | |
281 | } | |
282 | } | |
283 | } | |
87178dbd | 284 | |
7eebfc62 MM |
285 | static void |
286 | trace_output (result) | |
287 | enum op_types result; | |
288 | { | |
289 | if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES)) | |
87178dbd | 290 | { |
7eebfc62 | 291 | long tmp; |
87178dbd | 292 | |
7eebfc62 MM |
293 | switch (result) |
294 | { | |
295 | default: | |
296 | putchar ('\n'); | |
87178dbd MM |
297 | break; |
298 | ||
299 | case OP_REG: | |
7eebfc62 MM |
300 | case OP_REG_OUTPUT: |
301 | (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "", | |
302 | (uint16)State.regs[OP[0]], | |
303 | State.F0 != 0, State.F1 != 0, State.C != 0); | |
87178dbd MM |
304 | break; |
305 | ||
306 | case OP_DREG: | |
7eebfc62 MM |
307 | case OP_DREG_OUTPUT: |
308 | tmp = (long)((((uint32) State.regs[OP[0]]) << 16) | ((uint32) State.regs[OP[0]+1])); | |
309 | (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-10, "", tmp, | |
310 | State.F0 != 0, State.F1 != 0, State.C != 0); | |
87178dbd MM |
311 | break; |
312 | ||
313 | case OP_CR: | |
7eebfc62 MM |
314 | case OP_CR_OUTPUT: |
315 | (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "", | |
316 | (uint16)State.cregs[OP[0]], | |
317 | State.F0 != 0, State.F1 != 0, State.C != 0); | |
87178dbd MM |
318 | break; |
319 | ||
7eebfc62 MM |
320 | case OP_CR_REVERSE: |
321 | (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "", | |
322 | (uint16)State.cregs[OP[1]], | |
323 | State.F0 != 0, State.F1 != 0, State.C != 0); | |
87178dbd MM |
324 | break; |
325 | ||
7eebfc62 MM |
326 | case OP_ACCUM: |
327 | case OP_ACCUM_OUTPUT: | |
328 | (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-10, "", | |
329 | ((int)(State.a[OP[0]] >> 32) & 0xff), | |
330 | ((unsigned long)State.a[OP[0]]) & 0xffffffff, | |
331 | State.F0 != 0, State.F1 != 0, State.C != 0); | |
87178dbd MM |
332 | break; |
333 | ||
7eebfc62 MM |
334 | case OP_ACCUM_REVERSE: |
335 | (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-10, "", | |
336 | ((int)(State.a[OP[1]] >> 32) & 0xff), | |
337 | ((unsigned long)State.a[OP[1]]) & 0xffffffff, | |
338 | State.F0 != 0, State.F1 != 0, State.C != 0); | |
87178dbd MM |
339 | break; |
340 | ||
341 | case OP_FLAG: | |
7eebfc62 MM |
342 | (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s F0=%d F1=%d C=%d\n", SIZE_VALUES, "", |
343 | State.F0 != 0, State.F1 != 0, State.C != 0); | |
87178dbd MM |
344 | break; |
345 | } | |
346 | } | |
87178dbd MM |
347 | } |
348 | ||
349 | #else | |
350 | #define trace_input(NAME, IN1, IN2, IN3) | |
351 | #define trace_output(RESULT) | |
352 | #endif | |
2934d1c9 MH |
353 | |
354 | /* abs */ | |
355 | void | |
356 | OP_4607 () | |
357 | { | |
87178dbd | 358 | trace_input ("abs", OP_REG, OP_VOID, OP_VOID); |
2934d1c9 MH |
359 | State.F1 = State.F0; |
360 | if ((int16)(State.regs[OP[0]]) < 0) | |
361 | { | |
362 | State.regs[OP[0]] = -(int16)(State.regs[OP[0]]); | |
363 | State.F0 = 1; | |
364 | } | |
365 | else | |
366 | State.F0 = 0; | |
87178dbd | 367 | trace_output (OP_REG); |
2934d1c9 MH |
368 | } |
369 | ||
370 | /* abs */ | |
371 | void | |
372 | OP_5607 () | |
373 | { | |
374 | int64 tmp; | |
375 | ||
87178dbd | 376 | trace_input ("abs", OP_ACCUM, OP_VOID, OP_VOID); |
4f425a32 MH |
377 | State.F1 = State.F0; |
378 | State.a[OP[0]] = SEXT40(State.a[OP[0]]); | |
379 | ||
4c38885c | 380 | if (State.a[OP[0]] < 0 ) |
2934d1c9 | 381 | { |
4c38885c | 382 | tmp = -State.a[OP[0]]; |
2934d1c9 MH |
383 | if (State.ST) |
384 | { | |
4c38885c | 385 | if (tmp > MAX32) |
2934d1c9 | 386 | State.a[OP[0]] = MAX32; |
4c38885c | 387 | else if (tmp < MIN32) |
2934d1c9 MH |
388 | State.a[OP[0]] = MIN32; |
389 | else | |
4f425a32 | 390 | State.a[OP[0]] = tmp & MASK40; |
2934d1c9 MH |
391 | } |
392 | else | |
4f425a32 | 393 | State.a[OP[0]] = tmp & MASK40; |
2934d1c9 MH |
394 | State.F0 = 1; |
395 | } | |
396 | else | |
397 | State.F0 = 0; | |
87178dbd | 398 | trace_output (OP_ACCUM); |
2934d1c9 MH |
399 | } |
400 | ||
401 | /* add */ | |
402 | void | |
403 | OP_200 () | |
404 | { | |
405 | uint16 tmp = State.regs[OP[0]]; | |
87178dbd | 406 | trace_input ("add", OP_REG, OP_REG, OP_VOID); |
2934d1c9 MH |
407 | State.regs[OP[0]] += State.regs[OP[1]]; |
408 | if ( tmp > State.regs[OP[0]]) | |
409 | State.C = 1; | |
410 | else | |
411 | State.C = 0; | |
87178dbd | 412 | trace_output (OP_REG); |
2934d1c9 MH |
413 | } |
414 | ||
415 | /* add */ | |
416 | void | |
417 | OP_1201 () | |
418 | { | |
4c38885c | 419 | int64 tmp; |
4f425a32 | 420 | tmp = SEXT40(State.a[OP[0]]) + (SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]); |
87178dbd MM |
421 | |
422 | trace_input ("add", OP_ACCUM, OP_REG, OP_VOID); | |
4c38885c MH |
423 | if (State.ST) |
424 | { | |
425 | if ( tmp > MAX32) | |
426 | State.a[OP[0]] = MAX32; | |
427 | else if ( tmp < MIN32) | |
428 | State.a[OP[0]] = MIN32; | |
429 | else | |
4f425a32 | 430 | State.a[OP[0]] = tmp & MASK40; |
4c38885c MH |
431 | } |
432 | else | |
4f425a32 | 433 | State.a[OP[0]] = tmp & MASK40; |
87178dbd | 434 | trace_output (OP_ACCUM); |
2934d1c9 MH |
435 | } |
436 | ||
437 | /* add */ | |
438 | void | |
439 | OP_1203 () | |
440 | { | |
4c38885c | 441 | int64 tmp; |
4f425a32 | 442 | tmp = SEXT40(State.a[OP[0]]) + SEXT40(State.a[OP[1]]); |
87178dbd MM |
443 | |
444 | trace_input ("add", OP_ACCUM, OP_ACCUM, OP_VOID); | |
4c38885c MH |
445 | if (State.ST) |
446 | { | |
447 | if (tmp > MAX32) | |
448 | State.a[OP[0]] = MAX32; | |
449 | else if ( tmp < MIN32) | |
450 | State.a[OP[0]] = MIN32; | |
451 | else | |
4f425a32 | 452 | State.a[OP[0]] = tmp & MASK40; |
4c38885c MH |
453 | } |
454 | else | |
4f425a32 | 455 | State.a[OP[0]] = tmp & MASK40; |
87178dbd | 456 | trace_output (OP_ACCUM); |
2934d1c9 MH |
457 | } |
458 | ||
459 | /* add2w */ | |
460 | void | |
461 | OP_1200 () | |
462 | { | |
463 | uint32 tmp; | |
464 | uint32 tmp1 = (State.regs[OP[0]]) << 16 | State.regs[OP[0]+1]; | |
465 | uint32 tmp2 = (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]; | |
87178dbd MM |
466 | |
467 | trace_input ("add2w", OP_DREG, OP_DREG, OP_VOID); | |
2934d1c9 MH |
468 | tmp = tmp1 + tmp2; |
469 | if ( (tmp < tmp1) || (tmp < tmp2) ) | |
470 | State.C = 1; | |
471 | else | |
472 | State.C = 0; | |
473 | State.regs[OP[0]] = tmp >> 16; | |
474 | State.regs[OP[0]+1] = tmp & 0xFFFF; | |
87178dbd | 475 | trace_output (OP_DREG); |
2934d1c9 MH |
476 | } |
477 | ||
478 | /* add3 */ | |
479 | void | |
480 | OP_1000000 () | |
481 | { | |
482 | uint16 tmp = State.regs[OP[0]]; | |
2934d1c9 | 483 | State.regs[OP[0]] = State.regs[OP[1]] + OP[2]; |
87178dbd MM |
484 | |
485 | trace_input ("add3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16); | |
2934d1c9 MH |
486 | if ( tmp > State.regs[OP[0]]) |
487 | State.C = 1; | |
488 | else | |
489 | State.C = 0; | |
87178dbd | 490 | trace_output (OP_REG); |
2934d1c9 MH |
491 | } |
492 | ||
493 | /* addac3 */ | |
494 | void | |
495 | OP_17000200 () | |
496 | { | |
4c38885c | 497 | int64 tmp; |
4f425a32 | 498 | tmp = SEXT40(State.a[OP[2]]) + SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]); |
87178dbd MM |
499 | |
500 | trace_input ("addac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM); | |
4c38885c MH |
501 | State.regs[OP[0]] = (tmp >> 16) & 0xffff; |
502 | State.regs[OP[0]+1] = tmp & 0xffff; | |
87178dbd | 503 | trace_output (OP_DREG); |
2934d1c9 MH |
504 | } |
505 | ||
506 | /* addac3 */ | |
507 | void | |
508 | OP_17000202 () | |
509 | { | |
4c38885c | 510 | int64 tmp; |
4f425a32 | 511 | tmp = SEXT40(State.a[OP[1]]) + SEXT40(State.a[OP[2]]); |
87178dbd MM |
512 | |
513 | trace_input ("addac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM); | |
4c38885c MH |
514 | State.regs[OP[0]] = (tmp >> 16) & 0xffff; |
515 | State.regs[OP[0]+1] = tmp & 0xffff; | |
87178dbd | 516 | trace_output (OP_DREG); |
2934d1c9 MH |
517 | } |
518 | ||
519 | /* addac3s */ | |
520 | void | |
521 | OP_17001200 () | |
522 | { | |
4c38885c | 523 | int64 tmp; |
4c38885c | 524 | State.F1 = State.F0; |
87178dbd MM |
525 | |
526 | trace_input ("addac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM); | |
4f425a32 | 527 | tmp = SEXT40(State.a[OP[2]]) + SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]); |
4c38885c MH |
528 | if ( tmp > MAX32) |
529 | { | |
530 | State.regs[OP[0]] = 0x7fff; | |
531 | State.regs[OP[0]+1] = 0xffff; | |
532 | State.F0 = 1; | |
533 | } | |
534 | else if (tmp < MIN32) | |
535 | { | |
536 | State.regs[OP[0]] = 0x8000; | |
537 | State.regs[OP[0]+1] = 0; | |
538 | State.F0 = 1; | |
539 | } | |
540 | else | |
541 | { | |
542 | State.regs[OP[0]] = (tmp >> 16) & 0xffff; | |
543 | State.regs[OP[0]+1] = tmp & 0xffff; | |
544 | State.F0 = 0; | |
545 | } | |
87178dbd | 546 | trace_output (OP_DREG); |
2934d1c9 MH |
547 | } |
548 | ||
549 | /* addac3s */ | |
550 | void | |
551 | OP_17001202 () | |
552 | { | |
4c38885c | 553 | int64 tmp; |
4c38885c | 554 | State.F1 = State.F0; |
87178dbd MM |
555 | |
556 | trace_input ("addac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM); | |
4f425a32 | 557 | tmp = SEXT40(State.a[OP[1]]) + SEXT40(State.a[OP[2]]); |
4c38885c MH |
558 | if ( tmp > MAX32) |
559 | { | |
560 | State.regs[OP[0]] = 0x7fff; | |
561 | State.regs[OP[0]+1] = 0xffff; | |
562 | State.F0 = 1; | |
563 | } | |
564 | else if (tmp < MIN32) | |
565 | { | |
566 | State.regs[OP[0]] = 0x8000; | |
567 | State.regs[OP[0]+1] = 0; | |
568 | State.F0 = 1; | |
569 | } | |
570 | else | |
571 | { | |
572 | State.regs[OP[0]] = (tmp >> 16) & 0xffff; | |
573 | State.regs[OP[0]+1] = tmp & 0xffff; | |
574 | State.F0 = 0; | |
575 | } | |
87178dbd | 576 | trace_output (OP_DREG); |
2934d1c9 MH |
577 | } |
578 | ||
579 | /* addi */ | |
580 | void | |
581 | OP_201 () | |
582 | { | |
4f425a32 MH |
583 | if (OP[1] == 0) |
584 | OP[1] = 16; | |
87178dbd | 585 | trace_input ("addi", OP_REG, OP_CONSTANT16, OP_VOID); |
2934d1c9 | 586 | State.regs[OP[0]] += OP[1]; |
87178dbd | 587 | trace_output (OP_REG); |
2934d1c9 MH |
588 | } |
589 | ||
590 | /* and */ | |
591 | void | |
592 | OP_C00 () | |
593 | { | |
87178dbd | 594 | trace_input ("and", OP_REG, OP_REG, OP_VOID); |
2934d1c9 | 595 | State.regs[OP[0]] &= State.regs[OP[1]]; |
87178dbd | 596 | trace_output (OP_REG); |
2934d1c9 MH |
597 | } |
598 | ||
599 | /* and3 */ | |
600 | void | |
601 | OP_6000000 () | |
602 | { | |
87178dbd | 603 | trace_input ("and3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16); |
2934d1c9 | 604 | State.regs[OP[0]] = State.regs[OP[1]] & OP[2]; |
87178dbd | 605 | trace_output (OP_REG); |
2934d1c9 MH |
606 | } |
607 | ||
608 | /* bclri */ | |
609 | void | |
610 | OP_C01 () | |
611 | { | |
87178dbd | 612 | trace_input ("bclri", OP_REG, OP_CONSTANT16, OP_VOID); |
2934d1c9 | 613 | State.regs[OP[0]] &= ~(0x8000 >> OP[1]); |
87178dbd | 614 | trace_output (OP_REG); |
2934d1c9 MH |
615 | } |
616 | ||
617 | /* bl.s */ | |
618 | void | |
619 | OP_4900 () | |
620 | { | |
87178dbd | 621 | trace_input ("bl.s", OP_CONSTANT16, OP_VOID, OP_VOID); |
2934d1c9 MH |
622 | State.regs[13] = PC+1; |
623 | PC += SEXT8 (OP[0]); | |
87178dbd | 624 | trace_output (OP_VOID); |
2934d1c9 MH |
625 | } |
626 | ||
627 | /* bl.l */ | |
628 | void | |
629 | OP_24800000 () | |
630 | { | |
87178dbd | 631 | trace_input ("bl.l", OP_CONSTANT16, OP_VOID, OP_VOID); |
2934d1c9 MH |
632 | State.regs[13] = PC+1; |
633 | PC += OP[0]; | |
87178dbd | 634 | trace_output (OP_VOID); |
2934d1c9 MH |
635 | } |
636 | ||
637 | /* bnoti */ | |
638 | void | |
639 | OP_A01 () | |
640 | { | |
87178dbd | 641 | trace_input ("bnoti", OP_REG, OP_CONSTANT16, OP_VOID); |
2934d1c9 | 642 | State.regs[OP[0]] ^= 0x8000 >> OP[1]; |
87178dbd | 643 | trace_output (OP_REG); |
2934d1c9 MH |
644 | } |
645 | ||
646 | /* bra.s */ | |
647 | void | |
648 | OP_4800 () | |
649 | { | |
87178dbd | 650 | trace_input ("bra.s", OP_CONSTANT16, OP_VOID, OP_VOID); |
2934d1c9 | 651 | PC += SEXT8 (OP[0]); |
87178dbd | 652 | trace_output (OP_VOID); |
2934d1c9 MH |
653 | } |
654 | ||
655 | /* bra.l */ | |
656 | void | |
657 | OP_24000000 () | |
658 | { | |
87178dbd | 659 | trace_input ("bra.l", OP_CONSTANT16, OP_VOID, OP_VOID); |
2934d1c9 | 660 | PC += OP[0]; |
87178dbd | 661 | trace_output (OP_VOID); |
2934d1c9 MH |
662 | } |
663 | ||
664 | /* brf0f.s */ | |
665 | void | |
666 | OP_4A00 () | |
667 | { | |
87178dbd | 668 | trace_input ("brf0f.s", OP_CONSTANT16, OP_VOID, OP_VOID); |
2934d1c9 MH |
669 | if (State.F0 == 0) |
670 | PC += SEXT8 (OP[0]); | |
87178dbd | 671 | trace_output (OP_FLAG); |
2934d1c9 MH |
672 | } |
673 | ||
674 | /* brf0f.l */ | |
675 | void | |
676 | OP_25000000 () | |
677 | { | |
87178dbd | 678 | trace_input ("brf0f.l", OP_CONSTANT16, OP_VOID, OP_VOID); |
2934d1c9 MH |
679 | if (State.F0 == 0) |
680 | PC += OP[0]; | |
87178dbd | 681 | trace_output (OP_FLAG); |
2934d1c9 MH |
682 | } |
683 | ||
684 | /* brf0t.s */ | |
685 | void | |
686 | OP_4B00 () | |
687 | { | |
87178dbd | 688 | trace_input ("brf0t.s", OP_CONSTANT16, OP_VOID, OP_VOID); |
2934d1c9 MH |
689 | if (State.F0) |
690 | PC += SEXT8 (OP[0]); | |
87178dbd | 691 | trace_output (OP_FLAG); |
2934d1c9 MH |
692 | } |
693 | ||
694 | /* brf0t.l */ | |
695 | void | |
696 | OP_25800000 () | |
697 | { | |
87178dbd | 698 | trace_input ("brf0t.l", OP_CONSTANT16, OP_VOID, OP_VOID); |
2934d1c9 MH |
699 | if (State.F0) |
700 | PC += OP[0]; | |
87178dbd | 701 | trace_output (OP_FLAG); |
2934d1c9 MH |
702 | } |
703 | ||
704 | /* bseti */ | |
705 | void | |
706 | OP_801 () | |
707 | { | |
87178dbd | 708 | trace_input ("bseti", OP_REG, OP_CONSTANT16, OP_VOID); |
2934d1c9 | 709 | State.regs[OP[0]] |= 0x8000 >> OP[1]; |
87178dbd | 710 | trace_output (OP_REG); |
2934d1c9 MH |
711 | } |
712 | ||
713 | /* btsti */ | |
714 | void | |
715 | OP_E01 () | |
716 | { | |
87178dbd | 717 | trace_input ("btsti", OP_REG, OP_CONSTANT16, OP_VOID); |
2934d1c9 MH |
718 | State.F1 = State.F0; |
719 | State.F0 = (State.regs[OP[0]] & (0x8000 >> OP[1])) ? 1 : 0; | |
87178dbd | 720 | trace_output (OP_FLAG); |
2934d1c9 MH |
721 | } |
722 | ||
723 | /* clrac */ | |
724 | void | |
725 | OP_5601 () | |
726 | { | |
87178dbd | 727 | trace_input ("clrac", OP_ACCUM_OUTPUT, OP_VOID, OP_VOID); |
2934d1c9 | 728 | State.a[OP[0]] = 0; |
87178dbd | 729 | trace_output (OP_ACCUM); |
2934d1c9 MH |
730 | } |
731 | ||
732 | /* cmp */ | |
733 | void | |
734 | OP_600 () | |
735 | { | |
87178dbd | 736 | trace_input ("cmp", OP_REG, OP_REG, OP_VOID); |
2934d1c9 MH |
737 | State.F1 = State.F0; |
738 | State.F0 = ((int16)(State.regs[OP[0]]) < (int16)(State.regs[OP[1]])) ? 1 : 0; | |
87178dbd | 739 | trace_output (OP_FLAG); |
2934d1c9 MH |
740 | } |
741 | ||
742 | /* cmp */ | |
743 | void | |
744 | OP_1603 () | |
745 | { | |
87178dbd | 746 | trace_input ("cmp", OP_ACCUM, OP_ACCUM, OP_VOID); |
4c38885c | 747 | State.F1 = State.F0; |
4f425a32 | 748 | State.F0 = (SEXT40(State.a[OP[0]]) < SEXT40(State.a[OP[1]])) ? 1 : 0; |
87178dbd | 749 | trace_output (OP_FLAG); |
2934d1c9 MH |
750 | } |
751 | ||
752 | /* cmpeq */ | |
753 | void | |
754 | OP_400 () | |
755 | { | |
87178dbd | 756 | trace_input ("cmpeq", OP_REG, OP_REG, OP_VOID); |
2934d1c9 MH |
757 | State.F1 = State.F0; |
758 | State.F0 = (State.regs[OP[0]] == State.regs[OP[1]]) ? 1 : 0; | |
87178dbd | 759 | trace_output (OP_FLAG); |
2934d1c9 MH |
760 | } |
761 | ||
762 | /* cmpeq */ | |
763 | void | |
764 | OP_1403 () | |
765 | { | |
87178dbd | 766 | trace_input ("cmpeq", OP_ACCUM, OP_ACCUM, OP_VOID); |
4c38885c MH |
767 | State.F1 = State.F0; |
768 | State.F0 = (State.a[OP[0]] == State.a[OP[1]]) ? 1 : 0; | |
87178dbd | 769 | trace_output (OP_FLAG); |
2934d1c9 MH |
770 | } |
771 | ||
772 | /* cmpeqi.s */ | |
773 | void | |
774 | OP_401 () | |
775 | { | |
87178dbd | 776 | trace_input ("cmpeqi.s", OP_REG, OP_CONSTANT16, OP_VOID); |
2934d1c9 MH |
777 | State.F1 = State.F0; |
778 | State.F0 = (State.regs[OP[0]] == SEXT4(OP[1])) ? 1 : 0; | |
87178dbd | 779 | trace_output (OP_FLAG); |
2934d1c9 MH |
780 | } |
781 | ||
782 | /* cmpeqi.l */ | |
783 | void | |
784 | OP_2000000 () | |
785 | { | |
87178dbd | 786 | trace_input ("cmpeqi.l", OP_REG, OP_CONSTANT16, OP_VOID); |
2934d1c9 MH |
787 | State.F1 = State.F0; |
788 | State.F0 = (State.regs[OP[0]] == OP[1]) ? 1 : 0; | |
87178dbd | 789 | trace_output (OP_FLAG); |
2934d1c9 MH |
790 | } |
791 | ||
792 | /* cmpi.s */ | |
793 | void | |
794 | OP_601 () | |
795 | { | |
87178dbd | 796 | trace_input ("cmpi.s", OP_REG, OP_CONSTANT4, OP_VOID); |
2934d1c9 MH |
797 | State.F1 = State.F0; |
798 | State.F0 = ((int16)(State.regs[OP[0]]) < SEXT4(OP[1])) ? 1 : 0; | |
87178dbd | 799 | trace_output (OP_FLAG); |
2934d1c9 MH |
800 | } |
801 | ||
802 | /* cmpi.l */ | |
803 | void | |
804 | OP_3000000 () | |
805 | { | |
87178dbd | 806 | trace_input ("cmpi.l", OP_REG, OP_CONSTANT16, OP_VOID); |
2934d1c9 MH |
807 | State.F1 = State.F0; |
808 | State.F0 = ((int16)(State.regs[OP[0]]) < (int16)(OP[1])) ? 1 : 0; | |
87178dbd | 809 | trace_output (OP_FLAG); |
2934d1c9 MH |
810 | } |
811 | ||
812 | /* cmpu */ | |
813 | void | |
814 | OP_4600 () | |
815 | { | |
87178dbd | 816 | trace_input ("cmpu", OP_REG, OP_REG, OP_VOID); |
2934d1c9 MH |
817 | State.F1 = State.F0; |
818 | State.F0 = (State.regs[OP[0]] < State.regs[OP[1]]) ? 1 : 0; | |
87178dbd | 819 | trace_output (OP_FLAG); |
2934d1c9 MH |
820 | } |
821 | ||
822 | /* cmpui */ | |
823 | void | |
824 | OP_23000000 () | |
825 | { | |
87178dbd | 826 | trace_input ("cmpui", OP_REG, OP_CONSTANT16, OP_VOID); |
2934d1c9 MH |
827 | State.F1 = State.F0; |
828 | State.F0 = (State.regs[OP[0]] < OP[1]) ? 1 : 0; | |
87178dbd | 829 | trace_output (OP_FLAG); |
2934d1c9 MH |
830 | } |
831 | ||
832 | /* cpfg */ | |
833 | void | |
834 | OP_4E09 () | |
835 | { | |
836 | uint8 *src, *dst; | |
2934d1c9 | 837 | |
87178dbd | 838 | trace_input ("cpfg", OP_FLAG, OP_VOID, OP_VOID); |
2934d1c9 MH |
839 | if (OP[0] == 0) |
840 | dst = &State.F0; | |
841 | else | |
842 | dst = &State.F1; | |
843 | ||
844 | if (OP[1] == 0) | |
845 | src = &State.F0; | |
846 | else if (OP[1] == 1) | |
847 | src = &State.F1; | |
848 | else | |
849 | src = &State.C; | |
850 | ||
851 | *dst = *src; | |
87178dbd | 852 | trace_output (OP_FLAG); |
2934d1c9 MH |
853 | } |
854 | ||
855 | /* dbt */ | |
856 | void | |
857 | OP_5F20 () | |
858 | { | |
7eebfc62 | 859 | d10v_callback->printf_filtered(d10v_callback, "***** DBT ***** PC=%x\n",PC); |
4f425a32 | 860 | State.exception = SIGTRAP; |
2934d1c9 MH |
861 | } |
862 | ||
863 | /* divs */ | |
864 | void | |
865 | OP_14002800 () | |
866 | { | |
867 | uint16 foo, tmp, tmpf; | |
87178dbd MM |
868 | |
869 | trace_input ("divs", OP_DREG, OP_REG, OP_VOID); | |
2934d1c9 MH |
870 | foo = (State.regs[OP[0]] << 1) | (State.regs[OP[0]+1] >> 15); |
871 | tmp = (int16)foo - (int16)(State.regs[OP[1]]); | |
872 | tmpf = (foo >= State.regs[OP[1]]) ? 1 : 0; | |
873 | State.regs[OP[0]] = (tmpf == 1) ? tmp : foo; | |
874 | State.regs[OP[0]+1] = (State.regs[OP[0]+1] << 1) | tmpf; | |
87178dbd | 875 | trace_output (OP_DREG); |
2934d1c9 MH |
876 | } |
877 | ||
878 | /* exef0f */ | |
879 | void | |
880 | OP_4E04 () | |
881 | { | |
87178dbd | 882 | trace_input ("exef0f", OP_VOID, OP_VOID, OP_VOID); |
2934d1c9 | 883 | State.exe = (State.F0) ? 0 : 1; |
87178dbd | 884 | trace_output (OP_FLAG); |
2934d1c9 MH |
885 | } |
886 | ||
887 | /* exef0t */ | |
888 | void | |
889 | OP_4E24 () | |
890 | { | |
87178dbd | 891 | trace_input ("exef0t", OP_VOID, OP_VOID, OP_VOID); |
2934d1c9 | 892 | State.exe = State.F0; |
87178dbd | 893 | trace_output (OP_FLAG); |
2934d1c9 MH |
894 | } |
895 | ||
896 | /* exef1f */ | |
897 | void | |
898 | OP_4E40 () | |
899 | { | |
87178dbd | 900 | trace_input ("exef1f", OP_VOID, OP_VOID, OP_VOID); |
2934d1c9 | 901 | State.exe = (State.F1) ? 0 : 1; |
87178dbd | 902 | trace_output (OP_FLAG); |
2934d1c9 MH |
903 | } |
904 | ||
905 | /* exef1t */ | |
906 | void | |
907 | OP_4E42 () | |
908 | { | |
87178dbd | 909 | trace_input ("exef1t", OP_VOID, OP_VOID, OP_VOID); |
2934d1c9 | 910 | State.exe = State.F1; |
87178dbd | 911 | trace_output (OP_FLAG); |
2934d1c9 MH |
912 | } |
913 | ||
914 | /* exefaf */ | |
915 | void | |
916 | OP_4E00 () | |
917 | { | |
87178dbd | 918 | trace_input ("exefaf", OP_VOID, OP_VOID, OP_VOID); |
2934d1c9 | 919 | State.exe = (State.F0 | State.F1) ? 0 : 1; |
87178dbd | 920 | trace_output (OP_FLAG); |
2934d1c9 MH |
921 | } |
922 | ||
923 | /* exefat */ | |
924 | void | |
925 | OP_4E02 () | |
926 | { | |
87178dbd | 927 | trace_input ("exefat", OP_VOID, OP_VOID, OP_VOID); |
2934d1c9 | 928 | State.exe = (State.F0) ? 0 : (State.F1); |
87178dbd | 929 | trace_output (OP_FLAG); |
2934d1c9 MH |
930 | } |
931 | ||
932 | /* exetaf */ | |
933 | void | |
934 | OP_4E20 () | |
935 | { | |
87178dbd | 936 | trace_input ("exetaf", OP_VOID, OP_VOID, OP_VOID); |
2934d1c9 | 937 | State.exe = (State.F1) ? 0 : (State.F0); |
87178dbd | 938 | trace_output (OP_FLAG); |
2934d1c9 MH |
939 | } |
940 | ||
941 | /* exetat */ | |
942 | void | |
943 | OP_4E22 () | |
944 | { | |
87178dbd | 945 | trace_input ("exetat", OP_VOID, OP_VOID, OP_VOID); |
2934d1c9 | 946 | State.exe = (State.F0) ? (State.F1) : 0; |
87178dbd | 947 | trace_output (OP_FLAG); |
2934d1c9 MH |
948 | } |
949 | ||
950 | /* exp */ | |
951 | void | |
952 | OP_15002A00 () | |
953 | { | |
954 | uint32 tmp, foo; | |
955 | int i; | |
956 | ||
87178dbd | 957 | trace_input ("exp", OP_REG_OUTPUT, OP_DREG, OP_VOID); |
4c38885c MH |
958 | if (((int16)State.regs[OP[1]]) >= 0) |
959 | tmp = (State.regs[OP[1]] << 16) | State.regs[OP[1]+1]; | |
2934d1c9 | 960 | else |
4c38885c | 961 | tmp = ~((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]); |
2934d1c9 MH |
962 | |
963 | foo = 0x40000000; | |
4c38885c | 964 | for (i=1;i<17;i++) |
2934d1c9 MH |
965 | { |
966 | if (tmp & foo) | |
967 | { | |
968 | State.regs[OP[0]] = i-1; | |
87178dbd | 969 | trace_output (OP_REG); |
2934d1c9 MH |
970 | return; |
971 | } | |
4c38885c | 972 | foo >>= 1; |
2934d1c9 MH |
973 | } |
974 | State.regs[OP[0]] = 16; | |
87178dbd | 975 | trace_output (OP_REG); |
2934d1c9 MH |
976 | } |
977 | ||
978 | /* exp */ | |
979 | void | |
980 | OP_15002A02 () | |
981 | { | |
4c38885c MH |
982 | int64 tmp, foo; |
983 | int i; | |
87178dbd MM |
984 | |
985 | trace_input ("exp", OP_REG_OUTPUT, OP_ACCUM, OP_VOID); | |
4f425a32 | 986 | if (SEXT40(State.a[OP[1]]) >= 0) |
4c38885c MH |
987 | tmp = State.a[OP[1]]; |
988 | else | |
989 | tmp = ~(State.a[OP[1]]); | |
990 | ||
991 | foo = 0x4000000000LL; | |
992 | for (i=1;i<25;i++) | |
993 | { | |
994 | if (tmp & foo) | |
995 | { | |
996 | State.regs[OP[0]] = i-9; | |
87178dbd | 997 | trace_output (OP_REG); |
4c38885c MH |
998 | return; |
999 | } | |
1000 | foo >>= 1; | |
1001 | } | |
1002 | State.regs[OP[0]] = 16; | |
87178dbd | 1003 | trace_output (OP_REG); |
2934d1c9 MH |
1004 | } |
1005 | ||
1006 | /* jl */ | |
1007 | void | |
1008 | OP_4D00 () | |
1009 | { | |
87178dbd | 1010 | trace_input ("jl", OP_REG, OP_VOID, OP_VOID); |
2934d1c9 MH |
1011 | State.regs[13] = PC+1; |
1012 | PC = State.regs[OP[0]]; | |
87178dbd | 1013 | trace_output (OP_VOID); |
2934d1c9 MH |
1014 | } |
1015 | ||
1016 | /* jmp */ | |
1017 | void | |
1018 | OP_4C00 () | |
1019 | { | |
87178dbd | 1020 | trace_input ("jmp", OP_REG, OP_VOID, OP_VOID); |
2934d1c9 | 1021 | PC = State.regs[OP[0]]; |
87178dbd | 1022 | trace_output (OP_VOID); |
2934d1c9 MH |
1023 | } |
1024 | ||
1025 | /* ld */ | |
1026 | void | |
1027 | OP_30000000 () | |
1028 | { | |
87178dbd | 1029 | trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID); |
2934d1c9 | 1030 | State.regs[OP[0]] = RW (OP[1] + State.regs[OP[2]]); |
87178dbd | 1031 | trace_output (OP_REG); |
2934d1c9 MH |
1032 | } |
1033 | ||
1034 | /* ld */ | |
1035 | void | |
1036 | OP_6401 () | |
1037 | { | |
87178dbd | 1038 | trace_input ("ld", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID); |
4c38885c | 1039 | State.regs[OP[0]] = RW (State.regs[OP[1]]); |
4f425a32 | 1040 | INC_ADDR(State.regs[OP[1]],-2); |
87178dbd | 1041 | trace_output (OP_REG); |
2934d1c9 MH |
1042 | } |
1043 | ||
1044 | /* ld */ | |
1045 | void | |
1046 | OP_6001 () | |
1047 | { | |
87178dbd | 1048 | trace_input ("ld", OP_REG_OUTPUT, OP_POSTINC, OP_VOID); |
4c38885c | 1049 | State.regs[OP[0]] = RW (State.regs[OP[1]]); |
4f425a32 | 1050 | INC_ADDR(State.regs[OP[1]],2); |
87178dbd | 1051 | trace_output (OP_REG); |
2934d1c9 MH |
1052 | } |
1053 | ||
1054 | /* ld */ | |
1055 | void | |
1056 | OP_6000 () | |
1057 | { | |
87178dbd | 1058 | trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF, OP_VOID); |
2934d1c9 | 1059 | State.regs[OP[0]] = RW (State.regs[OP[1]]); |
87178dbd | 1060 | trace_output (OP_REG); |
2934d1c9 MH |
1061 | } |
1062 | ||
1063 | /* ld2w */ | |
1064 | void | |
1065 | OP_31000000 () | |
1066 | { | |
87178dbd | 1067 | trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF, OP_VOID); |
2934d1c9 MH |
1068 | State.regs[OP[0]] = RW (OP[1] + State.regs[OP[2]]); |
1069 | State.regs[OP[0]+1] = RW (OP[1] + State.regs[OP[2]] + 2); | |
87178dbd | 1070 | trace_output (OP_DREG); |
2934d1c9 MH |
1071 | } |
1072 | ||
1073 | /* ld2w */ | |
1074 | void | |
1075 | OP_6601 () | |
1076 | { | |
87178dbd | 1077 | trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID); |
4c38885c MH |
1078 | State.regs[OP[0]] = RW (State.regs[OP[1]]); |
1079 | State.regs[OP[0]+1] = RW (State.regs[OP[1]]+2); | |
4f425a32 | 1080 | INC_ADDR(State.regs[OP[1]],-4); |
87178dbd | 1081 | trace_output (OP_DREG); |
2934d1c9 MH |
1082 | } |
1083 | ||
1084 | /* ld2w */ | |
1085 | void | |
1086 | OP_6201 () | |
1087 | { | |
87178dbd | 1088 | trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTINC, OP_VOID); |
4c38885c MH |
1089 | State.regs[OP[0]] = RW (State.regs[OP[1]]); |
1090 | State.regs[OP[0]+1] = RW (State.regs[OP[1]]+2); | |
4f425a32 | 1091 | INC_ADDR(State.regs[OP[1]],4); |
87178dbd | 1092 | trace_output (OP_REG); |
2934d1c9 MH |
1093 | } |
1094 | ||
1095 | /* ld2w */ | |
1096 | void | |
1097 | OP_6200 () | |
1098 | { | |
87178dbd | 1099 | trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF, OP_VOID); |
4c38885c MH |
1100 | State.regs[OP[0]] = RW (State.regs[OP[1]]); |
1101 | State.regs[OP[0]+1] = RW (State.regs[OP[1]]+2); | |
87178dbd | 1102 | trace_output (OP_REG); |
2934d1c9 MH |
1103 | } |
1104 | ||
1105 | /* ldb */ | |
1106 | void | |
1107 | OP_38000000 () | |
1108 | { | |
87178dbd | 1109 | trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID); |
2934d1c9 MH |
1110 | State.regs[OP[0]] = RB (OP[1] + State.regs[OP[2]]); |
1111 | SEXT8 (State.regs[OP[0]]); | |
87178dbd | 1112 | trace_output (OP_REG); |
2934d1c9 MH |
1113 | } |
1114 | ||
1115 | /* ldb */ | |
1116 | void | |
1117 | OP_7000 () | |
1118 | { | |
87178dbd | 1119 | trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF, OP_VOID); |
2934d1c9 MH |
1120 | State.regs[OP[0]] = RB (State.regs[OP[1]]); |
1121 | SEXT8 (State.regs[OP[0]]); | |
87178dbd | 1122 | trace_output (OP_REG); |
2934d1c9 MH |
1123 | } |
1124 | ||
1125 | /* ldi.s */ | |
1126 | void | |
1127 | OP_4001 () | |
1128 | { | |
87178dbd | 1129 | trace_input ("ldi.s", OP_REG_OUTPUT, OP_CONSTANT4, OP_VOID); |
2934d1c9 | 1130 | State.regs[OP[0]] = SEXT4(OP[1]); |
87178dbd | 1131 | trace_output (OP_REG); |
2934d1c9 MH |
1132 | } |
1133 | ||
1134 | /* ldi.l */ | |
1135 | void | |
1136 | OP_20000000 () | |
1137 | { | |
87178dbd | 1138 | trace_input ("ldi.s", OP_REG_OUTPUT, OP_CONSTANT16, OP_VOID); |
2934d1c9 | 1139 | State.regs[OP[0]] = OP[1]; |
87178dbd | 1140 | trace_output (OP_REG); |
2934d1c9 MH |
1141 | } |
1142 | ||
1143 | /* ldub */ | |
1144 | void | |
1145 | OP_39000000 () | |
1146 | { | |
87178dbd | 1147 | trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID); |
2934d1c9 | 1148 | State.regs[OP[0]] = RB (OP[1] + State.regs[OP[2]]); |
87178dbd | 1149 | trace_output (OP_REG); |
2934d1c9 MH |
1150 | } |
1151 | ||
1152 | /* ldub */ | |
1153 | void | |
1154 | OP_7200 () | |
1155 | { | |
87178dbd | 1156 | trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF, OP_VOID); |
2934d1c9 | 1157 | State.regs[OP[0]] = RB (State.regs[OP[1]]); |
87178dbd | 1158 | trace_output (OP_REG); |
2934d1c9 MH |
1159 | } |
1160 | ||
1161 | /* mac */ | |
1162 | void | |
1163 | OP_2A00 () | |
1164 | { | |
4c38885c | 1165 | int64 tmp; |
87178dbd MM |
1166 | |
1167 | trace_input ("mac", OP_ACCUM, OP_REG, OP_REG); | |
4f425a32 | 1168 | tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]])); |
4c38885c MH |
1169 | |
1170 | if (State.FX) | |
4f425a32 | 1171 | tmp = SEXT40( (tmp << 1) & MASK40); |
4c38885c MH |
1172 | |
1173 | if (State.ST && tmp > MAX32) | |
1174 | tmp = MAX32; | |
1175 | ||
4f425a32 | 1176 | tmp += SEXT40(State.a[OP[0]]); |
4c38885c MH |
1177 | if (State.ST) |
1178 | { | |
1179 | if (tmp > MAX32) | |
1180 | State.a[OP[0]] = MAX32; | |
1181 | else if (tmp < MIN32) | |
1182 | State.a[OP[0]] = MIN32; | |
1183 | else | |
4f425a32 | 1184 | State.a[OP[0]] = tmp & MASK40; |
4c38885c MH |
1185 | } |
1186 | else | |
4f425a32 | 1187 | State.a[OP[0]] = tmp & MASK40; |
87178dbd | 1188 | trace_output (OP_ACCUM); |
2934d1c9 MH |
1189 | } |
1190 | ||
1191 | /* macsu */ | |
1192 | void | |
1193 | OP_1A00 () | |
1194 | { | |
4f425a32 | 1195 | int64 tmp; |
87178dbd MM |
1196 | |
1197 | trace_input ("macsu", OP_ACCUM, OP_REG, OP_REG); | |
4f425a32 MH |
1198 | tmp = SEXT40 ((int16)State.regs[OP[1]] * State.regs[OP[2]]); |
1199 | if (State.FX) | |
1200 | tmp = SEXT40( (tmp << 1) & MASK40); | |
1201 | ||
1202 | State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) + tmp) & MASK40; | |
87178dbd | 1203 | trace_output (OP_ACCUM); |
2934d1c9 MH |
1204 | } |
1205 | ||
1206 | /* macu */ | |
1207 | void | |
1208 | OP_3A00 () | |
1209 | { | |
4f425a32 | 1210 | int64 tmp; |
87178dbd MM |
1211 | |
1212 | trace_input ("macu", OP_ACCUM, OP_REG, OP_REG); | |
4f425a32 MH |
1213 | tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]); |
1214 | if (State.FX) | |
1215 | tmp = SEXT40( (tmp << 1) & MASK40); | |
1216 | State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) + tmp) & MASK40; | |
87178dbd | 1217 | trace_output (OP_ACCUM); |
2934d1c9 MH |
1218 | } |
1219 | ||
1220 | /* max */ | |
1221 | void | |
1222 | OP_2600 () | |
1223 | { | |
87178dbd | 1224 | trace_input ("max", OP_REG, OP_REG, OP_VOID); |
2934d1c9 | 1225 | State.F1 = State.F0; |
ea2155e8 | 1226 | if ((int16)State.regs[OP[1]] > (int16)State.regs[OP[0]]) |
2934d1c9 MH |
1227 | { |
1228 | State.regs[OP[0]] = State.regs[OP[1]]; | |
1229 | State.F0 = 1; | |
1230 | } | |
1231 | else | |
1232 | State.F0 = 0; | |
87178dbd | 1233 | trace_output (OP_REG); |
2934d1c9 MH |
1234 | } |
1235 | ||
1236 | /* max */ | |
1237 | void | |
1238 | OP_3600 () | |
1239 | { | |
4f425a32 | 1240 | int64 tmp; |
87178dbd MM |
1241 | |
1242 | trace_input ("max", OP_ACCUM, OP_DREG, OP_VOID); | |
4f425a32 MH |
1243 | State.F1 = State.F0; |
1244 | tmp = SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]; | |
1245 | if (tmp > SEXT40(State.a[OP[0]])) | |
1246 | { | |
1247 | State.a[OP[0]] = tmp & MASK40; | |
1248 | State.F0 = 1; | |
1249 | } | |
1250 | else | |
1251 | State.F0 = 0; | |
87178dbd | 1252 | trace_output (OP_ACCUM); |
2934d1c9 MH |
1253 | } |
1254 | ||
1255 | /* max */ | |
1256 | void | |
1257 | OP_3602 () | |
1258 | { | |
87178dbd | 1259 | trace_input ("max", OP_ACCUM, OP_ACCUM, OP_VOID); |
4f425a32 MH |
1260 | State.F1 = State.F0; |
1261 | if (SEXT40(State.a[OP[1]]) > SEXT40(State.a[OP[0]])) | |
1262 | { | |
1263 | State.a[OP[0]] = State.a[OP[1]]; | |
1264 | State.F0 = 1; | |
1265 | } | |
1266 | else | |
1267 | State.F0 = 0; | |
87178dbd | 1268 | trace_output (OP_ACCUM); |
2934d1c9 MH |
1269 | } |
1270 | ||
4f425a32 | 1271 | |
2934d1c9 MH |
1272 | /* min */ |
1273 | void | |
1274 | OP_2601 () | |
1275 | { | |
87178dbd | 1276 | trace_input ("min", OP_REG, OP_REG, OP_VOID); |
2934d1c9 | 1277 | State.F1 = State.F0; |
ea2155e8 | 1278 | if ((int16)State.regs[OP[1]] < (int16)State.regs[OP[0]]) |
2934d1c9 MH |
1279 | { |
1280 | State.regs[OP[0]] = State.regs[OP[1]]; | |
1281 | State.F0 = 1; | |
1282 | } | |
1283 | else | |
1284 | State.F0 = 0; | |
87178dbd | 1285 | trace_output (OP_REG); |
2934d1c9 MH |
1286 | } |
1287 | ||
1288 | /* min */ | |
1289 | void | |
1290 | OP_3601 () | |
1291 | { | |
4f425a32 | 1292 | int64 tmp; |
87178dbd MM |
1293 | |
1294 | trace_input ("min", OP_ACCUM, OP_DREG, OP_VOID); | |
4f425a32 MH |
1295 | State.F1 = State.F0; |
1296 | tmp = SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]; | |
1297 | if (tmp < SEXT40(State.a[OP[0]])) | |
1298 | { | |
1299 | State.a[OP[0]] = tmp & MASK40; | |
1300 | State.F0 = 1; | |
1301 | } | |
1302 | else | |
1303 | State.F0 = 0; | |
87178dbd | 1304 | trace_output (OP_ACCUM); |
2934d1c9 MH |
1305 | } |
1306 | ||
1307 | /* min */ | |
1308 | void | |
1309 | OP_3603 () | |
1310 | { | |
87178dbd | 1311 | trace_input ("min", OP_ACCUM, OP_ACCUM, OP_VOID); |
4f425a32 MH |
1312 | State.F1 = State.F0; |
1313 | if (SEXT40(State.a[OP[1]]) < SEXT40(State.a[OP[0]])) | |
1314 | { | |
1315 | State.a[OP[0]] = State.a[OP[1]]; | |
1316 | State.F0 = 1; | |
1317 | } | |
1318 | else | |
1319 | State.F0 = 0; | |
87178dbd | 1320 | trace_output (OP_ACCUM); |
2934d1c9 MH |
1321 | } |
1322 | ||
1323 | /* msb */ | |
1324 | void | |
1325 | OP_2800 () | |
1326 | { | |
4f425a32 | 1327 | int64 tmp; |
87178dbd MM |
1328 | |
1329 | trace_input ("msb", OP_ACCUM, OP_REG, OP_REG); | |
4f425a32 MH |
1330 | tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]])); |
1331 | ||
1332 | if (State.FX) | |
1333 | tmp = SEXT40 ((tmp << 1) & MASK40); | |
1334 | ||
1335 | if (State.ST && tmp > MAX32) | |
1336 | tmp = MAX32; | |
1337 | ||
1338 | tmp = SEXT40(State.a[OP[0]]) - tmp; | |
1339 | if (State.ST) | |
1340 | { | |
1341 | if (tmp > MAX32) | |
1342 | State.a[OP[0]] = MAX32; | |
1343 | else if (tmp < MIN32) | |
1344 | State.a[OP[0]] = MIN32; | |
1345 | else | |
1346 | State.a[OP[0]] = tmp & MASK40; | |
1347 | } | |
1348 | else | |
1349 | State.a[OP[0]] = tmp & MASK40; | |
87178dbd | 1350 | trace_output (OP_ACCUM); |
2934d1c9 MH |
1351 | } |
1352 | ||
1353 | /* msbsu */ | |
1354 | void | |
1355 | OP_1800 () | |
1356 | { | |
4f425a32 | 1357 | int64 tmp; |
87178dbd MM |
1358 | |
1359 | trace_input ("msbsu", OP_ACCUM, OP_REG, OP_REG); | |
4f425a32 MH |
1360 | tmp = SEXT40 ((int16)State.regs[OP[1]] * State.regs[OP[2]]); |
1361 | if (State.FX) | |
1362 | tmp = SEXT40( (tmp << 1) & MASK40); | |
1363 | ||
1364 | State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) - tmp) & MASK40; | |
87178dbd | 1365 | trace_output (OP_ACCUM); |
2934d1c9 MH |
1366 | } |
1367 | ||
1368 | /* msbu */ | |
1369 | void | |
1370 | OP_3800 () | |
1371 | { | |
4f425a32 | 1372 | int64 tmp; |
87178dbd MM |
1373 | |
1374 | trace_input ("msbu", OP_ACCUM, OP_REG, OP_REG); | |
4f425a32 MH |
1375 | tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]); |
1376 | if (State.FX) | |
1377 | tmp = SEXT40( (tmp << 1) & MASK40); | |
1378 | ||
1379 | State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) - tmp) & MASK40; | |
87178dbd | 1380 | trace_output (OP_ACCUM); |
2934d1c9 MH |
1381 | } |
1382 | ||
1383 | /* mul */ | |
1384 | void | |
1385 | OP_2E00 () | |
1386 | { | |
87178dbd | 1387 | trace_input ("mul", OP_REG, OP_REG, OP_VOID); |
2934d1c9 | 1388 | State.regs[OP[0]] *= State.regs[OP[1]]; |
87178dbd | 1389 | trace_output (OP_REG); |
2934d1c9 MH |
1390 | } |
1391 | ||
1392 | /* mulx */ | |
1393 | void | |
1394 | OP_2C00 () | |
1395 | { | |
4f425a32 | 1396 | int64 tmp; |
87178dbd MM |
1397 | |
1398 | trace_input ("mulx", OP_ACCUM_OUTPUT, OP_REG, OP_REG); | |
4f425a32 MH |
1399 | tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]])); |
1400 | ||
1401 | if (State.FX) | |
1402 | tmp = SEXT40 ((tmp << 1) & MASK40); | |
1403 | ||
1404 | if (State.ST && tmp > MAX32) | |
1405 | State.a[OP[0]] = MAX32; | |
1406 | else | |
1407 | State.a[OP[0]] = tmp & MASK40; | |
87178dbd | 1408 | trace_output (OP_ACCUM); |
2934d1c9 MH |
1409 | } |
1410 | ||
1411 | /* mulxsu */ | |
1412 | void | |
1413 | OP_1C00 () | |
1414 | { | |
4f425a32 | 1415 | int64 tmp; |
87178dbd MM |
1416 | |
1417 | trace_input ("mulxsu", OP_ACCUM_OUTPUT, OP_REG, OP_REG); | |
4f425a32 MH |
1418 | tmp = SEXT40 ((int16)(State.regs[OP[1]]) * State.regs[OP[2]]); |
1419 | ||
1420 | if (State.FX) | |
1421 | tmp <<= 1; | |
1422 | ||
1423 | State.a[OP[0]] = tmp & MASK40; | |
87178dbd | 1424 | trace_output (OP_ACCUM); |
2934d1c9 MH |
1425 | } |
1426 | ||
1427 | /* mulxu */ | |
1428 | void | |
1429 | OP_3C00 () | |
1430 | { | |
4f425a32 | 1431 | int64 tmp; |
87178dbd MM |
1432 | |
1433 | trace_input ("mulxu", OP_ACCUM_OUTPUT, OP_REG, OP_REG); | |
4f425a32 MH |
1434 | tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]); |
1435 | ||
1436 | if (State.FX) | |
1437 | tmp <<= 1; | |
1438 | ||
1439 | State.a[OP[0]] = tmp & MASK40; | |
87178dbd | 1440 | trace_output (OP_ACCUM); |
2934d1c9 MH |
1441 | } |
1442 | ||
1443 | /* mv */ | |
1444 | void | |
1445 | OP_4000 () | |
1446 | { | |
87178dbd | 1447 | trace_input ("mv", OP_REG_OUTPUT, OP_REG, OP_VOID); |
2934d1c9 | 1448 | State.regs[OP[0]] = State.regs[OP[1]]; |
87178dbd | 1449 | trace_output (OP_REG); |
2934d1c9 MH |
1450 | } |
1451 | ||
1452 | /* mv2w */ | |
1453 | void | |
1454 | OP_5000 () | |
1455 | { | |
87178dbd | 1456 | trace_input ("mv2w", OP_DREG_OUTPUT, OP_DREG, OP_VOID); |
2934d1c9 MH |
1457 | State.regs[OP[0]] = State.regs[OP[1]]; |
1458 | State.regs[OP[0]+1] = State.regs[OP[1]+1]; | |
87178dbd | 1459 | trace_output (OP_DREG); |
2934d1c9 MH |
1460 | } |
1461 | ||
1462 | /* mv2wfac */ | |
1463 | void | |
1464 | OP_3E00 () | |
1465 | { | |
87178dbd | 1466 | trace_input ("mv2wfac", OP_DREG_OUTPUT, OP_ACCUM, OP_VOID); |
2934d1c9 MH |
1467 | State.regs[OP[0]] = (State.a[OP[1]] >> 16) & 0xffff; |
1468 | State.regs[OP[0]+1] = State.a[OP[1]] & 0xffff; | |
87178dbd | 1469 | trace_output (OP_DREG); |
2934d1c9 MH |
1470 | } |
1471 | ||
1472 | /* mv2wtac */ | |
1473 | void | |
1474 | OP_3E01 () | |
1475 | { | |
87178dbd | 1476 | trace_input ("mv2wtac", OP_ACCUM_OUTPUT, OP_DREG, OP_VOID); |
4f425a32 | 1477 | State.a[OP[1]] = (SEXT16 (State.regs[OP[0]]) << 16 | State.regs[OP[0]+1]) & MASK40; |
87178dbd | 1478 | trace_output (OP_ACCUM); |
2934d1c9 MH |
1479 | } |
1480 | ||
1481 | /* mvac */ | |
1482 | void | |
1483 | OP_3E03 () | |
1484 | { | |
87178dbd | 1485 | trace_input ("mvac", OP_ACCUM_OUTPUT, OP_ACCUM, OP_VOID); |
2934d1c9 | 1486 | State.a[OP[0]] = State.a[OP[1]]; |
87178dbd | 1487 | trace_output (OP_ACCUM); |
2934d1c9 MH |
1488 | } |
1489 | ||
1490 | /* mvb */ | |
1491 | void | |
1492 | OP_5400 () | |
1493 | { | |
87178dbd | 1494 | trace_input ("mvb", OP_REG_OUTPUT, OP_REG, OP_VOID); |
2934d1c9 | 1495 | State.regs[OP[0]] = SEXT8 (State.regs[OP[1]] & 0xff); |
87178dbd | 1496 | trace_output (OP_REG); |
2934d1c9 MH |
1497 | } |
1498 | ||
1499 | /* mvf0f */ | |
1500 | void | |
1501 | OP_4400 () | |
1502 | { | |
87178dbd | 1503 | trace_input ("mf0f", OP_REG_OUTPUT, OP_REG, OP_VOID); |
2934d1c9 MH |
1504 | if (State.F0 == 0) |
1505 | State.regs[OP[0]] = State.regs[OP[1]]; | |
87178dbd | 1506 | trace_output (OP_REG); |
2934d1c9 MH |
1507 | } |
1508 | ||
1509 | /* mvf0t */ | |
1510 | void | |
1511 | OP_4401 () | |
1512 | { | |
87178dbd | 1513 | trace_input ("mf0t", OP_REG_OUTPUT, OP_REG, OP_VOID); |
2934d1c9 MH |
1514 | if (State.F0) |
1515 | State.regs[OP[0]] = State.regs[OP[1]]; | |
87178dbd | 1516 | trace_output (OP_REG); |
2934d1c9 MH |
1517 | } |
1518 | ||
1519 | /* mvfacg */ | |
1520 | void | |
1521 | OP_1E04 () | |
1522 | { | |
87178dbd | 1523 | trace_input ("mvfacg", OP_REG_OUTPUT, OP_ACCUM, OP_VOID); |
2934d1c9 | 1524 | State.regs[OP[0]] = (State.a[OP[1]] >> 32) & 0xff; |
87178dbd | 1525 | trace_output (OP_ACCUM); |
2934d1c9 MH |
1526 | } |
1527 | ||
1528 | /* mvfachi */ | |
1529 | void | |
1530 | OP_1E00 () | |
1531 | { | |
87178dbd | 1532 | trace_input ("mvfachi", OP_REG_OUTPUT, OP_ACCUM, OP_VOID); |
2934d1c9 | 1533 | State.regs[OP[0]] = (State.a[OP[1]] >> 16) & 0xffff; |
87178dbd | 1534 | trace_output (OP_REG); |
2934d1c9 MH |
1535 | } |
1536 | ||
1537 | /* mvfaclo */ | |
1538 | void | |
1539 | OP_1E02 () | |
1540 | { | |
87178dbd | 1541 | trace_input ("mvfaclo", OP_REG_OUTPUT, OP_ACCUM, OP_VOID); |
2934d1c9 | 1542 | State.regs[OP[0]] = State.a[OP[1]] & 0xffff; |
87178dbd | 1543 | trace_output (OP_REG); |
2934d1c9 MH |
1544 | } |
1545 | ||
1546 | /* mvfc */ | |
1547 | void | |
1548 | OP_5200 () | |
1549 | { | |
87178dbd | 1550 | trace_input ("mvfc", OP_REG_OUTPUT, OP_CR, OP_VOID); |
2934d1c9 MH |
1551 | if (OP[1] == 0) |
1552 | { | |
1553 | /* PSW is treated specially */ | |
1554 | PSW = 0; | |
1555 | if (State.SM) PSW |= 0x8000; | |
1556 | if (State.EA) PSW |= 0x2000; | |
1557 | if (State.DB) PSW |= 0x1000; | |
1558 | if (State.IE) PSW |= 0x400; | |
1559 | if (State.RP) PSW |= 0x200; | |
1560 | if (State.MD) PSW |= 0x100; | |
1561 | if (State.FX) PSW |= 0x80; | |
1562 | if (State.ST) PSW |= 0x40; | |
1563 | if (State.F0) PSW |= 8; | |
1564 | if (State.F1) PSW |= 4; | |
1565 | if (State.C) PSW |= 1; | |
1566 | } | |
1567 | State.regs[OP[0]] = State.cregs[OP[1]]; | |
87178dbd | 1568 | trace_output (OP_REG); |
2934d1c9 MH |
1569 | } |
1570 | ||
1571 | /* mvtacg */ | |
1572 | void | |
1573 | OP_1E41 () | |
1574 | { | |
87178dbd | 1575 | trace_input ("mvtacg", OP_REG, OP_ACCUM, OP_VOID); |
2934d1c9 MH |
1576 | State.a[OP[1]] &= MASK32; |
1577 | State.a[OP[1]] |= (int64)(State.regs[OP[0]] & 0xff) << 32; | |
87178dbd | 1578 | trace_output (OP_ACCUM_REVERSE); |
2934d1c9 MH |
1579 | } |
1580 | ||
1581 | /* mvtachi */ | |
1582 | void | |
1583 | OP_1E01 () | |
1584 | { | |
1585 | uint16 tmp; | |
87178dbd MM |
1586 | |
1587 | trace_input ("mvtachi", OP_REG, OP_ACCUM, OP_VOID); | |
2934d1c9 | 1588 | tmp = State.a[OP[1]] & 0xffff; |
4f425a32 | 1589 | State.a[OP[1]] = (SEXT16 (State.regs[OP[0]]) << 16 | tmp) & MASK40; |
87178dbd | 1590 | trace_output (OP_ACCUM_REVERSE); |
2934d1c9 MH |
1591 | } |
1592 | ||
1593 | /* mvtaclo */ | |
1594 | void | |
1595 | OP_1E21 () | |
1596 | { | |
87178dbd | 1597 | trace_input ("mvtaclo", OP_REG, OP_ACCUM, OP_VOID); |
4f425a32 | 1598 | State.a[OP[1]] = (SEXT16 (State.regs[OP[0]])) & MASK40; |
87178dbd | 1599 | trace_output (OP_ACCUM_REVERSE); |
2934d1c9 MH |
1600 | } |
1601 | ||
1602 | /* mvtc */ | |
1603 | void | |
1604 | OP_5600 () | |
1605 | { | |
87178dbd | 1606 | trace_input ("mvtc", OP_REG, OP_CR_OUTPUT, OP_VOID); |
2934d1c9 MH |
1607 | State.cregs[OP[1]] = State.regs[OP[0]]; |
1608 | if (OP[1] == 0) | |
1609 | { | |
1610 | /* PSW is treated specially */ | |
1611 | State.SM = (PSW & 0x8000) ? 1 : 0; | |
1612 | State.EA = (PSW & 0x2000) ? 1 : 0; | |
1613 | State.DB = (PSW & 0x1000) ? 1 : 0; | |
1614 | State.IE = (PSW & 0x400) ? 1 : 0; | |
1615 | State.RP = (PSW & 0x200) ? 1 : 0; | |
1616 | State.MD = (PSW & 0x100) ? 1 : 0; | |
1617 | State.FX = (PSW & 0x80) ? 1 : 0; | |
1618 | State.ST = (PSW & 0x40) ? 1 : 0; | |
1619 | State.F0 = (PSW & 8) ? 1 : 0; | |
1620 | State.F1 = (PSW & 4) ? 1 : 0; | |
1621 | State.C = PSW & 1; | |
1622 | if (State.ST && !State.FX) | |
1623 | { | |
7eebfc62 MM |
1624 | (*d10v_callback->printf_filtered) (d10v_callback, |
1625 | "ERROR at PC 0x%x: ST can only be set when FX is set.\n", | |
1626 | PC<<2); | |
4f425a32 | 1627 | State.exception = SIGILL; |
2934d1c9 MH |
1628 | } |
1629 | } | |
87178dbd | 1630 | trace_output (OP_CR_REVERSE); |
2934d1c9 MH |
1631 | } |
1632 | ||
1633 | /* mvub */ | |
1634 | void | |
1635 | OP_5401 () | |
1636 | { | |
87178dbd | 1637 | trace_input ("mvub", OP_REG_OUTPUT, OP_REG, OP_VOID); |
2934d1c9 | 1638 | State.regs[OP[0]] = State.regs[OP[1]] & 0xff; |
87178dbd | 1639 | trace_output (OP_REG); |
2934d1c9 MH |
1640 | } |
1641 | ||
1642 | /* neg */ | |
1643 | void | |
1644 | OP_4605 () | |
1645 | { | |
87178dbd | 1646 | trace_input ("neg", OP_REG, OP_VOID, OP_VOID); |
2934d1c9 | 1647 | State.regs[OP[0]] = 0 - State.regs[OP[0]]; |
87178dbd | 1648 | trace_output (OP_REG); |
2934d1c9 MH |
1649 | } |
1650 | ||
1651 | /* neg */ | |
1652 | void | |
1653 | OP_5605 () | |
1654 | { | |
1655 | int64 tmp; | |
87178dbd MM |
1656 | |
1657 | trace_input ("neg", OP_ACCUM, OP_VOID, OP_VOID); | |
4f425a32 | 1658 | tmp = -SEXT40(State.a[OP[0]]); |
2934d1c9 MH |
1659 | if (State.ST) |
1660 | { | |
4c38885c | 1661 | if ( tmp > MAX32) |
2934d1c9 | 1662 | State.a[OP[0]] = MAX32; |
4c38885c | 1663 | else if (tmp < MIN32) |
2934d1c9 MH |
1664 | State.a[OP[0]] = MIN32; |
1665 | else | |
4f425a32 | 1666 | State.a[OP[0]] = tmp & MASK40; |
2934d1c9 MH |
1667 | } |
1668 | else | |
4f425a32 | 1669 | State.a[OP[0]] = tmp & MASK40; |
87178dbd | 1670 | trace_output (OP_ACCUM); |
2934d1c9 MH |
1671 | } |
1672 | ||
1673 | ||
1674 | /* nop */ | |
1675 | void | |
1676 | OP_5E00 () | |
1677 | { | |
87178dbd MM |
1678 | trace_input ("nop", OP_VOID, OP_VOID, OP_VOID); |
1679 | trace_output (OP_VOID); | |
7eebfc62 MM |
1680 | |
1681 | if (State.ins_type == INS_LEFT || State.ins_type == INS_LEFT_PARALLEL) | |
1682 | left_nops++; | |
1683 | else | |
1684 | right_nops++; | |
2934d1c9 MH |
1685 | } |
1686 | ||
1687 | /* not */ | |
1688 | void | |
1689 | OP_4603 () | |
1690 | { | |
87178dbd | 1691 | trace_input ("not", OP_REG, OP_VOID, OP_VOID); |
2934d1c9 | 1692 | State.regs[OP[0]] = ~(State.regs[OP[0]]); |
87178dbd | 1693 | trace_output (OP_REG); |
2934d1c9 MH |
1694 | } |
1695 | ||
1696 | /* or */ | |
1697 | void | |
1698 | OP_800 () | |
1699 | { | |
87178dbd | 1700 | trace_input ("or", OP_REG, OP_REG, OP_VOID); |
2934d1c9 | 1701 | State.regs[OP[0]] |= State.regs[OP[1]]; |
87178dbd | 1702 | trace_output (OP_REG); |
2934d1c9 MH |
1703 | } |
1704 | ||
1705 | /* or3 */ | |
1706 | void | |
1707 | OP_4000000 () | |
1708 | { | |
87178dbd | 1709 | trace_input ("or3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16); |
2934d1c9 | 1710 | State.regs[OP[0]] = State.regs[OP[1]] | OP[2]; |
87178dbd | 1711 | trace_output (OP_REG); |
2934d1c9 MH |
1712 | } |
1713 | ||
1714 | /* rac */ | |
1715 | void | |
1716 | OP_5201 () | |
1717 | { | |
1718 | int64 tmp; | |
1719 | int shift = SEXT3 (OP[2]); | |
87178dbd MM |
1720 | |
1721 | trace_input ("rac", OP_DREG_OUTPUT, OP_ACCUM, OP_CONSTANT3); | |
166acb9f MH |
1722 | if (OP[1] != 0) |
1723 | { | |
7eebfc62 MM |
1724 | (*d10v_callback->printf_filtered) (d10v_callback, |
1725 | "ERROR at PC 0x%x: instruction only valid for A0\n", | |
1726 | PC<<2); | |
166acb9f MH |
1727 | State.exception = SIGILL; |
1728 | } | |
1729 | ||
2934d1c9 MH |
1730 | State.F1 = State.F0; |
1731 | if (shift >=0) | |
1732 | tmp = ((State.a[0] << 16) | (State.a[1] & 0xffff)) << shift; | |
1733 | else | |
1734 | tmp = ((State.a[0] << 16) | (State.a[1] & 0xffff)) >> -shift; | |
166acb9f | 1735 | tmp = ( SEXT60(tmp) + 0x8000 ) >> 16; |
4c38885c | 1736 | if (tmp > MAX32) |
2934d1c9 MH |
1737 | { |
1738 | State.regs[OP[0]] = 0x7fff; | |
1739 | State.regs[OP[0]+1] = 0xffff; | |
1740 | State.F0 = 1; | |
1741 | } | |
4c38885c | 1742 | else if (tmp < MIN32) |
2934d1c9 MH |
1743 | { |
1744 | State.regs[OP[0]] = 0x8000; | |
1745 | State.regs[OP[0]+1] = 0; | |
1746 | State.F0 = 1; | |
1747 | } | |
1748 | else | |
1749 | { | |
1750 | State.regs[OP[0]] = (tmp >> 16) & 0xffff; | |
1751 | State.regs[OP[0]+1] = tmp & 0xffff; | |
1752 | State.F0 = 0; | |
1753 | } | |
87178dbd | 1754 | trace_output (OP_DREG); |
2934d1c9 MH |
1755 | } |
1756 | ||
1757 | /* rachi */ | |
1758 | void | |
1759 | OP_4201 () | |
1760 | { | |
4c38885c MH |
1761 | int64 tmp; |
1762 | int shift = SEXT3 (OP[2]); | |
87178dbd MM |
1763 | |
1764 | trace_input ("rachi", OP_REG_OUTPUT, OP_ACCUM, OP_CONSTANT3); | |
4c38885c MH |
1765 | State.F1 = State.F0; |
1766 | if (shift >=0) | |
166acb9f | 1767 | tmp = SEXT44 (State.a[1]) << shift; |
4c38885c | 1768 | else |
166acb9f | 1769 | tmp = SEXT44 (State.a[1]) >> -shift; |
4c38885c | 1770 | tmp += 0x8000; |
63a91cfb | 1771 | |
4c38885c MH |
1772 | if (tmp > MAX32) |
1773 | { | |
1774 | State.regs[OP[0]] = 0x7fff; | |
1775 | State.F0 = 1; | |
1776 | } | |
1777 | else if (tmp < 0xfff80000000LL) | |
1778 | { | |
1779 | State.regs[OP[0]] = 0x8000; | |
1780 | State.F0 = 1; | |
1781 | } | |
1782 | else | |
1783 | { | |
1784 | State.regs[OP[0]] = (tmp >> 16) & 0xffff; | |
1785 | State.F0 = 0; | |
1786 | } | |
87178dbd | 1787 | trace_output (OP_REG); |
2934d1c9 MH |
1788 | } |
1789 | ||
1790 | /* rep */ | |
1791 | void | |
1792 | OP_27000000 () | |
1793 | { | |
87178dbd | 1794 | trace_input ("rep", OP_REG, OP_CONSTANT16, OP_VOID); |
2934d1c9 MH |
1795 | RPT_S = PC + 1; |
1796 | RPT_E = PC + OP[1]; | |
1797 | RPT_C = State.regs[OP[0]]; | |
1798 | State.RP = 1; | |
1799 | if (RPT_C == 0) | |
1800 | { | |
7eebfc62 | 1801 | (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep with count=0 is illegal.\n"); |
4f425a32 | 1802 | State.exception = SIGILL; |
2934d1c9 | 1803 | } |
4c38885c MH |
1804 | if (OP[1] < 4) |
1805 | { | |
7eebfc62 | 1806 | (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep must include at least 4 instructions.\n"); |
4f425a32 | 1807 | State.exception = SIGILL; |
4c38885c | 1808 | } |
87178dbd | 1809 | trace_output (OP_VOID); |
2934d1c9 MH |
1810 | } |
1811 | ||
1812 | /* repi */ | |
1813 | void | |
1814 | OP_2F000000 () | |
1815 | { | |
87178dbd | 1816 | trace_input ("repi", OP_CONSTANT16, OP_CONSTANT16, OP_VOID); |
2934d1c9 MH |
1817 | RPT_S = PC + 1; |
1818 | RPT_E = PC + OP[1]; | |
1819 | RPT_C = OP[0]; | |
1820 | State.RP = 1; | |
1821 | if (RPT_C == 0) | |
1822 | { | |
7eebfc62 | 1823 | (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi with count=0 is illegal.\n"); |
4f425a32 | 1824 | State.exception = SIGILL; |
4c38885c MH |
1825 | } |
1826 | if (OP[1] < 4) | |
1827 | { | |
7eebfc62 | 1828 | (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi must include at least 4 instructions.\n"); |
4f425a32 | 1829 | State.exception = SIGILL; |
2934d1c9 | 1830 | } |
87178dbd | 1831 | trace_output (OP_VOID); |
2934d1c9 MH |
1832 | } |
1833 | ||
1834 | /* rtd */ | |
1835 | void | |
1836 | OP_5F60 () | |
1837 | { | |
7eebfc62 | 1838 | d10v_callback->printf_filtered(d10v_callback, "ERROR: rtd - NOT IMPLEMENTED\n"); |
87178dbd | 1839 | State.exception = SIGILL; |
2934d1c9 MH |
1840 | } |
1841 | ||
1842 | /* rte */ | |
1843 | void | |
1844 | OP_5F40 () | |
1845 | { | |
87178dbd | 1846 | trace_input ("rte", OP_VOID, OP_VOID, OP_VOID); |
4c38885c MH |
1847 | PC = BPC; |
1848 | PSW = BPSW; | |
87178dbd | 1849 | trace_output (OP_VOID); |
2934d1c9 MH |
1850 | } |
1851 | ||
1852 | /* sadd */ | |
1853 | void | |
1854 | OP_1223 () | |
1855 | { | |
4c38885c | 1856 | int64 tmp; |
87178dbd MM |
1857 | |
1858 | trace_input ("sadd", OP_ACCUM, OP_ACCUM, OP_VOID); | |
4f425a32 | 1859 | tmp = SEXT40(State.a[OP[0]]) + (SEXT40(State.a[OP[1]]) >> 16); |
4c38885c MH |
1860 | if (State.ST) |
1861 | { | |
1862 | if (tmp > MAX32) | |
1863 | State.a[OP[0]] = MAX32; | |
1864 | else if (tmp < MIN32) | |
1865 | State.a[OP[0]] = MIN32; | |
1866 | else | |
4f425a32 | 1867 | State.a[OP[0]] = tmp & MASK40; |
4c38885c MH |
1868 | } |
1869 | else | |
4f425a32 | 1870 | State.a[OP[0]] = tmp & MASK40; |
87178dbd | 1871 | trace_output (OP_ACCUM); |
2934d1c9 MH |
1872 | } |
1873 | ||
1874 | /* setf0f */ | |
1875 | void | |
1876 | OP_4611 () | |
1877 | { | |
87178dbd | 1878 | trace_input ("setf0f", OP_REG_OUTPUT, OP_VOID, OP_VOID); |
4c38885c | 1879 | State.regs[OP[0]] = (State.F0 == 0) ? 1 : 0; |
87178dbd | 1880 | trace_output (OP_REG); |
2934d1c9 MH |
1881 | } |
1882 | ||
1883 | /* setf0t */ | |
1884 | void | |
1885 | OP_4613 () | |
1886 | { | |
87178dbd | 1887 | trace_input ("setf0t", OP_REG_OUTPUT, OP_VOID, OP_VOID); |
4c38885c | 1888 | State.regs[OP[0]] = (State.F0 == 1) ? 1 : 0; |
87178dbd | 1889 | trace_output (OP_REG); |
2934d1c9 MH |
1890 | } |
1891 | ||
1892 | /* sleep */ | |
1893 | void | |
1894 | OP_5FC0 () | |
1895 | { | |
87178dbd | 1896 | trace_input ("sleep", OP_VOID, OP_VOID, OP_VOID); |
4c38885c | 1897 | State.IE = 1; |
87178dbd | 1898 | trace_output (OP_VOID); |
2934d1c9 MH |
1899 | } |
1900 | ||
1901 | /* sll */ | |
1902 | void | |
1903 | OP_2200 () | |
1904 | { | |
87178dbd | 1905 | trace_input ("sll", OP_REG, OP_REG, OP_VOID); |
2934d1c9 | 1906 | State.regs[OP[0]] <<= (State.regs[OP[1]] & 0xf); |
87178dbd | 1907 | trace_output (OP_REG); |
2934d1c9 MH |
1908 | } |
1909 | ||
1910 | /* sll */ | |
1911 | void | |
1912 | OP_3200 () | |
1913 | { | |
4c38885c | 1914 | int64 tmp; |
87178dbd | 1915 | trace_input ("sll", OP_ACCUM, OP_REG, OP_VOID); |
4c38885c MH |
1916 | if (State.regs[OP[1]] & 31 <= 16) |
1917 | tmp = SEXT40 (State.a[OP[0]]) << (State.regs[OP[1]] & 31); | |
1918 | ||
1919 | if (State.ST) | |
1920 | { | |
1921 | if (tmp > MAX32) | |
1922 | State.a[OP[0]] = MAX32; | |
1923 | else if (tmp < 0xffffff80000000LL) | |
1924 | State.a[OP[0]] = MIN32; | |
1925 | else | |
1926 | State.a[OP[0]] = tmp & MASK40; | |
1927 | } | |
1928 | else | |
1929 | State.a[OP[0]] = tmp & MASK40; | |
87178dbd | 1930 | trace_output (OP_ACCUM); |
2934d1c9 MH |
1931 | } |
1932 | ||
1933 | /* slli */ | |
1934 | void | |
1935 | OP_2201 () | |
1936 | { | |
87178dbd | 1937 | trace_input ("slli", OP_REG, OP_CONSTANT16, OP_VOID); |
2934d1c9 | 1938 | State.regs[OP[0]] <<= OP[1]; |
87178dbd | 1939 | trace_output (OP_REG); |
2934d1c9 MH |
1940 | } |
1941 | ||
1942 | /* slli */ | |
1943 | void | |
1944 | OP_3201 () | |
1945 | { | |
4c38885c | 1946 | int64 tmp; |
4f425a32 MH |
1947 | |
1948 | if (OP[1] == 0) | |
1949 | OP[1] = 16; | |
4f425a32 | 1950 | |
87178dbd | 1951 | trace_input ("slli", OP_ACCUM, OP_CONSTANT16, OP_VOID); |
4f425a32 | 1952 | tmp = SEXT40(State.a[OP[0]]) << OP[1]; |
4c38885c MH |
1953 | |
1954 | if (State.ST) | |
1955 | { | |
1956 | if (tmp > MAX32) | |
1957 | State.a[OP[0]] = MAX32; | |
1958 | else if (tmp < 0xffffff80000000LL) | |
1959 | State.a[OP[0]] = MIN32; | |
1960 | else | |
1961 | State.a[OP[0]] = tmp & MASK40; | |
1962 | } | |
1963 | else | |
1964 | State.a[OP[0]] = tmp & MASK40; | |
87178dbd | 1965 | trace_output (OP_ACCUM); |
2934d1c9 MH |
1966 | } |
1967 | ||
1968 | /* slx */ | |
1969 | void | |
1970 | OP_460B () | |
1971 | { | |
1972 | uint16 tmp; | |
87178dbd MM |
1973 | |
1974 | trace_input ("slx", OP_REG, OP_FLAG, OP_VOID); | |
2934d1c9 | 1975 | State.regs[OP[0]] = (State.regs[OP[0]] << 1) | State.F0; |
87178dbd | 1976 | trace_output (OP_REG); |
2934d1c9 MH |
1977 | } |
1978 | ||
1979 | /* sra */ | |
1980 | void | |
1981 | OP_2400 () | |
1982 | { | |
87178dbd | 1983 | trace_input ("sra", OP_REG, OP_REG, OP_VOID); |
2934d1c9 | 1984 | State.regs[OP[0]] = ((int16)(State.regs[OP[0]])) >> (State.regs[OP[1]] & 0xf); |
87178dbd | 1985 | trace_output (OP_REG); |
2934d1c9 MH |
1986 | } |
1987 | ||
1988 | /* sra */ | |
1989 | void | |
1990 | OP_3400 () | |
1991 | { | |
87178dbd | 1992 | trace_input ("sra", OP_ACCUM, OP_REG, OP_VOID); |
4c38885c MH |
1993 | if (State.regs[OP[1]] & 31 <= 16) |
1994 | State.a[OP[0]] >>= (State.regs[OP[1]] & 31); | |
87178dbd | 1995 | trace_output (OP_ACCUM); |
2934d1c9 MH |
1996 | } |
1997 | ||
1998 | /* srai */ | |
1999 | void | |
2000 | OP_2401 () | |
2001 | { | |
87178dbd | 2002 | trace_input ("srai", OP_REG, OP_CONSTANT16, OP_VOID); |
2934d1c9 | 2003 | State.regs[OP[0]] = ((int16)(State.regs[OP[0]])) >> OP[1]; |
87178dbd | 2004 | trace_output (OP_REG); |
2934d1c9 MH |
2005 | } |
2006 | ||
2007 | /* srai */ | |
2008 | void | |
2009 | OP_3401 () | |
2010 | { | |
4f425a32 MH |
2011 | if (OP[1] == 0) |
2012 | OP[1] = 16; | |
87178dbd MM |
2013 | |
2014 | trace_input ("srai", OP_ACCUM, OP_CONSTANT16, OP_VOID); | |
2015 | State.a[OP[0]] >>= OP[1]; | |
2016 | trace_output (OP_ACCUM); | |
2934d1c9 MH |
2017 | } |
2018 | ||
2019 | /* srl */ | |
2020 | void | |
2021 | OP_2000 () | |
2022 | { | |
87178dbd | 2023 | trace_input ("srl", OP_REG, OP_REG, OP_VOID); |
2934d1c9 | 2024 | State.regs[OP[0]] >>= (State.regs[OP[1]] & 0xf); |
87178dbd | 2025 | trace_output (OP_REG); |
2934d1c9 MH |
2026 | } |
2027 | ||
2028 | /* srl */ | |
2029 | void | |
2030 | OP_3000 () | |
2031 | { | |
87178dbd | 2032 | trace_input ("srl", OP_ACCUM, OP_REG, OP_VOID); |
4c38885c MH |
2033 | if (State.regs[OP[1]] & 31 <= 16) |
2034 | State.a[OP[0]] >>= (State.regs[OP[1]] & 31); | |
87178dbd | 2035 | trace_output (OP_ACCUM); |
2934d1c9 MH |
2036 | } |
2037 | ||
2038 | /* srli */ | |
2039 | void | |
2040 | OP_2001 () | |
2041 | { | |
87178dbd | 2042 | trace_input ("srli", OP_REG, OP_CONSTANT16, OP_VOID); |
2934d1c9 | 2043 | State.regs[OP[0]] >>= OP[1]; |
87178dbd | 2044 | trace_output (OP_REG); |
2934d1c9 MH |
2045 | } |
2046 | ||
2047 | /* srli */ | |
2048 | void | |
2049 | OP_3001 () | |
2050 | { | |
4f425a32 MH |
2051 | if (OP[1] == 0) |
2052 | OP[1] = 16; | |
87178dbd MM |
2053 | |
2054 | trace_input ("srli", OP_ACCUM, OP_CONSTANT16, OP_VOID); | |
2055 | State.a[OP[0]] >>= OP[1]; | |
2056 | trace_output (OP_ACCUM); | |
2934d1c9 MH |
2057 | } |
2058 | ||
2059 | /* srx */ | |
2060 | void | |
2061 | OP_4609 () | |
2062 | { | |
2063 | uint16 tmp; | |
87178dbd MM |
2064 | |
2065 | trace_input ("srx", OP_REG, OP_FLAG, OP_VOID); | |
2934d1c9 MH |
2066 | tmp = State.F0 << 15; |
2067 | State.regs[OP[0]] = (State.regs[OP[0]] >> 1) | tmp; | |
87178dbd | 2068 | trace_output (OP_REG); |
2934d1c9 MH |
2069 | } |
2070 | ||
2071 | /* st */ | |
2072 | void | |
2073 | OP_34000000 () | |
2074 | { | |
87178dbd | 2075 | trace_input ("st", OP_REG, OP_MEMREF2, OP_VOID); |
2934d1c9 | 2076 | SW (OP[1] + State.regs[OP[2]], State.regs[OP[0]]); |
87178dbd | 2077 | trace_output (OP_VOID); |
2934d1c9 MH |
2078 | } |
2079 | ||
2080 | /* st */ | |
2081 | void | |
2082 | OP_6800 () | |
2083 | { | |
87178dbd | 2084 | trace_input ("st", OP_REG, OP_MEMREF, OP_VOID); |
2934d1c9 | 2085 | SW (State.regs[OP[1]], State.regs[OP[0]]); |
87178dbd | 2086 | trace_output (OP_VOID); |
2934d1c9 MH |
2087 | } |
2088 | ||
2089 | /* st */ | |
2090 | void | |
2091 | OP_6C1F () | |
2092 | { | |
87178dbd | 2093 | trace_input ("st", OP_REG, OP_PREDEC, OP_VOID); |
4c38885c MH |
2094 | if ( OP[1] != 15 ) |
2095 | { | |
7eebfc62 | 2096 | (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n"); |
4f425a32 MH |
2097 | State.exception = SIGILL; |
2098 | return; | |
4c38885c MH |
2099 | } |
2100 | State.regs[OP[1]] -= 2; | |
2101 | SW (State.regs[OP[1]], State.regs[OP[0]]); | |
87178dbd | 2102 | trace_output (OP_VOID); |
2934d1c9 MH |
2103 | } |
2104 | ||
2105 | /* st */ | |
2106 | void | |
2107 | OP_6801 () | |
2108 | { | |
87178dbd | 2109 | trace_input ("st", OP_REG, OP_POSTINC, OP_VOID); |
4c38885c | 2110 | SW (State.regs[OP[1]], State.regs[OP[0]]); |
4f425a32 | 2111 | INC_ADDR (State.regs[OP[1]],2); |
87178dbd | 2112 | trace_output (OP_VOID); |
2934d1c9 MH |
2113 | } |
2114 | ||
2115 | /* st */ | |
2116 | void | |
2117 | OP_6C01 () | |
2118 | { | |
87178dbd | 2119 | trace_input ("st", OP_REG, OP_POSTDEC, OP_VOID); |
4c38885c | 2120 | SW (State.regs[OP[1]], State.regs[OP[0]]); |
4f425a32 | 2121 | INC_ADDR (State.regs[OP[1]],-2); |
87178dbd | 2122 | trace_output (OP_VOID); |
2934d1c9 MH |
2123 | } |
2124 | ||
2125 | /* st2w */ | |
2126 | void | |
2127 | OP_35000000 () | |
2128 | { | |
87178dbd | 2129 | trace_input ("st2w", OP_DREG, OP_MEMREF2, OP_VOID); |
4f425a32 MH |
2130 | SW (State.regs[OP[2]]+OP[1], State.regs[OP[0]]); |
2131 | SW (State.regs[OP[2]]+OP[1]+2, State.regs[OP[0]+1]); | |
87178dbd | 2132 | trace_output (OP_VOID); |
2934d1c9 MH |
2133 | } |
2134 | ||
2135 | /* st2w */ | |
2136 | void | |
2137 | OP_6A00 () | |
2138 | { | |
87178dbd | 2139 | trace_input ("st2w", OP_REG, OP_MEMREF, OP_VOID); |
4c38885c MH |
2140 | SW (State.regs[OP[1]], State.regs[OP[0]]); |
2141 | SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]); | |
87178dbd | 2142 | trace_output (OP_VOID); |
2934d1c9 MH |
2143 | } |
2144 | ||
2145 | /* st2w */ | |
2146 | void | |
2147 | OP_6E1F () | |
2148 | { | |
87178dbd | 2149 | trace_input ("st2w", OP_REG, OP_PREDEC, OP_VOID); |
4c38885c MH |
2150 | if ( OP[1] != 15 ) |
2151 | { | |
7eebfc62 | 2152 | (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n"); |
4f425a32 MH |
2153 | State.exception = SIGILL; |
2154 | return; | |
4c38885c MH |
2155 | } |
2156 | State.regs[OP[1]] -= 4; | |
2157 | SW (State.regs[OP[1]], State.regs[OP[0]]); | |
2158 | SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]); | |
87178dbd | 2159 | trace_output (OP_VOID); |
2934d1c9 MH |
2160 | } |
2161 | ||
2162 | /* st2w */ | |
2163 | void | |
2164 | OP_6A01 () | |
2165 | { | |
87178dbd | 2166 | trace_input ("st2w", OP_REG, OP_POSTDEC, OP_VOID); |
4c38885c MH |
2167 | SW (State.regs[OP[1]], State.regs[OP[0]]); |
2168 | SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]); | |
4f425a32 | 2169 | INC_ADDR (State.regs[OP[1]],4); |
87178dbd | 2170 | trace_output (OP_VOID); |
2934d1c9 MH |
2171 | } |
2172 | ||
2173 | /* st2w */ | |
2174 | void | |
2175 | OP_6E01 () | |
2176 | { | |
87178dbd | 2177 | trace_input ("st2w", OP_REG, OP_POSTINC, OP_VOID); |
4c38885c MH |
2178 | SW (State.regs[OP[1]], State.regs[OP[0]]); |
2179 | SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]); | |
4f425a32 | 2180 | INC_ADDR (State.regs[OP[1]],-4); |
87178dbd | 2181 | trace_output (OP_VOID); |
2934d1c9 MH |
2182 | } |
2183 | ||
2184 | /* stb */ | |
2185 | void | |
2186 | OP_3C000000 () | |
2187 | { | |
87178dbd | 2188 | trace_input ("stb", OP_REG, OP_MEMREF2, OP_VOID); |
4f425a32 | 2189 | SB (State.regs[OP[2]]+OP[1], State.regs[OP[0]]); |
87178dbd | 2190 | trace_output (OP_VOID); |
2934d1c9 MH |
2191 | } |
2192 | ||
2193 | /* stb */ | |
2194 | void | |
2195 | OP_7800 () | |
2196 | { | |
87178dbd | 2197 | trace_input ("stb", OP_REG, OP_MEMREF, OP_VOID); |
4c38885c | 2198 | SB (State.regs[OP[1]], State.regs[OP[0]]); |
87178dbd | 2199 | trace_output (OP_VOID); |
2934d1c9 MH |
2200 | } |
2201 | ||
2202 | /* stop */ | |
2203 | void | |
2204 | OP_5FE0 () | |
2205 | { | |
87178dbd | 2206 | trace_input ("stop", OP_VOID, OP_VOID, OP_VOID); |
4f425a32 | 2207 | State.exception = SIGQUIT; |
87178dbd | 2208 | trace_output (OP_VOID); |
2934d1c9 MH |
2209 | } |
2210 | ||
2211 | /* sub */ | |
2212 | void | |
2213 | OP_0 () | |
4c38885c MH |
2214 | { |
2215 | int32 tmp; | |
87178dbd MM |
2216 | |
2217 | trace_input ("sub", OP_REG, OP_REG, OP_VOID); | |
4c38885c MH |
2218 | tmp = (int16)State.regs[OP[0]]- (int16)State.regs[OP[1]]; |
2219 | State.C = (tmp & 0xffff0000) ? 1 : 0; | |
2220 | State.regs[OP[0]] = tmp & 0xffff; | |
87178dbd | 2221 | trace_output (OP_REG); |
4c38885c MH |
2222 | } |
2223 | ||
2224 | /* sub */ | |
2225 | void | |
2226 | OP_1001 () | |
2227 | { | |
4f425a32 | 2228 | int64 tmp; |
87178dbd MM |
2229 | |
2230 | trace_input ("sub", OP_ACCUM, OP_DREG, OP_VOID); | |
4f425a32 MH |
2231 | tmp = SEXT40(State.a[OP[0]]) - (SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]); |
2232 | if (State.ST) | |
2233 | { | |
2234 | if ( tmp > MAX32) | |
2235 | State.a[OP[0]] = MAX32; | |
2236 | else if ( tmp < MIN32) | |
2237 | State.a[OP[0]] = MIN32; | |
2238 | else | |
2239 | State.a[OP[0]] = tmp & MASK40; | |
2240 | } | |
2241 | else | |
2242 | State.a[OP[0]] = tmp & MASK40; | |
87178dbd MM |
2243 | |
2244 | trace_output (OP_ACCUM); | |
4c38885c MH |
2245 | } |
2246 | ||
2247 | /* sub */ | |
2248 | ||
2249 | void | |
2250 | OP_1003 () | |
2934d1c9 | 2251 | { |
4f425a32 | 2252 | int64 tmp; |
87178dbd MM |
2253 | |
2254 | trace_input ("sub", OP_ACCUM, OP_ACCUM, OP_VOID); | |
4f425a32 MH |
2255 | tmp = SEXT40(State.a[OP[0]]) - SEXT40(State.a[OP[1]]); |
2256 | if (State.ST) | |
2257 | { | |
2258 | if (tmp > MAX32) | |
2259 | State.a[OP[0]] = MAX32; | |
2260 | else if ( tmp < MIN32) | |
2261 | State.a[OP[0]] = MIN32; | |
2262 | else | |
2263 | State.a[OP[0]] = tmp & MASK40; | |
2264 | } | |
2265 | else | |
2266 | State.a[OP[0]] = tmp & MASK40; | |
87178dbd MM |
2267 | |
2268 | trace_output (OP_ACCUM); | |
2934d1c9 MH |
2269 | } |
2270 | ||
2271 | /* sub2w */ | |
2272 | void | |
2273 | OP_1000 () | |
2274 | { | |
4c38885c MH |
2275 | int64 tmp; |
2276 | int32 a,b; | |
4c38885c | 2277 | |
87178dbd | 2278 | trace_input ("sub2w", OP_DREG, OP_DREG, OP_VOID); |
4c38885c MH |
2279 | a = (int32)((State.regs[OP[0]] << 16) | State.regs[OP[0]+1]); |
2280 | b = (int32)((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]); | |
2281 | tmp = a-b; | |
2282 | State.C = (tmp & 0xffffffff00000000LL) ? 1 : 0; | |
2283 | State.regs[OP[0]] = (tmp >> 16) & 0xffff; | |
2284 | State.regs[OP[0]+1] = tmp & 0xffff; | |
87178dbd | 2285 | trace_output (OP_DREG); |
2934d1c9 MH |
2286 | } |
2287 | ||
2288 | /* subac3 */ | |
2289 | void | |
2290 | OP_17000000 () | |
2291 | { | |
4f425a32 | 2292 | int64 tmp; |
87178dbd MM |
2293 | |
2294 | trace_input ("subac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM); | |
4f425a32 MH |
2295 | tmp = SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]) - SEXT40 (State.a[OP[2]]); |
2296 | State.regs[OP[0]] = (tmp >> 16) & 0xffff; | |
2297 | State.regs[OP[0]+1] = tmp & 0xffff; | |
87178dbd | 2298 | trace_output (OP_DREG); |
2934d1c9 MH |
2299 | } |
2300 | ||
2301 | /* subac3 */ | |
2302 | void | |
2303 | OP_17000002 () | |
2304 | { | |
4f425a32 | 2305 | int64 tmp; |
87178dbd MM |
2306 | |
2307 | trace_input ("subac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM); | |
4f425a32 MH |
2308 | tmp = SEXT40(State.a[OP[1]]) - SEXT40(State.a[OP[2]]); |
2309 | State.regs[OP[0]] = (tmp >> 16) & 0xffff; | |
2310 | State.regs[OP[0]+1] = tmp & 0xffff; | |
87178dbd | 2311 | trace_output (OP_DREG); |
2934d1c9 MH |
2312 | } |
2313 | ||
2314 | /* subac3s */ | |
2315 | void | |
2316 | OP_17001000 () | |
2317 | { | |
4f425a32 | 2318 | int64 tmp; |
87178dbd MM |
2319 | |
2320 | trace_input ("subac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM); | |
4f425a32 MH |
2321 | State.F1 = State.F0; |
2322 | tmp = SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]) - SEXT40(State.a[OP[2]]); | |
2323 | if ( tmp > MAX32) | |
2324 | { | |
2325 | State.regs[OP[0]] = 0x7fff; | |
2326 | State.regs[OP[0]+1] = 0xffff; | |
2327 | State.F0 = 1; | |
2328 | } | |
2329 | else if (tmp < MIN32) | |
2330 | { | |
2331 | State.regs[OP[0]] = 0x8000; | |
2332 | State.regs[OP[0]+1] = 0; | |
2333 | State.F0 = 1; | |
2334 | } | |
2335 | else | |
2336 | { | |
2337 | State.regs[OP[0]] = (tmp >> 16) & 0xffff; | |
2338 | State.regs[OP[0]+1] = tmp & 0xffff; | |
2339 | State.F0 = 0; | |
2340 | } | |
87178dbd | 2341 | trace_output (OP_DREG); |
2934d1c9 MH |
2342 | } |
2343 | ||
2344 | /* subac3s */ | |
2345 | void | |
2346 | OP_17001002 () | |
2347 | { | |
4f425a32 | 2348 | int64 tmp; |
87178dbd MM |
2349 | |
2350 | trace_input ("subac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM); | |
4f425a32 MH |
2351 | State.F1 = State.F0; |
2352 | tmp = SEXT40(State.a[OP[1]]) - SEXT40(State.a[OP[2]]); | |
2353 | if ( tmp > MAX32) | |
2354 | { | |
2355 | State.regs[OP[0]] = 0x7fff; | |
2356 | State.regs[OP[0]+1] = 0xffff; | |
2357 | State.F0 = 1; | |
2358 | } | |
2359 | else if (tmp < MIN32) | |
2360 | { | |
2361 | State.regs[OP[0]] = 0x8000; | |
2362 | State.regs[OP[0]+1] = 0; | |
2363 | State.F0 = 1; | |
2364 | } | |
2365 | else | |
2366 | { | |
2367 | State.regs[OP[0]] = (tmp >> 16) & 0xffff; | |
2368 | State.regs[OP[0]+1] = tmp & 0xffff; | |
2369 | State.F0 = 0; | |
2370 | } | |
87178dbd | 2371 | trace_output (OP_DREG); |
2934d1c9 MH |
2372 | } |
2373 | ||
2374 | /* subi */ | |
2375 | void | |
2376 | OP_1 () | |
2377 | { | |
4c38885c | 2378 | int32 tmp; |
4f425a32 MH |
2379 | if (OP[1] == 0) |
2380 | OP[1] = 16; | |
87178dbd MM |
2381 | |
2382 | trace_input ("subi", OP_REG, OP_CONSTANT16, OP_VOID); | |
4c38885c MH |
2383 | tmp = (int16)State.regs[OP[0]] - OP[1]; |
2384 | State.C = (tmp & 0xffff0000) ? 1 : 0; | |
2385 | State.regs[OP[0]] = tmp & 0xffff; | |
87178dbd | 2386 | trace_output (OP_REG); |
2934d1c9 MH |
2387 | } |
2388 | ||
2389 | /* trap */ | |
2390 | void | |
2391 | OP_5F00 () | |
2392 | { | |
87178dbd MM |
2393 | trace_input ("trap", OP_CONSTANT16, OP_REG, OP_VOID); |
2394 | trace_output (OP_VOID); | |
2934d1c9 | 2395 | |
63a91cfb | 2396 | switch (OP[0]) |
2934d1c9 | 2397 | { |
63a91cfb | 2398 | default: |
7eebfc62 | 2399 | (*d10v_callback->printf_filtered) (d10v_callback, "Unknown trap code %d\n", OP[0]); |
63a91cfb MM |
2400 | State.exception = SIGILL; |
2401 | ||
2402 | case 0: | |
2403 | /* Trap 0 is used for simulating low-level I/O */ | |
2404 | { | |
2405 | int save_errno = errno; | |
2406 | errno = 0; | |
2407 | ||
2408 | /* Registers passed to trap 0 */ | |
2409 | ||
2410 | #define FUNC State.regs[2] /* function number, return value */ | |
2411 | #define PARM1 State.regs[3] /* optional parm 1 */ | |
2412 | #define PARM2 State.regs[4] /* optional parm 2 */ | |
2413 | #define PARM3 State.regs[5] /* optional parm 3 */ | |
2414 | ||
2415 | /* Registers set by trap 0 */ | |
2416 | ||
2417 | #define RETVAL State.regs[2] /* return value */ | |
2418 | #define RETERR State.regs[3] /* return error code */ | |
2419 | ||
2420 | /* Turn a pointer in a register into a pointer into real memory. */ | |
2421 | ||
2422 | #define MEMPTR(x) ((char *)((x) + State.imem)) | |
2423 | ||
2424 | switch (FUNC) | |
2425 | { | |
2426 | #if !defined(__GO32__) && !defined(_WIN32) | |
2427 | #ifdef SYS_fork | |
2428 | case SYS_fork: | |
2429 | RETVAL = fork (); | |
2430 | break; | |
2431 | #endif | |
2432 | #ifdef SYS_execve | |
2433 | case SYS_execve: | |
2434 | RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), | |
2435 | (char **)MEMPTR (PARM3)); | |
2436 | break; | |
2437 | #endif | |
2438 | #ifdef SYS_execv | |
2439 | case SYS_execv: | |
2440 | RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL); | |
2441 | break; | |
2442 | #endif | |
2443 | #ifdef SYS_pipe | |
2444 | case SYS_pipe: | |
2445 | { | |
2446 | reg_t buf; | |
2447 | int host_fd[2]; | |
2448 | ||
2449 | buf = PARM1; | |
2450 | RETVAL = pipe (host_fd); | |
2451 | SW (buf, host_fd[0]); | |
2452 | buf += sizeof(uint16); | |
2453 | SW (buf, host_fd[1]); | |
2454 | } | |
2455 | break; | |
2456 | #endif | |
2457 | #ifdef SYS_wait | |
2458 | case SYS_wait: | |
2459 | { | |
2460 | int status; | |
2461 | ||
2462 | RETVAL = wait (&status); | |
2463 | SW (PARM1, status); | |
2464 | } | |
2465 | break; | |
2466 | #endif | |
2467 | #endif | |
2468 | ||
2469 | #ifdef SYS_read | |
2470 | case SYS_read: | |
2471 | RETVAL = d10v_callback->read (d10v_callback, PARM1, MEMPTR (PARM2), | |
2472 | PARM3); | |
2473 | break; | |
2474 | #endif | |
2475 | #ifdef SYS_write | |
2476 | case SYS_write: | |
2477 | if (PARM1 == 1) | |
2478 | RETVAL = (int)d10v_callback->write_stdout (d10v_callback, | |
2479 | MEMPTR (PARM2), PARM3); | |
2480 | else | |
2481 | RETVAL = (int)d10v_callback->write (d10v_callback, PARM1, | |
2482 | MEMPTR (PARM2), PARM3); | |
2483 | break; | |
2484 | #endif | |
2485 | #ifdef SYS_lseek | |
2486 | case SYS_lseek: | |
2487 | RETVAL = d10v_callback->lseek (d10v_callback, PARM1, PARM2, PARM3); | |
2488 | break; | |
2489 | #endif | |
2490 | #ifdef SYS_close | |
2491 | case SYS_close: | |
2492 | RETVAL = d10v_callback->close (d10v_callback, PARM1); | |
2493 | break; | |
2494 | #endif | |
2495 | #ifdef SYS_open | |
2496 | case SYS_open: | |
2497 | RETVAL = d10v_callback->open (d10v_callback, MEMPTR (PARM1), PARM2); | |
2498 | break; | |
2499 | #endif | |
2500 | #ifdef SYS_exit | |
2501 | case SYS_exit: | |
2502 | /* EXIT - caller can look in PARM1 to work out the | |
2503 | reason */ | |
2504 | State.exception = SIGQUIT; | |
2505 | break; | |
2506 | #endif | |
2507 | ||
8719be26 MA |
2508 | #ifdef SYS_stat |
2509 | case SYS_stat: | |
63a91cfb MM |
2510 | /* stat system call */ |
2511 | { | |
2512 | struct stat host_stat; | |
2513 | reg_t buf; | |
2514 | ||
2515 | RETVAL = stat (MEMPTR (PARM1), &host_stat); | |
2516 | ||
2517 | buf = PARM2; | |
2518 | ||
2519 | /* The hard-coded offsets and sizes were determined by using | |
2520 | * the D10V compiler on a test program that used struct stat. | |
2521 | */ | |
2522 | SW (buf, host_stat.st_dev); | |
2523 | SW (buf+2, host_stat.st_ino); | |
2524 | SW (buf+4, host_stat.st_mode); | |
2525 | SW (buf+6, host_stat.st_nlink); | |
2526 | SW (buf+8, host_stat.st_uid); | |
2527 | SW (buf+10, host_stat.st_gid); | |
2528 | SW (buf+12, host_stat.st_rdev); | |
2529 | SLW (buf+16, host_stat.st_size); | |
2530 | SLW (buf+20, host_stat.st_atime); | |
2531 | SLW (buf+28, host_stat.st_mtime); | |
2532 | SLW (buf+36, host_stat.st_ctime); | |
2533 | } | |
2534 | break; | |
2535 | #endif | |
2536 | ||
2537 | #ifdef SYS_chown | |
2538 | case SYS_chown: | |
2539 | RETVAL = chown (MEMPTR (PARM1), PARM2, PARM3); | |
2540 | break; | |
2541 | #endif | |
2542 | #ifdef SYS_chmod | |
2543 | case SYS_chmod: | |
2544 | RETVAL = chmod (MEMPTR (PARM1), PARM2); | |
2545 | break; | |
2546 | #endif | |
2547 | #ifdef SYS_utime | |
2548 | case SYS_utime: | |
2549 | /* Cast the second argument to void *, to avoid type mismatch | |
2550 | if a prototype is present. */ | |
2551 | RETVAL = utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2)); | |
2552 | break; | |
2553 | #endif | |
2554 | default: | |
2555 | abort (); | |
2556 | } | |
2557 | RETERR = errno; | |
2558 | errno = save_errno; | |
2559 | break; | |
2560 | } | |
2561 | ||
2562 | case 1: | |
2563 | /* Trap 1 prints a string */ | |
2564 | { | |
2565 | char *fstr = State.regs[2] + State.imem; | |
2566 | fputs (fstr, stdout); | |
2567 | break; | |
2568 | } | |
2569 | ||
2570 | case 2: | |
2571 | /* Trap 2 calls printf */ | |
2572 | { | |
2573 | char *fstr = State.regs[2] + State.imem; | |
7eebfc62 MM |
2574 | (*d10v_callback->printf_filtered) (d10v_callback, fstr, |
2575 | (int16)State.regs[3], | |
2576 | (int16)State.regs[4], | |
2577 | (int16)State.regs[5]); | |
63a91cfb MM |
2578 | break; |
2579 | } | |
2580 | ||
2581 | case 3: | |
2582 | /* Trap 3 writes a character */ | |
2583 | putchar (State.regs[2]); | |
2584 | break; | |
2934d1c9 MH |
2585 | } |
2586 | } | |
2587 | ||
2588 | /* tst0i */ | |
2589 | void | |
2590 | OP_7000000 () | |
2591 | { | |
87178dbd | 2592 | trace_input ("tst0i", OP_REG, OP_CONSTANT16, OP_VOID); |
4c38885c | 2593 | State.F1 = State.F0; |
4f425a32 | 2594 | State.F0 = (State.regs[OP[0]] & OP[1]) ? 1 : 0; |
87178dbd | 2595 | trace_output (OP_FLAG); |
2934d1c9 MH |
2596 | } |
2597 | ||
2598 | /* tst1i */ | |
2599 | void | |
2600 | OP_F000000 () | |
2601 | { | |
87178dbd | 2602 | trace_input ("tst1i", OP_REG, OP_CONSTANT16, OP_VOID); |
4c38885c | 2603 | State.F1 = State.F0; |
4f425a32 | 2604 | State.F0 = (~(State.regs[OP[0]]) & OP[1]) ? 1 : 0; |
87178dbd | 2605 | trace_output (OP_FLAG); |
2934d1c9 MH |
2606 | } |
2607 | ||
2608 | /* wait */ | |
2609 | void | |
2610 | OP_5F80 () | |
2611 | { | |
87178dbd | 2612 | trace_input ("wait", OP_VOID, OP_VOID, OP_VOID); |
4c38885c | 2613 | State.IE = 1; |
87178dbd | 2614 | trace_output (OP_VOID); |
2934d1c9 MH |
2615 | } |
2616 | ||
2617 | /* xor */ | |
2618 | void | |
2619 | OP_A00 () | |
2620 | { | |
87178dbd | 2621 | trace_input ("xor", OP_REG, OP_REG, OP_VOID); |
4c38885c | 2622 | State.regs[OP[0]] ^= State.regs[OP[1]]; |
87178dbd | 2623 | trace_output (OP_REG); |
2934d1c9 MH |
2624 | } |
2625 | ||
2626 | /* xor3 */ | |
2627 | void | |
2628 | OP_5000000 () | |
2629 | { | |
87178dbd | 2630 | trace_input ("xor3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16); |
4c38885c | 2631 | State.regs[OP[0]] = State.regs[OP[1]] ^ OP[2]; |
87178dbd | 2632 | trace_output (OP_REG); |
2934d1c9 MH |
2633 | } |
2634 |