[deliverable/binutils-gdb.git] / sim / d30v / cpu.h

/* Mitsubishi Electric Corp. D30V Simulator.
   Copyright (C) 1997, Free Software Foundation, Inc.
   Contributed by Cygnus Support.

This file is part of GDB, the GNU debugger.

This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.

This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */


#ifndef _CPU_H_
#define _CPU_H_

enum {
  NR_GENERAL_PURPOSE_REGISTERS = 64,
  NR_CONTROL_REGISTERS = 64,
  NR_ACCUMULATORS = 2,
  STACK_POINTER_GPR = 63,
  NR_STACK_POINTERS = 2,
};

enum {
  processor_status_word_cr = 0,
  backup_processor_status_word_cr = 1,
  program_counter_cr = 2,
  backup_program_counter_cr = 3,
  debug_backup_processor_status_word_cr = 4,
  debug_backup_program_counter_cr = 5,
  reserved_6_cr = 6,
  repeat_count_cr = 7,
  repeat_start_address_cr = 8,
  repeat_end_address_cr = 9,
  modulo_start_address_cr = 10,
  modulo_end_address_cr = 11,
  instruction_break_address_cr = 14,
  eit_vector_base_cr = 15,
};


enum {
  PSW_SM = 0,
  PSW_EA = 2,
  PSW_DB = 3,
  PSW_DS = 4,
  PSW_IE = 5,
  PSW_RP = 6,
  PSW_MD = 7,
  PSW_F0 = 17,
  PSW_F1 = 19,
  PSW_F2 = 21,
  PSW_F3 = 23,
  PSW_S = 25,
  PSW_V = 27,
  PSW_VA = 29,
  PSW_C = 31,
};

/* aliases for PSW flag numbers (F0..F7) */
enum
{
  PSW_S_FLAG = 4,
};

typedef struct _registers {
  unsigned32 general_purpose[NR_GENERAL_PURPOSE_REGISTERS];
  /* keep track of the stack pointer */
  unsigned32 sp[NR_STACK_POINTERS]; /* swap with SP */
  unsigned32 current_sp;
  unsigned32 control[NR_CONTROL_REGISTERS];
  unsigned64 accumulator[NR_ACCUMULATORS];
} registers;

typedef enum _cpu_units {
  memory_unit,
  integer_unit,
  any_unit,
} cpu_units;

/* In order to support parallel instructions, which one instruction can be
   writing to a register that is used as input to another, queue up the
   writes to the end of the instruction boundaries.  */

#define MAX_WRITE32	16
#define MAX_WRITE64	2

struct _write32 {
  int num;				/* # of 32-bit writes queued up */
  unsigned32 value[MAX_WRITE32];	/* value to write */
  unsigned32 mask[MAX_WRITE32];		/* mask to use */
  unsigned32 *ptr[MAX_WRITE32];		/* address to write to */
};

struct _write64 {
  int num;				/* # of 64-bit writes queued up */
  unsigned64 value[MAX_WRITE64];	/* value to write */
  unsigned64 *ptr[MAX_WRITE64];		/* address to write to */
};

struct _sim_cpu {
  cpu_units unit;
  registers regs;
  sim_cpu_base base;
  int trace_call_p;			/* Whether to do call tracing.  */
  int trace_trap_p;			/* If unknown traps dump out the regs */
  int trace_action;			/* trace bits at end of instructions */
  int left_kills_right_p;               /* left insn kills insn in right slot of -> */
  int mvtsys_left_p;			/* left insn was mvtsys */
  int did_trap;				/* we did a trap & need to finish it */
  struct _write32 write32;		/* queued up 32-bit writes */
  struct _write64 write64;		/* queued up 64-bit writes */
};

#define PC	(STATE_CPU (sd, 0)->regs.control[program_counter_cr])
#define PSW 	(STATE_CPU (sd, 0)->regs.control[processor_status_word_cr])
#define PSWL    (*AL2_4(&PSW))
#define PSWH    (*AH2_4(&PSW))
#define DPSW 	(STATE_CPU (sd, 0)->regs.control[debug_backup_processor_status_word_cr])
#define DPC 	(STATE_CPU (sd, 0)->regs.control[debug_backup_program_counter_cr])
#define bPC 	(STATE_CPU (sd, 0)->regs.control[backup_program_counter_cr])
#define bPSW 	(STATE_CPU (sd, 0)->regs.control[backup_processor_status_word_cr])
#define RPT_C 	(STATE_CPU (sd, 0)->regs.control[repeat_count_cr])
#define RPT_S 	(STATE_CPU (sd, 0)->regs.control[repeat_start_address_cr])
#define RPT_E 	(STATE_CPU (sd, 0)->regs.control[repeat_end_address_cr])
#define MOD_S 	(STATE_CPU (sd, 0)->regs.control[modulo_start_address_cr])
#define MOD_E 	(STATE_CPU (sd, 0)->regs.control[modulo_end_address_cr])
#define IBA 	(STATE_CPU (sd, 0)->regs.control[instruction_break_address_cr])
#define EIT_VB	(STATE_CPU (sd, 0)->regs.control[eit_vector_base_cr])
#define GPR	(STATE_CPU (sd, 0)->regs.general_purpose)
#define GPR_CLEAR(N) (GPR[(N)] = 0)
#define ACC	(STATE_CPU (sd, 0)->regs.accumulator)
#define CREG	(STATE_CPU (sd, 0)->regs.control)
#define SP      (GPR[STACK_POINTER_GPR])
#define TRACE_CALL_P (STATE_CPU (sd, 0)->trace_call_p)
#define TRACE_TRAP_P (STATE_CPU (sd, 0)->trace_trap_p)
#define TRACE_ACTION (STATE_CPU (sd, 0)->trace_action)
#define     TRACE_ACTION_CALL	0x00000001	/* call occurred */
#define     TRACE_ACTION_RETURN	0x00000002	/* return occurred */

#define WRITE32 (STATE_CPU (sd, 0)->write32)
#define WRITE32_NUM	 (WRITE32.num)
#define WRITE32_PTR(N)	 (WRITE32.ptr[N])
#define WRITE32_MASK(N)	 (WRITE32.mask[N])
#define WRITE32_VALUE(N) (WRITE32.value[N])
#define WRITE32_QUEUE(PTR, VALUE) WRITE32_QUEUE_MASK (PTR, VALUE, 0xffffffff)

#define WRITE32_QUEUE_MASK(PTR, VALUE, MASK)				\
do {									\
  int _num = WRITE32_NUM;						\
  if (_num >= MAX_WRITE32)						\
    sim_engine_abort (sd, STATE_CPU (sd, 0), cia,			\
		      "Too many queued 32-bit writes");			\
  WRITE32_PTR(_num) = PTR;						\
  WRITE32_VALUE(_num) = VALUE;						\
  WRITE32_MASK(_num) = MASK;						\
  WRITE32_NUM = _num+1;							\
} while (0)

#define DID_TRAP	(STATE_CPU (sd, 0)->did_trap)

#define WRITE64 (STATE_CPU (sd, 0)->write64)
#define WRITE64_NUM	 (WRITE64.num)
#define WRITE64_PTR(N)	 (WRITE64.ptr[N])
#define WRITE64_VALUE(N) (WRITE64.value[N])
#define WRITE64_QUEUE(PTR, VALUE)					\
do {									\
  int _num = WRITE64_NUM;						\
  if (_num >= MAX_WRITE64)						\
    sim_engine_abort (sd, STATE_CPU (sd, 0), cia,			\
		      "Too many queued 64-bit writes");			\
  WRITE64_PTR(_num) = PTR;						\
  WRITE64_VALUE(_num) = VALUE;						\
  WRITE64_NUM = _num+1;							\
} while (0)

#define DPSW_VALID	0xbf005555
#define PSW_VALID	0xb7005555
#define EIT_VALID	0xfffff000	/* From page 7-4 of D30V/MPEG arch. manual  */
#define EIT_VB_DEFAULT	0xfffff000	/* Value of the EIT_VB register after reset */

/* Verify that the instruction is in the correct slot */

#define IS_WRONG_SLOT is_wrong_slot(sd, cia, MY_INDEX)
extern int is_wrong_slot
(SIM_DESC sd,
 address_word cia,
 itable_index index);

#define IS_CONDITION_OK is_condition_ok(sd, cia, CCC)
extern int is_condition_ok
(SIM_DESC sd,
 address_word cia,
 int cond);

#define SIM_HAVE_BREAKPOINTS	/* Turn on internal breakpoint module */

/* Internal breakpoint instruction is syscall 5 */
#define SIM_BREAKPOINT {0x0e, 0x00, 0x00, 0x05}
#define SIM_BREAKPOINT_SIZE (4)

/* Call occurred */
extern void call_occurred
(SIM_DESC sd,
 sim_cpu *cpu,
 address_word cia,
 address_word nia);

/* Return occurred */
extern void return_occurred
(SIM_DESC sd,
 sim_cpu *cpu,
 address_word cia,
 address_word nia);

/* Whether to do call tracing.  */
extern int d30v_call_trace_p;

/* Read/write functions for system call interface.  */
extern int d30v_read_mem
(host_callback *cb,
 struct cb_syscall *sc,
 unsigned long taddr,
 char *buf,
 int bytes);

extern int d30v_write_mem
(host_callback *cb,
 struct cb_syscall *sc,
 unsigned long taddr,
 const char *buf,
 int bytes);

/* Process all of the queued up writes in order now */
void unqueue_writes
(SIM_DESC sd,
 sim_cpu *cpu,
 address_word cia);

#endif /* _CPU_H_ */
Commit	Line	Data
c906108c SS	1	/* Mitsubishi Electric Corp. D30V Simulator.
	2	Copyright (C) 1997, Free Software Foundation, Inc.
	3	Contributed by Cygnus Support.
	4
	5	This file is part of GDB, the GNU debugger.
	6
	7	This program is free software; you can redistribute it and/or modify
	8	it under the terms of the GNU General Public License as published by
	9	the Free Software Foundation; either version 2, or (at your option)
	10	any later version.
	11
	12	This program is distributed in the hope that it will be useful,
	13	but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	GNU General Public License for more details.
	16
	17	You should have received a copy of the GNU General Public License along
	18	with this program; if not, write to the Free Software Foundation, Inc.,
	19	59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
	20
	21
	22	#ifndef _CPU_H_
	23	#define _CPU_H_
	24
	25	enum {
	26	NR_GENERAL_PURPOSE_REGISTERS = 64,
	27	NR_CONTROL_REGISTERS = 64,
	28	NR_ACCUMULATORS = 2,
	29	STACK_POINTER_GPR = 63,
	30	NR_STACK_POINTERS = 2,
	31	};
	32
	33	enum {
	34	processor_status_word_cr = 0,
	35	backup_processor_status_word_cr = 1,
	36	program_counter_cr = 2,
	37	backup_program_counter_cr = 3,
	38	debug_backup_processor_status_word_cr = 4,
	39	debug_backup_program_counter_cr = 5,
	40	reserved_6_cr = 6,
	41	repeat_count_cr = 7,
	42	repeat_start_address_cr = 8,
	43	repeat_end_address_cr = 9,
	44	modulo_start_address_cr = 10,
	45	modulo_end_address_cr = 11,
	46	instruction_break_address_cr = 14,
	47	eit_vector_base_cr = 15,
	48	};
	49
	50
	51	enum {
	52	PSW_SM = 0,
	53	PSW_EA = 2,
	54	PSW_DB = 3,
	55	PSW_DS = 4,
	56	PSW_IE = 5,
	57	PSW_RP = 6,
	58	PSW_MD = 7,
	59	PSW_F0 = 17,
	60	PSW_F1 = 19,
	61	PSW_F2 = 21,
	62	PSW_F3 = 23,
	63	PSW_S = 25,
	64	PSW_V = 27,
65	PSW_VA = 29,
66	PSW_C = 31,
67	};
68
69	/* aliases for PSW flag numbers (F0..F7) */
70	enum
71	{
72	PSW_S_FLAG = 4,
73	};
74
75	typedef struct _registers {
76	unsigned32 general_purpose[NR_GENERAL_PURPOSE_REGISTERS];
77	/* keep track of the stack pointer */
78	unsigned32 sp[NR_STACK_POINTERS]; /* swap with SP */
79	unsigned32 current_sp;
80	unsigned32 control[NR_CONTROL_REGISTERS];
81	unsigned64 accumulator[NR_ACCUMULATORS];
82	} registers;
83
84	typedef enum _cpu_units {
85	memory_unit,
86	integer_unit,
87	any_unit,
88	} cpu_units;
89
90	/* In order to support parallel instructions, which one instruction can be
91	writing to a register that is used as input to another, queue up the
92	writes to the end of the instruction boundaries. */
93
94	#define MAX_WRITE32 16
95	#define MAX_WRITE64 2
96
97	struct _write32 {
98	int num; /* # of 32-bit writes queued up */
99	unsigned32 value[MAX_WRITE32]; /* value to write */
100	unsigned32 mask[MAX_WRITE32]; /* mask to use */
101	unsigned32 ptr[MAX_WRITE32]; / address to write to */
102	};
103
104	struct _write64 {
105	int num; /* # of 64-bit writes queued up */
106	unsigned64 value[MAX_WRITE64]; /* value to write */
107	unsigned64 ptr[MAX_WRITE64]; / address to write to */
108	};
109
110	struct _sim_cpu {
111	cpu_units unit;
112	registers regs;
113	sim_cpu_base base;
114	int trace_call_p; /* Whether to do call tracing. */
115	int trace_trap_p; /* If unknown traps dump out the regs */
116	int trace_action; /* trace bits at end of instructions */
117	int left_kills_right_p; /* left insn kills insn in right slot of -> */
7a292a7a	118	int mvtsys_left_p; /* left insn was mvtsys */
c906108c SS	119	int did_trap; /* we did a trap & need to finish it */
	120	struct _write32 write32; /* queued up 32-bit writes */
	121	struct _write64 write64; /* queued up 64-bit writes */
	122	};
	123
	124	#define PC (STATE_CPU (sd, 0)->regs.control[program_counter_cr])
	125	#define PSW (STATE_CPU (sd, 0)->regs.control[processor_status_word_cr])
	126	#define PSWL (*AL2_4(&PSW))
	127	#define PSWH (*AH2_4(&PSW))
	128	#define DPSW (STATE_CPU (sd, 0)->regs.control[debug_backup_processor_status_word_cr])
	129	#define DPC (STATE_CPU (sd, 0)->regs.control[debug_backup_program_counter_cr])
	130	#define bPC (STATE_CPU (sd, 0)->regs.control[backup_program_counter_cr])
	131	#define bPSW (STATE_CPU (sd, 0)->regs.control[backup_processor_status_word_cr])
	132	#define RPT_C (STATE_CPU (sd, 0)->regs.control[repeat_count_cr])
	133	#define RPT_S (STATE_CPU (sd, 0)->regs.control[repeat_start_address_cr])
	134	#define RPT_E (STATE_CPU (sd, 0)->regs.control[repeat_end_address_cr])
	135	#define MOD_S (STATE_CPU (sd, 0)->regs.control[modulo_start_address_cr])
	136	#define MOD_E (STATE_CPU (sd, 0)->regs.control[modulo_end_address_cr])
	137	#define IBA (STATE_CPU (sd, 0)->regs.control[instruction_break_address_cr])
	138	#define EIT_VB (STATE_CPU (sd, 0)->regs.control[eit_vector_base_cr])
	139	#define GPR (STATE_CPU (sd, 0)->regs.general_purpose)
f23b768a	140	#define GPR_CLEAR(N) (GPR[(N)] = 0)
c906108c SS	141	#define ACC (STATE_CPU (sd, 0)->regs.accumulator)
	142	#define CREG (STATE_CPU (sd, 0)->regs.control)
	143	#define SP (GPR[STACK_POINTER_GPR])
	144	#define TRACE_CALL_P (STATE_CPU (sd, 0)->trace_call_p)
	145	#define TRACE_TRAP_P (STATE_CPU (sd, 0)->trace_trap_p)
	146	#define TRACE_ACTION (STATE_CPU (sd, 0)->trace_action)
	147	#define TRACE_ACTION_CALL 0x00000001 /* call occurred */
	148	#define TRACE_ACTION_RETURN 0x00000002 /* return occurred */
	149
	150	#define WRITE32 (STATE_CPU (sd, 0)->write32)
	151	#define WRITE32_NUM (WRITE32.num)
	152	#define WRITE32_PTR(N) (WRITE32.ptr[N])
	153	#define WRITE32_MASK(N) (WRITE32.mask[N])
	154	#define WRITE32_VALUE(N) (WRITE32.value[N])
	155	#define WRITE32_QUEUE(PTR, VALUE) WRITE32_QUEUE_MASK (PTR, VALUE, 0xffffffff)
	156
	157	#define WRITE32_QUEUE_MASK(PTR, VALUE, MASK) \
	158	do { \
	159	int _num = WRITE32_NUM; \
	160	if (_num >= MAX_WRITE32) \
	161	sim_engine_abort (sd, STATE_CPU (sd, 0), cia, \
	162	"Too many queued 32-bit writes"); \
	163	WRITE32_PTR(_num) = PTR; \
	164	WRITE32_VALUE(_num) = VALUE; \
	165	WRITE32_MASK(_num) = MASK; \
	166	WRITE32_NUM = _num+1; \
	167	} while (0)
	168
	169	#define DID_TRAP (STATE_CPU (sd, 0)->did_trap)
	170
	171	#define WRITE64 (STATE_CPU (sd, 0)->write64)
	172	#define WRITE64_NUM (WRITE64.num)
	173	#define WRITE64_PTR(N) (WRITE64.ptr[N])
	174	#define WRITE64_VALUE(N) (WRITE64.value[N])
	175	#define WRITE64_QUEUE(PTR, VALUE) \
	176	do { \
	177	int _num = WRITE64_NUM; \
	178	if (_num >= MAX_WRITE64) \
	179	sim_engine_abort (sd, STATE_CPU (sd, 0), cia, \
	180	"Too many queued 64-bit writes"); \
	181	WRITE64_PTR(_num) = PTR; \
	182	WRITE64_VALUE(_num) = VALUE; \
	183	WRITE64_NUM = _num+1; \
	184	} while (0)
	185
	186	#define DPSW_VALID 0xbf005555
	187	#define PSW_VALID 0xb7005555
	188	#define EIT_VALID 0xfffff000 /* From page 7-4 of D30V/MPEG arch. manual */
	189	#define EIT_VB_DEFAULT 0xfffff000 /* Value of the EIT_VB register after reset */
	190
	191	/* Verify that the instruction is in the correct slot */
	192
	193	#define IS_WRONG_SLOT is_wrong_slot(sd, cia, MY_INDEX)
	194	extern int is_wrong_slot
	195	(SIM_DESC sd,
	196	address_word cia,
	197	itable_index index);
	198
	199	#define IS_CONDITION_OK is_condition_ok(sd, cia, CCC)
	200	extern int is_condition_ok
	201	(SIM_DESC sd,
	202	address_word cia,
	203	int cond);
	204
205	#define SIM_HAVE_BREAKPOINTS /* Turn on internal breakpoint module */
206
207	/* Internal breakpoint instruction is syscall 5 */
208	#define SIM_BREAKPOINT {0x0e, 0x00, 0x00, 0x05}
209	#define SIM_BREAKPOINT_SIZE (4)
210
211	/* Call occurred */
212	extern void call_occurred
213	(SIM_DESC sd,
214	sim_cpu *cpu,
215	address_word cia,
216	address_word nia);
217
218	/* Return occurred */
219	extern void return_occurred
220	(SIM_DESC sd,
221	sim_cpu *cpu,
222	address_word cia,
223	address_word nia);
224
225	/* Whether to do call tracing. */
226	extern int d30v_call_trace_p;
227
228	/* Read/write functions for system call interface. */
229	extern int d30v_read_mem
230	(host_callback *cb,
231	struct cb_syscall *sc,
232	unsigned long taddr,
233	char *buf,
234	int bytes);
235
236	extern int d30v_write_mem
237	(host_callback *cb,
238	struct cb_syscall *sc,
239	unsigned long taddr,
240	const char *buf,
241	int bytes);
242
d4f3574e SS	243	/* Process all of the queued up writes in order now */
	244	void unqueue_writes
	245	(SIM_DESC sd,
	246	sim_cpu *cpu,
	247	address_word cia);
	248
c906108c	249	#endif /* _CPU_H_ */