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3fbeef0b AC |
1 | /* OBSOLETE /* This file is part of the program psim. */ |
2 | /* OBSOLETE */ | |
3 | /* OBSOLETE Copyright (C) 1994-1997, Andrew Cagney <cagney@highland.com.au> */ | |
4 | /* OBSOLETE Copyright (C) 1996, 1997, Free Software Foundation */ | |
5 | /* OBSOLETE */ | |
6 | /* OBSOLETE This program is free software; you can redistribute it and/or modify */ | |
7 | /* OBSOLETE it under the terms of the GNU General Public License as published by */ | |
8 | /* OBSOLETE the Free Software Foundation; either version 2 of the License, or */ | |
9 | /* OBSOLETE (at your option) any later version. */ | |
10 | /* OBSOLETE */ | |
11 | /* OBSOLETE This program is distributed in the hope that it will be useful, */ | |
12 | /* OBSOLETE but WITHOUT ANY WARRANTY; without even the implied warranty of */ | |
13 | /* OBSOLETE MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the */ | |
14 | /* OBSOLETE GNU General Public License for more details. */ | |
15 | /* OBSOLETE */ | |
16 | /* OBSOLETE You should have received a copy of the GNU General Public License */ | |
17 | /* OBSOLETE along with this program; if not, write to the Free Software */ | |
18 | /* OBSOLETE Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ | |
19 | /* OBSOLETE */ | |
20 | /* OBSOLETE */ */ | |
21 | /* OBSOLETE */ | |
22 | /* OBSOLETE */ | |
23 | /* OBSOLETE #ifndef ENGINE_C */ | |
24 | /* OBSOLETE #define ENGINE_C */ | |
25 | /* OBSOLETE */ | |
26 | /* OBSOLETE #include "sim-main.h" */ | |
27 | /* OBSOLETE */ | |
28 | /* OBSOLETE #include <stdio.h> */ | |
29 | /* OBSOLETE #include <ctype.h> */ | |
30 | /* OBSOLETE */ | |
31 | /* OBSOLETE #ifdef HAVE_STDLIB_H */ | |
32 | /* OBSOLETE #include <stdlib.h> */ | |
33 | /* OBSOLETE #endif */ | |
34 | /* OBSOLETE */ | |
35 | /* OBSOLETE #ifdef HAVE_STRING_H */ | |
36 | /* OBSOLETE #include <string.h> */ | |
37 | /* OBSOLETE #else */ | |
38 | /* OBSOLETE #ifdef HAVE_STRINGS_H */ | |
39 | /* OBSOLETE #include <strings.h> */ | |
40 | /* OBSOLETE #endif */ | |
41 | /* OBSOLETE #endif */ | |
42 | /* OBSOLETE */ | |
43 | /* OBSOLETE static void */ | |
44 | /* OBSOLETE do_stack_swap (SIM_DESC sd) */ | |
45 | /* OBSOLETE { */ | |
46 | /* OBSOLETE sim_cpu *cpu = STATE_CPU (sd, 0); */ | |
47 | /* OBSOLETE unsigned new_sp = (PSW_VAL(PSW_SM) != 0); */ | |
48 | /* OBSOLETE if (cpu->regs.current_sp != new_sp) */ | |
49 | /* OBSOLETE { */ | |
50 | /* OBSOLETE cpu->regs.sp[cpu->regs.current_sp] = SP; */ | |
51 | /* OBSOLETE cpu->regs.current_sp = new_sp; */ | |
52 | /* OBSOLETE SP = cpu->regs.sp[cpu->regs.current_sp]; */ | |
53 | /* OBSOLETE } */ | |
54 | /* OBSOLETE } */ | |
55 | /* OBSOLETE */ | |
56 | /* OBSOLETE #if WITH_TRACE */ | |
57 | /* OBSOLETE /* Implement ALU tracing of 32-bit registers. */ */ | |
58 | /* OBSOLETE static void */ | |
59 | /* OBSOLETE trace_alu32 (SIM_DESC sd, */ | |
60 | /* OBSOLETE sim_cpu *cpu, */ | |
61 | /* OBSOLETE address_word cia, */ | |
62 | /* OBSOLETE unsigned32 *ptr) */ | |
63 | /* OBSOLETE { */ | |
64 | /* OBSOLETE unsigned32 value = *ptr; */ | |
65 | /* OBSOLETE */ | |
66 | /* OBSOLETE if (ptr >= &GPR[0] && ptr <= &GPR[NR_GENERAL_PURPOSE_REGISTERS]) */ | |
67 | /* OBSOLETE trace_one_insn (sd, cpu, cia, 1, "engine.c", __LINE__, "alu", */ | |
68 | /* OBSOLETE "Set register r%-2d = 0x%.8lx (%ld)", */ | |
69 | /* OBSOLETE ptr - &GPR[0], (long)value, (long)value); */ | |
70 | /* OBSOLETE */ | |
71 | /* OBSOLETE else if (ptr == &PSW || ptr == &bPSW || ptr == &DPSW) */ | |
72 | /* OBSOLETE trace_one_insn (sd, cpu, cia, 1, "engine.c", __LINE__, "alu", */ | |
73 | /* OBSOLETE "Set register %s = 0x%.8lx%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s", */ | |
74 | /* OBSOLETE (ptr == &PSW) ? "psw" : ((ptr == &bPSW) ? "bpsw" : "dpsw"), */ | |
75 | /* OBSOLETE (long)value, */ | |
76 | /* OBSOLETE (value & (0x80000000 >> PSW_SM)) ? ", sm" : "", */ | |
77 | /* OBSOLETE (value & (0x80000000 >> PSW_EA)) ? ", ea" : "", */ | |
78 | /* OBSOLETE (value & (0x80000000 >> PSW_DB)) ? ", db" : "", */ | |
79 | /* OBSOLETE (value & (0x80000000 >> PSW_DS)) ? ", ds" : "", */ | |
80 | /* OBSOLETE (value & (0x80000000 >> PSW_IE)) ? ", ie" : "", */ | |
81 | /* OBSOLETE (value & (0x80000000 >> PSW_RP)) ? ", rp" : "", */ | |
82 | /* OBSOLETE (value & (0x80000000 >> PSW_MD)) ? ", md" : "", */ | |
83 | /* OBSOLETE (value & (0x80000000 >> PSW_F0)) ? ", f0" : "", */ | |
84 | /* OBSOLETE (value & (0x80000000 >> PSW_F1)) ? ", f1" : "", */ | |
85 | /* OBSOLETE (value & (0x80000000 >> PSW_F2)) ? ", f2" : "", */ | |
86 | /* OBSOLETE (value & (0x80000000 >> PSW_F3)) ? ", f3" : "", */ | |
87 | /* OBSOLETE (value & (0x80000000 >> PSW_S)) ? ", s" : "", */ | |
88 | /* OBSOLETE (value & (0x80000000 >> PSW_V)) ? ", v" : "", */ | |
89 | /* OBSOLETE (value & (0x80000000 >> PSW_VA)) ? ", va" : "", */ | |
90 | /* OBSOLETE (value & (0x80000000 >> PSW_C)) ? ", c" : ""); */ | |
91 | /* OBSOLETE */ | |
92 | /* OBSOLETE else if (ptr >= &CREG[0] && ptr <= &CREG[NR_CONTROL_REGISTERS]) */ | |
93 | /* OBSOLETE trace_one_insn (sd, cpu, cia, 1, "engine.c", __LINE__, "alu", */ | |
94 | /* OBSOLETE "Set register cr%d = 0x%.8lx (%ld)", */ | |
95 | /* OBSOLETE ptr - &CREG[0], (long)value, (long)value); */ | |
96 | /* OBSOLETE } */ | |
97 | /* OBSOLETE */ | |
98 | /* OBSOLETE /* Implement ALU tracing of 32-bit registers. */ */ | |
99 | /* OBSOLETE static void */ | |
100 | /* OBSOLETE trace_alu64 (SIM_DESC sd, */ | |
101 | /* OBSOLETE sim_cpu *cpu, */ | |
102 | /* OBSOLETE address_word cia, */ | |
103 | /* OBSOLETE unsigned64 *ptr) */ | |
104 | /* OBSOLETE { */ | |
105 | /* OBSOLETE unsigned64 value = *ptr; */ | |
106 | /* OBSOLETE */ | |
107 | /* OBSOLETE if (ptr >= &ACC[0] && ptr <= &ACC[NR_ACCUMULATORS]) */ | |
108 | /* OBSOLETE trace_one_insn (sd, cpu, cia, 1, "engine.c", __LINE__, "alu", */ | |
109 | /* OBSOLETE "Set register a%-2d = 0x%.8lx 0x%.8lx", */ | |
110 | /* OBSOLETE ptr - &ACC[0], */ | |
111 | /* OBSOLETE (unsigned long)(unsigned32)(value >> 32), */ | |
112 | /* OBSOLETE (unsigned long)(unsigned32)value); */ | |
113 | /* OBSOLETE */ | |
114 | /* OBSOLETE } */ | |
115 | /* OBSOLETE #endif */ | |
116 | /* OBSOLETE */ | |
117 | /* OBSOLETE /* Process all of the queued up writes in order now */ */ | |
118 | /* OBSOLETE void */ | |
119 | /* OBSOLETE unqueue_writes (SIM_DESC sd, */ | |
120 | /* OBSOLETE sim_cpu *cpu, */ | |
121 | /* OBSOLETE address_word cia) */ | |
122 | /* OBSOLETE { */ | |
123 | /* OBSOLETE int i, num; */ | |
124 | /* OBSOLETE int did_psw = 0; */ | |
125 | /* OBSOLETE unsigned32 *psw_addr = &PSW; */ | |
126 | /* OBSOLETE */ | |
127 | /* OBSOLETE num = WRITE32_NUM; */ | |
128 | /* OBSOLETE for (i = 0; i < num; i++) */ | |
129 | /* OBSOLETE { */ | |
130 | /* OBSOLETE unsigned32 mask = WRITE32_MASK (i); */ | |
131 | /* OBSOLETE unsigned32 *ptr = WRITE32_PTR (i); */ | |
132 | /* OBSOLETE unsigned32 value = (*ptr & ~mask) | (WRITE32_VALUE (i) & mask); */ | |
133 | /* OBSOLETE int j; */ | |
134 | /* OBSOLETE */ | |
135 | /* OBSOLETE if (ptr == psw_addr) */ | |
136 | /* OBSOLETE { */ | |
137 | /* OBSOLETE /* If MU instruction was not a MVTSYS, resolve PSW */ | |
138 | /* OBSOLETE contention in favour of IU. */ */ | |
139 | /* OBSOLETE if(! STATE_CPU (sd, 0)->mvtsys_left_p) */ | |
140 | /* OBSOLETE { */ | |
141 | /* OBSOLETE /* Detect contention in parallel writes to the same PSW flags. */ | |
142 | /* OBSOLETE The hardware allows the updates from IU to prevail over */ | |
143 | /* OBSOLETE those from MU. */ */ | |
144 | /* OBSOLETE */ | |
145 | /* OBSOLETE unsigned32 flag_bits = */ | |
146 | /* OBSOLETE BIT32 (PSW_F0) | BIT32 (PSW_F1) | */ | |
147 | /* OBSOLETE BIT32 (PSW_F2) | BIT32 (PSW_F3) | */ | |
148 | /* OBSOLETE BIT32 (PSW_S) | BIT32 (PSW_V) | */ | |
149 | /* OBSOLETE BIT32 (PSW_VA) | BIT32 (PSW_C); */ | |
150 | /* OBSOLETE unsigned32 my_flag_bits = mask & flag_bits; */ | |
151 | /* OBSOLETE */ | |
152 | /* OBSOLETE for (j = i + 1; j < num; j++) */ | |
153 | /* OBSOLETE if (WRITE32_PTR (j) == psw_addr && /* write to PSW */ */ | |
154 | /* OBSOLETE WRITE32_MASK (j) & my_flag_bits) /* some of the same flags */ */ | |
155 | /* OBSOLETE { */ | |
156 | /* OBSOLETE /* Recompute local mask & value, to suppress this */ | |
157 | /* OBSOLETE earlier write to the same flag bits. */ */ | |
158 | /* OBSOLETE */ | |
159 | /* OBSOLETE unsigned32 new_mask = mask & ~(WRITE32_MASK (j) & my_flag_bits); */ | |
160 | /* OBSOLETE */ | |
161 | /* OBSOLETE /* There is a special case for the VA (accumulated */ | |
162 | /* OBSOLETE overflow) flag, in that it is only included in the */ | |
163 | /* OBSOLETE second instruction's mask if the overflow */ | |
164 | /* OBSOLETE occurred. Yet the hardware still suppresses the */ | |
165 | /* OBSOLETE first instruction's update to VA. So we kludge */ | |
166 | /* OBSOLETE this by inferring PSW_V -> PSW_VA for the second */ | |
167 | /* OBSOLETE instruction. */ */ | |
168 | /* OBSOLETE */ | |
169 | /* OBSOLETE if (WRITE32_MASK (j) & BIT32 (PSW_V)) */ | |
170 | /* OBSOLETE { */ | |
171 | /* OBSOLETE new_mask &= ~BIT32 (PSW_VA); */ | |
172 | /* OBSOLETE } */ | |
173 | /* OBSOLETE */ | |
174 | /* OBSOLETE value = (*ptr & ~new_mask) | (WRITE32_VALUE (i) & new_mask); */ | |
175 | /* OBSOLETE } */ | |
176 | /* OBSOLETE } */ | |
177 | /* OBSOLETE */ | |
178 | /* OBSOLETE did_psw = 1; */ | |
179 | /* OBSOLETE } */ | |
180 | /* OBSOLETE */ | |
181 | /* OBSOLETE *ptr = value; */ | |
182 | /* OBSOLETE */ | |
183 | /* OBSOLETE #if WITH_TRACE */ | |
184 | /* OBSOLETE if (TRACE_ALU_P (cpu)) */ | |
185 | /* OBSOLETE trace_alu32 (sd, cpu, cia, ptr); */ | |
186 | /* OBSOLETE #endif */ | |
187 | /* OBSOLETE } */ | |
188 | /* OBSOLETE */ | |
189 | /* OBSOLETE num = WRITE64_NUM; */ | |
190 | /* OBSOLETE for (i = 0; i < num; i++) */ | |
191 | /* OBSOLETE { */ | |
192 | /* OBSOLETE unsigned64 *ptr = WRITE64_PTR (i); */ | |
193 | /* OBSOLETE *ptr = WRITE64_VALUE (i); */ | |
194 | /* OBSOLETE */ | |
195 | /* OBSOLETE #if WITH_TRACE */ | |
196 | /* OBSOLETE if (TRACE_ALU_P (cpu)) */ | |
197 | /* OBSOLETE trace_alu64 (sd, cpu, cia, ptr); */ | |
198 | /* OBSOLETE #endif */ | |
199 | /* OBSOLETE } */ | |
200 | /* OBSOLETE */ | |
201 | /* OBSOLETE WRITE32_NUM = 0; */ | |
202 | /* OBSOLETE WRITE64_NUM = 0; */ | |
203 | /* OBSOLETE */ | |
204 | /* OBSOLETE if (DID_TRAP == 1) /* ordinary trap */ */ | |
205 | /* OBSOLETE { */ | |
206 | /* OBSOLETE bPSW = PSW; */ | |
207 | /* OBSOLETE PSW &= (BIT32 (PSW_DB) | BIT32 (PSW_SM)); */ | |
208 | /* OBSOLETE did_psw = 1; */ | |
209 | /* OBSOLETE } */ | |
210 | /* OBSOLETE else if (DID_TRAP == 2) /* debug trap */ */ | |
211 | /* OBSOLETE { */ | |
212 | /* OBSOLETE DPSW = PSW; */ | |
213 | /* OBSOLETE PSW &= BIT32 (PSW_DS); */ | |
214 | /* OBSOLETE PSW |= BIT32 (PSW_DS); */ | |
215 | /* OBSOLETE did_psw = 1; */ | |
216 | /* OBSOLETE } */ | |
217 | /* OBSOLETE DID_TRAP = 0; */ | |
218 | /* OBSOLETE */ | |
219 | /* OBSOLETE if (did_psw) */ | |
220 | /* OBSOLETE do_stack_swap (sd); */ | |
221 | /* OBSOLETE } */ | |
222 | /* OBSOLETE */ | |
223 | /* OBSOLETE */ | |
224 | /* OBSOLETE /* SIMULATE INSTRUCTIONS, various different ways of achieving the same */ | |
225 | /* OBSOLETE thing */ */ | |
226 | /* OBSOLETE */ | |
227 | /* OBSOLETE static address_word */ | |
228 | /* OBSOLETE do_long (SIM_DESC sd, */ | |
229 | /* OBSOLETE l_instruction_word instruction, */ | |
230 | /* OBSOLETE address_word cia) */ | |
231 | /* OBSOLETE { */ | |
232 | /* OBSOLETE address_word nia = l_idecode_issue(sd, */ | |
233 | /* OBSOLETE instruction, */ | |
234 | /* OBSOLETE cia); */ | |
235 | /* OBSOLETE */ | |
236 | /* OBSOLETE unqueue_writes (sd, STATE_CPU (sd, 0), cia); */ | |
237 | /* OBSOLETE return nia; */ | |
238 | /* OBSOLETE } */ | |
239 | /* OBSOLETE */ | |
240 | /* OBSOLETE static address_word */ | |
241 | /* OBSOLETE do_2_short (SIM_DESC sd, */ | |
242 | /* OBSOLETE s_instruction_word insn1, */ | |
243 | /* OBSOLETE s_instruction_word insn2, */ | |
244 | /* OBSOLETE cpu_units unit, */ | |
245 | /* OBSOLETE address_word cia) */ | |
246 | /* OBSOLETE { */ | |
247 | /* OBSOLETE address_word nia; */ | |
248 | /* OBSOLETE */ | |
249 | /* OBSOLETE /* run the first instruction */ */ | |
250 | /* OBSOLETE STATE_CPU (sd, 0)->unit = unit; */ | |
251 | /* OBSOLETE STATE_CPU (sd, 0)->left_kills_right_p = 0; */ | |
252 | /* OBSOLETE STATE_CPU (sd, 0)->mvtsys_left_p = 0; */ | |
253 | /* OBSOLETE nia = s_idecode_issue(sd, */ | |
254 | /* OBSOLETE insn1, */ | |
255 | /* OBSOLETE cia); */ | |
256 | /* OBSOLETE */ | |
257 | /* OBSOLETE unqueue_writes (sd, STATE_CPU (sd, 0), cia); */ | |
258 | /* OBSOLETE */ | |
259 | /* OBSOLETE /* Only do the second instruction if the PC has not changed */ */ | |
260 | /* OBSOLETE if ((nia == INVALID_INSTRUCTION_ADDRESS) && */ | |
261 | /* OBSOLETE (! STATE_CPU (sd, 0)->left_kills_right_p)) { */ | |
262 | /* OBSOLETE STATE_CPU (sd, 0)->unit = any_unit; */ | |
263 | /* OBSOLETE nia = s_idecode_issue (sd, */ | |
264 | /* OBSOLETE insn2, */ | |
265 | /* OBSOLETE cia); */ | |
266 | /* OBSOLETE */ | |
267 | /* OBSOLETE unqueue_writes (sd, STATE_CPU (sd, 0), cia); */ | |
268 | /* OBSOLETE } */ | |
269 | /* OBSOLETE */ | |
270 | /* OBSOLETE STATE_CPU (sd, 0)->left_kills_right_p = 0; */ | |
271 | /* OBSOLETE STATE_CPU (sd, 0)->mvtsys_left_p = 0; */ | |
272 | /* OBSOLETE return nia; */ | |
273 | /* OBSOLETE } */ | |
274 | /* OBSOLETE */ | |
275 | /* OBSOLETE static address_word */ | |
276 | /* OBSOLETE do_parallel (SIM_DESC sd, */ | |
277 | /* OBSOLETE s_instruction_word left_insn, */ | |
278 | /* OBSOLETE s_instruction_word right_insn, */ | |
279 | /* OBSOLETE address_word cia) */ | |
280 | /* OBSOLETE { */ | |
281 | /* OBSOLETE address_word nia_left; */ | |
282 | /* OBSOLETE address_word nia_right; */ | |
283 | /* OBSOLETE address_word nia; */ | |
284 | /* OBSOLETE */ | |
285 | /* OBSOLETE /* run the first instruction */ */ | |
286 | /* OBSOLETE STATE_CPU (sd, 0)->unit = memory_unit; */ | |
287 | /* OBSOLETE STATE_CPU (sd, 0)->left_kills_right_p = 0; */ | |
288 | /* OBSOLETE STATE_CPU (sd, 0)->mvtsys_left_p = 0; */ | |
289 | /* OBSOLETE nia_left = s_idecode_issue(sd, */ | |
290 | /* OBSOLETE left_insn, */ | |
291 | /* OBSOLETE cia); */ | |
292 | /* OBSOLETE */ | |
293 | /* OBSOLETE /* run the second instruction */ */ | |
294 | /* OBSOLETE STATE_CPU (sd, 0)->unit = integer_unit; */ | |
295 | /* OBSOLETE nia_right = s_idecode_issue(sd, */ | |
296 | /* OBSOLETE right_insn, */ | |
297 | /* OBSOLETE cia); */ | |
298 | /* OBSOLETE */ | |
299 | /* OBSOLETE /* merge the PC's */ */ | |
300 | /* OBSOLETE if (nia_left == INVALID_INSTRUCTION_ADDRESS) { */ | |
301 | /* OBSOLETE if (nia_right == INVALID_INSTRUCTION_ADDRESS) */ | |
302 | /* OBSOLETE nia = INVALID_INSTRUCTION_ADDRESS; */ | |
303 | /* OBSOLETE else */ | |
304 | /* OBSOLETE nia = nia_right; */ | |
305 | /* OBSOLETE } */ | |
306 | /* OBSOLETE else { */ | |
307 | /* OBSOLETE if (nia_right == INVALID_INSTRUCTION_ADDRESS) */ | |
308 | /* OBSOLETE nia = nia_left; */ | |
309 | /* OBSOLETE else { */ | |
310 | /* OBSOLETE sim_engine_abort (sd, STATE_CPU (sd, 0), cia, "parallel jumps"); */ | |
311 | /* OBSOLETE nia = INVALID_INSTRUCTION_ADDRESS; */ | |
312 | /* OBSOLETE } */ | |
313 | /* OBSOLETE } */ | |
314 | /* OBSOLETE */ | |
315 | /* OBSOLETE unqueue_writes (sd, STATE_CPU (sd, 0), cia); */ | |
316 | /* OBSOLETE return nia; */ | |
317 | /* OBSOLETE } */ | |
318 | /* OBSOLETE */ | |
319 | /* OBSOLETE */ | |
320 | /* OBSOLETE typedef enum { */ | |
321 | /* OBSOLETE p_insn = 0, */ | |
322 | /* OBSOLETE long_insn = 3, */ | |
323 | /* OBSOLETE l_r_insn = 1, */ | |
324 | /* OBSOLETE r_l_insn = 2, */ | |
325 | /* OBSOLETE } instruction_types; */ | |
326 | /* OBSOLETE */ | |
327 | /* OBSOLETE STATIC_INLINE instruction_types */ | |
328 | /* OBSOLETE instruction_type(l_instruction_word insn) */ | |
329 | /* OBSOLETE { */ | |
330 | /* OBSOLETE int fm0 = MASKED64(insn, 0, 0) != 0; */ | |
331 | /* OBSOLETE int fm1 = MASKED64(insn, 32, 32) != 0; */ | |
332 | /* OBSOLETE return ((fm0 << 1) | fm1); */ | |
333 | /* OBSOLETE } */ | |
334 | /* OBSOLETE */ | |
335 | /* OBSOLETE */ | |
336 | /* OBSOLETE */ | |
337 | /* OBSOLETE void */ | |
338 | /* OBSOLETE sim_engine_run (SIM_DESC sd, */ | |
339 | /* OBSOLETE int last_cpu_nr, */ | |
340 | /* OBSOLETE int nr_cpus, */ | |
341 | /* OBSOLETE int siggnal) */ | |
342 | /* OBSOLETE { */ | |
343 | /* OBSOLETE while (1) */ | |
344 | /* OBSOLETE { */ | |
345 | /* OBSOLETE address_word cia = PC; */ | |
346 | /* OBSOLETE address_word nia; */ | |
347 | /* OBSOLETE l_instruction_word insn = IMEM(cia); */ | |
348 | /* OBSOLETE int rp_was_set; */ | |
349 | /* OBSOLETE int rpt_c_was_nonzero; */ | |
350 | /* OBSOLETE */ | |
351 | /* OBSOLETE /* Before executing the instruction, we need to test whether or */ | |
352 | /* OBSOLETE not RPT_C is greater than zero, and save that state for use */ | |
353 | /* OBSOLETE after executing the instruction. In particular, we need to */ | |
354 | /* OBSOLETE not care whether the instruction changes RPT_C itself. */ */ | |
355 | /* OBSOLETE */ | |
356 | /* OBSOLETE rpt_c_was_nonzero = (RPT_C > 0); */ | |
357 | /* OBSOLETE */ | |
358 | /* OBSOLETE /* Before executing the instruction, we need to check to see if */ | |
359 | /* OBSOLETE we have to decrement RPT_C, the repeat count register. Do this */ | |
360 | /* OBSOLETE if PC == RPT_E, but only if we are in an active repeat block. */ */ | |
361 | /* OBSOLETE */ | |
362 | /* OBSOLETE if (PC == RPT_E && */ | |
363 | /* OBSOLETE (RPT_C > 0 || PSW_VAL (PSW_RP) != 0)) */ | |
364 | /* OBSOLETE { */ | |
365 | /* OBSOLETE RPT_C --; */ | |
366 | /* OBSOLETE } */ | |
367 | /* OBSOLETE */ | |
368 | /* OBSOLETE /* Now execute the instruction at PC */ */ | |
369 | /* OBSOLETE */ | |
370 | /* OBSOLETE switch (instruction_type (insn)) */ | |
371 | /* OBSOLETE { */ | |
372 | /* OBSOLETE case long_insn: */ | |
373 | /* OBSOLETE nia = do_long (sd, insn, cia); */ | |
374 | /* OBSOLETE break; */ | |
375 | /* OBSOLETE case r_l_insn: */ | |
376 | /* OBSOLETE /* L <- R */ */ | |
377 | /* OBSOLETE nia = do_2_short (sd, insn, insn >> 32, integer_unit, cia); */ | |
378 | /* OBSOLETE break; */ | |
379 | /* OBSOLETE case l_r_insn: */ | |
380 | /* OBSOLETE /* L -> R */ */ | |
381 | /* OBSOLETE nia = do_2_short (sd, insn >> 32, insn, memory_unit, cia); */ | |
382 | /* OBSOLETE break; */ | |
383 | /* OBSOLETE case p_insn: */ | |
384 | /* OBSOLETE nia = do_parallel (sd, insn >> 32, insn, cia); */ | |
385 | /* OBSOLETE break; */ | |
386 | /* OBSOLETE default: */ | |
387 | /* OBSOLETE sim_engine_abort (sd, STATE_CPU (sd, 0), cia, */ | |
388 | /* OBSOLETE "internal error - engine_run_until_stop - bad switch"); */ | |
389 | /* OBSOLETE nia = -1; */ | |
390 | /* OBSOLETE } */ | |
391 | /* OBSOLETE */ | |
392 | /* OBSOLETE if (TRACE_ACTION) */ | |
393 | /* OBSOLETE { */ | |
394 | /* OBSOLETE if (TRACE_ACTION & TRACE_ACTION_CALL) */ | |
395 | /* OBSOLETE call_occurred (sd, STATE_CPU (sd, 0), cia, nia); */ | |
396 | /* OBSOLETE */ | |
397 | /* OBSOLETE if (TRACE_ACTION & TRACE_ACTION_RETURN) */ | |
398 | /* OBSOLETE return_occurred (sd, STATE_CPU (sd, 0), cia, nia); */ | |
399 | /* OBSOLETE */ | |
400 | /* OBSOLETE TRACE_ACTION = 0; */ | |
401 | /* OBSOLETE } */ | |
402 | /* OBSOLETE */ | |
403 | /* OBSOLETE /* Check now to see if we need to reset the RP bit in the PSW. */ | |
404 | /* OBSOLETE There are three conditions for this, the RP bit is already */ | |
405 | /* OBSOLETE set (just a speed optimization), the instruction we just */ | |
406 | /* OBSOLETE executed is the last instruction in the loop, and the repeat */ | |
407 | /* OBSOLETE count is currently zero. */ */ | |
408 | /* OBSOLETE */ | |
409 | /* OBSOLETE rp_was_set = PSW_VAL (PSW_RP); */ | |
410 | /* OBSOLETE if (rp_was_set && (PC == RPT_E) && RPT_C == 0) */ | |
411 | /* OBSOLETE { */ | |
412 | /* OBSOLETE PSW_SET (PSW_RP, 0); */ | |
413 | /* OBSOLETE } */ | |
414 | /* OBSOLETE */ | |
415 | /* OBSOLETE /* Now update the PC. If we just executed a jump instruction, */ | |
416 | /* OBSOLETE that takes precedence over everything else. Next comes */ | |
417 | /* OBSOLETE branching back to RPT_S as a result of a loop. Finally, the */ | |
418 | /* OBSOLETE default is to simply advance to the next inline */ | |
419 | /* OBSOLETE instruction. */ */ | |
420 | /* OBSOLETE */ | |
421 | /* OBSOLETE if (nia != INVALID_INSTRUCTION_ADDRESS) */ | |
422 | /* OBSOLETE { */ | |
423 | /* OBSOLETE PC = nia; */ | |
424 | /* OBSOLETE } */ | |
425 | /* OBSOLETE else if (rp_was_set && rpt_c_was_nonzero && (PC == RPT_E)) */ | |
426 | /* OBSOLETE { */ | |
427 | /* OBSOLETE PC = RPT_S; */ | |
428 | /* OBSOLETE } */ | |
429 | /* OBSOLETE else */ | |
430 | /* OBSOLETE { */ | |
431 | /* OBSOLETE PC = cia + 8; */ | |
432 | /* OBSOLETE } */ | |
433 | /* OBSOLETE */ | |
434 | /* OBSOLETE /* Check for DDBT (debugger debug trap) condition. Do this after */ | |
435 | /* OBSOLETE the repeat block checks so the excursion to the trap handler does */ | |
436 | /* OBSOLETE not alter looping state. */ */ | |
437 | /* OBSOLETE */ | |
438 | /* OBSOLETE if (cia == IBA && PSW_VAL (PSW_DB)) */ | |
439 | /* OBSOLETE { */ | |
440 | /* OBSOLETE DPC = PC; */ | |
441 | /* OBSOLETE PSW_SET (PSW_EA, 1); */ | |
442 | /* OBSOLETE DPSW = PSW; */ | |
443 | /* OBSOLETE /* clear all bits in PSW except SM */ */ | |
444 | /* OBSOLETE PSW &= BIT32 (PSW_SM); */ | |
445 | /* OBSOLETE /* add DS bit */ */ | |
446 | /* OBSOLETE PSW |= BIT32 (PSW_DS); */ | |
447 | /* OBSOLETE /* dispatch to DDBT handler */ */ | |
448 | /* OBSOLETE PC = 0xfffff128; /* debugger_debug_trap_address */ */ | |
449 | /* OBSOLETE } */ | |
450 | /* OBSOLETE */ | |
451 | /* OBSOLETE /* process any events */ */ | |
452 | /* OBSOLETE /* FIXME - should L->R or L<-R insns count as two cycles? */ */ | |
453 | /* OBSOLETE if (sim_events_tick (sd)) */ | |
454 | /* OBSOLETE { */ | |
455 | /* OBSOLETE sim_events_process (sd); */ | |
456 | /* OBSOLETE } */ | |
457 | /* OBSOLETE } */ | |
458 | /* OBSOLETE } */ | |
459 | /* OBSOLETE */ | |
460 | /* OBSOLETE */ | |
461 | /* OBSOLETE /* d30v external interrupt handler. */ | |
462 | /* OBSOLETE */ | |
463 | /* OBSOLETE Note: This should be replaced by a proper interrupt delivery */ | |
464 | /* OBSOLETE mechanism. This interrupt mechanism discards later interrupts if */ | |
465 | /* OBSOLETE an earlier interrupt hasn't been delivered. */ | |
466 | /* OBSOLETE */ | |
467 | /* OBSOLETE Note: This interrupt mechanism does not reset its self when the */ | |
468 | /* OBSOLETE simulator is re-opened. */ */ | |
469 | /* OBSOLETE */ | |
470 | /* OBSOLETE void */ | |
471 | /* OBSOLETE d30v_interrupt_event (SIM_DESC sd, */ | |
472 | /* OBSOLETE void *data) */ | |
473 | /* OBSOLETE { */ | |
474 | /* OBSOLETE if (PSW_VAL (PSW_IE)) */ | |
475 | /* OBSOLETE /* interrupts not masked */ */ | |
476 | /* OBSOLETE { */ | |
477 | /* OBSOLETE /* scrub any pending interrupt */ */ | |
478 | /* OBSOLETE if (sd->pending_interrupt != NULL) */ | |
479 | /* OBSOLETE sim_events_deschedule (sd, sd->pending_interrupt); */ | |
480 | /* OBSOLETE /* deliver */ */ | |
481 | /* OBSOLETE bPSW = PSW; */ | |
482 | /* OBSOLETE bPC = PC; */ | |
483 | /* OBSOLETE PSW = 0; */ | |
484 | /* OBSOLETE PC = 0xfffff138; /* external interrupt */ */ | |
485 | /* OBSOLETE do_stack_swap (sd); */ | |
486 | /* OBSOLETE } */ | |
487 | /* OBSOLETE else if (sd->pending_interrupt == NULL) */ | |
488 | /* OBSOLETE /* interrupts masked and no interrupt pending */ */ | |
489 | /* OBSOLETE { */ | |
490 | /* OBSOLETE sd->pending_interrupt = sim_events_schedule (sd, 1, */ | |
491 | /* OBSOLETE d30v_interrupt_event, */ | |
492 | /* OBSOLETE data); */ | |
493 | /* OBSOLETE } */ | |
494 | /* OBSOLETE } */ | |
495 | /* OBSOLETE */ | |
496 | /* OBSOLETE #endif */ |