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[deliverable/binutils-gdb.git] / sim / erc32 / erc32.c
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c906108c
SS		 1/*
2 * This file is part of SIS.
3 *
4 * SIS, SPARC instruction simulator V2.5 Copyright (C) 1995 Jiri Gaisler,
5 * European Space Agency
6 *
7 * This program is free software; you can redistribute it and/or modify it under
8 * the terms of the GNU General Public License as published by the Free
3fd725ef 9 * Software Foundation; either version 3 of the License, or (at your option)
c906108c
SS		 10 * any later version.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
51b318de 18 * this program; if not, see <http://www.gnu.org/licenses/>.
c906108c
SS		 19 *
20 */
21
22/* The control space devices */
23
5272643f 24#include "config.h"
c906108c
SS		 25#include <sys/types.h>
26#include <stdio.h>
d68c23cd 27#include <string.h>
c906108c
SS		 28#include <termios.h>
29#include <sys/fcntl.h>
30#include <sys/file.h>
31#include <unistd.h>
32#include "sis.h"
c906108c
SS		 33#include "sim-config.h"
34
35extern int ctrl_c;
36extern int32 sis_verbose;
37extern int32 sparclite, sparclite_board;
38extern int rom8,wrp,uben;
39extern char uart_dev1[], uart_dev2[];
40
41int dumbio = 0; /* normal, smart, terminal oriented IO by default */
42
43/* MEC registers */
44#define MEC_START 0x01f80000
45#define MEC_END 0x01f80100
46
47/* Memory exception waitstates */
48#define MEM_EX_WS 1
49
50/* ERC32 always adds one waitstate during RAM std */
51#define STD_WS 1
52
53#ifdef ERRINJ
54extern int errmec;
55#endif
56
c906108c
SS		 57#define MEC_WS 0 /* Waitstates per MEC access (0 ws) */
58#define MOK 0
59
60/* MEC register addresses */
61
62#define MEC_MCR 0x000
63#define MEC_SFR 0x004
64#define MEC_PWDR 0x008
65#define MEC_MEMCFG 0x010
66#define MEC_IOCR 0x014
67#define MEC_WCR 0x018
68
69#define MEC_MAR0 0x020
70#define MEC_MAR1 0x024
71
72#define MEC_SSA1 0x020
73#define MEC_SEA1 0x024
74#define MEC_SSA2 0x028
75#define MEC_SEA2 0x02C
76#define MEC_ISR 0x044
77#define MEC_IPR 0x048
78#define MEC_IMR 0x04C
79#define MEC_ICR 0x050
80#define MEC_IFR 0x054
81#define MEC_WDOG 0x060
82#define MEC_TRAPD 0x064
83#define MEC_RTC_COUNTER 0x080
84#define MEC_RTC_RELOAD 0x080
85#define MEC_RTC_SCALER 0x084
86#define MEC_GPT_COUNTER 0x088
87#define MEC_GPT_RELOAD 0x088
88#define MEC_GPT_SCALER 0x08C
89#define MEC_TIMER_CTRL 0x098
90#define MEC_SFSR 0x0A0
91#define MEC_FFAR 0x0A4
92#define MEC_ERSR 0x0B0
93#define MEC_DBG 0x0C0
94#define MEC_TCR 0x0D0
95
96#define MEC_BRK 0x0C4
97#define MEC_WPR 0x0C8
98
99#define MEC_UARTA 0x0E0
100#define MEC_UARTB 0x0E4
101#define MEC_UART_CTRL 0x0E8
102#define SIM_LOAD 0x0F0
103
104/* Memory exception causes */
105#define PROT_EXC 0x3
106#define UIMP_ACC 0x4
107#define MEC_ACC 0x6
108#define WATCH_EXC 0xa
109#define BREAK_EXC 0xb
110
111/* Size of UART buffers (bytes) */
112#define UARTBUF 1024
113
114/* Number of simulator ticks between flushing the UARTS. */
115/* For good performance, keep above 1000 */
116#define UART_FLUSH_TIME 3000
117
118/* MEC timer control register bits */
119#define TCR_GACR 1
120#define TCR_GACL 2
121#define TCR_GASE 4
122#define TCR_GASL 8
123#define TCR_TCRCR 0x100
124#define TCR_TCRCL 0x200
125#define TCR_TCRSE 0x400
126#define TCR_TCRSL 0x800
127
128/* New uart defines */
129#define UART_TX_TIME 1000
130#define UART_RX_TIME 1000
131#define UARTA_DR 0x1
132#define UARTA_SRE 0x2
133#define UARTA_HRE 0x4
134#define UARTA_OR 0x40
135#define UARTA_CLR 0x80
136#define UARTB_DR 0x10000
137#define UARTB_SRE 0x20000
138#define UARTB_HRE 0x40000
139#define UARTB_OR 0x400000
140#define UARTB_CLR 0x800000
141
142#define UART_DR 0x100
143#define UART_TSE 0x200
144#define UART_THE 0x400
145
146/* MEC registers */
147
148static char fname[256];
149static int32 find = 0;
150static uint32 mec_ssa[2]; /* Write protection start address */
151static uint32 mec_sea[2]; /* Write protection end address */
152static uint32 mec_wpr[2]; /* Write protection control fields */
153static uint32 mec_sfsr;
154static uint32 mec_ffar;
155static uint32 mec_ipr;
156static uint32 mec_imr;
157static uint32 mec_isr;
158static uint32 mec_icr;
159static uint32 mec_ifr;
160static uint32 mec_mcr; /* MEC control register */
161static uint32 mec_memcfg; /* Memory control register */
162static uint32 mec_wcr; /* MEC waitstate register */
163static uint32 mec_iocr; /* MEC IO control register */
164static uint32 posted_irq;
165static uint32 mec_ersr; /* MEC error and status register */
166static uint32 mec_tcr; /* MEC test comtrol register */
167
168static uint32 rtc_counter;
169static uint32 rtc_reload;
170static uint32 rtc_scaler;
171static uint32 rtc_scaler_start;
172static uint32 rtc_enabled;
173static uint32 rtc_cr;
174static uint32 rtc_se;
175
176static uint32 gpt_counter;
177static uint32 gpt_reload;
178static uint32 gpt_scaler;
179static uint32 gpt_scaler_start;
180static uint32 gpt_enabled;
181static uint32 gpt_cr;
182static uint32 gpt_se;
183
184static uint32 wdog_scaler;
185static uint32 wdog_counter;
186static uint32 wdog_rst_delay;
187static uint32 wdog_rston;
188
189enum wdog_type {
190 init, disabled, enabled, stopped
191};
192
193static enum wdog_type wdog_status;
194
195
196/* ROM size 1024 Kbyte */
197#define ROM_SZ 0x100000
198#define ROM_MASK 0x0fffff
199
200/* RAM size 4 Mbyte */
201#define RAM_START 0x02000000
202#define RAM_END 0x02400000
203#define RAM_MASK 0x003fffff
204
205/* SPARClite boards all seem to have RAM at the same place. */
206#define RAM_START_SLITE 0x40000000
207#define RAM_END_SLITE 0x40400000
208#define RAM_MASK_SLITE 0x003fffff
209
210/* Memory support variables */
211
212static uint32 mem_ramr_ws; /* RAM read waitstates */
213static uint32 mem_ramw_ws; /* RAM write waitstates */
214static uint32 mem_romr_ws; /* ROM read waitstates */
215static uint32 mem_romw_ws; /* ROM write waitstates */
216static uint32 mem_ramstart; /* RAM start */
217static uint32 mem_ramend; /* RAM end */
218static uint32 mem_rammask; /* RAM address mask */
219static uint32 mem_ramsz; /* RAM size */
220static uint32 mem_romsz; /* ROM size */
221static uint32 mem_accprot; /* RAM write protection enabled */
222static uint32 mem_blockprot; /* RAM block write protection enabled */
223
224static unsigned char romb[ROM_SZ];
225static unsigned char ramb[RAM_END - RAM_START];
226
227
228/* UART support variables */
229
230static int32 fd1, fd2; /* file descriptor for input file */
231static int32 Ucontrol; /* UART status register */
232static unsigned char aq[UARTBUF], bq[UARTBUF];
233static int32 anum, aind = 0;
234static int32 bnum, bind = 0;
235static char wbufa[UARTBUF], wbufb[UARTBUF];
236static unsigned wnuma;
237static unsigned wnumb;
238static FILE *f1in, *f1out, *f2in, *f2out;
239static struct termios ioc1, ioc2, iocold1, iocold2;
240static int f1open = 0, f2open = 0;
241
242static char uarta_sreg, uarta_hreg, uartb_sreg, uartb_hreg;
243static uint32 uart_stat_reg;
244static uint32 uarta_data, uartb_data;
245
246#ifdef ERA
247int era = 0;
248int erareg;
249#endif
250
251/* Forward declarations */
252
bdca5ee4 253static void decode_ersr (void);
c906108c 254#ifdef ERRINJ
bdca5ee4 255static void iucomperr (void);
c906108c 256#endif
bdca5ee4
TT		 257static void mecparerror (void);
258static void decode_memcfg (void);
259static void decode_wcr (void);
260static void decode_mcr (void);
261static void close_port (void);
262static void mec_reset (void);
263static void mec_intack (int32 level);
264static void chk_irq (void);
265static void mec_irq (int32 level);
266static void set_sfsr (uint32 fault, uint32 addr,
267 uint32 asi, uint32 read);
268static int32 mec_read (uint32 addr, uint32 asi, uint32 *data);
269static int mec_write (uint32 addr, uint32 data);
270static void port_init (void);
271static uint32 read_uart (uint32 addr);
272static void write_uart (uint32 addr, uint32 data);
273static void flush_uart (void);
274static void uarta_tx (void);
275static void uartb_tx (void);
276static void uart_rx (caddr_t arg);
277static void uart_intr (caddr_t arg);
278static void uart_irq_start (void);
279static void wdog_intr (caddr_t arg);
280static void wdog_start (void);
281static void rtc_intr (caddr_t arg);
282static void rtc_start (void);
283static uint32 rtc_counter_read (void);
284static void rtc_scaler_set (uint32 val);
285static void rtc_reload_set (uint32 val);
286static void gpt_intr (caddr_t arg);
287static void gpt_start (void);
288static uint32 gpt_counter_read (void);
289static void gpt_scaler_set (uint32 val);
290static void gpt_reload_set (uint32 val);
291static void timer_ctrl (uint32 val);
c906108c 292static unsigned char *
bdca5ee4 293 get_mem_ptr (uint32 addr, uint32 size);
d3e9b40a
JG		 294static void store_bytes (unsigned char *mem, uint32 waddr,
295 uint32 *data, int sz, int32 *ws);
c906108c
SS		 296
297extern int ext_irl;
298
299
300/* One-time init */
301
302void
303init_sim()
304{
305 port_init();
306}
307
308/* Power-on reset init */
309
310void
311reset()
312{
313 mec_reset();
314 uart_irq_start();
315 wdog_start();
316}
317
318static void
319decode_ersr()
320{
321 if (mec_ersr & 0x01) {
322 if (!(mec_mcr & 0x20)) {
323 if (mec_mcr & 0x40) {
324 sys_reset();
325 mec_ersr = 0x8000;
326 if (sis_verbose)
327 printf("Error manager reset - IU in error mode\n");
328 } else {
329 sys_halt();
330 mec_ersr |= 0x2000;
331 if (sis_verbose)
332 printf("Error manager halt - IU in error mode\n");
333 }
334 } else
335 mec_irq(1);
336 }
337 if (mec_ersr & 0x04) {
338 if (!(mec_mcr & 0x200)) {
339 if (mec_mcr & 0x400) {
340 sys_reset();
341 mec_ersr = 0x8000;
342 if (sis_verbose)
343 printf("Error manager reset - IU comparison error\n");
344 } else {
345 sys_halt();
346 mec_ersr |= 0x2000;
347 if (sis_verbose)
348 printf("Error manager halt - IU comparison error\n");
349 }
350 } else
351 mec_irq(1);
352 }
353 if (mec_ersr & 0x20) {
354 if (!(mec_mcr & 0x2000)) {
355 if (mec_mcr & 0x4000) {
356 sys_reset();
357 mec_ersr = 0x8000;
358 if (sis_verbose)
359 printf("Error manager reset - MEC hardware error\n");
360 } else {
361 sys_halt();
362 mec_ersr |= 0x2000;
363 if (sis_verbose)
364 printf("Error manager halt - MEC hardware error\n");
365 }
366 } else
367 mec_irq(1);
368 }
369}
370
371#ifdef ERRINJ
372static void
373iucomperr()
374{
375 mec_ersr |= 0x04;
376 decode_ersr();
377}
378#endif
379
380static void
381mecparerror()
382{
383 mec_ersr |= 0x20;
384 decode_ersr();
385}
386
387
388/* IU error mode manager */
389
390void
391error_mode(pc)
392 uint32 pc;
393{
394
395 mec_ersr |= 0x1;
396 decode_ersr();
397}
398
399
400/* Check memory settings */
401
402static void
403decode_memcfg()
404{
405 if (rom8) mec_memcfg &= ~0x20000;
406 else mec_memcfg |= 0x20000;
407
408 mem_ramsz = (256 * 1024) << ((mec_memcfg >> 10) & 7);
409 mem_romsz = (128 * 1024) << ((mec_memcfg >> 18) & 7);
410
411 if (sparclite_board) {
412 mem_ramstart = RAM_START_SLITE;
413 mem_ramend = RAM_END_SLITE;
414 mem_rammask = RAM_MASK_SLITE;
415 }
416 else {
417 mem_ramstart = RAM_START;
418 mem_ramend = RAM_END;
419 mem_rammask = RAM_MASK;
420 }
421 if (sis_verbose)
422 printf("RAM start: 0x%x, RAM size: %d K, ROM size: %d K\n",
423 mem_ramstart, mem_ramsz >> 10, mem_romsz >> 10);
424}
425
426static void
427decode_wcr()
428{
429 mem_ramr_ws = mec_wcr & 3;
430 mem_ramw_ws = (mec_wcr >> 2) & 3;
431 mem_romr_ws = (mec_wcr >> 4) & 0x0f;
432 if (rom8) {
433 if (mem_romr_ws > 0 ) mem_romr_ws--;
434 mem_romr_ws = 5 + (4*mem_romr_ws);
435 }
436 mem_romw_ws = (mec_wcr >> 8) & 0x0f;
437 if (sis_verbose)
438 printf("Waitstates = RAM read: %d, RAM write: %d, ROM read: %d, ROM write: %d\n",
439 mem_ramr_ws, mem_ramw_ws, mem_romr_ws, mem_romw_ws);
440}
441
442static void
443decode_mcr()
444{
445 mem_accprot = (mec_wpr[0] | mec_wpr[1]);
446 mem_blockprot = (mec_mcr >> 3) & 1;
447 if (sis_verbose && mem_accprot)
448 printf("Memory block write protection enabled\n");
449 if (mec_mcr & 0x08000) {
450 mec_ersr |= 0x20;
451 decode_ersr();
452 }
453 if (sis_verbose && (mec_mcr & 2))
454 printf("Software reset enabled\n");
455 if (sis_verbose && (mec_mcr & 1))
456 printf("Power-down mode enabled\n");
457}
458
459/* Flush ports when simulator stops */
460
461void
462sim_halt()
463{
464#ifdef FAST_UART
465 flush_uart();
466#endif
467}
468
469int
470sim_stop(SIM_DESC sd)
471{
472 ctrl_c = 1;
473 return 1;
474}
475
476static void
477close_port()
478{
479 if (f1open && f1in != stdin)
480 fclose(f1in);
481 if (f2open && f2in != stdin)
482 fclose(f2in);
483}
484
485void
486exit_sim()
487{
488 close_port();
489}
490
491static void
492mec_reset()
493{
494 int i;
495
496 find = 0;
497 for (i = 0; i < 2; i++)
498 mec_ssa[i] = mec_sea[i] = mec_wpr[i] = 0;
499 mec_mcr = 0x01350014;
500 mec_iocr = 0;
501 mec_sfsr = 0x078;
502 mec_ffar = 0;
503 mec_ipr = 0;
504 mec_imr = 0x7ffe;
505 mec_isr = 0;
506 mec_icr = 0;
507 mec_ifr = 0;
508 mec_memcfg = 0x10000;
509 mec_wcr = -1;
510 mec_ersr = 0; /* MEC error and status register */
511 mec_tcr = 0; /* MEC test comtrol register */
512
513 decode_memcfg();
514 decode_wcr();
515 decode_mcr();
516
517 posted_irq = 0;
518 wnuma = wnumb = 0;
519 anum = aind = bnum = bind = 0;
520
521 uart_stat_reg = UARTA_SRE | UARTA_HRE | UARTB_SRE | UARTB_HRE;
522 uarta_data = uartb_data = UART_THE | UART_TSE;
523
524 rtc_counter = 0xffffffff;
525 rtc_reload = 0xffffffff;
526 rtc_scaler = 0xff;
527 rtc_enabled = 0;
528 rtc_cr = 0;
529 rtc_se = 0;
530
531 gpt_counter = 0xffffffff;
532 gpt_reload = 0xffffffff;
533 gpt_scaler = 0xffff;
534 gpt_enabled = 0;
535 gpt_cr = 0;
536 gpt_se = 0;
537
538 wdog_scaler = 255;
539 wdog_rst_delay = 255;
540 wdog_counter = 0xffff;
541 wdog_rston = 0;
542 wdog_status = init;
543
544#ifdef ERA
545 erareg = 0;
546#endif
547
548}
549
550
551
552static void
553mec_intack(level)
554 int32 level;
555{
556 int irq_test;
557
558 if (sis_verbose)
559 printf("interrupt %d acknowledged\n", level);
560 irq_test = mec_tcr & 0x80000;
561 if ((irq_test) && (mec_ifr & (1 << level)))
562 mec_ifr &= ~(1 << level);
563 else
564 mec_ipr &= ~(1 << level);
565 chk_irq();
566}
567
568static void
569chk_irq()
570{
571 int32 i;
572 uint32 itmp;
573 int old_irl;
574
575 old_irl = ext_irl;
576 if (mec_tcr & 0x80000) itmp = mec_ifr;
577 else itmp = 0;
578 itmp = ((mec_ipr | itmp) & ~mec_imr) & 0x0fffe;
579 ext_irl = 0;
580 if (itmp != 0) {
581 for (i = 15; i > 0; i--) {
582 if (((itmp >> i) & 1) != 0) {
583 if ((sis_verbose) && (i > old_irl))
584 printf("IU irl: %d\n", i);
585 ext_irl = i;
586 set_int(i, mec_intack, i);
587 break;
588 }
589 }
590 }
591}
592
593static void
594mec_irq(level)
595 int32 level;
596{
597 mec_ipr |= (1 << level);
598 chk_irq();
599}
600
601static void
602set_sfsr(fault, addr, asi, read)
603 uint32 fault;
604 uint32 addr;
605 uint32 asi;
606 uint32 read;
607{
608 if ((asi == 0xa) || (asi == 0xb)) {
609 mec_ffar = addr;
610 mec_sfsr = (fault << 3) | (!read << 15);
611 mec_sfsr |= ((mec_sfsr & 1) ^ 1) | (mec_sfsr & 1);
612 switch (asi) {
613 case 0xa:
614 mec_sfsr |= 0x0004;
615 break;
616 case 0xb:
617 mec_sfsr |= 0x1004;
618 break;
619 }
620 }
621}
622
623static int32
624mec_read(addr, asi, data)
625 uint32 addr;
626 uint32 asi;
627 uint32 *data;
628{
629
630 switch (addr & 0x0ff) {
631
632 case MEC_MCR: /* 0x00 */
633 *data = mec_mcr;
634 break;
635
636 case MEC_MEMCFG: /* 0x10 */
637 *data = mec_memcfg;
638 break;
639
640 case MEC_IOCR:
641 *data = mec_iocr; /* 0x14 */
642 break;
643
644 case MEC_SSA1: /* 0x20 */
645 *data = mec_ssa[0] | (mec_wpr[0] << 23);
646 break;
647 case MEC_SEA1: /* 0x24 */
648 *data = mec_sea[0];
649 break;
650 case MEC_SSA2: /* 0x28 */
651 *data = mec_ssa[1] | (mec_wpr[1] << 23);
652 break;
653 case MEC_SEA2: /* 0x2c */
654 *data = mec_sea[1];
655 break;
656
657 case MEC_ISR: /* 0x44 */
658 *data = mec_isr;
659 break;
660
661 case MEC_IPR: /* 0x48 */
662 *data = mec_ipr;
663 break;
664
665 case MEC_IMR: /* 0x4c */
666 *data = mec_imr;
667 break;
668
669 case MEC_IFR: /* 0x54 */
670 *data = mec_ifr;
671 break;
672
673 case MEC_RTC_COUNTER: /* 0x80 */
674 *data = rtc_counter_read();
675 break;
676 case MEC_RTC_SCALER: /* 0x84 */
677 if (rtc_enabled)
678 *data = rtc_scaler - (now() - rtc_scaler_start);
679 else
680 *data = rtc_scaler;
681 break;
682
683 case MEC_GPT_COUNTER: /* 0x88 */
684 *data = gpt_counter_read();
685 break;
686
687 case MEC_GPT_SCALER: /* 0x8c */
688 if (rtc_enabled)
689 *data = gpt_scaler - (now() - gpt_scaler_start);
690 else
691 *data = gpt_scaler;
692 break;
693
694
695 case MEC_SFSR: /* 0xA0 */
696 *data = mec_sfsr;
697 break;
698
699 case MEC_FFAR: /* 0xA4 */
700 *data = mec_ffar;
701 break;
702
703 case SIM_LOAD:
704 fname[find] = 0;
705 if (find == 0)
706 strcpy(fname, "simload");
707 find = bfd_load(fname);
708 if (find == -1)
709 *data = 0;
710 else
711 *data = 1;
712 find = 0;
713 break;
714
715 case MEC_ERSR: /* 0xB0 */
716 *data = mec_ersr;
717 break;
718
719 case MEC_TCR: /* 0xD0 */
720 *data = mec_tcr;
721 break;
722
723 case MEC_UARTA: /* 0xE0 */
724 case MEC_UARTB: /* 0xE4 */
725 if (asi != 0xb) {
726 set_sfsr(MEC_ACC, addr, asi, 1);
5831e29b 727 return 1;
c906108c
SS		 728 }
729 *data = read_uart(addr);
730 break;
731
732 case MEC_UART_CTRL: /* 0xE8 */
733
734 *data = read_uart(addr);
735 break;
736
20a0ffe3
JG		 737 case 0xF4: /* simulator RAM size in bytes */
738 *data = 4096*1024;
739 break;
740
741 case 0xF8: /* simulator ROM size in bytes */
742 *data = 1024*1024;
743 break;
744
c906108c
SS		 745 default:
746 set_sfsr(MEC_ACC, addr, asi, 1);
5831e29b 747 return 1;
c906108c
SS		 748 break;
749 }
5831e29b 750 return MOK;
c906108c
SS		 751}
752
753static int
754mec_write(addr, data)
755 uint32 addr;
756 uint32 data;
757{
758 if (sis_verbose > 1)
759 printf("MEC write a: %08x, d: %08x\n",addr,data);
760 switch (addr & 0x0ff) {
761
762 case MEC_MCR:
763 mec_mcr = data;
764 decode_mcr();
765 if (mec_mcr & 0x08000) mecparerror();
766 break;
767
768 case MEC_SFR:
769 if (mec_mcr & 0x2) {
770 sys_reset();
771 mec_ersr = 0x4000;
772 if (sis_verbose)
773 printf(" Software reset issued\n");
774 }
775 break;
776
777 case MEC_IOCR:
778 mec_iocr = data;
779 if (mec_iocr & 0xC0C0C0C0) mecparerror();
780 break;
781
782 case MEC_SSA1: /* 0x20 */
783 if (data & 0xFE000000) mecparerror();
784 mec_ssa[0] = data & 0x7fffff;
785 mec_wpr[0] = (data >> 23) & 0x03;
786 mem_accprot = mec_wpr[0] || mec_wpr[1];
787 if (sis_verbose && mec_wpr[0])
788 printf("Segment 1 memory protection enabled (0x02%06x - 0x02%06x)\n",
789 mec_ssa[0] << 2, mec_sea[0] << 2);
790 break;
791 case MEC_SEA1: /* 0x24 */
792 if (data & 0xFF800000) mecparerror();
793 mec_sea[0] = data & 0x7fffff;
794 break;
795 case MEC_SSA2: /* 0x28 */
796 if (data & 0xFE000000) mecparerror();
797 mec_ssa[1] = data & 0x7fffff;
798 mec_wpr[1] = (data >> 23) & 0x03;
799 mem_accprot = mec_wpr[0] || mec_wpr[1];
800 if (sis_verbose && mec_wpr[1])
801 printf("Segment 2 memory protection enabled (0x02%06x - 0x02%06x)\n",
802 mec_ssa[1] << 2, mec_sea[1] << 2);
803 break;
804 case MEC_SEA2: /* 0x2c */
805 if (data & 0xFF800000) mecparerror();
806 mec_sea[1] = data & 0x7fffff;
807 break;
808
809 case MEC_UARTA:
810 case MEC_UARTB:
811 if (data & 0xFFFFFF00) mecparerror();
812 case MEC_UART_CTRL:
813 if (data & 0xFF00FF00) mecparerror();
814 write_uart(addr, data);
815 break;
816
817 case MEC_GPT_RELOAD:
818 gpt_reload_set(data);
819 break;
820
821 case MEC_GPT_SCALER:
822 if (data & 0xFFFF0000) mecparerror();
823 gpt_scaler_set(data);
824 break;
825
826 case MEC_TIMER_CTRL:
827 if (data & 0xFFFFF0F0) mecparerror();
828 timer_ctrl(data);
829 break;
830
831 case MEC_RTC_RELOAD:
832 rtc_reload_set(data);
833 break;
834
835 case MEC_RTC_SCALER:
836 if (data & 0xFFFFFF00) mecparerror();
837 rtc_scaler_set(data);
838 break;
839
840 case MEC_SFSR: /* 0xA0 */
841 if (data & 0xFFFF0880) mecparerror();
842 mec_sfsr = 0x78;
843 break;
844
845 case MEC_ISR:
846 if (data & 0xFFFFE000) mecparerror();
847 mec_isr = data;
848 break;
849
850 case MEC_IMR: /* 0x4c */
851
852 if (data & 0xFFFF8001) mecparerror();
853 mec_imr = data & 0x7ffe;
854 chk_irq();
855 break;
856
857 case MEC_ICR: /* 0x50 */
858
859 if (data & 0xFFFF0001) mecparerror();
860 mec_ipr &= ~data & 0x0fffe;
861 chk_irq();
862 break;
863
864 case MEC_IFR: /* 0x54 */
865
866 if (mec_tcr & 0x080000) {
867 if (data & 0xFFFF0001) mecparerror();
868 mec_ifr = data & 0xfffe;
869 chk_irq();
870 }
871 break;
872 case SIM_LOAD:
873 fname[find++] = (char) data;
874 break;
875
876
877 case MEC_MEMCFG: /* 0x10 */
878 if (data & 0xC0E08000) mecparerror();
879 mec_memcfg = data;
880 decode_memcfg();
881 if (mec_memcfg & 0xc0e08000)
882 mecparerror();
883 break;
884
885 case MEC_WCR: /* 0x18 */
886 mec_wcr = data;
887 decode_wcr();
888 break;
889
890 case MEC_ERSR: /* 0xB0 */
891 if (mec_tcr & 0x100000)
892 if (data & 0xFFFFEFC0) mecparerror();
893 mec_ersr = data & 0x103f;
894 break;
895
896 case MEC_TCR: /* 0xD0 */
897 if (data & 0xFFE1FFC0) mecparerror();
898 mec_tcr = data & 0x1e003f;
899 break;
900
901 case MEC_WDOG: /* 0x60 */
902 wdog_scaler = (data >> 16) & 0x0ff;
903 wdog_counter = data & 0x0ffff;
904 wdog_rst_delay = data >> 24;
905 wdog_rston = 0;
906 if (wdog_status == stopped)
907 wdog_start();
908 wdog_status = enabled;
909 break;
910
911 case MEC_TRAPD: /* 0x64 */
912 if (wdog_status == init) {
913 wdog_status = disabled;
914 if (sis_verbose)
915 printf("Watchdog disabled\n");
916 }
917 break;
918
919 case MEC_PWDR:
920 if (mec_mcr & 1)
921 wait_for_irq();
922 break;
923
924 default:
925 set_sfsr(MEC_ACC, addr, 0xb, 0);
5831e29b 926 return 1;
c906108c
SS		 927 break;
928 }
5831e29b 929 return MOK;
c906108c
SS		 930}
931
932
933/* MEC UARTS */
934
935static int ifd1 = -1, ifd2 = -1, ofd1 = -1, ofd2 = -1;
936
937void
938init_stdio()
939{
940 if (dumbio)
941 return; /* do nothing */
942 if (!ifd1)
943 tcsetattr(0, TCSANOW, &ioc1);
944 if (!ifd2)
945 tcsetattr(0, TCSANOW, &ioc2);
946}
947
948void
949restore_stdio()
950{
951 if (dumbio)
952 return; /* do nothing */
953 if (!ifd1)
954 tcsetattr(0, TCSANOW, &iocold1);
955 if (!ifd2)
956 tcsetattr(0, TCSANOW, &iocold2);
957}
958
959#define DO_STDIO_READ( _fd_, _buf_, _len_ ) \
960 ( dumbio \
961 ? (0) /* no bytes read, no delay */ \
962 : read( _fd_, _buf_, _len_ ) )
963
964
965static void
966port_init()
967{
968
969 if (uben) {
970 f2in = stdin;
971 f1in = NULL;
972 f2out = stdout;
973 f1out = NULL;
974 } else {
975 f1in = stdin;
976 f2in = NULL;
977 f1out = stdout;
978 f2out = NULL;
979 }
980 if (uart_dev1[0] != 0)
981 if ((fd1 = open(uart_dev1, O_RDWR | O_NONBLOCK)) < 0) {
982 printf("Warning, couldn't open output device %s\n", uart_dev1);
983 } else {
984 if (sis_verbose)
985 printf("serial port A on %s\n", uart_dev1);
986 f1in = f1out = fdopen(fd1, "r+");
987 setbuf(f1out, NULL);
988 f1open = 1;
989 }
990 if (f1in) ifd1 = fileno(f1in);
991 if (ifd1 == 0) {
992 if (sis_verbose)
993 printf("serial port A on stdin/stdout\n");
994 if (!dumbio) {
995 tcgetattr(ifd1, &ioc1);
996 iocold1 = ioc1;
997 ioc1.c_lflag &= ~(ICANON | ECHO);
998 ioc1.c_cc[VMIN] = 0;
999 ioc1.c_cc[VTIME] = 0;
1000 }
1001 f1open = 1;
1002 }
1003
1004 if (f1out) {
1005 ofd1 = fileno(f1out);
1006 if (!dumbio && ofd1 == 1) setbuf(f1out, NULL);
1007 }
1008
1009 if (uart_dev2[0] != 0)
1010 if ((fd2 = open(uart_dev2, O_RDWR | O_NONBLOCK)) < 0) {
1011 printf("Warning, couldn't open output device %s\n", uart_dev2);
1012 } else {
1013 if (sis_verbose)
1014 printf("serial port B on %s\n", uart_dev2);
1015 f2in = f2out = fdopen(fd2, "r+");
1016 setbuf(f2out, NULL);
1017 f2open = 1;
1018 }
1019 if (f2in) ifd2 = fileno(f2in);
1020 if (ifd2 == 0) {
1021 if (sis_verbose)
1022 printf("serial port B on stdin/stdout\n");
1023 if (!dumbio) {
1024 tcgetattr(ifd2, &ioc2);
1025 iocold2 = ioc2;
1026 ioc2.c_lflag &= ~(ICANON | ECHO);
1027 ioc2.c_cc[VMIN] = 0;
1028 ioc2.c_cc[VTIME] = 0;
1029 }
1030 f2open = 1;
1031 }
1032
1033 if (f2out) {
1034 ofd2 = fileno(f2out);
1035 if (!dumbio && ofd2 == 1) setbuf(f2out, NULL);
1036 }
1037
1038 wnuma = wnumb = 0;
1039
1040}
1041
1042static uint32
1043read_uart(addr)
1044 uint32 addr;
1045{
1046
1047 unsigned tmp;
1048
1049 tmp = 0;
1050 switch (addr & 0xff) {
1051
1052 case 0xE0: /* UART 1 */
1053#ifndef _WIN32
1054#ifdef FAST_UART
1055
1056 if (aind < anum) {
1057 if ((aind + 1) < anum)
1058 mec_irq(4);
1059 return (0x700 | (uint32) aq[aind++]);
1060 } else {
1061 if (f1open) {
1062 anum = DO_STDIO_READ(ifd1, aq, UARTBUF);
1063 }
1064 if (anum > 0) {
1065 aind = 0;
1066 if ((aind + 1) < anum)
1067 mec_irq(4);
1068 return (0x700 | (uint32) aq[aind++]);
1069 } else {
1070 return (0x600 | (uint32) aq[aind]);
1071 }
1072
1073 }
1074#else
1075 tmp = uarta_data;
1076 uarta_data &= ~UART_DR;
1077 uart_stat_reg &= ~UARTA_DR;
1078 return tmp;
1079#endif
1080#else
5831e29b 1081 return 0;
c906108c
SS		 1082#endif
1083 break;
1084
1085 case 0xE4: /* UART 2 */
1086#ifndef _WIN32
1087#ifdef FAST_UART
1088 if (bind < bnum) {
1089 if ((bind + 1) < bnum)
1090 mec_irq(5);
1091 return (0x700 | (uint32) bq[bind++]);
1092 } else {
1093 if (f2open) {
1094 bnum = DO_STDIO_READ(ifd2, bq, UARTBUF);
1095 }
1096 if (bnum > 0) {
1097 bind = 0;
1098 if ((bind + 1) < bnum)
1099 mec_irq(5);
1100 return (0x700 | (uint32) bq[bind++]);
1101 } else {
1102 return (0x600 | (uint32) bq[bind]);
1103 }
1104
1105 }
1106#else
1107 tmp = uartb_data;
1108 uartb_data &= ~UART_DR;
1109 uart_stat_reg &= ~UARTB_DR;
1110 return tmp;
1111#endif
1112#else
5831e29b 1113 return 0;
c906108c
SS		 1114#endif
1115 break;
1116
1117 case 0xE8: /* UART status register */
1118#ifndef _WIN32
1119#ifdef FAST_UART
1120
1121 Ucontrol = 0;
1122 if (aind < anum) {
1123 Ucontrol |= 0x00000001;
1124 } else {
1125 if (f1open) {
1126 anum = DO_STDIO_READ(ifd1, aq, UARTBUF);
1127 }
1128 if (anum > 0) {
1129 Ucontrol |= 0x00000001;
1130 aind = 0;
1131 mec_irq(4);
1132 }
1133 }
1134 if (bind < bnum) {
1135 Ucontrol |= 0x00010000;
1136 } else {
1137 if (f2open) {
1138 bnum = DO_STDIO_READ(ifd2, bq, UARTBUF);
1139 }
1140 if (bnum > 0) {
1141 Ucontrol |= 0x00010000;
1142 bind = 0;
1143 mec_irq(5);
1144 }
1145 }
1146
1147 Ucontrol |= 0x00060006;
5831e29b 1148 return Ucontrol;
c906108c 1149#else
5831e29b 1150 return uart_stat_reg;
c906108c
SS		 1151#endif
1152#else
5831e29b 1153 return 0x00060006;
c906108c
SS		 1154#endif
1155 break;
1156 default:
1157 if (sis_verbose)
1158 printf("Read from unimplemented MEC register (%x)\n", addr);
1159
1160 }
5831e29b 1161 return 0;
c906108c
SS		 1162}
1163
1164static void
1165write_uart(addr, data)
1166 uint32 addr;
1167 uint32 data;
1168{
1169 unsigned char c;
1170
1171 c = (unsigned char) data;
1172 switch (addr & 0xff) {
1173
1174 case 0xE0: /* UART A */
1175#ifdef FAST_UART
1176 if (f1open) {
1177 if (wnuma < UARTBUF)
1178 wbufa[wnuma++] = c;
1179 else {
1180 while (wnuma)
1181 wnuma -= fwrite(wbufa, 1, wnuma, f1out);
1182 wbufa[wnuma++] = c;
1183 }
1184 }
1185 mec_irq(4);
1186#else
1187 if (uart_stat_reg & UARTA_SRE) {
1188 uarta_sreg = c;
1189 uart_stat_reg &= ~UARTA_SRE;
1190 event(uarta_tx, 0, UART_TX_TIME);
1191 } else {
1192 uarta_hreg = c;
1193 uart_stat_reg &= ~UARTA_HRE;
1194 }
1195#endif
1196 break;
1197
1198 case 0xE4: /* UART B */
1199#ifdef FAST_UART
1200 if (f2open) {
1201 if (wnumb < UARTBUF)
1202 wbufb[wnumb++] = c;
1203 else {
1204 while (wnumb)
1205 wnumb -= fwrite(wbufb, 1, wnumb, f2out);
1206 wbufb[wnumb++] = c;
1207 }
1208 }
1209 mec_irq(5);
1210#else
1211 if (uart_stat_reg & UARTB_SRE) {
1212 uartb_sreg = c;
1213 uart_stat_reg &= ~UARTB_SRE;
1214 event(uartb_tx, 0, UART_TX_TIME);
1215 } else {
1216 uartb_hreg = c;
1217 uart_stat_reg &= ~UARTB_HRE;
1218 }
1219#endif
1220 break;
1221 case 0xE8: /* UART status register */
1222#ifndef FAST_UART
1223 if (data & UARTA_CLR) {
1224 uart_stat_reg &= 0xFFFF0000;
1225 uart_stat_reg |= UARTA_SRE | UARTA_HRE;
1226 }
1227 if (data & UARTB_CLR) {
1228 uart_stat_reg &= 0x0000FFFF;
1229 uart_stat_reg |= UARTB_SRE | UARTB_HRE;
1230 }
1231#endif
1232 break;
1233 default:
1234 if (sis_verbose)
1235 printf("Write to unimplemented MEC register (%x)\n", addr);
1236
1237 }
1238}
1239
1240static void
1241flush_uart()
1242{
1243 while (wnuma && f1open)
1244 wnuma -= fwrite(wbufa, 1, wnuma, f1out);
1245 while (wnumb && f2open)
1246 wnumb -= fwrite(wbufb, 1, wnumb, f2out);
1247}
1248
1249
1250
1251static void
1252uarta_tx()
1253{
1254
1255 while (f1open && fwrite(&uarta_sreg, 1, 1, f1out) != 1);
1256 if (uart_stat_reg & UARTA_HRE) {
1257 uart_stat_reg |= UARTA_SRE;
1258 } else {
1259 uarta_sreg = uarta_hreg;
1260 uart_stat_reg |= UARTA_HRE;
1261 event(uarta_tx, 0, UART_TX_TIME);
1262 }
1263 mec_irq(4);
1264}
1265
1266static void
1267uartb_tx()
1268{
1269 while (f2open && fwrite(&uartb_sreg, 1, 1, f2out) != 1);
1270 if (uart_stat_reg & UARTB_HRE) {
1271 uart_stat_reg |= UARTB_SRE;
1272 } else {
1273 uartb_sreg = uartb_hreg;
1274 uart_stat_reg |= UARTB_HRE;
1275 event(uartb_tx, 0, UART_TX_TIME);
1276 }
1277 mec_irq(5);
1278}
1279
1280static void
1281uart_rx(arg)
1282 caddr_t arg;
1283{
1284 int32 rsize;
1285 char rxd;
1286
1287
1288 rsize = 0;
1289 if (f1open)
1290 rsize = DO_STDIO_READ(ifd1, &rxd, 1);
1291 if (rsize > 0) {
1292 uarta_data = UART_DR | rxd;
1293 if (uart_stat_reg & UARTA_HRE)
1294 uarta_data |= UART_THE;
1295 if (uart_stat_reg & UARTA_SRE)
1296 uarta_data |= UART_TSE;
1297 if (uart_stat_reg & UARTA_DR) {
1298 uart_stat_reg |= UARTA_OR;
1299 mec_irq(7); /* UART error interrupt */
1300 }
1301 uart_stat_reg |= UARTA_DR;
1302 mec_irq(4);
1303 }
1304 rsize = 0;
1305 if (f2open)
1306 rsize = DO_STDIO_READ(ifd2, &rxd, 1);
1307 if (rsize) {
1308 uartb_data = UART_DR | rxd;
1309 if (uart_stat_reg & UARTB_HRE)
1310 uartb_data |= UART_THE;
1311 if (uart_stat_reg & UARTB_SRE)
1312 uartb_data |= UART_TSE;
1313 if (uart_stat_reg & UARTB_DR) {
1314 uart_stat_reg |= UARTB_OR;
1315 mec_irq(7); /* UART error interrupt */
1316 }
1317 uart_stat_reg |= UARTB_DR;
1318 mec_irq(5);
1319 }
1320 event(uart_rx, 0, UART_RX_TIME);
1321}
1322
1323static void
1324uart_intr(arg)
1325 caddr_t arg;
1326{
1327 read_uart(0xE8); /* Check for UART interrupts every 1000 clk */
1328 flush_uart(); /* Flush UART ports */
1329 event(uart_intr, 0, UART_FLUSH_TIME);
1330}
1331
1332
1333static void
1334uart_irq_start()
1335{
1336#ifdef FAST_UART
1337 event(uart_intr, 0, UART_FLUSH_TIME);
1338#else
1339#ifndef _WIN32
1340 event(uart_rx, 0, UART_RX_TIME);
1341#endif
1342#endif
1343}
1344
1345/* Watch-dog */
1346
1347static void
1348wdog_intr(arg)
1349 caddr_t arg;
1350{
1351 if (wdog_status == disabled) {
1352 wdog_status = stopped;
1353 } else {
1354
1355 if (wdog_counter) {
1356 wdog_counter--;
1357 event(wdog_intr, 0, wdog_scaler + 1);
1358 } else {
1359 if (wdog_rston) {
1360 printf("Watchdog reset!\n");
1361 sys_reset();
1362 mec_ersr = 0xC000;
1363 } else {
1364 mec_irq(15);
1365 wdog_rston = 1;
1366 wdog_counter = wdog_rst_delay;
1367 event(wdog_intr, 0, wdog_scaler + 1);
1368 }
1369 }
1370 }
1371}
1372
1373static void
1374wdog_start()
1375{
1376 event(wdog_intr, 0, wdog_scaler + 1);
1377 if (sis_verbose)
1378 printf("Watchdog started, scaler = %d, counter = %d\n",
1379 wdog_scaler, wdog_counter);
1380}
1381
1382
1383/* MEC timers */
1384
1385
1386static void
1387rtc_intr(arg)
1388 caddr_t arg;
1389{
1390 if (rtc_counter == 0) {
1391
1392 mec_irq(13);
1393 if (rtc_cr)
1394 rtc_counter = rtc_reload;
1395 else
1396 rtc_se = 0;
1397 } else
1398 rtc_counter -= 1;
1399 if (rtc_se) {
1400 event(rtc_intr, 0, rtc_scaler + 1);
1401 rtc_scaler_start = now();
1402 rtc_enabled = 1;
1403 } else {
1404 if (sis_verbose)
1405 printf("RTC stopped\n\r");
1406 rtc_enabled = 0;
1407 }
1408}
1409
1410static void
1411rtc_start()
1412{
1413 if (sis_verbose)
1414 printf("RTC started (period %d)\n\r", rtc_scaler + 1);
1415 event(rtc_intr, 0, rtc_scaler + 1);
1416 rtc_scaler_start = now();
1417 rtc_enabled = 1;
1418}
1419
1420static uint32
1421rtc_counter_read()
1422{
5831e29b 1423 return rtc_counter;
c906108c
SS		 1424}
1425
1426static void
1427rtc_scaler_set(val)
1428 uint32 val;
1429{
1430 rtc_scaler = val & 0x0ff; /* eight-bit scaler only */
1431}
1432
1433static void
1434rtc_reload_set(val)
1435 uint32 val;
1436{
1437 rtc_reload = val;
1438}
1439
1440static void
1441gpt_intr(arg)
1442 caddr_t arg;
1443{
1444 if (gpt_counter == 0) {
1445 mec_irq(12);
1446 if (gpt_cr)
1447 gpt_counter = gpt_reload;
1448 else
1449 gpt_se = 0;
1450 } else
1451 gpt_counter -= 1;
1452 if (gpt_se) {
1453 event(gpt_intr, 0, gpt_scaler + 1);
1454 gpt_scaler_start = now();
1455 gpt_enabled = 1;
1456 } else {
1457 if (sis_verbose)
1458 printf("GPT stopped\n\r");
1459 gpt_enabled = 0;
1460 }
1461}
1462
1463static void
1464gpt_start()
1465{
1466 if (sis_verbose)
1467 printf("GPT started (period %d)\n\r", gpt_scaler + 1);
1468 event(gpt_intr, 0, gpt_scaler + 1);
1469 gpt_scaler_start = now();
1470 gpt_enabled = 1;
1471}
1472
1473static uint32
1474gpt_counter_read()
1475{
5831e29b 1476 return gpt_counter;
c906108c
SS		 1477}
1478
1479static void
1480gpt_scaler_set(val)
1481 uint32 val;
1482{
1483 gpt_scaler = val & 0x0ffff; /* 16-bit scaler */
1484}
1485
1486static void
1487gpt_reload_set(val)
1488 uint32 val;
1489{
1490 gpt_reload = val;
1491}
1492
1493static void
1494timer_ctrl(val)
1495 uint32 val;
1496{
1497
1498 rtc_cr = ((val & TCR_TCRCR) != 0);
1499 if (val & TCR_TCRCL) {
1500 rtc_counter = rtc_reload;
1501 }
1502 if (val & TCR_TCRSL) {
1503 }
1504 rtc_se = ((val & TCR_TCRSE) != 0);
1505 if (rtc_se && (rtc_enabled == 0))
1506 rtc_start();
1507
1508 gpt_cr = (val & TCR_GACR);
1509 if (val & TCR_GACL) {
1510 gpt_counter = gpt_reload;
1511 }
1512 if (val & TCR_GACL) {
1513 }
1514 gpt_se = (val & TCR_GASE) >> 2;
1515 if (gpt_se && (gpt_enabled == 0))
1516 gpt_start();
1517}
1518
d3e9b40a
JG		 1519/* Store data in host byte order. MEM points to the beginning of the
1520 emulated memory; WADDR contains the index the emulated memory,
1521 DATA points to words in host byte order to be stored. SZ contains log(2)
1522 of the number of bytes to retrieve, and can be 0 (1 byte), 1 (one half-word),
1523 2 (one word), or 3 (two words); WS should return the number of
1524 wait-states. */
c906108c
SS		 1525
1526static void
d3e9b40a
JG		 1527store_bytes (unsigned char *mem, uint32 waddr, uint32 *data, int32 sz,
1528 int32 *ws)
c906108c 1529{
d3e9b40a 1530 switch (sz) {
c906108c 1531 case 0:
d3e9b40a
JG		 1532 waddr ^= EBT;
1533 mem[waddr] = *data & 0x0ff;
1534 *ws = mem_ramw_ws + 3;
c906108c
SS		 1535 break;
1536 case 1:
d3e9b40a
JG		 1537#ifdef HOST_LITTLE_ENDIAN
1538 waddr ^= 2;
1539#endif
1540 memcpy (&mem[waddr], data, 2);
1541 *ws = mem_ramw_ws + 3;
c906108c 1542 break;
c906108c 1543 case 2:
d3e9b40a
JG		 1544 memcpy (&mem[waddr], data, 4);
1545 *ws = mem_ramw_ws;
c906108c 1546 break;
c906108c 1547 case 3:
d3e9b40a
JG		 1548 memcpy (&mem[waddr], data, 8);
1549 *ws = 2 * mem_ramw_ws + STD_WS;
c906108c 1550 break;
c906108c
SS		 1551 }
1552}
1553
1554
1555/* Memory emulation */
1556
102b920e
JG		 1557int
1558memory_iread (uint32 addr, uint32 *data, int32 *ws)
1559{
1560 uint32 asi;
1561 if ((addr >= mem_ramstart) && (addr < (mem_ramstart + mem_ramsz))) {
1562 memcpy (data, &ramb[addr & mem_rammask & ~3], 4);
1563 *ws = mem_ramr_ws;
1564 return 0;
1565 } else if (addr < mem_romsz) {
1566 memcpy (data, &romb[addr & ~3], 4);
1567 *ws = mem_romr_ws;
1568 return 0;
1569 }
1570
1571 if (sis_verbose)
1572 printf ("Memory exception at %x (illegal address)\n", addr);
1573 if (sregs.psr & 0x080)
1574 asi = 9;
1575 else
1576 asi = 8;
1577 set_sfsr (UIMP_ACC, addr, asi, 1);
1578 *ws = MEM_EX_WS;
1579 return 1;
1580}
1581
c906108c
SS		 1582int
1583memory_read(asi, addr, data, sz, ws)
1584 int32 asi;
1585 uint32 addr;
1586 uint32 *data;
1587 int32 sz;
1588 int32 *ws;
1589{
1590 int32 mexc;
1591
1592#ifdef ERRINJ
1593 if (errmec) {
1594 if (sis_verbose)
1595 printf("Inserted MEC error %d\n",errmec);
1596 set_sfsr(errmec, addr, asi, 1);
1597 if (errmec == 5) mecparerror();
1598 if (errmec == 6) iucomperr();
1599 errmec = 0;
5831e29b 1600 return 1;
c906108c 1601 }
d68c23cd 1602#endif
c906108c
SS		 1603
1604 if ((addr >= mem_ramstart) && (addr < (mem_ramstart + mem_ramsz))) {
d3e9b40a 1605 memcpy (data, &ramb[addr & mem_rammask & ~3], 4);
c906108c 1606 *ws = mem_ramr_ws;
5831e29b 1607 return 0;
c906108c
SS		 1608 } else if ((addr >= MEC_START) && (addr < MEC_END)) {
1609 mexc = mec_read(addr, asi, data);
1610 if (mexc) {
1611 set_sfsr(MEC_ACC, addr, asi, 1);
1612 *ws = MEM_EX_WS;
1613 } else {
1614 *ws = 0;
1615 }
5831e29b 1616 return mexc;
c906108c
SS		 1617
1618#ifdef ERA
1619
1620 } else if (era) {
1621 if ((addr < 0x100000) ||
1622 ((addr>= 0x80000000) && (addr < 0x80100000))) {
d3e9b40a 1623 memcpy (data, &romb[addr & ROM_MASK & ~3], 4);
c906108c 1624 *ws = 4;
5831e29b 1625 return 0;
c906108c
SS		 1626 } else if ((addr >= 0x10000000) &&
1627 (addr < (0x10000000 + (512 << (mec_iocr & 0x0f)))) &&
1628 (mec_iocr & 0x10)) {
1629 *data = erareg;
5831e29b 1630 return 0;
c906108c
SS		 1631 }
1632
1633 } else if (addr < mem_romsz) {
d3e9b40a
JG		 1634 memcpy (data, &romb[addr & ~3], 4);
1635 *ws = mem_romr_ws;
1636 return 0;
c906108c
SS		 1637#else
1638 } else if (addr < mem_romsz) {
d3e9b40a 1639 memcpy (data, &romb[addr & ~3], 4);
c906108c 1640 *ws = mem_romr_ws;
5831e29b 1641 return 0;
c906108c
SS		 1642#endif
1643
1644 }
1645
102b920e
JG		 1646 if (sis_verbose)
1647 printf ("Memory exception at %x (illegal address)\n", addr);
c906108c
SS		 1648 set_sfsr(UIMP_ACC, addr, asi, 1);
1649 *ws = MEM_EX_WS;
5831e29b 1650 return 1;
c906108c
SS		 1651}
1652
1653int
1654memory_write(asi, addr, data, sz, ws)
1655 int32 asi;
1656 uint32 addr;
1657 uint32 *data;
1658 int32 sz;
1659 int32 *ws;
1660{
1661 uint32 byte_addr;
1662 uint32 byte_mask;
1663 uint32 waddr;
1664 uint32 *ram;
1665 int32 mexc;
1666 int i;
1667 int wphit[2];
1668
1669#ifdef ERRINJ
1670 if (errmec) {
1671 if (sis_verbose)
1672 printf("Inserted MEC error %d\n",errmec);
1673 set_sfsr(errmec, addr, asi, 0);
1674 if (errmec == 5) mecparerror();
1675 if (errmec == 6) iucomperr();
1676 errmec = 0;
5831e29b 1677 return 1;
c906108c 1678 }
d68c23cd 1679#endif
c906108c
SS		 1680
1681 if ((addr >= mem_ramstart) && (addr < (mem_ramstart + mem_ramsz))) {
1682 if (mem_accprot) {
1683
1684 waddr = (addr & 0x7fffff) >> 2;
1685 for (i = 0; i < 2; i++)
1686 wphit[i] =
1687 (((asi == 0xa) && (mec_wpr[i] & 1)) ||
1688 ((asi == 0xb) && (mec_wpr[i] & 2))) &&
1689 ((waddr >= mec_ssa[i]) && ((waddr | (sz == 3)) < mec_sea[i]));
1690
1691 if (((mem_blockprot) && (wphit[0] || wphit[1])) ||
1692 ((!mem_blockprot) &&
1693 !((mec_wpr[0] && wphit[0]) || (mec_wpr[1] && wphit[1]))
1694 )) {
1695 if (sis_verbose)
1696 printf("Memory access protection error at 0x%08x\n", addr);
1697 set_sfsr(PROT_EXC, addr, asi, 0);
1698 *ws = MEM_EX_WS;
5831e29b 1699 return 1;
c906108c
SS		 1700 }
1701 }
d3e9b40a
JG		 1702 waddr = addr & mem_rammask;
1703 store_bytes (ramb, waddr, data, sz, ws);
5831e29b 1704 return 0;
c906108c
SS		 1705 } else if ((addr >= MEC_START) && (addr < MEC_END)) {
1706 if ((sz != 2) || (asi != 0xb)) {
1707 set_sfsr(MEC_ACC, addr, asi, 0);
1708 *ws = MEM_EX_WS;
5831e29b 1709 return 1;
c906108c
SS		 1710 }
1711 mexc = mec_write(addr, *data);
1712 if (mexc) {
1713 set_sfsr(MEC_ACC, addr, asi, 0);
1714 *ws = MEM_EX_WS;
1715 } else {
1716 *ws = 0;
1717 }
5831e29b 1718 return mexc;
c906108c
SS		 1719
1720#ifdef ERA
1721
1722 } else if (era) {
1723 if ((erareg & 2) &&
1724 ((addr < 0x100000) || ((addr >= 0x80000000) && (addr < 0x80100000)))) {
1725 addr &= ROM_MASK;
1726 *ws = sz == 3 ? 8 : 4;
d3e9b40a 1727 store_bytes (romb, addr, data, sz, ws);
5831e29b 1728 return 0;
c906108c
SS		 1729 } else if ((addr >= 0x10000000) &&
1730 (addr < (0x10000000 + (512 << (mec_iocr & 0x0f)))) &&
1731 (mec_iocr & 0x10)) {
1732 erareg = *data & 0x0e;
5831e29b 1733 return 0;
c906108c
SS		 1734 }
1735
1736 } else if ((addr < mem_romsz) && (mec_memcfg & 0x10000) && (wrp) &&
1737 (((mec_memcfg & 0x20000) && (sz > 1)) ||
1738 (!(mec_memcfg & 0x20000) && (sz == 0)))) {
1739
1740 *ws = mem_romw_ws + 1;
1741 if (sz == 3)
1742 *ws += mem_romw_ws + STD_WS;
d3e9b40a 1743 store_bytes (romb, addr, data, sz, ws);
5831e29b 1744 return 0;
c906108c
SS		 1745
1746#else
1747 } else if ((addr < mem_romsz) && (mec_memcfg & 0x10000) && (wrp) &&
1748 (((mec_memcfg & 0x20000) && (sz > 1)) ||
1749 (!(mec_memcfg & 0x20000) && (sz == 0)))) {
1750
1751 *ws = mem_romw_ws + 1;
1752 if (sz == 3)
1753 *ws += mem_romw_ws + STD_WS;
d3e9b40a 1754 store_bytes (romb, addr, data, sz, ws);
5831e29b 1755 return 0;
c906108c
SS		 1756
1757#endif
1758
1759 }
1760
1761 *ws = MEM_EX_WS;
1762 set_sfsr(UIMP_ACC, addr, asi, 0);
5831e29b 1763 return 1;
c906108c
SS		 1764}
1765
1766static unsigned char *
1767get_mem_ptr(addr, size)
1768 uint32 addr;
1769 uint32 size;
1770{
1771 if ((addr + size) < ROM_SZ) {
5831e29b 1772 return &romb[addr];
c906108c 1773 } else if ((addr >= mem_ramstart) && ((addr + size) < mem_ramend)) {
5831e29b 1774 return &ramb[addr & mem_rammask];
c906108c
SS		 1775 }
1776
1777#ifdef ERA
1778 else if ((era) && ((addr <0x100000) ||
1779 ((addr >= (unsigned) 0x80000000) && ((addr + size) < (unsigned) 0x80100000)))) {
5831e29b 1780 return &romb[addr & ROM_MASK];
c906108c
SS		 1781 }
1782#endif
1783
5831e29b 1784 return (char *) -1;
c906108c
SS		 1785}
1786
1787int
1788sis_memory_write(addr, data, length)
94110024
JS		 1789 uint32 addr;
1790 const unsigned char *data;
1791 uint32 length;
c906108c
SS		 1792{
1793 char *mem;
1794
1795 if ((mem = get_mem_ptr(addr, length)) == ((char *) -1))
5831e29b 1796 return 0;
c906108c
SS		 1797
1798 memcpy(mem, data, length);
5831e29b 1799 return length;
c906108c
SS		 1800}
1801
1802int
1803sis_memory_read(addr, data, length)
1804 uint32 addr;
1805 char *data;
1806 uint32 length;
1807{
1808 char *mem;
1809
1810 if ((mem = get_mem_ptr(addr, length)) == ((char *) -1))
5831e29b 1811 return 0;
c906108c
SS		 1812
1813 memcpy(data, mem, length);
5831e29b 1814 return length;
c906108c 1815}
20a0ffe3
JG		 1816
1817extern struct pstate sregs;
1818
1819void
1820boot_init (void)
1821{
1822 mec_write(MEC_WCR, 0); /* zero waitstates */
1823 mec_write(MEC_TRAPD, 0); /* turn off watch-dog */
1824 mec_write(MEC_RTC_SCALER, sregs.freq - 1); /* generate 1 MHz RTC tick */
1825 mec_write(MEC_MEMCFG, (3 << 18) | (4 << 10)); /* 1 MB ROM, 4 MB RAM */
1826 sregs.wim = 2;
1827 sregs.psr = 0x110010e0;
1828 sregs.r[30] = RAM_END;
1829 sregs.r[14] = sregs.r[30] - 96 * 4;
1830 mec_mcr |= 1; /* power-down enabled */
1831}
GDB Binutils - Deliverables
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