Commit | Line | Data |
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296730a5 MF |
1 | /* This file is part of SIS (SPARC instruction simulator) |
2 | ||
61baf725 | 3 | Copyright (C) 1995-2017 Free Software Foundation, Inc. |
296730a5 | 4 | Contributed by Jiri Gaisler, European Space Agency |
17d88f73 JB |
5 | |
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 3 of the License, or | |
9 | (at your option) any later version. | |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
c906108c SS |
18 | |
19 | /* The control space devices */ | |
20 | ||
5272643f | 21 | #include "config.h" |
c906108c SS |
22 | #include <sys/types.h> |
23 | #include <stdio.h> | |
d68c23cd | 24 | #include <string.h> |
c906108c SS |
25 | #include <termios.h> |
26 | #include <sys/fcntl.h> | |
27 | #include <sys/file.h> | |
28 | #include <unistd.h> | |
29 | #include "sis.h" | |
c906108c SS |
30 | #include "sim-config.h" |
31 | ||
32 | extern int ctrl_c; | |
33 | extern int32 sis_verbose; | |
34 | extern int32 sparclite, sparclite_board; | |
35 | extern int rom8,wrp,uben; | |
36 | extern char uart_dev1[], uart_dev2[]; | |
37 | ||
38 | int dumbio = 0; /* normal, smart, terminal oriented IO by default */ | |
39 | ||
40 | /* MEC registers */ | |
41 | #define MEC_START 0x01f80000 | |
42 | #define MEC_END 0x01f80100 | |
43 | ||
44 | /* Memory exception waitstates */ | |
45 | #define MEM_EX_WS 1 | |
46 | ||
47 | /* ERC32 always adds one waitstate during RAM std */ | |
48 | #define STD_WS 1 | |
49 | ||
50 | #ifdef ERRINJ | |
51 | extern int errmec; | |
52 | #endif | |
53 | ||
c906108c SS |
54 | #define MEC_WS 0 /* Waitstates per MEC access (0 ws) */ |
55 | #define MOK 0 | |
56 | ||
57 | /* MEC register addresses */ | |
58 | ||
59 | #define MEC_MCR 0x000 | |
60 | #define MEC_SFR 0x004 | |
61 | #define MEC_PWDR 0x008 | |
62 | #define MEC_MEMCFG 0x010 | |
63 | #define MEC_IOCR 0x014 | |
64 | #define MEC_WCR 0x018 | |
65 | ||
66 | #define MEC_MAR0 0x020 | |
67 | #define MEC_MAR1 0x024 | |
68 | ||
69 | #define MEC_SSA1 0x020 | |
70 | #define MEC_SEA1 0x024 | |
71 | #define MEC_SSA2 0x028 | |
72 | #define MEC_SEA2 0x02C | |
73 | #define MEC_ISR 0x044 | |
74 | #define MEC_IPR 0x048 | |
75 | #define MEC_IMR 0x04C | |
76 | #define MEC_ICR 0x050 | |
77 | #define MEC_IFR 0x054 | |
78 | #define MEC_WDOG 0x060 | |
79 | #define MEC_TRAPD 0x064 | |
80 | #define MEC_RTC_COUNTER 0x080 | |
81 | #define MEC_RTC_RELOAD 0x080 | |
82 | #define MEC_RTC_SCALER 0x084 | |
83 | #define MEC_GPT_COUNTER 0x088 | |
84 | #define MEC_GPT_RELOAD 0x088 | |
85 | #define MEC_GPT_SCALER 0x08C | |
86 | #define MEC_TIMER_CTRL 0x098 | |
87 | #define MEC_SFSR 0x0A0 | |
88 | #define MEC_FFAR 0x0A4 | |
89 | #define MEC_ERSR 0x0B0 | |
90 | #define MEC_DBG 0x0C0 | |
91 | #define MEC_TCR 0x0D0 | |
92 | ||
93 | #define MEC_BRK 0x0C4 | |
94 | #define MEC_WPR 0x0C8 | |
95 | ||
96 | #define MEC_UARTA 0x0E0 | |
97 | #define MEC_UARTB 0x0E4 | |
98 | #define MEC_UART_CTRL 0x0E8 | |
99 | #define SIM_LOAD 0x0F0 | |
100 | ||
101 | /* Memory exception causes */ | |
102 | #define PROT_EXC 0x3 | |
103 | #define UIMP_ACC 0x4 | |
104 | #define MEC_ACC 0x6 | |
105 | #define WATCH_EXC 0xa | |
106 | #define BREAK_EXC 0xb | |
107 | ||
108 | /* Size of UART buffers (bytes) */ | |
109 | #define UARTBUF 1024 | |
110 | ||
111 | /* Number of simulator ticks between flushing the UARTS. */ | |
112 | /* For good performance, keep above 1000 */ | |
113 | #define UART_FLUSH_TIME 3000 | |
114 | ||
115 | /* MEC timer control register bits */ | |
116 | #define TCR_GACR 1 | |
117 | #define TCR_GACL 2 | |
118 | #define TCR_GASE 4 | |
119 | #define TCR_GASL 8 | |
120 | #define TCR_TCRCR 0x100 | |
121 | #define TCR_TCRCL 0x200 | |
122 | #define TCR_TCRSE 0x400 | |
123 | #define TCR_TCRSL 0x800 | |
124 | ||
125 | /* New uart defines */ | |
126 | #define UART_TX_TIME 1000 | |
127 | #define UART_RX_TIME 1000 | |
128 | #define UARTA_DR 0x1 | |
129 | #define UARTA_SRE 0x2 | |
130 | #define UARTA_HRE 0x4 | |
131 | #define UARTA_OR 0x40 | |
132 | #define UARTA_CLR 0x80 | |
133 | #define UARTB_DR 0x10000 | |
134 | #define UARTB_SRE 0x20000 | |
135 | #define UARTB_HRE 0x40000 | |
136 | #define UARTB_OR 0x400000 | |
137 | #define UARTB_CLR 0x800000 | |
138 | ||
139 | #define UART_DR 0x100 | |
140 | #define UART_TSE 0x200 | |
141 | #define UART_THE 0x400 | |
142 | ||
143 | /* MEC registers */ | |
144 | ||
145 | static char fname[256]; | |
146 | static int32 find = 0; | |
147 | static uint32 mec_ssa[2]; /* Write protection start address */ | |
148 | static uint32 mec_sea[2]; /* Write protection end address */ | |
149 | static uint32 mec_wpr[2]; /* Write protection control fields */ | |
150 | static uint32 mec_sfsr; | |
151 | static uint32 mec_ffar; | |
152 | static uint32 mec_ipr; | |
153 | static uint32 mec_imr; | |
154 | static uint32 mec_isr; | |
155 | static uint32 mec_icr; | |
156 | static uint32 mec_ifr; | |
157 | static uint32 mec_mcr; /* MEC control register */ | |
158 | static uint32 mec_memcfg; /* Memory control register */ | |
159 | static uint32 mec_wcr; /* MEC waitstate register */ | |
160 | static uint32 mec_iocr; /* MEC IO control register */ | |
161 | static uint32 posted_irq; | |
162 | static uint32 mec_ersr; /* MEC error and status register */ | |
163 | static uint32 mec_tcr; /* MEC test comtrol register */ | |
164 | ||
165 | static uint32 rtc_counter; | |
166 | static uint32 rtc_reload; | |
167 | static uint32 rtc_scaler; | |
168 | static uint32 rtc_scaler_start; | |
169 | static uint32 rtc_enabled; | |
170 | static uint32 rtc_cr; | |
171 | static uint32 rtc_se; | |
172 | ||
173 | static uint32 gpt_counter; | |
174 | static uint32 gpt_reload; | |
175 | static uint32 gpt_scaler; | |
176 | static uint32 gpt_scaler_start; | |
177 | static uint32 gpt_enabled; | |
178 | static uint32 gpt_cr; | |
179 | static uint32 gpt_se; | |
180 | ||
181 | static uint32 wdog_scaler; | |
182 | static uint32 wdog_counter; | |
183 | static uint32 wdog_rst_delay; | |
184 | static uint32 wdog_rston; | |
185 | ||
186 | enum wdog_type { | |
187 | init, disabled, enabled, stopped | |
188 | }; | |
189 | ||
190 | static enum wdog_type wdog_status; | |
191 | ||
192 | ||
193 | /* ROM size 1024 Kbyte */ | |
194 | #define ROM_SZ 0x100000 | |
195 | #define ROM_MASK 0x0fffff | |
196 | ||
197 | /* RAM size 4 Mbyte */ | |
198 | #define RAM_START 0x02000000 | |
199 | #define RAM_END 0x02400000 | |
200 | #define RAM_MASK 0x003fffff | |
201 | ||
202 | /* SPARClite boards all seem to have RAM at the same place. */ | |
203 | #define RAM_START_SLITE 0x40000000 | |
204 | #define RAM_END_SLITE 0x40400000 | |
205 | #define RAM_MASK_SLITE 0x003fffff | |
206 | ||
207 | /* Memory support variables */ | |
208 | ||
209 | static uint32 mem_ramr_ws; /* RAM read waitstates */ | |
210 | static uint32 mem_ramw_ws; /* RAM write waitstates */ | |
211 | static uint32 mem_romr_ws; /* ROM read waitstates */ | |
212 | static uint32 mem_romw_ws; /* ROM write waitstates */ | |
213 | static uint32 mem_ramstart; /* RAM start */ | |
214 | static uint32 mem_ramend; /* RAM end */ | |
215 | static uint32 mem_rammask; /* RAM address mask */ | |
216 | static uint32 mem_ramsz; /* RAM size */ | |
217 | static uint32 mem_romsz; /* ROM size */ | |
218 | static uint32 mem_accprot; /* RAM write protection enabled */ | |
219 | static uint32 mem_blockprot; /* RAM block write protection enabled */ | |
220 | ||
221 | static unsigned char romb[ROM_SZ]; | |
222 | static unsigned char ramb[RAM_END - RAM_START]; | |
223 | ||
224 | ||
225 | /* UART support variables */ | |
226 | ||
227 | static int32 fd1, fd2; /* file descriptor for input file */ | |
228 | static int32 Ucontrol; /* UART status register */ | |
229 | static unsigned char aq[UARTBUF], bq[UARTBUF]; | |
230 | static int32 anum, aind = 0; | |
231 | static int32 bnum, bind = 0; | |
232 | static char wbufa[UARTBUF], wbufb[UARTBUF]; | |
233 | static unsigned wnuma; | |
234 | static unsigned wnumb; | |
235 | static FILE *f1in, *f1out, *f2in, *f2out; | |
236 | static struct termios ioc1, ioc2, iocold1, iocold2; | |
237 | static int f1open = 0, f2open = 0; | |
238 | ||
239 | static char uarta_sreg, uarta_hreg, uartb_sreg, uartb_hreg; | |
240 | static uint32 uart_stat_reg; | |
241 | static uint32 uarta_data, uartb_data; | |
242 | ||
243 | #ifdef ERA | |
244 | int era = 0; | |
245 | int erareg; | |
246 | #endif | |
247 | ||
248 | /* Forward declarations */ | |
249 | ||
bdca5ee4 | 250 | static void decode_ersr (void); |
c906108c | 251 | #ifdef ERRINJ |
bdca5ee4 | 252 | static void iucomperr (void); |
c906108c | 253 | #endif |
bdca5ee4 TT |
254 | static void mecparerror (void); |
255 | static void decode_memcfg (void); | |
256 | static void decode_wcr (void); | |
257 | static void decode_mcr (void); | |
258 | static void close_port (void); | |
259 | static void mec_reset (void); | |
260 | static void mec_intack (int32 level); | |
261 | static void chk_irq (void); | |
262 | static void mec_irq (int32 level); | |
263 | static void set_sfsr (uint32 fault, uint32 addr, | |
264 | uint32 asi, uint32 read); | |
265 | static int32 mec_read (uint32 addr, uint32 asi, uint32 *data); | |
266 | static int mec_write (uint32 addr, uint32 data); | |
267 | static void port_init (void); | |
268 | static uint32 read_uart (uint32 addr); | |
269 | static void write_uart (uint32 addr, uint32 data); | |
270 | static void flush_uart (void); | |
271 | static void uarta_tx (void); | |
272 | static void uartb_tx (void); | |
273 | static void uart_rx (caddr_t arg); | |
274 | static void uart_intr (caddr_t arg); | |
275 | static void uart_irq_start (void); | |
276 | static void wdog_intr (caddr_t arg); | |
277 | static void wdog_start (void); | |
278 | static void rtc_intr (caddr_t arg); | |
279 | static void rtc_start (void); | |
280 | static uint32 rtc_counter_read (void); | |
281 | static void rtc_scaler_set (uint32 val); | |
282 | static void rtc_reload_set (uint32 val); | |
283 | static void gpt_intr (caddr_t arg); | |
284 | static void gpt_start (void); | |
285 | static uint32 gpt_counter_read (void); | |
286 | static void gpt_scaler_set (uint32 val); | |
287 | static void gpt_reload_set (uint32 val); | |
288 | static void timer_ctrl (uint32 val); | |
c906108c | 289 | static unsigned char * |
bdca5ee4 | 290 | get_mem_ptr (uint32 addr, uint32 size); |
d3e9b40a JG |
291 | static void store_bytes (unsigned char *mem, uint32 waddr, |
292 | uint32 *data, int sz, int32 *ws); | |
c906108c SS |
293 | |
294 | extern int ext_irl; | |
295 | ||
296 | ||
297 | /* One-time init */ | |
298 | ||
299 | void | |
300 | init_sim() | |
301 | { | |
302 | port_init(); | |
303 | } | |
304 | ||
305 | /* Power-on reset init */ | |
306 | ||
307 | void | |
308 | reset() | |
309 | { | |
310 | mec_reset(); | |
311 | uart_irq_start(); | |
312 | wdog_start(); | |
313 | } | |
314 | ||
315 | static void | |
316 | decode_ersr() | |
317 | { | |
318 | if (mec_ersr & 0x01) { | |
319 | if (!(mec_mcr & 0x20)) { | |
320 | if (mec_mcr & 0x40) { | |
321 | sys_reset(); | |
322 | mec_ersr = 0x8000; | |
323 | if (sis_verbose) | |
324 | printf("Error manager reset - IU in error mode\n"); | |
325 | } else { | |
326 | sys_halt(); | |
327 | mec_ersr |= 0x2000; | |
328 | if (sis_verbose) | |
329 | printf("Error manager halt - IU in error mode\n"); | |
330 | } | |
331 | } else | |
332 | mec_irq(1); | |
333 | } | |
334 | if (mec_ersr & 0x04) { | |
335 | if (!(mec_mcr & 0x200)) { | |
336 | if (mec_mcr & 0x400) { | |
337 | sys_reset(); | |
338 | mec_ersr = 0x8000; | |
339 | if (sis_verbose) | |
340 | printf("Error manager reset - IU comparison error\n"); | |
341 | } else { | |
342 | sys_halt(); | |
343 | mec_ersr |= 0x2000; | |
344 | if (sis_verbose) | |
345 | printf("Error manager halt - IU comparison error\n"); | |
346 | } | |
347 | } else | |
348 | mec_irq(1); | |
349 | } | |
350 | if (mec_ersr & 0x20) { | |
351 | if (!(mec_mcr & 0x2000)) { | |
352 | if (mec_mcr & 0x4000) { | |
353 | sys_reset(); | |
354 | mec_ersr = 0x8000; | |
355 | if (sis_verbose) | |
356 | printf("Error manager reset - MEC hardware error\n"); | |
357 | } else { | |
358 | sys_halt(); | |
359 | mec_ersr |= 0x2000; | |
360 | if (sis_verbose) | |
361 | printf("Error manager halt - MEC hardware error\n"); | |
362 | } | |
363 | } else | |
364 | mec_irq(1); | |
365 | } | |
366 | } | |
367 | ||
368 | #ifdef ERRINJ | |
369 | static void | |
370 | iucomperr() | |
371 | { | |
372 | mec_ersr |= 0x04; | |
373 | decode_ersr(); | |
374 | } | |
375 | #endif | |
376 | ||
377 | static void | |
378 | mecparerror() | |
379 | { | |
380 | mec_ersr |= 0x20; | |
381 | decode_ersr(); | |
382 | } | |
383 | ||
384 | ||
385 | /* IU error mode manager */ | |
386 | ||
387 | void | |
388 | error_mode(pc) | |
389 | uint32 pc; | |
390 | { | |
391 | ||
392 | mec_ersr |= 0x1; | |
393 | decode_ersr(); | |
394 | } | |
395 | ||
396 | ||
397 | /* Check memory settings */ | |
398 | ||
399 | static void | |
400 | decode_memcfg() | |
401 | { | |
402 | if (rom8) mec_memcfg &= ~0x20000; | |
403 | else mec_memcfg |= 0x20000; | |
404 | ||
405 | mem_ramsz = (256 * 1024) << ((mec_memcfg >> 10) & 7); | |
406 | mem_romsz = (128 * 1024) << ((mec_memcfg >> 18) & 7); | |
407 | ||
408 | if (sparclite_board) { | |
409 | mem_ramstart = RAM_START_SLITE; | |
410 | mem_ramend = RAM_END_SLITE; | |
411 | mem_rammask = RAM_MASK_SLITE; | |
412 | } | |
413 | else { | |
414 | mem_ramstart = RAM_START; | |
415 | mem_ramend = RAM_END; | |
416 | mem_rammask = RAM_MASK; | |
417 | } | |
418 | if (sis_verbose) | |
419 | printf("RAM start: 0x%x, RAM size: %d K, ROM size: %d K\n", | |
420 | mem_ramstart, mem_ramsz >> 10, mem_romsz >> 10); | |
421 | } | |
422 | ||
423 | static void | |
424 | decode_wcr() | |
425 | { | |
426 | mem_ramr_ws = mec_wcr & 3; | |
427 | mem_ramw_ws = (mec_wcr >> 2) & 3; | |
428 | mem_romr_ws = (mec_wcr >> 4) & 0x0f; | |
429 | if (rom8) { | |
430 | if (mem_romr_ws > 0 ) mem_romr_ws--; | |
431 | mem_romr_ws = 5 + (4*mem_romr_ws); | |
432 | } | |
433 | mem_romw_ws = (mec_wcr >> 8) & 0x0f; | |
434 | if (sis_verbose) | |
435 | printf("Waitstates = RAM read: %d, RAM write: %d, ROM read: %d, ROM write: %d\n", | |
436 | mem_ramr_ws, mem_ramw_ws, mem_romr_ws, mem_romw_ws); | |
437 | } | |
438 | ||
439 | static void | |
440 | decode_mcr() | |
441 | { | |
442 | mem_accprot = (mec_wpr[0] | mec_wpr[1]); | |
443 | mem_blockprot = (mec_mcr >> 3) & 1; | |
444 | if (sis_verbose && mem_accprot) | |
445 | printf("Memory block write protection enabled\n"); | |
446 | if (mec_mcr & 0x08000) { | |
447 | mec_ersr |= 0x20; | |
448 | decode_ersr(); | |
449 | } | |
450 | if (sis_verbose && (mec_mcr & 2)) | |
451 | printf("Software reset enabled\n"); | |
452 | if (sis_verbose && (mec_mcr & 1)) | |
453 | printf("Power-down mode enabled\n"); | |
454 | } | |
455 | ||
456 | /* Flush ports when simulator stops */ | |
457 | ||
458 | void | |
459 | sim_halt() | |
460 | { | |
461 | #ifdef FAST_UART | |
462 | flush_uart(); | |
463 | #endif | |
464 | } | |
465 | ||
466 | int | |
467 | sim_stop(SIM_DESC sd) | |
468 | { | |
469 | ctrl_c = 1; | |
470 | return 1; | |
471 | } | |
472 | ||
473 | static void | |
474 | close_port() | |
475 | { | |
476 | if (f1open && f1in != stdin) | |
477 | fclose(f1in); | |
478 | if (f2open && f2in != stdin) | |
479 | fclose(f2in); | |
480 | } | |
481 | ||
482 | void | |
483 | exit_sim() | |
484 | { | |
485 | close_port(); | |
486 | } | |
487 | ||
488 | static void | |
489 | mec_reset() | |
490 | { | |
491 | int i; | |
492 | ||
493 | find = 0; | |
494 | for (i = 0; i < 2; i++) | |
495 | mec_ssa[i] = mec_sea[i] = mec_wpr[i] = 0; | |
496 | mec_mcr = 0x01350014; | |
497 | mec_iocr = 0; | |
498 | mec_sfsr = 0x078; | |
499 | mec_ffar = 0; | |
500 | mec_ipr = 0; | |
501 | mec_imr = 0x7ffe; | |
502 | mec_isr = 0; | |
503 | mec_icr = 0; | |
504 | mec_ifr = 0; | |
505 | mec_memcfg = 0x10000; | |
506 | mec_wcr = -1; | |
507 | mec_ersr = 0; /* MEC error and status register */ | |
508 | mec_tcr = 0; /* MEC test comtrol register */ | |
509 | ||
510 | decode_memcfg(); | |
511 | decode_wcr(); | |
512 | decode_mcr(); | |
513 | ||
514 | posted_irq = 0; | |
515 | wnuma = wnumb = 0; | |
516 | anum = aind = bnum = bind = 0; | |
517 | ||
518 | uart_stat_reg = UARTA_SRE | UARTA_HRE | UARTB_SRE | UARTB_HRE; | |
519 | uarta_data = uartb_data = UART_THE | UART_TSE; | |
520 | ||
521 | rtc_counter = 0xffffffff; | |
522 | rtc_reload = 0xffffffff; | |
523 | rtc_scaler = 0xff; | |
524 | rtc_enabled = 0; | |
525 | rtc_cr = 0; | |
526 | rtc_se = 0; | |
527 | ||
528 | gpt_counter = 0xffffffff; | |
529 | gpt_reload = 0xffffffff; | |
530 | gpt_scaler = 0xffff; | |
531 | gpt_enabled = 0; | |
532 | gpt_cr = 0; | |
533 | gpt_se = 0; | |
534 | ||
535 | wdog_scaler = 255; | |
536 | wdog_rst_delay = 255; | |
537 | wdog_counter = 0xffff; | |
538 | wdog_rston = 0; | |
539 | wdog_status = init; | |
540 | ||
541 | #ifdef ERA | |
542 | erareg = 0; | |
543 | #endif | |
544 | ||
545 | } | |
546 | ||
547 | ||
548 | ||
549 | static void | |
550 | mec_intack(level) | |
551 | int32 level; | |
552 | { | |
553 | int irq_test; | |
554 | ||
555 | if (sis_verbose) | |
556 | printf("interrupt %d acknowledged\n", level); | |
557 | irq_test = mec_tcr & 0x80000; | |
558 | if ((irq_test) && (mec_ifr & (1 << level))) | |
559 | mec_ifr &= ~(1 << level); | |
560 | else | |
561 | mec_ipr &= ~(1 << level); | |
562 | chk_irq(); | |
563 | } | |
564 | ||
565 | static void | |
566 | chk_irq() | |
567 | { | |
568 | int32 i; | |
569 | uint32 itmp; | |
570 | int old_irl; | |
571 | ||
572 | old_irl = ext_irl; | |
573 | if (mec_tcr & 0x80000) itmp = mec_ifr; | |
574 | else itmp = 0; | |
575 | itmp = ((mec_ipr | itmp) & ~mec_imr) & 0x0fffe; | |
576 | ext_irl = 0; | |
577 | if (itmp != 0) { | |
578 | for (i = 15; i > 0; i--) { | |
579 | if (((itmp >> i) & 1) != 0) { | |
580 | if ((sis_verbose) && (i > old_irl)) | |
581 | printf("IU irl: %d\n", i); | |
582 | ext_irl = i; | |
583 | set_int(i, mec_intack, i); | |
584 | break; | |
585 | } | |
586 | } | |
587 | } | |
588 | } | |
589 | ||
590 | static void | |
591 | mec_irq(level) | |
592 | int32 level; | |
593 | { | |
594 | mec_ipr |= (1 << level); | |
595 | chk_irq(); | |
596 | } | |
597 | ||
598 | static void | |
599 | set_sfsr(fault, addr, asi, read) | |
600 | uint32 fault; | |
601 | uint32 addr; | |
602 | uint32 asi; | |
603 | uint32 read; | |
604 | { | |
605 | if ((asi == 0xa) || (asi == 0xb)) { | |
606 | mec_ffar = addr; | |
607 | mec_sfsr = (fault << 3) | (!read << 15); | |
608 | mec_sfsr |= ((mec_sfsr & 1) ^ 1) | (mec_sfsr & 1); | |
609 | switch (asi) { | |
610 | case 0xa: | |
611 | mec_sfsr |= 0x0004; | |
612 | break; | |
613 | case 0xb: | |
614 | mec_sfsr |= 0x1004; | |
615 | break; | |
616 | } | |
617 | } | |
618 | } | |
619 | ||
620 | static int32 | |
621 | mec_read(addr, asi, data) | |
622 | uint32 addr; | |
623 | uint32 asi; | |
624 | uint32 *data; | |
625 | { | |
626 | ||
627 | switch (addr & 0x0ff) { | |
628 | ||
629 | case MEC_MCR: /* 0x00 */ | |
630 | *data = mec_mcr; | |
631 | break; | |
632 | ||
633 | case MEC_MEMCFG: /* 0x10 */ | |
634 | *data = mec_memcfg; | |
635 | break; | |
636 | ||
637 | case MEC_IOCR: | |
638 | *data = mec_iocr; /* 0x14 */ | |
639 | break; | |
640 | ||
641 | case MEC_SSA1: /* 0x20 */ | |
642 | *data = mec_ssa[0] | (mec_wpr[0] << 23); | |
643 | break; | |
644 | case MEC_SEA1: /* 0x24 */ | |
645 | *data = mec_sea[0]; | |
646 | break; | |
647 | case MEC_SSA2: /* 0x28 */ | |
648 | *data = mec_ssa[1] | (mec_wpr[1] << 23); | |
649 | break; | |
650 | case MEC_SEA2: /* 0x2c */ | |
651 | *data = mec_sea[1]; | |
652 | break; | |
653 | ||
654 | case MEC_ISR: /* 0x44 */ | |
655 | *data = mec_isr; | |
656 | break; | |
657 | ||
658 | case MEC_IPR: /* 0x48 */ | |
659 | *data = mec_ipr; | |
660 | break; | |
661 | ||
662 | case MEC_IMR: /* 0x4c */ | |
663 | *data = mec_imr; | |
664 | break; | |
665 | ||
666 | case MEC_IFR: /* 0x54 */ | |
667 | *data = mec_ifr; | |
668 | break; | |
669 | ||
670 | case MEC_RTC_COUNTER: /* 0x80 */ | |
671 | *data = rtc_counter_read(); | |
672 | break; | |
673 | case MEC_RTC_SCALER: /* 0x84 */ | |
674 | if (rtc_enabled) | |
675 | *data = rtc_scaler - (now() - rtc_scaler_start); | |
676 | else | |
677 | *data = rtc_scaler; | |
678 | break; | |
679 | ||
680 | case MEC_GPT_COUNTER: /* 0x88 */ | |
681 | *data = gpt_counter_read(); | |
682 | break; | |
683 | ||
684 | case MEC_GPT_SCALER: /* 0x8c */ | |
685 | if (rtc_enabled) | |
686 | *data = gpt_scaler - (now() - gpt_scaler_start); | |
687 | else | |
688 | *data = gpt_scaler; | |
689 | break; | |
690 | ||
691 | ||
692 | case MEC_SFSR: /* 0xA0 */ | |
693 | *data = mec_sfsr; | |
694 | break; | |
695 | ||
696 | case MEC_FFAR: /* 0xA4 */ | |
697 | *data = mec_ffar; | |
698 | break; | |
699 | ||
700 | case SIM_LOAD: | |
701 | fname[find] = 0; | |
702 | if (find == 0) | |
703 | strcpy(fname, "simload"); | |
704 | find = bfd_load(fname); | |
705 | if (find == -1) | |
706 | *data = 0; | |
707 | else | |
708 | *data = 1; | |
709 | find = 0; | |
710 | break; | |
711 | ||
712 | case MEC_ERSR: /* 0xB0 */ | |
713 | *data = mec_ersr; | |
714 | break; | |
715 | ||
716 | case MEC_TCR: /* 0xD0 */ | |
717 | *data = mec_tcr; | |
718 | break; | |
719 | ||
720 | case MEC_UARTA: /* 0xE0 */ | |
721 | case MEC_UARTB: /* 0xE4 */ | |
722 | if (asi != 0xb) { | |
723 | set_sfsr(MEC_ACC, addr, asi, 1); | |
5831e29b | 724 | return 1; |
c906108c SS |
725 | } |
726 | *data = read_uart(addr); | |
727 | break; | |
728 | ||
729 | case MEC_UART_CTRL: /* 0xE8 */ | |
730 | ||
731 | *data = read_uart(addr); | |
732 | break; | |
733 | ||
20a0ffe3 JG |
734 | case 0xF4: /* simulator RAM size in bytes */ |
735 | *data = 4096*1024; | |
736 | break; | |
737 | ||
738 | case 0xF8: /* simulator ROM size in bytes */ | |
739 | *data = 1024*1024; | |
740 | break; | |
741 | ||
c906108c SS |
742 | default: |
743 | set_sfsr(MEC_ACC, addr, asi, 1); | |
5831e29b | 744 | return 1; |
c906108c SS |
745 | break; |
746 | } | |
5831e29b | 747 | return MOK; |
c906108c SS |
748 | } |
749 | ||
750 | static int | |
751 | mec_write(addr, data) | |
752 | uint32 addr; | |
753 | uint32 data; | |
754 | { | |
755 | if (sis_verbose > 1) | |
756 | printf("MEC write a: %08x, d: %08x\n",addr,data); | |
757 | switch (addr & 0x0ff) { | |
758 | ||
759 | case MEC_MCR: | |
760 | mec_mcr = data; | |
761 | decode_mcr(); | |
762 | if (mec_mcr & 0x08000) mecparerror(); | |
763 | break; | |
764 | ||
765 | case MEC_SFR: | |
766 | if (mec_mcr & 0x2) { | |
767 | sys_reset(); | |
768 | mec_ersr = 0x4000; | |
769 | if (sis_verbose) | |
770 | printf(" Software reset issued\n"); | |
771 | } | |
772 | break; | |
773 | ||
774 | case MEC_IOCR: | |
775 | mec_iocr = data; | |
776 | if (mec_iocr & 0xC0C0C0C0) mecparerror(); | |
777 | break; | |
778 | ||
779 | case MEC_SSA1: /* 0x20 */ | |
780 | if (data & 0xFE000000) mecparerror(); | |
781 | mec_ssa[0] = data & 0x7fffff; | |
782 | mec_wpr[0] = (data >> 23) & 0x03; | |
783 | mem_accprot = mec_wpr[0] || mec_wpr[1]; | |
784 | if (sis_verbose && mec_wpr[0]) | |
785 | printf("Segment 1 memory protection enabled (0x02%06x - 0x02%06x)\n", | |
786 | mec_ssa[0] << 2, mec_sea[0] << 2); | |
787 | break; | |
788 | case MEC_SEA1: /* 0x24 */ | |
789 | if (data & 0xFF800000) mecparerror(); | |
790 | mec_sea[0] = data & 0x7fffff; | |
791 | break; | |
792 | case MEC_SSA2: /* 0x28 */ | |
793 | if (data & 0xFE000000) mecparerror(); | |
794 | mec_ssa[1] = data & 0x7fffff; | |
795 | mec_wpr[1] = (data >> 23) & 0x03; | |
796 | mem_accprot = mec_wpr[0] || mec_wpr[1]; | |
797 | if (sis_verbose && mec_wpr[1]) | |
798 | printf("Segment 2 memory protection enabled (0x02%06x - 0x02%06x)\n", | |
799 | mec_ssa[1] << 2, mec_sea[1] << 2); | |
800 | break; | |
801 | case MEC_SEA2: /* 0x2c */ | |
802 | if (data & 0xFF800000) mecparerror(); | |
803 | mec_sea[1] = data & 0x7fffff; | |
804 | break; | |
805 | ||
806 | case MEC_UARTA: | |
807 | case MEC_UARTB: | |
808 | if (data & 0xFFFFFF00) mecparerror(); | |
809 | case MEC_UART_CTRL: | |
810 | if (data & 0xFF00FF00) mecparerror(); | |
811 | write_uart(addr, data); | |
812 | break; | |
813 | ||
814 | case MEC_GPT_RELOAD: | |
815 | gpt_reload_set(data); | |
816 | break; | |
817 | ||
818 | case MEC_GPT_SCALER: | |
819 | if (data & 0xFFFF0000) mecparerror(); | |
820 | gpt_scaler_set(data); | |
821 | break; | |
822 | ||
823 | case MEC_TIMER_CTRL: | |
824 | if (data & 0xFFFFF0F0) mecparerror(); | |
825 | timer_ctrl(data); | |
826 | break; | |
827 | ||
828 | case MEC_RTC_RELOAD: | |
829 | rtc_reload_set(data); | |
830 | break; | |
831 | ||
832 | case MEC_RTC_SCALER: | |
833 | if (data & 0xFFFFFF00) mecparerror(); | |
834 | rtc_scaler_set(data); | |
835 | break; | |
836 | ||
837 | case MEC_SFSR: /* 0xA0 */ | |
838 | if (data & 0xFFFF0880) mecparerror(); | |
839 | mec_sfsr = 0x78; | |
840 | break; | |
841 | ||
842 | case MEC_ISR: | |
843 | if (data & 0xFFFFE000) mecparerror(); | |
844 | mec_isr = data; | |
845 | break; | |
846 | ||
847 | case MEC_IMR: /* 0x4c */ | |
848 | ||
849 | if (data & 0xFFFF8001) mecparerror(); | |
850 | mec_imr = data & 0x7ffe; | |
851 | chk_irq(); | |
852 | break; | |
853 | ||
854 | case MEC_ICR: /* 0x50 */ | |
855 | ||
856 | if (data & 0xFFFF0001) mecparerror(); | |
857 | mec_ipr &= ~data & 0x0fffe; | |
858 | chk_irq(); | |
859 | break; | |
860 | ||
861 | case MEC_IFR: /* 0x54 */ | |
862 | ||
863 | if (mec_tcr & 0x080000) { | |
864 | if (data & 0xFFFF0001) mecparerror(); | |
865 | mec_ifr = data & 0xfffe; | |
866 | chk_irq(); | |
867 | } | |
868 | break; | |
869 | case SIM_LOAD: | |
870 | fname[find++] = (char) data; | |
871 | break; | |
872 | ||
873 | ||
874 | case MEC_MEMCFG: /* 0x10 */ | |
875 | if (data & 0xC0E08000) mecparerror(); | |
876 | mec_memcfg = data; | |
877 | decode_memcfg(); | |
878 | if (mec_memcfg & 0xc0e08000) | |
879 | mecparerror(); | |
880 | break; | |
881 | ||
882 | case MEC_WCR: /* 0x18 */ | |
883 | mec_wcr = data; | |
884 | decode_wcr(); | |
885 | break; | |
886 | ||
887 | case MEC_ERSR: /* 0xB0 */ | |
888 | if (mec_tcr & 0x100000) | |
889 | if (data & 0xFFFFEFC0) mecparerror(); | |
890 | mec_ersr = data & 0x103f; | |
891 | break; | |
892 | ||
893 | case MEC_TCR: /* 0xD0 */ | |
894 | if (data & 0xFFE1FFC0) mecparerror(); | |
895 | mec_tcr = data & 0x1e003f; | |
896 | break; | |
897 | ||
898 | case MEC_WDOG: /* 0x60 */ | |
899 | wdog_scaler = (data >> 16) & 0x0ff; | |
900 | wdog_counter = data & 0x0ffff; | |
901 | wdog_rst_delay = data >> 24; | |
902 | wdog_rston = 0; | |
903 | if (wdog_status == stopped) | |
904 | wdog_start(); | |
905 | wdog_status = enabled; | |
906 | break; | |
907 | ||
908 | case MEC_TRAPD: /* 0x64 */ | |
909 | if (wdog_status == init) { | |
910 | wdog_status = disabled; | |
911 | if (sis_verbose) | |
912 | printf("Watchdog disabled\n"); | |
913 | } | |
914 | break; | |
915 | ||
916 | case MEC_PWDR: | |
917 | if (mec_mcr & 1) | |
918 | wait_for_irq(); | |
919 | break; | |
920 | ||
921 | default: | |
922 | set_sfsr(MEC_ACC, addr, 0xb, 0); | |
5831e29b | 923 | return 1; |
c906108c SS |
924 | break; |
925 | } | |
5831e29b | 926 | return MOK; |
c906108c SS |
927 | } |
928 | ||
929 | ||
930 | /* MEC UARTS */ | |
931 | ||
932 | static int ifd1 = -1, ifd2 = -1, ofd1 = -1, ofd2 = -1; | |
933 | ||
934 | void | |
935 | init_stdio() | |
936 | { | |
937 | if (dumbio) | |
938 | return; /* do nothing */ | |
939 | if (!ifd1) | |
940 | tcsetattr(0, TCSANOW, &ioc1); | |
941 | if (!ifd2) | |
942 | tcsetattr(0, TCSANOW, &ioc2); | |
943 | } | |
944 | ||
945 | void | |
946 | restore_stdio() | |
947 | { | |
948 | if (dumbio) | |
949 | return; /* do nothing */ | |
950 | if (!ifd1) | |
951 | tcsetattr(0, TCSANOW, &iocold1); | |
952 | if (!ifd2) | |
953 | tcsetattr(0, TCSANOW, &iocold2); | |
954 | } | |
955 | ||
956 | #define DO_STDIO_READ( _fd_, _buf_, _len_ ) \ | |
957 | ( dumbio \ | |
958 | ? (0) /* no bytes read, no delay */ \ | |
959 | : read( _fd_, _buf_, _len_ ) ) | |
960 | ||
961 | ||
962 | static void | |
963 | port_init() | |
964 | { | |
965 | ||
966 | if (uben) { | |
967 | f2in = stdin; | |
968 | f1in = NULL; | |
969 | f2out = stdout; | |
970 | f1out = NULL; | |
971 | } else { | |
972 | f1in = stdin; | |
973 | f2in = NULL; | |
974 | f1out = stdout; | |
975 | f2out = NULL; | |
976 | } | |
977 | if (uart_dev1[0] != 0) | |
978 | if ((fd1 = open(uart_dev1, O_RDWR | O_NONBLOCK)) < 0) { | |
979 | printf("Warning, couldn't open output device %s\n", uart_dev1); | |
980 | } else { | |
981 | if (sis_verbose) | |
982 | printf("serial port A on %s\n", uart_dev1); | |
983 | f1in = f1out = fdopen(fd1, "r+"); | |
984 | setbuf(f1out, NULL); | |
985 | f1open = 1; | |
986 | } | |
987 | if (f1in) ifd1 = fileno(f1in); | |
988 | if (ifd1 == 0) { | |
989 | if (sis_verbose) | |
990 | printf("serial port A on stdin/stdout\n"); | |
991 | if (!dumbio) { | |
992 | tcgetattr(ifd1, &ioc1); | |
993 | iocold1 = ioc1; | |
994 | ioc1.c_lflag &= ~(ICANON | ECHO); | |
995 | ioc1.c_cc[VMIN] = 0; | |
996 | ioc1.c_cc[VTIME] = 0; | |
997 | } | |
998 | f1open = 1; | |
999 | } | |
1000 | ||
1001 | if (f1out) { | |
1002 | ofd1 = fileno(f1out); | |
1003 | if (!dumbio && ofd1 == 1) setbuf(f1out, NULL); | |
1004 | } | |
1005 | ||
1006 | if (uart_dev2[0] != 0) | |
1007 | if ((fd2 = open(uart_dev2, O_RDWR | O_NONBLOCK)) < 0) { | |
1008 | printf("Warning, couldn't open output device %s\n", uart_dev2); | |
1009 | } else { | |
1010 | if (sis_verbose) | |
1011 | printf("serial port B on %s\n", uart_dev2); | |
1012 | f2in = f2out = fdopen(fd2, "r+"); | |
1013 | setbuf(f2out, NULL); | |
1014 | f2open = 1; | |
1015 | } | |
1016 | if (f2in) ifd2 = fileno(f2in); | |
1017 | if (ifd2 == 0) { | |
1018 | if (sis_verbose) | |
1019 | printf("serial port B on stdin/stdout\n"); | |
1020 | if (!dumbio) { | |
1021 | tcgetattr(ifd2, &ioc2); | |
1022 | iocold2 = ioc2; | |
1023 | ioc2.c_lflag &= ~(ICANON | ECHO); | |
1024 | ioc2.c_cc[VMIN] = 0; | |
1025 | ioc2.c_cc[VTIME] = 0; | |
1026 | } | |
1027 | f2open = 1; | |
1028 | } | |
1029 | ||
1030 | if (f2out) { | |
1031 | ofd2 = fileno(f2out); | |
1032 | if (!dumbio && ofd2 == 1) setbuf(f2out, NULL); | |
1033 | } | |
1034 | ||
1035 | wnuma = wnumb = 0; | |
1036 | ||
1037 | } | |
1038 | ||
1039 | static uint32 | |
1040 | read_uart(addr) | |
1041 | uint32 addr; | |
1042 | { | |
1043 | ||
1044 | unsigned tmp; | |
1045 | ||
1046 | tmp = 0; | |
1047 | switch (addr & 0xff) { | |
1048 | ||
1049 | case 0xE0: /* UART 1 */ | |
1050 | #ifndef _WIN32 | |
1051 | #ifdef FAST_UART | |
1052 | ||
1053 | if (aind < anum) { | |
1054 | if ((aind + 1) < anum) | |
1055 | mec_irq(4); | |
1056 | return (0x700 | (uint32) aq[aind++]); | |
1057 | } else { | |
1058 | if (f1open) { | |
1059 | anum = DO_STDIO_READ(ifd1, aq, UARTBUF); | |
1060 | } | |
1061 | if (anum > 0) { | |
1062 | aind = 0; | |
1063 | if ((aind + 1) < anum) | |
1064 | mec_irq(4); | |
1065 | return (0x700 | (uint32) aq[aind++]); | |
1066 | } else { | |
1067 | return (0x600 | (uint32) aq[aind]); | |
1068 | } | |
1069 | ||
1070 | } | |
1071 | #else | |
1072 | tmp = uarta_data; | |
1073 | uarta_data &= ~UART_DR; | |
1074 | uart_stat_reg &= ~UARTA_DR; | |
1075 | return tmp; | |
1076 | #endif | |
1077 | #else | |
5831e29b | 1078 | return 0; |
c906108c SS |
1079 | #endif |
1080 | break; | |
1081 | ||
1082 | case 0xE4: /* UART 2 */ | |
1083 | #ifndef _WIN32 | |
1084 | #ifdef FAST_UART | |
1085 | if (bind < bnum) { | |
1086 | if ((bind + 1) < bnum) | |
1087 | mec_irq(5); | |
1088 | return (0x700 | (uint32) bq[bind++]); | |
1089 | } else { | |
1090 | if (f2open) { | |
1091 | bnum = DO_STDIO_READ(ifd2, bq, UARTBUF); | |
1092 | } | |
1093 | if (bnum > 0) { | |
1094 | bind = 0; | |
1095 | if ((bind + 1) < bnum) | |
1096 | mec_irq(5); | |
1097 | return (0x700 | (uint32) bq[bind++]); | |
1098 | } else { | |
1099 | return (0x600 | (uint32) bq[bind]); | |
1100 | } | |
1101 | ||
1102 | } | |
1103 | #else | |
1104 | tmp = uartb_data; | |
1105 | uartb_data &= ~UART_DR; | |
1106 | uart_stat_reg &= ~UARTB_DR; | |
1107 | return tmp; | |
1108 | #endif | |
1109 | #else | |
5831e29b | 1110 | return 0; |
c906108c SS |
1111 | #endif |
1112 | break; | |
1113 | ||
1114 | case 0xE8: /* UART status register */ | |
1115 | #ifndef _WIN32 | |
1116 | #ifdef FAST_UART | |
1117 | ||
1118 | Ucontrol = 0; | |
1119 | if (aind < anum) { | |
1120 | Ucontrol |= 0x00000001; | |
1121 | } else { | |
1122 | if (f1open) { | |
1123 | anum = DO_STDIO_READ(ifd1, aq, UARTBUF); | |
1124 | } | |
1125 | if (anum > 0) { | |
1126 | Ucontrol |= 0x00000001; | |
1127 | aind = 0; | |
1128 | mec_irq(4); | |
1129 | } | |
1130 | } | |
1131 | if (bind < bnum) { | |
1132 | Ucontrol |= 0x00010000; | |
1133 | } else { | |
1134 | if (f2open) { | |
1135 | bnum = DO_STDIO_READ(ifd2, bq, UARTBUF); | |
1136 | } | |
1137 | if (bnum > 0) { | |
1138 | Ucontrol |= 0x00010000; | |
1139 | bind = 0; | |
1140 | mec_irq(5); | |
1141 | } | |
1142 | } | |
1143 | ||
1144 | Ucontrol |= 0x00060006; | |
5831e29b | 1145 | return Ucontrol; |
c906108c | 1146 | #else |
5831e29b | 1147 | return uart_stat_reg; |
c906108c SS |
1148 | #endif |
1149 | #else | |
5831e29b | 1150 | return 0x00060006; |
c906108c SS |
1151 | #endif |
1152 | break; | |
1153 | default: | |
1154 | if (sis_verbose) | |
1155 | printf("Read from unimplemented MEC register (%x)\n", addr); | |
1156 | ||
1157 | } | |
5831e29b | 1158 | return 0; |
c906108c SS |
1159 | } |
1160 | ||
1161 | static void | |
1162 | write_uart(addr, data) | |
1163 | uint32 addr; | |
1164 | uint32 data; | |
1165 | { | |
1166 | unsigned char c; | |
1167 | ||
1168 | c = (unsigned char) data; | |
1169 | switch (addr & 0xff) { | |
1170 | ||
1171 | case 0xE0: /* UART A */ | |
1172 | #ifdef FAST_UART | |
1173 | if (f1open) { | |
1174 | if (wnuma < UARTBUF) | |
1175 | wbufa[wnuma++] = c; | |
1176 | else { | |
1177 | while (wnuma) | |
1178 | wnuma -= fwrite(wbufa, 1, wnuma, f1out); | |
1179 | wbufa[wnuma++] = c; | |
1180 | } | |
1181 | } | |
1182 | mec_irq(4); | |
1183 | #else | |
1184 | if (uart_stat_reg & UARTA_SRE) { | |
1185 | uarta_sreg = c; | |
1186 | uart_stat_reg &= ~UARTA_SRE; | |
1187 | event(uarta_tx, 0, UART_TX_TIME); | |
1188 | } else { | |
1189 | uarta_hreg = c; | |
1190 | uart_stat_reg &= ~UARTA_HRE; | |
1191 | } | |
1192 | #endif | |
1193 | break; | |
1194 | ||
1195 | case 0xE4: /* UART B */ | |
1196 | #ifdef FAST_UART | |
1197 | if (f2open) { | |
1198 | if (wnumb < UARTBUF) | |
1199 | wbufb[wnumb++] = c; | |
1200 | else { | |
1201 | while (wnumb) | |
1202 | wnumb -= fwrite(wbufb, 1, wnumb, f2out); | |
1203 | wbufb[wnumb++] = c; | |
1204 | } | |
1205 | } | |
1206 | mec_irq(5); | |
1207 | #else | |
1208 | if (uart_stat_reg & UARTB_SRE) { | |
1209 | uartb_sreg = c; | |
1210 | uart_stat_reg &= ~UARTB_SRE; | |
1211 | event(uartb_tx, 0, UART_TX_TIME); | |
1212 | } else { | |
1213 | uartb_hreg = c; | |
1214 | uart_stat_reg &= ~UARTB_HRE; | |
1215 | } | |
1216 | #endif | |
1217 | break; | |
1218 | case 0xE8: /* UART status register */ | |
1219 | #ifndef FAST_UART | |
1220 | if (data & UARTA_CLR) { | |
1221 | uart_stat_reg &= 0xFFFF0000; | |
1222 | uart_stat_reg |= UARTA_SRE | UARTA_HRE; | |
1223 | } | |
1224 | if (data & UARTB_CLR) { | |
1225 | uart_stat_reg &= 0x0000FFFF; | |
1226 | uart_stat_reg |= UARTB_SRE | UARTB_HRE; | |
1227 | } | |
1228 | #endif | |
1229 | break; | |
1230 | default: | |
1231 | if (sis_verbose) | |
1232 | printf("Write to unimplemented MEC register (%x)\n", addr); | |
1233 | ||
1234 | } | |
1235 | } | |
1236 | ||
1237 | static void | |
1238 | flush_uart() | |
1239 | { | |
1240 | while (wnuma && f1open) | |
1241 | wnuma -= fwrite(wbufa, 1, wnuma, f1out); | |
1242 | while (wnumb && f2open) | |
1243 | wnumb -= fwrite(wbufb, 1, wnumb, f2out); | |
1244 | } | |
1245 | ||
1246 | ||
1247 | ||
1248 | static void | |
1249 | uarta_tx() | |
1250 | { | |
1251 | ||
1252 | while (f1open && fwrite(&uarta_sreg, 1, 1, f1out) != 1); | |
1253 | if (uart_stat_reg & UARTA_HRE) { | |
1254 | uart_stat_reg |= UARTA_SRE; | |
1255 | } else { | |
1256 | uarta_sreg = uarta_hreg; | |
1257 | uart_stat_reg |= UARTA_HRE; | |
1258 | event(uarta_tx, 0, UART_TX_TIME); | |
1259 | } | |
1260 | mec_irq(4); | |
1261 | } | |
1262 | ||
1263 | static void | |
1264 | uartb_tx() | |
1265 | { | |
1266 | while (f2open && fwrite(&uartb_sreg, 1, 1, f2out) != 1); | |
1267 | if (uart_stat_reg & UARTB_HRE) { | |
1268 | uart_stat_reg |= UARTB_SRE; | |
1269 | } else { | |
1270 | uartb_sreg = uartb_hreg; | |
1271 | uart_stat_reg |= UARTB_HRE; | |
1272 | event(uartb_tx, 0, UART_TX_TIME); | |
1273 | } | |
1274 | mec_irq(5); | |
1275 | } | |
1276 | ||
1277 | static void | |
1278 | uart_rx(arg) | |
1279 | caddr_t arg; | |
1280 | { | |
1281 | int32 rsize; | |
1282 | char rxd; | |
1283 | ||
1284 | ||
1285 | rsize = 0; | |
1286 | if (f1open) | |
1287 | rsize = DO_STDIO_READ(ifd1, &rxd, 1); | |
1288 | if (rsize > 0) { | |
1289 | uarta_data = UART_DR | rxd; | |
1290 | if (uart_stat_reg & UARTA_HRE) | |
1291 | uarta_data |= UART_THE; | |
1292 | if (uart_stat_reg & UARTA_SRE) | |
1293 | uarta_data |= UART_TSE; | |
1294 | if (uart_stat_reg & UARTA_DR) { | |
1295 | uart_stat_reg |= UARTA_OR; | |
1296 | mec_irq(7); /* UART error interrupt */ | |
1297 | } | |
1298 | uart_stat_reg |= UARTA_DR; | |
1299 | mec_irq(4); | |
1300 | } | |
1301 | rsize = 0; | |
1302 | if (f2open) | |
1303 | rsize = DO_STDIO_READ(ifd2, &rxd, 1); | |
1304 | if (rsize) { | |
1305 | uartb_data = UART_DR | rxd; | |
1306 | if (uart_stat_reg & UARTB_HRE) | |
1307 | uartb_data |= UART_THE; | |
1308 | if (uart_stat_reg & UARTB_SRE) | |
1309 | uartb_data |= UART_TSE; | |
1310 | if (uart_stat_reg & UARTB_DR) { | |
1311 | uart_stat_reg |= UARTB_OR; | |
1312 | mec_irq(7); /* UART error interrupt */ | |
1313 | } | |
1314 | uart_stat_reg |= UARTB_DR; | |
1315 | mec_irq(5); | |
1316 | } | |
1317 | event(uart_rx, 0, UART_RX_TIME); | |
1318 | } | |
1319 | ||
1320 | static void | |
1321 | uart_intr(arg) | |
1322 | caddr_t arg; | |
1323 | { | |
1324 | read_uart(0xE8); /* Check for UART interrupts every 1000 clk */ | |
1325 | flush_uart(); /* Flush UART ports */ | |
1326 | event(uart_intr, 0, UART_FLUSH_TIME); | |
1327 | } | |
1328 | ||
1329 | ||
1330 | static void | |
1331 | uart_irq_start() | |
1332 | { | |
1333 | #ifdef FAST_UART | |
1334 | event(uart_intr, 0, UART_FLUSH_TIME); | |
1335 | #else | |
1336 | #ifndef _WIN32 | |
1337 | event(uart_rx, 0, UART_RX_TIME); | |
1338 | #endif | |
1339 | #endif | |
1340 | } | |
1341 | ||
1342 | /* Watch-dog */ | |
1343 | ||
1344 | static void | |
1345 | wdog_intr(arg) | |
1346 | caddr_t arg; | |
1347 | { | |
1348 | if (wdog_status == disabled) { | |
1349 | wdog_status = stopped; | |
1350 | } else { | |
1351 | ||
1352 | if (wdog_counter) { | |
1353 | wdog_counter--; | |
1354 | event(wdog_intr, 0, wdog_scaler + 1); | |
1355 | } else { | |
1356 | if (wdog_rston) { | |
1357 | printf("Watchdog reset!\n"); | |
1358 | sys_reset(); | |
1359 | mec_ersr = 0xC000; | |
1360 | } else { | |
1361 | mec_irq(15); | |
1362 | wdog_rston = 1; | |
1363 | wdog_counter = wdog_rst_delay; | |
1364 | event(wdog_intr, 0, wdog_scaler + 1); | |
1365 | } | |
1366 | } | |
1367 | } | |
1368 | } | |
1369 | ||
1370 | static void | |
1371 | wdog_start() | |
1372 | { | |
1373 | event(wdog_intr, 0, wdog_scaler + 1); | |
1374 | if (sis_verbose) | |
1375 | printf("Watchdog started, scaler = %d, counter = %d\n", | |
1376 | wdog_scaler, wdog_counter); | |
1377 | } | |
1378 | ||
1379 | ||
1380 | /* MEC timers */ | |
1381 | ||
1382 | ||
1383 | static void | |
1384 | rtc_intr(arg) | |
1385 | caddr_t arg; | |
1386 | { | |
1387 | if (rtc_counter == 0) { | |
1388 | ||
1389 | mec_irq(13); | |
1390 | if (rtc_cr) | |
1391 | rtc_counter = rtc_reload; | |
1392 | else | |
1393 | rtc_se = 0; | |
1394 | } else | |
1395 | rtc_counter -= 1; | |
1396 | if (rtc_se) { | |
1397 | event(rtc_intr, 0, rtc_scaler + 1); | |
1398 | rtc_scaler_start = now(); | |
1399 | rtc_enabled = 1; | |
1400 | } else { | |
1401 | if (sis_verbose) | |
1402 | printf("RTC stopped\n\r"); | |
1403 | rtc_enabled = 0; | |
1404 | } | |
1405 | } | |
1406 | ||
1407 | static void | |
1408 | rtc_start() | |
1409 | { | |
1410 | if (sis_verbose) | |
1411 | printf("RTC started (period %d)\n\r", rtc_scaler + 1); | |
1412 | event(rtc_intr, 0, rtc_scaler + 1); | |
1413 | rtc_scaler_start = now(); | |
1414 | rtc_enabled = 1; | |
1415 | } | |
1416 | ||
1417 | static uint32 | |
1418 | rtc_counter_read() | |
1419 | { | |
5831e29b | 1420 | return rtc_counter; |
c906108c SS |
1421 | } |
1422 | ||
1423 | static void | |
1424 | rtc_scaler_set(val) | |
1425 | uint32 val; | |
1426 | { | |
1427 | rtc_scaler = val & 0x0ff; /* eight-bit scaler only */ | |
1428 | } | |
1429 | ||
1430 | static void | |
1431 | rtc_reload_set(val) | |
1432 | uint32 val; | |
1433 | { | |
1434 | rtc_reload = val; | |
1435 | } | |
1436 | ||
1437 | static void | |
1438 | gpt_intr(arg) | |
1439 | caddr_t arg; | |
1440 | { | |
1441 | if (gpt_counter == 0) { | |
1442 | mec_irq(12); | |
1443 | if (gpt_cr) | |
1444 | gpt_counter = gpt_reload; | |
1445 | else | |
1446 | gpt_se = 0; | |
1447 | } else | |
1448 | gpt_counter -= 1; | |
1449 | if (gpt_se) { | |
1450 | event(gpt_intr, 0, gpt_scaler + 1); | |
1451 | gpt_scaler_start = now(); | |
1452 | gpt_enabled = 1; | |
1453 | } else { | |
1454 | if (sis_verbose) | |
1455 | printf("GPT stopped\n\r"); | |
1456 | gpt_enabled = 0; | |
1457 | } | |
1458 | } | |
1459 | ||
1460 | static void | |
1461 | gpt_start() | |
1462 | { | |
1463 | if (sis_verbose) | |
1464 | printf("GPT started (period %d)\n\r", gpt_scaler + 1); | |
1465 | event(gpt_intr, 0, gpt_scaler + 1); | |
1466 | gpt_scaler_start = now(); | |
1467 | gpt_enabled = 1; | |
1468 | } | |
1469 | ||
1470 | static uint32 | |
1471 | gpt_counter_read() | |
1472 | { | |
5831e29b | 1473 | return gpt_counter; |
c906108c SS |
1474 | } |
1475 | ||
1476 | static void | |
1477 | gpt_scaler_set(val) | |
1478 | uint32 val; | |
1479 | { | |
1480 | gpt_scaler = val & 0x0ffff; /* 16-bit scaler */ | |
1481 | } | |
1482 | ||
1483 | static void | |
1484 | gpt_reload_set(val) | |
1485 | uint32 val; | |
1486 | { | |
1487 | gpt_reload = val; | |
1488 | } | |
1489 | ||
1490 | static void | |
1491 | timer_ctrl(val) | |
1492 | uint32 val; | |
1493 | { | |
1494 | ||
1495 | rtc_cr = ((val & TCR_TCRCR) != 0); | |
1496 | if (val & TCR_TCRCL) { | |
1497 | rtc_counter = rtc_reload; | |
1498 | } | |
1499 | if (val & TCR_TCRSL) { | |
1500 | } | |
1501 | rtc_se = ((val & TCR_TCRSE) != 0); | |
1502 | if (rtc_se && (rtc_enabled == 0)) | |
1503 | rtc_start(); | |
1504 | ||
1505 | gpt_cr = (val & TCR_GACR); | |
1506 | if (val & TCR_GACL) { | |
1507 | gpt_counter = gpt_reload; | |
1508 | } | |
1509 | if (val & TCR_GACL) { | |
1510 | } | |
1511 | gpt_se = (val & TCR_GASE) >> 2; | |
1512 | if (gpt_se && (gpt_enabled == 0)) | |
1513 | gpt_start(); | |
1514 | } | |
1515 | ||
d3e9b40a JG |
1516 | /* Store data in host byte order. MEM points to the beginning of the |
1517 | emulated memory; WADDR contains the index the emulated memory, | |
1518 | DATA points to words in host byte order to be stored. SZ contains log(2) | |
1519 | of the number of bytes to retrieve, and can be 0 (1 byte), 1 (one half-word), | |
1520 | 2 (one word), or 3 (two words); WS should return the number of | |
1521 | wait-states. */ | |
c906108c SS |
1522 | |
1523 | static void | |
d3e9b40a JG |
1524 | store_bytes (unsigned char *mem, uint32 waddr, uint32 *data, int32 sz, |
1525 | int32 *ws) | |
c906108c | 1526 | { |
d3e9b40a | 1527 | switch (sz) { |
c906108c | 1528 | case 0: |
d3e9b40a JG |
1529 | waddr ^= EBT; |
1530 | mem[waddr] = *data & 0x0ff; | |
1531 | *ws = mem_ramw_ws + 3; | |
c906108c SS |
1532 | break; |
1533 | case 1: | |
d3e9b40a JG |
1534 | #ifdef HOST_LITTLE_ENDIAN |
1535 | waddr ^= 2; | |
1536 | #endif | |
1537 | memcpy (&mem[waddr], data, 2); | |
1538 | *ws = mem_ramw_ws + 3; | |
c906108c | 1539 | break; |
c906108c | 1540 | case 2: |
d3e9b40a JG |
1541 | memcpy (&mem[waddr], data, 4); |
1542 | *ws = mem_ramw_ws; | |
c906108c | 1543 | break; |
c906108c | 1544 | case 3: |
d3e9b40a JG |
1545 | memcpy (&mem[waddr], data, 8); |
1546 | *ws = 2 * mem_ramw_ws + STD_WS; | |
c906108c | 1547 | break; |
c906108c SS |
1548 | } |
1549 | } | |
1550 | ||
1551 | ||
1552 | /* Memory emulation */ | |
1553 | ||
102b920e JG |
1554 | int |
1555 | memory_iread (uint32 addr, uint32 *data, int32 *ws) | |
1556 | { | |
1557 | uint32 asi; | |
1558 | if ((addr >= mem_ramstart) && (addr < (mem_ramstart + mem_ramsz))) { | |
1559 | memcpy (data, &ramb[addr & mem_rammask & ~3], 4); | |
1560 | *ws = mem_ramr_ws; | |
1561 | return 0; | |
1562 | } else if (addr < mem_romsz) { | |
1563 | memcpy (data, &romb[addr & ~3], 4); | |
1564 | *ws = mem_romr_ws; | |
1565 | return 0; | |
1566 | } | |
1567 | ||
1568 | if (sis_verbose) | |
1569 | printf ("Memory exception at %x (illegal address)\n", addr); | |
1570 | if (sregs.psr & 0x080) | |
1571 | asi = 9; | |
1572 | else | |
1573 | asi = 8; | |
1574 | set_sfsr (UIMP_ACC, addr, asi, 1); | |
1575 | *ws = MEM_EX_WS; | |
1576 | return 1; | |
1577 | } | |
1578 | ||
c906108c SS |
1579 | int |
1580 | memory_read(asi, addr, data, sz, ws) | |
1581 | int32 asi; | |
1582 | uint32 addr; | |
1583 | uint32 *data; | |
1584 | int32 sz; | |
1585 | int32 *ws; | |
1586 | { | |
1587 | int32 mexc; | |
1588 | ||
1589 | #ifdef ERRINJ | |
1590 | if (errmec) { | |
1591 | if (sis_verbose) | |
1592 | printf("Inserted MEC error %d\n",errmec); | |
1593 | set_sfsr(errmec, addr, asi, 1); | |
1594 | if (errmec == 5) mecparerror(); | |
1595 | if (errmec == 6) iucomperr(); | |
1596 | errmec = 0; | |
5831e29b | 1597 | return 1; |
c906108c | 1598 | } |
d68c23cd | 1599 | #endif |
c906108c SS |
1600 | |
1601 | if ((addr >= mem_ramstart) && (addr < (mem_ramstart + mem_ramsz))) { | |
d3e9b40a | 1602 | memcpy (data, &ramb[addr & mem_rammask & ~3], 4); |
c906108c | 1603 | *ws = mem_ramr_ws; |
5831e29b | 1604 | return 0; |
c906108c SS |
1605 | } else if ((addr >= MEC_START) && (addr < MEC_END)) { |
1606 | mexc = mec_read(addr, asi, data); | |
1607 | if (mexc) { | |
1608 | set_sfsr(MEC_ACC, addr, asi, 1); | |
1609 | *ws = MEM_EX_WS; | |
1610 | } else { | |
1611 | *ws = 0; | |
1612 | } | |
5831e29b | 1613 | return mexc; |
c906108c SS |
1614 | |
1615 | #ifdef ERA | |
1616 | ||
1617 | } else if (era) { | |
1618 | if ((addr < 0x100000) || | |
1619 | ((addr>= 0x80000000) && (addr < 0x80100000))) { | |
d3e9b40a | 1620 | memcpy (data, &romb[addr & ROM_MASK & ~3], 4); |
c906108c | 1621 | *ws = 4; |
5831e29b | 1622 | return 0; |
c906108c SS |
1623 | } else if ((addr >= 0x10000000) && |
1624 | (addr < (0x10000000 + (512 << (mec_iocr & 0x0f)))) && | |
1625 | (mec_iocr & 0x10)) { | |
1626 | *data = erareg; | |
5831e29b | 1627 | return 0; |
c906108c SS |
1628 | } |
1629 | ||
1630 | } else if (addr < mem_romsz) { | |
d3e9b40a JG |
1631 | memcpy (data, &romb[addr & ~3], 4); |
1632 | *ws = mem_romr_ws; | |
1633 | return 0; | |
c906108c SS |
1634 | #else |
1635 | } else if (addr < mem_romsz) { | |
d3e9b40a | 1636 | memcpy (data, &romb[addr & ~3], 4); |
c906108c | 1637 | *ws = mem_romr_ws; |
5831e29b | 1638 | return 0; |
c906108c SS |
1639 | #endif |
1640 | ||
1641 | } | |
1642 | ||
102b920e JG |
1643 | if (sis_verbose) |
1644 | printf ("Memory exception at %x (illegal address)\n", addr); | |
c906108c SS |
1645 | set_sfsr(UIMP_ACC, addr, asi, 1); |
1646 | *ws = MEM_EX_WS; | |
5831e29b | 1647 | return 1; |
c906108c SS |
1648 | } |
1649 | ||
1650 | int | |
1651 | memory_write(asi, addr, data, sz, ws) | |
1652 | int32 asi; | |
1653 | uint32 addr; | |
1654 | uint32 *data; | |
1655 | int32 sz; | |
1656 | int32 *ws; | |
1657 | { | |
1658 | uint32 byte_addr; | |
1659 | uint32 byte_mask; | |
1660 | uint32 waddr; | |
1661 | uint32 *ram; | |
1662 | int32 mexc; | |
1663 | int i; | |
1664 | int wphit[2]; | |
1665 | ||
1666 | #ifdef ERRINJ | |
1667 | if (errmec) { | |
1668 | if (sis_verbose) | |
1669 | printf("Inserted MEC error %d\n",errmec); | |
1670 | set_sfsr(errmec, addr, asi, 0); | |
1671 | if (errmec == 5) mecparerror(); | |
1672 | if (errmec == 6) iucomperr(); | |
1673 | errmec = 0; | |
5831e29b | 1674 | return 1; |
c906108c | 1675 | } |
d68c23cd | 1676 | #endif |
c906108c SS |
1677 | |
1678 | if ((addr >= mem_ramstart) && (addr < (mem_ramstart + mem_ramsz))) { | |
1679 | if (mem_accprot) { | |
1680 | ||
1681 | waddr = (addr & 0x7fffff) >> 2; | |
1682 | for (i = 0; i < 2; i++) | |
1683 | wphit[i] = | |
1684 | (((asi == 0xa) && (mec_wpr[i] & 1)) || | |
1685 | ((asi == 0xb) && (mec_wpr[i] & 2))) && | |
1686 | ((waddr >= mec_ssa[i]) && ((waddr | (sz == 3)) < mec_sea[i])); | |
1687 | ||
1688 | if (((mem_blockprot) && (wphit[0] || wphit[1])) || | |
1689 | ((!mem_blockprot) && | |
1690 | !((mec_wpr[0] && wphit[0]) || (mec_wpr[1] && wphit[1])) | |
1691 | )) { | |
1692 | if (sis_verbose) | |
1693 | printf("Memory access protection error at 0x%08x\n", addr); | |
1694 | set_sfsr(PROT_EXC, addr, asi, 0); | |
1695 | *ws = MEM_EX_WS; | |
5831e29b | 1696 | return 1; |
c906108c SS |
1697 | } |
1698 | } | |
d3e9b40a JG |
1699 | waddr = addr & mem_rammask; |
1700 | store_bytes (ramb, waddr, data, sz, ws); | |
5831e29b | 1701 | return 0; |
c906108c SS |
1702 | } else if ((addr >= MEC_START) && (addr < MEC_END)) { |
1703 | if ((sz != 2) || (asi != 0xb)) { | |
1704 | set_sfsr(MEC_ACC, addr, asi, 0); | |
1705 | *ws = MEM_EX_WS; | |
5831e29b | 1706 | return 1; |
c906108c SS |
1707 | } |
1708 | mexc = mec_write(addr, *data); | |
1709 | if (mexc) { | |
1710 | set_sfsr(MEC_ACC, addr, asi, 0); | |
1711 | *ws = MEM_EX_WS; | |
1712 | } else { | |
1713 | *ws = 0; | |
1714 | } | |
5831e29b | 1715 | return mexc; |
c906108c SS |
1716 | |
1717 | #ifdef ERA | |
1718 | ||
1719 | } else if (era) { | |
1720 | if ((erareg & 2) && | |
1721 | ((addr < 0x100000) || ((addr >= 0x80000000) && (addr < 0x80100000)))) { | |
1722 | addr &= ROM_MASK; | |
1723 | *ws = sz == 3 ? 8 : 4; | |
d3e9b40a | 1724 | store_bytes (romb, addr, data, sz, ws); |
5831e29b | 1725 | return 0; |
c906108c SS |
1726 | } else if ((addr >= 0x10000000) && |
1727 | (addr < (0x10000000 + (512 << (mec_iocr & 0x0f)))) && | |
1728 | (mec_iocr & 0x10)) { | |
1729 | erareg = *data & 0x0e; | |
5831e29b | 1730 | return 0; |
c906108c SS |
1731 | } |
1732 | ||
1733 | } else if ((addr < mem_romsz) && (mec_memcfg & 0x10000) && (wrp) && | |
1734 | (((mec_memcfg & 0x20000) && (sz > 1)) || | |
1735 | (!(mec_memcfg & 0x20000) && (sz == 0)))) { | |
1736 | ||
1737 | *ws = mem_romw_ws + 1; | |
1738 | if (sz == 3) | |
1739 | *ws += mem_romw_ws + STD_WS; | |
d3e9b40a | 1740 | store_bytes (romb, addr, data, sz, ws); |
5831e29b | 1741 | return 0; |
c906108c SS |
1742 | |
1743 | #else | |
1744 | } else if ((addr < mem_romsz) && (mec_memcfg & 0x10000) && (wrp) && | |
1745 | (((mec_memcfg & 0x20000) && (sz > 1)) || | |
1746 | (!(mec_memcfg & 0x20000) && (sz == 0)))) { | |
1747 | ||
1748 | *ws = mem_romw_ws + 1; | |
1749 | if (sz == 3) | |
1750 | *ws += mem_romw_ws + STD_WS; | |
d3e9b40a | 1751 | store_bytes (romb, addr, data, sz, ws); |
5831e29b | 1752 | return 0; |
c906108c SS |
1753 | |
1754 | #endif | |
1755 | ||
1756 | } | |
1757 | ||
1758 | *ws = MEM_EX_WS; | |
1759 | set_sfsr(UIMP_ACC, addr, asi, 0); | |
5831e29b | 1760 | return 1; |
c906108c SS |
1761 | } |
1762 | ||
1763 | static unsigned char * | |
1764 | get_mem_ptr(addr, size) | |
1765 | uint32 addr; | |
1766 | uint32 size; | |
1767 | { | |
1768 | if ((addr + size) < ROM_SZ) { | |
5831e29b | 1769 | return &romb[addr]; |
c906108c | 1770 | } else if ((addr >= mem_ramstart) && ((addr + size) < mem_ramend)) { |
5831e29b | 1771 | return &ramb[addr & mem_rammask]; |
c906108c SS |
1772 | } |
1773 | ||
1774 | #ifdef ERA | |
1775 | else if ((era) && ((addr <0x100000) || | |
1776 | ((addr >= (unsigned) 0x80000000) && ((addr + size) < (unsigned) 0x80100000)))) { | |
5831e29b | 1777 | return &romb[addr & ROM_MASK]; |
c906108c SS |
1778 | } |
1779 | #endif | |
1780 | ||
5831e29b | 1781 | return (char *) -1; |
c906108c SS |
1782 | } |
1783 | ||
1784 | int | |
1785 | sis_memory_write(addr, data, length) | |
94110024 JS |
1786 | uint32 addr; |
1787 | const unsigned char *data; | |
1788 | uint32 length; | |
c906108c SS |
1789 | { |
1790 | char *mem; | |
1791 | ||
1792 | if ((mem = get_mem_ptr(addr, length)) == ((char *) -1)) | |
5831e29b | 1793 | return 0; |
c906108c SS |
1794 | |
1795 | memcpy(mem, data, length); | |
5831e29b | 1796 | return length; |
c906108c SS |
1797 | } |
1798 | ||
1799 | int | |
1800 | sis_memory_read(addr, data, length) | |
1801 | uint32 addr; | |
1802 | char *data; | |
1803 | uint32 length; | |
1804 | { | |
1805 | char *mem; | |
1806 | ||
1807 | if ((mem = get_mem_ptr(addr, length)) == ((char *) -1)) | |
5831e29b | 1808 | return 0; |
c906108c SS |
1809 | |
1810 | memcpy(data, mem, length); | |
5831e29b | 1811 | return length; |
c906108c | 1812 | } |
20a0ffe3 JG |
1813 | |
1814 | extern struct pstate sregs; | |
1815 | ||
1816 | void | |
1817 | boot_init (void) | |
1818 | { | |
1819 | mec_write(MEC_WCR, 0); /* zero waitstates */ | |
1820 | mec_write(MEC_TRAPD, 0); /* turn off watch-dog */ | |
1821 | mec_write(MEC_RTC_SCALER, sregs.freq - 1); /* generate 1 MHz RTC tick */ | |
1822 | mec_write(MEC_MEMCFG, (3 << 18) | (4 << 10)); /* 1 MB ROM, 4 MB RAM */ | |
1823 | sregs.wim = 2; | |
1824 | sregs.psr = 0x110010e0; | |
1825 | sregs.r[30] = RAM_END; | |
1826 | sregs.r[14] = sregs.r[30] - 96 * 4; | |
1827 | mec_mcr |= 1; /* power-down enabled */ | |
1828 | } |