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sim: erc32: strip paren from return statements
[deliverable/binutils-gdb.git] / sim / erc32 / erc32.c
CommitLineData
c906108c
SS		 1/*
2 * This file is part of SIS.
3 *
4 * SIS, SPARC instruction simulator V2.5 Copyright (C) 1995 Jiri Gaisler,
5 * European Space Agency
6 *
7 * This program is free software; you can redistribute it and/or modify it under
8 * the terms of the GNU General Public License as published by the Free
3fd725ef 9 * Software Foundation; either version 3 of the License, or (at your option)
c906108c
SS		 10 * any later version.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
51b318de 18 * this program; if not, see <http://www.gnu.org/licenses/>.
c906108c
SS		 19 *
20 */
21
22/* The control space devices */
23
5272643f 24#include "config.h"
c906108c
SS		 25#include <sys/types.h>
26#include <stdio.h>
d68c23cd 27#include <string.h>
c906108c
SS		 28#include <termios.h>
29#include <sys/fcntl.h>
30#include <sys/file.h>
31#include <unistd.h>
32#include "sis.h"
c906108c
SS		 33#include "sim-config.h"
34
35extern int ctrl_c;
36extern int32 sis_verbose;
37extern int32 sparclite, sparclite_board;
38extern int rom8,wrp,uben;
39extern char uart_dev1[], uart_dev2[];
40
41int dumbio = 0; /* normal, smart, terminal oriented IO by default */
42
43/* MEC registers */
44#define MEC_START 0x01f80000
45#define MEC_END 0x01f80100
46
47/* Memory exception waitstates */
48#define MEM_EX_WS 1
49
50/* ERC32 always adds one waitstate during RAM std */
51#define STD_WS 1
52
53#ifdef ERRINJ
54extern int errmec;
55#endif
56
57/* The target's byte order is big-endian by default until we load a
58 little-endian program. */
59
60int current_target_byte_order = BIG_ENDIAN;
61
62#define MEC_WS 0 /* Waitstates per MEC access (0 ws) */
63#define MOK 0
64
65/* MEC register addresses */
66
67#define MEC_MCR 0x000
68#define MEC_SFR 0x004
69#define MEC_PWDR 0x008
70#define MEC_MEMCFG 0x010
71#define MEC_IOCR 0x014
72#define MEC_WCR 0x018
73
74#define MEC_MAR0 0x020
75#define MEC_MAR1 0x024
76
77#define MEC_SSA1 0x020
78#define MEC_SEA1 0x024
79#define MEC_SSA2 0x028
80#define MEC_SEA2 0x02C
81#define MEC_ISR 0x044
82#define MEC_IPR 0x048
83#define MEC_IMR 0x04C
84#define MEC_ICR 0x050
85#define MEC_IFR 0x054
86#define MEC_WDOG 0x060
87#define MEC_TRAPD 0x064
88#define MEC_RTC_COUNTER 0x080
89#define MEC_RTC_RELOAD 0x080
90#define MEC_RTC_SCALER 0x084
91#define MEC_GPT_COUNTER 0x088
92#define MEC_GPT_RELOAD 0x088
93#define MEC_GPT_SCALER 0x08C
94#define MEC_TIMER_CTRL 0x098
95#define MEC_SFSR 0x0A0
96#define MEC_FFAR 0x0A4
97#define MEC_ERSR 0x0B0
98#define MEC_DBG 0x0C0
99#define MEC_TCR 0x0D0
100
101#define MEC_BRK 0x0C4
102#define MEC_WPR 0x0C8
103
104#define MEC_UARTA 0x0E0
105#define MEC_UARTB 0x0E4
106#define MEC_UART_CTRL 0x0E8
107#define SIM_LOAD 0x0F0
108
109/* Memory exception causes */
110#define PROT_EXC 0x3
111#define UIMP_ACC 0x4
112#define MEC_ACC 0x6
113#define WATCH_EXC 0xa
114#define BREAK_EXC 0xb
115
116/* Size of UART buffers (bytes) */
117#define UARTBUF 1024
118
119/* Number of simulator ticks between flushing the UARTS. */
120/* For good performance, keep above 1000 */
121#define UART_FLUSH_TIME 3000
122
123/* MEC timer control register bits */
124#define TCR_GACR 1
125#define TCR_GACL 2
126#define TCR_GASE 4
127#define TCR_GASL 8
128#define TCR_TCRCR 0x100
129#define TCR_TCRCL 0x200
130#define TCR_TCRSE 0x400
131#define TCR_TCRSL 0x800
132
133/* New uart defines */
134#define UART_TX_TIME 1000
135#define UART_RX_TIME 1000
136#define UARTA_DR 0x1
137#define UARTA_SRE 0x2
138#define UARTA_HRE 0x4
139#define UARTA_OR 0x40
140#define UARTA_CLR 0x80
141#define UARTB_DR 0x10000
142#define UARTB_SRE 0x20000
143#define UARTB_HRE 0x40000
144#define UARTB_OR 0x400000
145#define UARTB_CLR 0x800000
146
147#define UART_DR 0x100
148#define UART_TSE 0x200
149#define UART_THE 0x400
150
151/* MEC registers */
152
153static char fname[256];
154static int32 find = 0;
155static uint32 mec_ssa[2]; /* Write protection start address */
156static uint32 mec_sea[2]; /* Write protection end address */
157static uint32 mec_wpr[2]; /* Write protection control fields */
158static uint32 mec_sfsr;
159static uint32 mec_ffar;
160static uint32 mec_ipr;
161static uint32 mec_imr;
162static uint32 mec_isr;
163static uint32 mec_icr;
164static uint32 mec_ifr;
165static uint32 mec_mcr; /* MEC control register */
166static uint32 mec_memcfg; /* Memory control register */
167static uint32 mec_wcr; /* MEC waitstate register */
168static uint32 mec_iocr; /* MEC IO control register */
169static uint32 posted_irq;
170static uint32 mec_ersr; /* MEC error and status register */
171static uint32 mec_tcr; /* MEC test comtrol register */
172
173static uint32 rtc_counter;
174static uint32 rtc_reload;
175static uint32 rtc_scaler;
176static uint32 rtc_scaler_start;
177static uint32 rtc_enabled;
178static uint32 rtc_cr;
179static uint32 rtc_se;
180
181static uint32 gpt_counter;
182static uint32 gpt_reload;
183static uint32 gpt_scaler;
184static uint32 gpt_scaler_start;
185static uint32 gpt_enabled;
186static uint32 gpt_cr;
187static uint32 gpt_se;
188
189static uint32 wdog_scaler;
190static uint32 wdog_counter;
191static uint32 wdog_rst_delay;
192static uint32 wdog_rston;
193
194enum wdog_type {
195 init, disabled, enabled, stopped
196};
197
198static enum wdog_type wdog_status;
199
200
201/* ROM size 1024 Kbyte */
202#define ROM_SZ 0x100000
203#define ROM_MASK 0x0fffff
204
205/* RAM size 4 Mbyte */
206#define RAM_START 0x02000000
207#define RAM_END 0x02400000
208#define RAM_MASK 0x003fffff
209
210/* SPARClite boards all seem to have RAM at the same place. */
211#define RAM_START_SLITE 0x40000000
212#define RAM_END_SLITE 0x40400000
213#define RAM_MASK_SLITE 0x003fffff
214
215/* Memory support variables */
216
217static uint32 mem_ramr_ws; /* RAM read waitstates */
218static uint32 mem_ramw_ws; /* RAM write waitstates */
219static uint32 mem_romr_ws; /* ROM read waitstates */
220static uint32 mem_romw_ws; /* ROM write waitstates */
221static uint32 mem_ramstart; /* RAM start */
222static uint32 mem_ramend; /* RAM end */
223static uint32 mem_rammask; /* RAM address mask */
224static uint32 mem_ramsz; /* RAM size */
225static uint32 mem_romsz; /* ROM size */
226static uint32 mem_accprot; /* RAM write protection enabled */
227static uint32 mem_blockprot; /* RAM block write protection enabled */
228
229static unsigned char romb[ROM_SZ];
230static unsigned char ramb[RAM_END - RAM_START];
231
232
233/* UART support variables */
234
235static int32 fd1, fd2; /* file descriptor for input file */
236static int32 Ucontrol; /* UART status register */
237static unsigned char aq[UARTBUF], bq[UARTBUF];
238static int32 anum, aind = 0;
239static int32 bnum, bind = 0;
240static char wbufa[UARTBUF], wbufb[UARTBUF];
241static unsigned wnuma;
242static unsigned wnumb;
243static FILE *f1in, *f1out, *f2in, *f2out;
244static struct termios ioc1, ioc2, iocold1, iocold2;
245static int f1open = 0, f2open = 0;
246
247static char uarta_sreg, uarta_hreg, uartb_sreg, uartb_hreg;
248static uint32 uart_stat_reg;
249static uint32 uarta_data, uartb_data;
250
251#ifdef ERA
252int era = 0;
253int erareg;
254#endif
255
256/* Forward declarations */
257
bdca5ee4 258static void decode_ersr (void);
c906108c 259#ifdef ERRINJ
bdca5ee4 260static void iucomperr (void);
c906108c 261#endif
bdca5ee4
TT		 262static void mecparerror (void);
263static void decode_memcfg (void);
264static void decode_wcr (void);
265static void decode_mcr (void);
266static void close_port (void);
267static void mec_reset (void);
268static void mec_intack (int32 level);
269static void chk_irq (void);
270static void mec_irq (int32 level);
271static void set_sfsr (uint32 fault, uint32 addr,
272 uint32 asi, uint32 read);
273static int32 mec_read (uint32 addr, uint32 asi, uint32 *data);
274static int mec_write (uint32 addr, uint32 data);
275static void port_init (void);
276static uint32 read_uart (uint32 addr);
277static void write_uart (uint32 addr, uint32 data);
278static void flush_uart (void);
279static void uarta_tx (void);
280static void uartb_tx (void);
281static void uart_rx (caddr_t arg);
282static void uart_intr (caddr_t arg);
283static void uart_irq_start (void);
284static void wdog_intr (caddr_t arg);
285static void wdog_start (void);
286static void rtc_intr (caddr_t arg);
287static void rtc_start (void);
288static uint32 rtc_counter_read (void);
289static void rtc_scaler_set (uint32 val);
290static void rtc_reload_set (uint32 val);
291static void gpt_intr (caddr_t arg);
292static void gpt_start (void);
293static uint32 gpt_counter_read (void);
294static void gpt_scaler_set (uint32 val);
295static void gpt_reload_set (uint32 val);
296static void timer_ctrl (uint32 val);
c906108c 297static unsigned char *
bdca5ee4 298 get_mem_ptr (uint32 addr, uint32 size);
c906108c 299
bdca5ee4
TT		 300static void fetch_bytes (int asi, unsigned char *mem,
301 uint32 *data, int sz);
c906108c 302
bdca5ee4 303static void store_bytes (unsigned char *mem, uint32 *data, int sz);
c906108c
SS		 304
305extern int ext_irl;
306
307
308/* One-time init */
309
310void
311init_sim()
312{
313 port_init();
314}
315
316/* Power-on reset init */
317
318void
319reset()
320{
321 mec_reset();
322 uart_irq_start();
323 wdog_start();
324}
325
326static void
327decode_ersr()
328{
329 if (mec_ersr & 0x01) {
330 if (!(mec_mcr & 0x20)) {
331 if (mec_mcr & 0x40) {
332 sys_reset();
333 mec_ersr = 0x8000;
334 if (sis_verbose)
335 printf("Error manager reset - IU in error mode\n");
336 } else {
337 sys_halt();
338 mec_ersr |= 0x2000;
339 if (sis_verbose)
340 printf("Error manager halt - IU in error mode\n");
341 }
342 } else
343 mec_irq(1);
344 }
345 if (mec_ersr & 0x04) {
346 if (!(mec_mcr & 0x200)) {
347 if (mec_mcr & 0x400) {
348 sys_reset();
349 mec_ersr = 0x8000;
350 if (sis_verbose)
351 printf("Error manager reset - IU comparison error\n");
352 } else {
353 sys_halt();
354 mec_ersr |= 0x2000;
355 if (sis_verbose)
356 printf("Error manager halt - IU comparison error\n");
357 }
358 } else
359 mec_irq(1);
360 }
361 if (mec_ersr & 0x20) {
362 if (!(mec_mcr & 0x2000)) {
363 if (mec_mcr & 0x4000) {
364 sys_reset();
365 mec_ersr = 0x8000;
366 if (sis_verbose)
367 printf("Error manager reset - MEC hardware error\n");
368 } else {
369 sys_halt();
370 mec_ersr |= 0x2000;
371 if (sis_verbose)
372 printf("Error manager halt - MEC hardware error\n");
373 }
374 } else
375 mec_irq(1);
376 }
377}
378
379#ifdef ERRINJ
380static void
381iucomperr()
382{
383 mec_ersr |= 0x04;
384 decode_ersr();
385}
386#endif
387
388static void
389mecparerror()
390{
391 mec_ersr |= 0x20;
392 decode_ersr();
393}
394
395
396/* IU error mode manager */
397
398void
399error_mode(pc)
400 uint32 pc;
401{
402
403 mec_ersr |= 0x1;
404 decode_ersr();
405}
406
407
408/* Check memory settings */
409
410static void
411decode_memcfg()
412{
413 if (rom8) mec_memcfg &= ~0x20000;
414 else mec_memcfg |= 0x20000;
415
416 mem_ramsz = (256 * 1024) << ((mec_memcfg >> 10) & 7);
417 mem_romsz = (128 * 1024) << ((mec_memcfg >> 18) & 7);
418
419 if (sparclite_board) {
420 mem_ramstart = RAM_START_SLITE;
421 mem_ramend = RAM_END_SLITE;
422 mem_rammask = RAM_MASK_SLITE;
423 }
424 else {
425 mem_ramstart = RAM_START;
426 mem_ramend = RAM_END;
427 mem_rammask = RAM_MASK;
428 }
429 if (sis_verbose)
430 printf("RAM start: 0x%x, RAM size: %d K, ROM size: %d K\n",
431 mem_ramstart, mem_ramsz >> 10, mem_romsz >> 10);
432}
433
434static void
435decode_wcr()
436{
437 mem_ramr_ws = mec_wcr & 3;
438 mem_ramw_ws = (mec_wcr >> 2) & 3;
439 mem_romr_ws = (mec_wcr >> 4) & 0x0f;
440 if (rom8) {
441 if (mem_romr_ws > 0 ) mem_romr_ws--;
442 mem_romr_ws = 5 + (4*mem_romr_ws);
443 }
444 mem_romw_ws = (mec_wcr >> 8) & 0x0f;
445 if (sis_verbose)
446 printf("Waitstates = RAM read: %d, RAM write: %d, ROM read: %d, ROM write: %d\n",
447 mem_ramr_ws, mem_ramw_ws, mem_romr_ws, mem_romw_ws);
448}
449
450static void
451decode_mcr()
452{
453 mem_accprot = (mec_wpr[0] | mec_wpr[1]);
454 mem_blockprot = (mec_mcr >> 3) & 1;
455 if (sis_verbose && mem_accprot)
456 printf("Memory block write protection enabled\n");
457 if (mec_mcr & 0x08000) {
458 mec_ersr |= 0x20;
459 decode_ersr();
460 }
461 if (sis_verbose && (mec_mcr & 2))
462 printf("Software reset enabled\n");
463 if (sis_verbose && (mec_mcr & 1))
464 printf("Power-down mode enabled\n");
465}
466
467/* Flush ports when simulator stops */
468
469void
470sim_halt()
471{
472#ifdef FAST_UART
473 flush_uart();
474#endif
475}
476
477int
478sim_stop(SIM_DESC sd)
479{
480 ctrl_c = 1;
481 return 1;
482}
483
484static void
485close_port()
486{
487 if (f1open && f1in != stdin)
488 fclose(f1in);
489 if (f2open && f2in != stdin)
490 fclose(f2in);
491}
492
493void
494exit_sim()
495{
496 close_port();
497}
498
499static void
500mec_reset()
501{
502 int i;
503
504 find = 0;
505 for (i = 0; i < 2; i++)
506 mec_ssa[i] = mec_sea[i] = mec_wpr[i] = 0;
507 mec_mcr = 0x01350014;
508 mec_iocr = 0;
509 mec_sfsr = 0x078;
510 mec_ffar = 0;
511 mec_ipr = 0;
512 mec_imr = 0x7ffe;
513 mec_isr = 0;
514 mec_icr = 0;
515 mec_ifr = 0;
516 mec_memcfg = 0x10000;
517 mec_wcr = -1;
518 mec_ersr = 0; /* MEC error and status register */
519 mec_tcr = 0; /* MEC test comtrol register */
520
521 decode_memcfg();
522 decode_wcr();
523 decode_mcr();
524
525 posted_irq = 0;
526 wnuma = wnumb = 0;
527 anum = aind = bnum = bind = 0;
528
529 uart_stat_reg = UARTA_SRE | UARTA_HRE | UARTB_SRE | UARTB_HRE;
530 uarta_data = uartb_data = UART_THE | UART_TSE;
531
532 rtc_counter = 0xffffffff;
533 rtc_reload = 0xffffffff;
534 rtc_scaler = 0xff;
535 rtc_enabled = 0;
536 rtc_cr = 0;
537 rtc_se = 0;
538
539 gpt_counter = 0xffffffff;
540 gpt_reload = 0xffffffff;
541 gpt_scaler = 0xffff;
542 gpt_enabled = 0;
543 gpt_cr = 0;
544 gpt_se = 0;
545
546 wdog_scaler = 255;
547 wdog_rst_delay = 255;
548 wdog_counter = 0xffff;
549 wdog_rston = 0;
550 wdog_status = init;
551
552#ifdef ERA
553 erareg = 0;
554#endif
555
556}
557
558
559
560static void
561mec_intack(level)
562 int32 level;
563{
564 int irq_test;
565
566 if (sis_verbose)
567 printf("interrupt %d acknowledged\n", level);
568 irq_test = mec_tcr & 0x80000;
569 if ((irq_test) && (mec_ifr & (1 << level)))
570 mec_ifr &= ~(1 << level);
571 else
572 mec_ipr &= ~(1 << level);
573 chk_irq();
574}
575
576static void
577chk_irq()
578{
579 int32 i;
580 uint32 itmp;
581 int old_irl;
582
583 old_irl = ext_irl;
584 if (mec_tcr & 0x80000) itmp = mec_ifr;
585 else itmp = 0;
586 itmp = ((mec_ipr | itmp) & ~mec_imr) & 0x0fffe;
587 ext_irl = 0;
588 if (itmp != 0) {
589 for (i = 15; i > 0; i--) {
590 if (((itmp >> i) & 1) != 0) {
591 if ((sis_verbose) && (i > old_irl))
592 printf("IU irl: %d\n", i);
593 ext_irl = i;
594 set_int(i, mec_intack, i);
595 break;
596 }
597 }
598 }
599}
600
601static void
602mec_irq(level)
603 int32 level;
604{
605 mec_ipr |= (1 << level);
606 chk_irq();
607}
608
609static void
610set_sfsr(fault, addr, asi, read)
611 uint32 fault;
612 uint32 addr;
613 uint32 asi;
614 uint32 read;
615{
616 if ((asi == 0xa) || (asi == 0xb)) {
617 mec_ffar = addr;
618 mec_sfsr = (fault << 3) | (!read << 15);
619 mec_sfsr |= ((mec_sfsr & 1) ^ 1) | (mec_sfsr & 1);
620 switch (asi) {
621 case 0xa:
622 mec_sfsr |= 0x0004;
623 break;
624 case 0xb:
625 mec_sfsr |= 0x1004;
626 break;
627 }
628 }
629}
630
631static int32
632mec_read(addr, asi, data)
633 uint32 addr;
634 uint32 asi;
635 uint32 *data;
636{
637
638 switch (addr & 0x0ff) {
639
640 case MEC_MCR: /* 0x00 */
641 *data = mec_mcr;
642 break;
643
644 case MEC_MEMCFG: /* 0x10 */
645 *data = mec_memcfg;
646 break;
647
648 case MEC_IOCR:
649 *data = mec_iocr; /* 0x14 */
650 break;
651
652 case MEC_SSA1: /* 0x20 */
653 *data = mec_ssa[0] | (mec_wpr[0] << 23);
654 break;
655 case MEC_SEA1: /* 0x24 */
656 *data = mec_sea[0];
657 break;
658 case MEC_SSA2: /* 0x28 */
659 *data = mec_ssa[1] | (mec_wpr[1] << 23);
660 break;
661 case MEC_SEA2: /* 0x2c */
662 *data = mec_sea[1];
663 break;
664
665 case MEC_ISR: /* 0x44 */
666 *data = mec_isr;
667 break;
668
669 case MEC_IPR: /* 0x48 */
670 *data = mec_ipr;
671 break;
672
673 case MEC_IMR: /* 0x4c */
674 *data = mec_imr;
675 break;
676
677 case MEC_IFR: /* 0x54 */
678 *data = mec_ifr;
679 break;
680
681 case MEC_RTC_COUNTER: /* 0x80 */
682 *data = rtc_counter_read();
683 break;
684 case MEC_RTC_SCALER: /* 0x84 */
685 if (rtc_enabled)
686 *data = rtc_scaler - (now() - rtc_scaler_start);
687 else
688 *data = rtc_scaler;
689 break;
690
691 case MEC_GPT_COUNTER: /* 0x88 */
692 *data = gpt_counter_read();
693 break;
694
695 case MEC_GPT_SCALER: /* 0x8c */
696 if (rtc_enabled)
697 *data = gpt_scaler - (now() - gpt_scaler_start);
698 else
699 *data = gpt_scaler;
700 break;
701
702
703 case MEC_SFSR: /* 0xA0 */
704 *data = mec_sfsr;
705 break;
706
707 case MEC_FFAR: /* 0xA4 */
708 *data = mec_ffar;
709 break;
710
711 case SIM_LOAD:
712 fname[find] = 0;
713 if (find == 0)
714 strcpy(fname, "simload");
715 find = bfd_load(fname);
716 if (find == -1)
717 *data = 0;
718 else
719 *data = 1;
720 find = 0;
721 break;
722
723 case MEC_ERSR: /* 0xB0 */
724 *data = mec_ersr;
725 break;
726
727 case MEC_TCR: /* 0xD0 */
728 *data = mec_tcr;
729 break;
730
731 case MEC_UARTA: /* 0xE0 */
732 case MEC_UARTB: /* 0xE4 */
733 if (asi != 0xb) {
734 set_sfsr(MEC_ACC, addr, asi, 1);
5831e29b 735 return 1;
c906108c
SS		 736 }
737 *data = read_uart(addr);
738 break;
739
740 case MEC_UART_CTRL: /* 0xE8 */
741
742 *data = read_uart(addr);
743 break;
744
20a0ffe3
JG		 745 case 0xF4: /* simulator RAM size in bytes */
746 *data = 4096*1024;
747 break;
748
749 case 0xF8: /* simulator ROM size in bytes */
750 *data = 1024*1024;
751 break;
752
c906108c
SS		 753 default:
754 set_sfsr(MEC_ACC, addr, asi, 1);
5831e29b 755 return 1;
c906108c
SS		 756 break;
757 }
5831e29b 758 return MOK;
c906108c
SS		 759}
760
761static int
762mec_write(addr, data)
763 uint32 addr;
764 uint32 data;
765{
766 if (sis_verbose > 1)
767 printf("MEC write a: %08x, d: %08x\n",addr,data);
768 switch (addr & 0x0ff) {
769
770 case MEC_MCR:
771 mec_mcr = data;
772 decode_mcr();
773 if (mec_mcr & 0x08000) mecparerror();
774 break;
775
776 case MEC_SFR:
777 if (mec_mcr & 0x2) {
778 sys_reset();
779 mec_ersr = 0x4000;
780 if (sis_verbose)
781 printf(" Software reset issued\n");
782 }
783 break;
784
785 case MEC_IOCR:
786 mec_iocr = data;
787 if (mec_iocr & 0xC0C0C0C0) mecparerror();
788 break;
789
790 case MEC_SSA1: /* 0x20 */
791 if (data & 0xFE000000) mecparerror();
792 mec_ssa[0] = data & 0x7fffff;
793 mec_wpr[0] = (data >> 23) & 0x03;
794 mem_accprot = mec_wpr[0] || mec_wpr[1];
795 if (sis_verbose && mec_wpr[0])
796 printf("Segment 1 memory protection enabled (0x02%06x - 0x02%06x)\n",
797 mec_ssa[0] << 2, mec_sea[0] << 2);
798 break;
799 case MEC_SEA1: /* 0x24 */
800 if (data & 0xFF800000) mecparerror();
801 mec_sea[0] = data & 0x7fffff;
802 break;
803 case MEC_SSA2: /* 0x28 */
804 if (data & 0xFE000000) mecparerror();
805 mec_ssa[1] = data & 0x7fffff;
806 mec_wpr[1] = (data >> 23) & 0x03;
807 mem_accprot = mec_wpr[0] || mec_wpr[1];
808 if (sis_verbose && mec_wpr[1])
809 printf("Segment 2 memory protection enabled (0x02%06x - 0x02%06x)\n",
810 mec_ssa[1] << 2, mec_sea[1] << 2);
811 break;
812 case MEC_SEA2: /* 0x2c */
813 if (data & 0xFF800000) mecparerror();
814 mec_sea[1] = data & 0x7fffff;
815 break;
816
817 case MEC_UARTA:
818 case MEC_UARTB:
819 if (data & 0xFFFFFF00) mecparerror();
820 case MEC_UART_CTRL:
821 if (data & 0xFF00FF00) mecparerror();
822 write_uart(addr, data);
823 break;
824
825 case MEC_GPT_RELOAD:
826 gpt_reload_set(data);
827 break;
828
829 case MEC_GPT_SCALER:
830 if (data & 0xFFFF0000) mecparerror();
831 gpt_scaler_set(data);
832 break;
833
834 case MEC_TIMER_CTRL:
835 if (data & 0xFFFFF0F0) mecparerror();
836 timer_ctrl(data);
837 break;
838
839 case MEC_RTC_RELOAD:
840 rtc_reload_set(data);
841 break;
842
843 case MEC_RTC_SCALER:
844 if (data & 0xFFFFFF00) mecparerror();
845 rtc_scaler_set(data);
846 break;
847
848 case MEC_SFSR: /* 0xA0 */
849 if (data & 0xFFFF0880) mecparerror();
850 mec_sfsr = 0x78;
851 break;
852
853 case MEC_ISR:
854 if (data & 0xFFFFE000) mecparerror();
855 mec_isr = data;
856 break;
857
858 case MEC_IMR: /* 0x4c */
859
860 if (data & 0xFFFF8001) mecparerror();
861 mec_imr = data & 0x7ffe;
862 chk_irq();
863 break;
864
865 case MEC_ICR: /* 0x50 */
866
867 if (data & 0xFFFF0001) mecparerror();
868 mec_ipr &= ~data & 0x0fffe;
869 chk_irq();
870 break;
871
872 case MEC_IFR: /* 0x54 */
873
874 if (mec_tcr & 0x080000) {
875 if (data & 0xFFFF0001) mecparerror();
876 mec_ifr = data & 0xfffe;
877 chk_irq();
878 }
879 break;
880 case SIM_LOAD:
881 fname[find++] = (char) data;
882 break;
883
884
885 case MEC_MEMCFG: /* 0x10 */
886 if (data & 0xC0E08000) mecparerror();
887 mec_memcfg = data;
888 decode_memcfg();
889 if (mec_memcfg & 0xc0e08000)
890 mecparerror();
891 break;
892
893 case MEC_WCR: /* 0x18 */
894 mec_wcr = data;
895 decode_wcr();
896 break;
897
898 case MEC_ERSR: /* 0xB0 */
899 if (mec_tcr & 0x100000)
900 if (data & 0xFFFFEFC0) mecparerror();
901 mec_ersr = data & 0x103f;
902 break;
903
904 case MEC_TCR: /* 0xD0 */
905 if (data & 0xFFE1FFC0) mecparerror();
906 mec_tcr = data & 0x1e003f;
907 break;
908
909 case MEC_WDOG: /* 0x60 */
910 wdog_scaler = (data >> 16) & 0x0ff;
911 wdog_counter = data & 0x0ffff;
912 wdog_rst_delay = data >> 24;
913 wdog_rston = 0;
914 if (wdog_status == stopped)
915 wdog_start();
916 wdog_status = enabled;
917 break;
918
919 case MEC_TRAPD: /* 0x64 */
920 if (wdog_status == init) {
921 wdog_status = disabled;
922 if (sis_verbose)
923 printf("Watchdog disabled\n");
924 }
925 break;
926
927 case MEC_PWDR:
928 if (mec_mcr & 1)
929 wait_for_irq();
930 break;
931
932 default:
933 set_sfsr(MEC_ACC, addr, 0xb, 0);
5831e29b 934 return 1;
c906108c
SS		 935 break;
936 }
5831e29b 937 return MOK;
c906108c
SS		 938}
939
940
941/* MEC UARTS */
942
943static int ifd1 = -1, ifd2 = -1, ofd1 = -1, ofd2 = -1;
944
945void
946init_stdio()
947{
948 if (dumbio)
949 return; /* do nothing */
950 if (!ifd1)
951 tcsetattr(0, TCSANOW, &ioc1);
952 if (!ifd2)
953 tcsetattr(0, TCSANOW, &ioc2);
954}
955
956void
957restore_stdio()
958{
959 if (dumbio)
960 return; /* do nothing */
961 if (!ifd1)
962 tcsetattr(0, TCSANOW, &iocold1);
963 if (!ifd2)
964 tcsetattr(0, TCSANOW, &iocold2);
965}
966
967#define DO_STDIO_READ( _fd_, _buf_, _len_ ) \
968 ( dumbio \
969 ? (0) /* no bytes read, no delay */ \
970 : read( _fd_, _buf_, _len_ ) )
971
972
973static void
974port_init()
975{
976
977 if (uben) {
978 f2in = stdin;
979 f1in = NULL;
980 f2out = stdout;
981 f1out = NULL;
982 } else {
983 f1in = stdin;
984 f2in = NULL;
985 f1out = stdout;
986 f2out = NULL;
987 }
988 if (uart_dev1[0] != 0)
989 if ((fd1 = open(uart_dev1, O_RDWR | O_NONBLOCK)) < 0) {
990 printf("Warning, couldn't open output device %s\n", uart_dev1);
991 } else {
992 if (sis_verbose)
993 printf("serial port A on %s\n", uart_dev1);
994 f1in = f1out = fdopen(fd1, "r+");
995 setbuf(f1out, NULL);
996 f1open = 1;
997 }
998 if (f1in) ifd1 = fileno(f1in);
999 if (ifd1 == 0) {
1000 if (sis_verbose)
1001 printf("serial port A on stdin/stdout\n");
1002 if (!dumbio) {
1003 tcgetattr(ifd1, &ioc1);
1004 iocold1 = ioc1;
1005 ioc1.c_lflag &= ~(ICANON | ECHO);
1006 ioc1.c_cc[VMIN] = 0;
1007 ioc1.c_cc[VTIME] = 0;
1008 }
1009 f1open = 1;
1010 }
1011
1012 if (f1out) {
1013 ofd1 = fileno(f1out);
1014 if (!dumbio && ofd1 == 1) setbuf(f1out, NULL);
1015 }
1016
1017 if (uart_dev2[0] != 0)
1018 if ((fd2 = open(uart_dev2, O_RDWR | O_NONBLOCK)) < 0) {
1019 printf("Warning, couldn't open output device %s\n", uart_dev2);
1020 } else {
1021 if (sis_verbose)
1022 printf("serial port B on %s\n", uart_dev2);
1023 f2in = f2out = fdopen(fd2, "r+");
1024 setbuf(f2out, NULL);
1025 f2open = 1;
1026 }
1027 if (f2in) ifd2 = fileno(f2in);
1028 if (ifd2 == 0) {
1029 if (sis_verbose)
1030 printf("serial port B on stdin/stdout\n");
1031 if (!dumbio) {
1032 tcgetattr(ifd2, &ioc2);
1033 iocold2 = ioc2;
1034 ioc2.c_lflag &= ~(ICANON | ECHO);
1035 ioc2.c_cc[VMIN] = 0;
1036 ioc2.c_cc[VTIME] = 0;
1037 }
1038 f2open = 1;
1039 }
1040
1041 if (f2out) {
1042 ofd2 = fileno(f2out);
1043 if (!dumbio && ofd2 == 1) setbuf(f2out, NULL);
1044 }
1045
1046 wnuma = wnumb = 0;
1047
1048}
1049
1050static uint32
1051read_uart(addr)
1052 uint32 addr;
1053{
1054
1055 unsigned tmp;
1056
1057 tmp = 0;
1058 switch (addr & 0xff) {
1059
1060 case 0xE0: /* UART 1 */
1061#ifndef _WIN32
1062#ifdef FAST_UART
1063
1064 if (aind < anum) {
1065 if ((aind + 1) < anum)
1066 mec_irq(4);
1067 return (0x700 | (uint32) aq[aind++]);
1068 } else {
1069 if (f1open) {
1070 anum = DO_STDIO_READ(ifd1, aq, UARTBUF);
1071 }
1072 if (anum > 0) {
1073 aind = 0;
1074 if ((aind + 1) < anum)
1075 mec_irq(4);
1076 return (0x700 | (uint32) aq[aind++]);
1077 } else {
1078 return (0x600 | (uint32) aq[aind]);
1079 }
1080
1081 }
1082#else
1083 tmp = uarta_data;
1084 uarta_data &= ~UART_DR;
1085 uart_stat_reg &= ~UARTA_DR;
1086 return tmp;
1087#endif
1088#else
5831e29b 1089 return 0;
c906108c
SS		 1090#endif
1091 break;
1092
1093 case 0xE4: /* UART 2 */
1094#ifndef _WIN32
1095#ifdef FAST_UART
1096 if (bind < bnum) {
1097 if ((bind + 1) < bnum)
1098 mec_irq(5);
1099 return (0x700 | (uint32) bq[bind++]);
1100 } else {
1101 if (f2open) {
1102 bnum = DO_STDIO_READ(ifd2, bq, UARTBUF);
1103 }
1104 if (bnum > 0) {
1105 bind = 0;
1106 if ((bind + 1) < bnum)
1107 mec_irq(5);
1108 return (0x700 | (uint32) bq[bind++]);
1109 } else {
1110 return (0x600 | (uint32) bq[bind]);
1111 }
1112
1113 }
1114#else
1115 tmp = uartb_data;
1116 uartb_data &= ~UART_DR;
1117 uart_stat_reg &= ~UARTB_DR;
1118 return tmp;
1119#endif
1120#else
5831e29b 1121 return 0;
c906108c
SS		 1122#endif
1123 break;
1124
1125 case 0xE8: /* UART status register */
1126#ifndef _WIN32
1127#ifdef FAST_UART
1128
1129 Ucontrol = 0;
1130 if (aind < anum) {
1131 Ucontrol |= 0x00000001;
1132 } else {
1133 if (f1open) {
1134 anum = DO_STDIO_READ(ifd1, aq, UARTBUF);
1135 }
1136 if (anum > 0) {
1137 Ucontrol |= 0x00000001;
1138 aind = 0;
1139 mec_irq(4);
1140 }
1141 }
1142 if (bind < bnum) {
1143 Ucontrol |= 0x00010000;
1144 } else {
1145 if (f2open) {
1146 bnum = DO_STDIO_READ(ifd2, bq, UARTBUF);
1147 }
1148 if (bnum > 0) {
1149 Ucontrol |= 0x00010000;
1150 bind = 0;
1151 mec_irq(5);
1152 }
1153 }
1154
1155 Ucontrol |= 0x00060006;
5831e29b 1156 return Ucontrol;
c906108c 1157#else
5831e29b 1158 return uart_stat_reg;
c906108c
SS		 1159#endif
1160#else
5831e29b 1161 return 0x00060006;
c906108c
SS		 1162#endif
1163 break;
1164 default:
1165 if (sis_verbose)
1166 printf("Read from unimplemented MEC register (%x)\n", addr);
1167
1168 }
5831e29b 1169 return 0;
c906108c
SS		 1170}
1171
1172static void
1173write_uart(addr, data)
1174 uint32 addr;
1175 uint32 data;
1176{
1177 unsigned char c;
1178
1179 c = (unsigned char) data;
1180 switch (addr & 0xff) {
1181
1182 case 0xE0: /* UART A */
1183#ifdef FAST_UART
1184 if (f1open) {
1185 if (wnuma < UARTBUF)
1186 wbufa[wnuma++] = c;
1187 else {
1188 while (wnuma)
1189 wnuma -= fwrite(wbufa, 1, wnuma, f1out);
1190 wbufa[wnuma++] = c;
1191 }
1192 }
1193 mec_irq(4);
1194#else
1195 if (uart_stat_reg & UARTA_SRE) {
1196 uarta_sreg = c;
1197 uart_stat_reg &= ~UARTA_SRE;
1198 event(uarta_tx, 0, UART_TX_TIME);
1199 } else {
1200 uarta_hreg = c;
1201 uart_stat_reg &= ~UARTA_HRE;
1202 }
1203#endif
1204 break;
1205
1206 case 0xE4: /* UART B */
1207#ifdef FAST_UART
1208 if (f2open) {
1209 if (wnumb < UARTBUF)
1210 wbufb[wnumb++] = c;
1211 else {
1212 while (wnumb)
1213 wnumb -= fwrite(wbufb, 1, wnumb, f2out);
1214 wbufb[wnumb++] = c;
1215 }
1216 }
1217 mec_irq(5);
1218#else
1219 if (uart_stat_reg & UARTB_SRE) {
1220 uartb_sreg = c;
1221 uart_stat_reg &= ~UARTB_SRE;
1222 event(uartb_tx, 0, UART_TX_TIME);
1223 } else {
1224 uartb_hreg = c;
1225 uart_stat_reg &= ~UARTB_HRE;
1226 }
1227#endif
1228 break;
1229 case 0xE8: /* UART status register */
1230#ifndef FAST_UART
1231 if (data & UARTA_CLR) {
1232 uart_stat_reg &= 0xFFFF0000;
1233 uart_stat_reg |= UARTA_SRE | UARTA_HRE;
1234 }
1235 if (data & UARTB_CLR) {
1236 uart_stat_reg &= 0x0000FFFF;
1237 uart_stat_reg |= UARTB_SRE | UARTB_HRE;
1238 }
1239#endif
1240 break;
1241 default:
1242 if (sis_verbose)
1243 printf("Write to unimplemented MEC register (%x)\n", addr);
1244
1245 }
1246}
1247
1248static void
1249flush_uart()
1250{
1251 while (wnuma && f1open)
1252 wnuma -= fwrite(wbufa, 1, wnuma, f1out);
1253 while (wnumb && f2open)
1254 wnumb -= fwrite(wbufb, 1, wnumb, f2out);
1255}
1256
1257
1258
1259static void
1260uarta_tx()
1261{
1262
1263 while (f1open && fwrite(&uarta_sreg, 1, 1, f1out) != 1);
1264 if (uart_stat_reg & UARTA_HRE) {
1265 uart_stat_reg |= UARTA_SRE;
1266 } else {
1267 uarta_sreg = uarta_hreg;
1268 uart_stat_reg |= UARTA_HRE;
1269 event(uarta_tx, 0, UART_TX_TIME);
1270 }
1271 mec_irq(4);
1272}
1273
1274static void
1275uartb_tx()
1276{
1277 while (f2open && fwrite(&uartb_sreg, 1, 1, f2out) != 1);
1278 if (uart_stat_reg & UARTB_HRE) {
1279 uart_stat_reg |= UARTB_SRE;
1280 } else {
1281 uartb_sreg = uartb_hreg;
1282 uart_stat_reg |= UARTB_HRE;
1283 event(uartb_tx, 0, UART_TX_TIME);
1284 }
1285 mec_irq(5);
1286}
1287
1288static void
1289uart_rx(arg)
1290 caddr_t arg;
1291{
1292 int32 rsize;
1293 char rxd;
1294
1295
1296 rsize = 0;
1297 if (f1open)
1298 rsize = DO_STDIO_READ(ifd1, &rxd, 1);
1299 if (rsize > 0) {
1300 uarta_data = UART_DR | rxd;
1301 if (uart_stat_reg & UARTA_HRE)
1302 uarta_data |= UART_THE;
1303 if (uart_stat_reg & UARTA_SRE)
1304 uarta_data |= UART_TSE;
1305 if (uart_stat_reg & UARTA_DR) {
1306 uart_stat_reg |= UARTA_OR;
1307 mec_irq(7); /* UART error interrupt */
1308 }
1309 uart_stat_reg |= UARTA_DR;
1310 mec_irq(4);
1311 }
1312 rsize = 0;
1313 if (f2open)
1314 rsize = DO_STDIO_READ(ifd2, &rxd, 1);
1315 if (rsize) {
1316 uartb_data = UART_DR | rxd;
1317 if (uart_stat_reg & UARTB_HRE)
1318 uartb_data |= UART_THE;
1319 if (uart_stat_reg & UARTB_SRE)
1320 uartb_data |= UART_TSE;
1321 if (uart_stat_reg & UARTB_DR) {
1322 uart_stat_reg |= UARTB_OR;
1323 mec_irq(7); /* UART error interrupt */
1324 }
1325 uart_stat_reg |= UARTB_DR;
1326 mec_irq(5);
1327 }
1328 event(uart_rx, 0, UART_RX_TIME);
1329}
1330
1331static void
1332uart_intr(arg)
1333 caddr_t arg;
1334{
1335 read_uart(0xE8); /* Check for UART interrupts every 1000 clk */
1336 flush_uart(); /* Flush UART ports */
1337 event(uart_intr, 0, UART_FLUSH_TIME);
1338}
1339
1340
1341static void
1342uart_irq_start()
1343{
1344#ifdef FAST_UART
1345 event(uart_intr, 0, UART_FLUSH_TIME);
1346#else
1347#ifndef _WIN32
1348 event(uart_rx, 0, UART_RX_TIME);
1349#endif
1350#endif
1351}
1352
1353/* Watch-dog */
1354
1355static void
1356wdog_intr(arg)
1357 caddr_t arg;
1358{
1359 if (wdog_status == disabled) {
1360 wdog_status = stopped;
1361 } else {
1362
1363 if (wdog_counter) {
1364 wdog_counter--;
1365 event(wdog_intr, 0, wdog_scaler + 1);
1366 } else {
1367 if (wdog_rston) {
1368 printf("Watchdog reset!\n");
1369 sys_reset();
1370 mec_ersr = 0xC000;
1371 } else {
1372 mec_irq(15);
1373 wdog_rston = 1;
1374 wdog_counter = wdog_rst_delay;
1375 event(wdog_intr, 0, wdog_scaler + 1);
1376 }
1377 }
1378 }
1379}
1380
1381static void
1382wdog_start()
1383{
1384 event(wdog_intr, 0, wdog_scaler + 1);
1385 if (sis_verbose)
1386 printf("Watchdog started, scaler = %d, counter = %d\n",
1387 wdog_scaler, wdog_counter);
1388}
1389
1390
1391/* MEC timers */
1392
1393
1394static void
1395rtc_intr(arg)
1396 caddr_t arg;
1397{
1398 if (rtc_counter == 0) {
1399
1400 mec_irq(13);
1401 if (rtc_cr)
1402 rtc_counter = rtc_reload;
1403 else
1404 rtc_se = 0;
1405 } else
1406 rtc_counter -= 1;
1407 if (rtc_se) {
1408 event(rtc_intr, 0, rtc_scaler + 1);
1409 rtc_scaler_start = now();
1410 rtc_enabled = 1;
1411 } else {
1412 if (sis_verbose)
1413 printf("RTC stopped\n\r");
1414 rtc_enabled = 0;
1415 }
1416}
1417
1418static void
1419rtc_start()
1420{
1421 if (sis_verbose)
1422 printf("RTC started (period %d)\n\r", rtc_scaler + 1);
1423 event(rtc_intr, 0, rtc_scaler + 1);
1424 rtc_scaler_start = now();
1425 rtc_enabled = 1;
1426}
1427
1428static uint32
1429rtc_counter_read()
1430{
5831e29b 1431 return rtc_counter;
c906108c
SS		 1432}
1433
1434static void
1435rtc_scaler_set(val)
1436 uint32 val;
1437{
1438 rtc_scaler = val & 0x0ff; /* eight-bit scaler only */
1439}
1440
1441static void
1442rtc_reload_set(val)
1443 uint32 val;
1444{
1445 rtc_reload = val;
1446}
1447
1448static void
1449gpt_intr(arg)
1450 caddr_t arg;
1451{
1452 if (gpt_counter == 0) {
1453 mec_irq(12);
1454 if (gpt_cr)
1455 gpt_counter = gpt_reload;
1456 else
1457 gpt_se = 0;
1458 } else
1459 gpt_counter -= 1;
1460 if (gpt_se) {
1461 event(gpt_intr, 0, gpt_scaler + 1);
1462 gpt_scaler_start = now();
1463 gpt_enabled = 1;
1464 } else {
1465 if (sis_verbose)
1466 printf("GPT stopped\n\r");
1467 gpt_enabled = 0;
1468 }
1469}
1470
1471static void
1472gpt_start()
1473{
1474 if (sis_verbose)
1475 printf("GPT started (period %d)\n\r", gpt_scaler + 1);
1476 event(gpt_intr, 0, gpt_scaler + 1);
1477 gpt_scaler_start = now();
1478 gpt_enabled = 1;
1479}
1480
1481static uint32
1482gpt_counter_read()
1483{
5831e29b 1484 return gpt_counter;
c906108c
SS		 1485}
1486
1487static void
1488gpt_scaler_set(val)
1489 uint32 val;
1490{
1491 gpt_scaler = val & 0x0ffff; /* 16-bit scaler */
1492}
1493
1494static void
1495gpt_reload_set(val)
1496 uint32 val;
1497{
1498 gpt_reload = val;
1499}
1500
1501static void
1502timer_ctrl(val)
1503 uint32 val;
1504{
1505
1506 rtc_cr = ((val & TCR_TCRCR) != 0);
1507 if (val & TCR_TCRCL) {
1508 rtc_counter = rtc_reload;
1509 }
1510 if (val & TCR_TCRSL) {
1511 }
1512 rtc_se = ((val & TCR_TCRSE) != 0);
1513 if (rtc_se && (rtc_enabled == 0))
1514 rtc_start();
1515
1516 gpt_cr = (val & TCR_GACR);
1517 if (val & TCR_GACL) {
1518 gpt_counter = gpt_reload;
1519 }
1520 if (val & TCR_GACL) {
1521 }
1522 gpt_se = (val & TCR_GASE) >> 2;
1523 if (gpt_se && (gpt_enabled == 0))
1524 gpt_start();
1525}
1526
1527
1528/* Retrieve data from target memory. MEM points to location from which
1529 to read the data; DATA points to words where retrieved data will be
1530 stored in host byte order. SZ contains log(2) of the number of bytes
1531 to retrieve, and can be 0 (1 byte), 1 (one half-word), 2 (one word),
1532 or 3 (two words). */
1533
1534static void
1535fetch_bytes (asi, mem, data, sz)
1536 int asi;
1537 unsigned char *mem;
1538 uint32 *data;
1539 int sz;
1540{
1541 if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN
1542 || asi == 8 || asi == 9) {
1543 switch (sz) {
1544 case 3:
1545 data[1] = (((uint32) mem[7]) & 0xff) |
1546 ((((uint32) mem[6]) & 0xff) << 8) |
1547 ((((uint32) mem[5]) & 0xff) << 16) |
1548 ((((uint32) mem[4]) & 0xff) << 24);
1549 /* Fall through to 2 */
1550 case 2:
1551 data[0] = (((uint32) mem[3]) & 0xff) |
1552 ((((uint32) mem[2]) & 0xff) << 8) |
1553 ((((uint32) mem[1]) & 0xff) << 16) |
1554 ((((uint32) mem[0]) & 0xff) << 24);
1555 break;
1556 case 1:
1557 data[0] = (((uint32) mem[1]) & 0xff) |
1558 ((((uint32) mem[0]) & 0xff) << 8);
1559 break;
1560 case 0:
1561 data[0] = mem[0] & 0xff;
1562 break;
1563
1564 }
1565 } else {
1566 switch (sz) {
1567 case 3:
1568 data[1] = ((((uint32) mem[7]) & 0xff) << 24) |
1569 ((((uint32) mem[6]) & 0xff) << 16) |
1570 ((((uint32) mem[5]) & 0xff) << 8) |
1571 (((uint32) mem[4]) & 0xff);
1572 /* Fall through to 4 */
1573 case 2:
1574 data[0] = ((((uint32) mem[3]) & 0xff) << 24) |
1575 ((((uint32) mem[2]) & 0xff) << 16) |
1576 ((((uint32) mem[1]) & 0xff) << 8) |
1577 (((uint32) mem[0]) & 0xff);
1578 break;
1579 case 1:
1580 data[0] = ((((uint32) mem[1]) & 0xff) << 8) |
1581 (((uint32) mem[0]) & 0xff);
1582 break;
1583 case 0:
1584 data[0] = mem[0] & 0xff;
1585 break;
1586 }
1587 }
1588}
1589
1590
1591/* Store data in target byte order. MEM points to location to store data;
1592 DATA points to words in host byte order to be stored. SZ contains log(2)
1593 of the number of bytes to retrieve, and can be 0 (1 byte), 1 (one half-word),
1594 2 (one word), or 3 (two words). */
1595
1596static void
1597store_bytes (mem, data, sz)
1598 unsigned char *mem;
1599 uint32 *data;
1600 int sz;
1601{
1602 if (CURRENT_TARGET_BYTE_ORDER == LITTLE_ENDIAN) {
1603 switch (sz) {
1604 case 3:
1605 mem[7] = (data[1] >> 24) & 0xff;
1606 mem[6] = (data[1] >> 16) & 0xff;
1607 mem[5] = (data[1] >> 8) & 0xff;
1608 mem[4] = data[1] & 0xff;
1609 /* Fall through to 2 */
1610 case 2:
1611 mem[3] = (data[0] >> 24) & 0xff;
1612 mem[2] = (data[0] >> 16) & 0xff;
1613 /* Fall through to 1 */
1614 case 1:
1615 mem[1] = (data[0] >> 8) & 0xff;
1616 /* Fall through to 0 */
1617 case 0:
1618 mem[0] = data[0] & 0xff;
1619 break;
1620 }
1621 } else {
1622 switch (sz) {
1623 case 3:
1624 mem[7] = data[1] & 0xff;
1625 mem[6] = (data[1] >> 8) & 0xff;
1626 mem[5] = (data[1] >> 16) & 0xff;
1627 mem[4] = (data[1] >> 24) & 0xff;
1628 /* Fall through to 2 */
1629 case 2:
1630 mem[3] = data[0] & 0xff;
1631 mem[2] = (data[0] >> 8) & 0xff;
1632 mem[1] = (data[0] >> 16) & 0xff;
1633 mem[0] = (data[0] >> 24) & 0xff;
1634 break;
1635 case 1:
1636 mem[1] = data[0] & 0xff;
1637 mem[0] = (data[0] >> 8) & 0xff;
1638 break;
1639 case 0:
1640 mem[0] = data[0] & 0xff;
1641 break;
1642
1643 }
1644 }
1645}
1646
1647
1648/* Memory emulation */
1649
1650int
1651memory_read(asi, addr, data, sz, ws)
1652 int32 asi;
1653 uint32 addr;
1654 uint32 *data;
1655 int32 sz;
1656 int32 *ws;
1657{
1658 int32 mexc;
1659
1660#ifdef ERRINJ
1661 if (errmec) {
1662 if (sis_verbose)
1663 printf("Inserted MEC error %d\n",errmec);
1664 set_sfsr(errmec, addr, asi, 1);
1665 if (errmec == 5) mecparerror();
1666 if (errmec == 6) iucomperr();
1667 errmec = 0;
5831e29b 1668 return 1;
c906108c 1669 }
d68c23cd 1670#endif
c906108c
SS		 1671
1672 if ((addr >= mem_ramstart) && (addr < (mem_ramstart + mem_ramsz))) {
1673 fetch_bytes (asi, &ramb[addr & mem_rammask], data, sz);
1674 *ws = mem_ramr_ws;
5831e29b 1675 return 0;
c906108c
SS		 1676 } else if ((addr >= MEC_START) && (addr < MEC_END)) {
1677 mexc = mec_read(addr, asi, data);
1678 if (mexc) {
1679 set_sfsr(MEC_ACC, addr, asi, 1);
1680 *ws = MEM_EX_WS;
1681 } else {
1682 *ws = 0;
1683 }
5831e29b 1684 return mexc;
c906108c
SS		 1685
1686#ifdef ERA
1687
1688 } else if (era) {
1689 if ((addr < 0x100000) ||
1690 ((addr>= 0x80000000) && (addr < 0x80100000))) {
1691 fetch_bytes (asi, &romb[addr & ROM_MASK], data, sz);
1692 *ws = 4;
5831e29b 1693 return 0;
c906108c
SS		 1694 } else if ((addr >= 0x10000000) &&
1695 (addr < (0x10000000 + (512 << (mec_iocr & 0x0f)))) &&
1696 (mec_iocr & 0x10)) {
1697 *data = erareg;
5831e29b 1698 return 0;
c906108c
SS		 1699 }
1700
1701 } else if (addr < mem_romsz) {
1702 fetch_bytes (asi, &romb[addr], data, sz);
1703 *ws = mem_romr_ws;
5831e29b 1704 return 0;
c906108c
SS		 1705
1706#else
1707 } else if (addr < mem_romsz) {
1708 fetch_bytes (asi, &romb[addr], data, sz);
1709 *ws = mem_romr_ws;
5831e29b 1710 return 0;
c906108c
SS		 1711#endif
1712
1713 }
1714
1715 printf("Memory exception at %x (illegal address)\n", addr);
1716 set_sfsr(UIMP_ACC, addr, asi, 1);
1717 *ws = MEM_EX_WS;
5831e29b 1718 return 1;
c906108c
SS		 1719}
1720
1721int
1722memory_write(asi, addr, data, sz, ws)
1723 int32 asi;
1724 uint32 addr;
1725 uint32 *data;
1726 int32 sz;
1727 int32 *ws;
1728{
1729 uint32 byte_addr;
1730 uint32 byte_mask;
1731 uint32 waddr;
1732 uint32 *ram;
1733 int32 mexc;
1734 int i;
1735 int wphit[2];
1736
1737#ifdef ERRINJ
1738 if (errmec) {
1739 if (sis_verbose)
1740 printf("Inserted MEC error %d\n",errmec);
1741 set_sfsr(errmec, addr, asi, 0);
1742 if (errmec == 5) mecparerror();
1743 if (errmec == 6) iucomperr();
1744 errmec = 0;
5831e29b 1745 return 1;
c906108c 1746 }
d68c23cd 1747#endif
c906108c
SS		 1748
1749 if ((addr >= mem_ramstart) && (addr < (mem_ramstart + mem_ramsz))) {
1750 if (mem_accprot) {
1751
1752 waddr = (addr & 0x7fffff) >> 2;
1753 for (i = 0; i < 2; i++)
1754 wphit[i] =
1755 (((asi == 0xa) && (mec_wpr[i] & 1)) ||
1756 ((asi == 0xb) && (mec_wpr[i] & 2))) &&
1757 ((waddr >= mec_ssa[i]) && ((waddr | (sz == 3)) < mec_sea[i]));
1758
1759 if (((mem_blockprot) && (wphit[0] || wphit[1])) ||
1760 ((!mem_blockprot) &&
1761 !((mec_wpr[0] && wphit[0]) || (mec_wpr[1] && wphit[1]))
1762 )) {
1763 if (sis_verbose)
1764 printf("Memory access protection error at 0x%08x\n", addr);
1765 set_sfsr(PROT_EXC, addr, asi, 0);
1766 *ws = MEM_EX_WS;
5831e29b 1767 return 1;
c906108c
SS		 1768 }
1769 }
1770
1771 store_bytes (&ramb[addr & mem_rammask], data, sz);
1772
1773 switch (sz) {
1774 case 0:
1775 case 1:
1776 *ws = mem_ramw_ws + 3;
1777 break;
1778 case 2:
1779 *ws = mem_ramw_ws;
1780 break;
1781 case 3:
1782 *ws = 2 * mem_ramw_ws + STD_WS;
1783 break;
1784 }
5831e29b 1785 return 0;
c906108c
SS		 1786 } else if ((addr >= MEC_START) && (addr < MEC_END)) {
1787 if ((sz != 2) || (asi != 0xb)) {
1788 set_sfsr(MEC_ACC, addr, asi, 0);
1789 *ws = MEM_EX_WS;
5831e29b 1790 return 1;
c906108c
SS		 1791 }
1792 mexc = mec_write(addr, *data);
1793 if (mexc) {
1794 set_sfsr(MEC_ACC, addr, asi, 0);
1795 *ws = MEM_EX_WS;
1796 } else {
1797 *ws = 0;
1798 }
5831e29b 1799 return mexc;
c906108c
SS		 1800
1801#ifdef ERA
1802
1803 } else if (era) {
1804 if ((erareg & 2) &&
1805 ((addr < 0x100000) || ((addr >= 0x80000000) && (addr < 0x80100000)))) {
1806 addr &= ROM_MASK;
1807 *ws = sz == 3 ? 8 : 4;
1808 store_bytes (&romb[addr], data, sz);
5831e29b 1809 return 0;
c906108c
SS		 1810 } else if ((addr >= 0x10000000) &&
1811 (addr < (0x10000000 + (512 << (mec_iocr & 0x0f)))) &&
1812 (mec_iocr & 0x10)) {
1813 erareg = *data & 0x0e;
5831e29b 1814 return 0;
c906108c
SS		 1815 }
1816
1817 } else if ((addr < mem_romsz) && (mec_memcfg & 0x10000) && (wrp) &&
1818 (((mec_memcfg & 0x20000) && (sz > 1)) ||
1819 (!(mec_memcfg & 0x20000) && (sz == 0)))) {
1820
1821 *ws = mem_romw_ws + 1;
1822 if (sz == 3)
1823 *ws += mem_romw_ws + STD_WS;
1824 store_bytes (&romb[addr], data, sz);
5831e29b 1825 return 0;
c906108c
SS		 1826
1827#else
1828 } else if ((addr < mem_romsz) && (mec_memcfg & 0x10000) && (wrp) &&
1829 (((mec_memcfg & 0x20000) && (sz > 1)) ||
1830 (!(mec_memcfg & 0x20000) && (sz == 0)))) {
1831
1832 *ws = mem_romw_ws + 1;
1833 if (sz == 3)
1834 *ws += mem_romw_ws + STD_WS;
1835 store_bytes (&romb[addr], data, sz);
5831e29b 1836 return 0;
c906108c
SS		 1837
1838#endif
1839
1840 }
1841
1842 *ws = MEM_EX_WS;
1843 set_sfsr(UIMP_ACC, addr, asi, 0);
5831e29b 1844 return 1;
c906108c
SS		 1845}
1846
1847static unsigned char *
1848get_mem_ptr(addr, size)
1849 uint32 addr;
1850 uint32 size;
1851{
1852 if ((addr + size) < ROM_SZ) {
5831e29b 1853 return &romb[addr];
c906108c 1854 } else if ((addr >= mem_ramstart) && ((addr + size) < mem_ramend)) {
5831e29b 1855 return &ramb[addr & mem_rammask];
c906108c
SS		 1856 }
1857
1858#ifdef ERA
1859 else if ((era) && ((addr <0x100000) ||
1860 ((addr >= (unsigned) 0x80000000) && ((addr + size) < (unsigned) 0x80100000)))) {
5831e29b 1861 return &romb[addr & ROM_MASK];
c906108c
SS		 1862 }
1863#endif
1864
5831e29b 1865 return (char *) -1;
c906108c
SS		 1866}
1867
1868int
1869sis_memory_write(addr, data, length)
94110024
JS		 1870 uint32 addr;
1871 const unsigned char *data;
1872 uint32 length;
c906108c
SS		 1873{
1874 char *mem;
1875
1876 if ((mem = get_mem_ptr(addr, length)) == ((char *) -1))
5831e29b 1877 return 0;
c906108c
SS		 1878
1879 memcpy(mem, data, length);
5831e29b 1880 return length;
c906108c
SS		 1881}
1882
1883int
1884sis_memory_read(addr, data, length)
1885 uint32 addr;
1886 char *data;
1887 uint32 length;
1888{
1889 char *mem;
1890
1891 if ((mem = get_mem_ptr(addr, length)) == ((char *) -1))
5831e29b 1892 return 0;
c906108c
SS		 1893
1894 memcpy(data, mem, length);
5831e29b 1895 return length;
c906108c 1896}
20a0ffe3
JG		 1897
1898extern struct pstate sregs;
1899
1900void
1901boot_init (void)
1902{
1903 mec_write(MEC_WCR, 0); /* zero waitstates */
1904 mec_write(MEC_TRAPD, 0); /* turn off watch-dog */
1905 mec_write(MEC_RTC_SCALER, sregs.freq - 1); /* generate 1 MHz RTC tick */
1906 mec_write(MEC_MEMCFG, (3 << 18) | (4 << 10)); /* 1 MB ROM, 4 MB RAM */
1907 sregs.wim = 2;
1908 sregs.psr = 0x110010e0;
1909 sregs.r[30] = RAM_END;
1910 sregs.r[14] = sregs.r[30] - 96 * 4;
1911 mec_mcr |= 1; /* power-down enabled */
1912}
GDB Binutils - Deliverables
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