Add znver1 processor
[deliverable/binutils-gdb.git] / sim / erc32 / sis.c
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1/*
2 * This file is part of SIS.
3 *
4 * SIS, SPARC instruction simulator. Copyright (C) 1995 Jiri Gaisler, European
5 * Space Agency
6 *
7 * This program is free software; you can redistribute it and/or modify it under
8 * the terms of the GNU General Public License as published by the Free
3fd725ef 9 * Software Foundation; either version 3 of the License, or (at your option)
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10 * any later version.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
51b318de 18 * this program; if not, see <http://www.gnu.org/licenses/>.
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19 *
20 */
21
22#include "config.h"
23#include <signal.h>
24#include <string.h>
25#ifdef HAVE_STDLIB_H
26#include <stdlib.h>
27#endif
28#include <stdio.h>
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29#include <sys/fcntl.h>
30#include "sis.h"
31#include <dis-asm.h>
32#include "sim-config.h"
33
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34#define VAL(x) strtol(x,(char **)NULL,0)
35
36/* Structures and functions from readline library */
37
5634e839
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38#include "readline/readline.h"
39#include "readline/history.h"
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40
41/* Command history buffer length - MUST be binary */
42#define HIST_LEN 64
43
44extern struct disassemble_info dinfo;
45extern struct pstate sregs;
46extern struct estate ebase;
47
48extern int ctrl_c;
49extern int nfp;
50extern int ift;
51extern int wrp;
52extern int rom8;
53extern int uben;
54extern int sis_verbose;
55extern char *sis_version;
56extern struct estate ebase;
57extern struct evcell evbuf[];
58extern struct irqcell irqarr[];
59extern int irqpend, ext_irl;
60extern int termsave;
61extern int sparclite;
62extern int dumbio;
63extern char uart_dev1[];
64extern char uart_dev2[];
65extern uint32 last_load_addr;
66
67#ifdef ERA
68extern int era;
69#endif
70
71int
72run_sim(sregs, icount, dis)
73 struct pstate *sregs;
94110024 74 uint64 icount;
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75 int dis;
76{
77 int irq, mexc, deb, asi;
78
96d67095 79 sregs->starttime = get_time();
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80 init_stdio();
81 if (sregs->err_mode) icount = 0;
82 deb = dis || sregs->histlen || sregs->bptnum;
83 irq = 0;
84 while (icount > 0) {
85
86 if (sregs->psr & 0x080)
87 asi = 9;
88 else
89 asi = 8;
90 mexc = memory_read(asi, sregs->pc, &sregs->inst, 2, &sregs->hold);
91 sregs->icnt = 1;
92 if (sregs->annul) {
93 sregs->annul = 0;
94 sregs->pc = sregs->npc;
95 sregs->npc = sregs->npc + 4;
96 } else {
97 sregs->fhold = 0;
98 if (ext_irl) irq = check_interrupts(sregs);
99 if (!irq) {
100 if (mexc) {
101 sregs->trap = I_ACC_EXC;
102 } else {
103 if (deb) {
104 if ((sregs->bphit = check_bpt(sregs)) != 0) {
105 restore_stdio();
106 return (BPT_HIT);
107 }
108 if (sregs->histlen) {
109 sregs->histbuf[sregs->histind].addr = sregs->pc;
110 sregs->histbuf[sregs->histind].time = ebase.simtime;
111 sregs->histind++;
112 if (sregs->histind >= sregs->histlen)
113 sregs->histind = 0;
114 }
115 if (dis) {
116 printf(" %8u ", ebase.simtime);
117 dis_mem(sregs->pc, 1, &dinfo);
118 }
119 }
120 dispatch_instruction(sregs);
121 icount--;
122 }
123 }
124 if (sregs->trap) {
125 irq = 0;
126 sregs->err_mode = execute_trap(sregs);
127 if (sregs->err_mode) {
128 error_mode(sregs->pc);
129 icount = 0;
130 }
131 }
132 }
133 advance_time(sregs);
134 if (ctrl_c || (sregs->tlimit <= ebase.simtime)) {
135 icount = 0;
136 if (sregs->tlimit <= ebase.simtime) sregs->tlimit = -1;
137 }
138 }
96d67095 139 sregs->tottime += get_time() - sregs->starttime;
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140 restore_stdio();
141 if (sregs->err_mode)
142 return (ERROR);
143 if (ctrl_c) {
144 ctrl_c = 0;
145 return (CTRL_C);
146 }
147 return (TIME_OUT);
148}
149
150int
151main(argc, argv)
152 int argc;
153 char **argv;
154{
155
156 int cont = 1;
157 int stat = 1;
158 int freq = 14;
159 int copt = 0;
160
161 char *cfile, *bacmd;
162 char *cmdq[HIST_LEN];
163 int cmdi = 0;
164 int i;
e26473a1 165 int lfile = 0;
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166
167 cfile = 0;
168 for (i = 0; i < 64; i++)
169 cmdq[i] = 0;
14e1f957 170 printf("\n SIS - SPARC instruction simulator %s, copyright Jiri Gaisler 1995\n", sis_version);
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171 printf(" Bug-reports to jgais@wd.estec.esa.nl\n\n");
172 while (stat < argc) {
173 if (argv[stat][0] == '-') {
174 if (strcmp(argv[stat], "-v") == 0) {
175 sis_verbose = 1;
176 } else if (strcmp(argv[stat], "-c") == 0) {
177 if ((stat + 1) < argc) {
178 copt = 1;
179 cfile = argv[++stat];
180 }
181 } else if (strcmp(argv[stat], "-nfp") == 0)
182 nfp = 1;
183 else if (strcmp(argv[stat], "-ift") == 0)
184 ift = 1;
185 else if (strcmp(argv[stat], "-wrp") == 0)
186 wrp = 1;
187 else if (strcmp(argv[stat], "-rom8") == 0)
188 rom8 = 1;
189 else if (strcmp(argv[stat], "-uben") == 0)
190 uben = 1;
191 else if (strcmp(argv[stat], "-uart1") == 0) {
192 if ((stat + 1) < argc)
193 strcpy(uart_dev1, argv[++stat]);
194 } else if (strcmp(argv[stat], "-uart2") == 0) {
195 if ((stat + 1) < argc)
196 strcpy(uart_dev2, argv[++stat]);
197 } else if (strcmp(argv[stat], "-freq") == 0) {
198 if ((stat + 1) < argc)
199 freq = VAL(argv[++stat]);
200 } else if (strcmp(argv[stat], "-sparclite") == 0) {
201 sparclite = 1;
202#ifdef ERA
203 } else if (strcmp(argv[stat], "-era") == 0) {
204 era = 1;
205#endif
206 } else if (strcmp(argv[stat], "-dumbio") == 0) {
207 dumbio = 1;
208 } else {
209 printf("unknown option %s\n", argv[stat]);
210 usage();
211 exit(1);
212 }
213 } else {
e26473a1 214 lfile = stat;
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215 }
216 stat++;
217 }
218 if (nfp)
219 printf("FPU disabled\n");
220#ifdef ERA
221 if (era)
222 printf("ERA ECC emulation enabled\n");
223#endif
224 sregs.freq = freq;
225
226 INIT_DISASSEMBLE_INFO(dinfo, stdout, (fprintf_ftype) fprintf);
227 dinfo.endian = BFD_ENDIAN_BIG;
228
229 termsave = fcntl(0, F_GETFL, 0);
230 using_history();
231 init_signals();
232 ebase.simtime = 0;
233 reset_all();
234 init_bpt(&sregs);
235 init_sim();
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236 if (lfile)
237 last_load_addr = bfd_load(argv[lfile]);
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238#ifdef STAT
239 reset_stat(&sregs);
240#endif
241
242 if (copt) {
243 bacmd = (char *) malloc(256);
244 strcpy(bacmd, "batch ");
245 strcat(bacmd, cfile);
246 exec_cmd(&sregs, bacmd);
247 }
248 while (cont) {
249
250 if (cmdq[cmdi] != 0) {
251#if 0
252 remove_history(cmdq[cmdi]);
253#else
254 remove_history(cmdi);
255#endif
256 free(cmdq[cmdi]);
257 cmdq[cmdi] = 0;
258 }
259 cmdq[cmdi] = readline("sis> ");
260 if (cmdq[cmdi] && *cmdq[cmdi])
261 add_history(cmdq[cmdi]);
262 if (cmdq[cmdi])
263 stat = exec_cmd(&sregs, cmdq[cmdi]);
264 else {
265 puts("\n");
266 exit(0);
267 }
268 switch (stat) {
269 case OK:
270 break;
271 case CTRL_C:
272 printf("\b\bInterrupt!\n");
273 case TIME_OUT:
274 printf(" Stopped at time %d (%.3f ms)\n", ebase.simtime,
275 ((double) ebase.simtime / (double) sregs.freq) / 1000.0);
276 break;
277 case BPT_HIT:
278 printf("breakpoint at 0x%08x reached\n", sregs.pc);
279 sregs.bphit = 1;
280 break;
281 case ERROR:
282 printf("IU in error mode (%d)\n", sregs.trap);
283 stat = 0;
284 printf(" %8d ", ebase.simtime);
285 dis_mem(sregs.pc, 1, &dinfo);
286 break;
287 default:
288 break;
289 }
290 ctrl_c = 0;
291 stat = OK;
292
293 cmdi = (cmdi + 1) & (HIST_LEN - 1);
294
295 }
296 return 0;
297}
298
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