[deliverable/binutils-gdb.git] / sim / erc32 / sis.h

/*
 * This file is part of SIS.
 * 
 * ERC32SIM, SPARC instruction simulator. Copyright (C) 1995 Jiri Gaisler,
 * European Space Agency
 * 
 * This program is free software; you can redistribute it and/or modify it under
 * the terms of the GNU General Public License as published by the Free
 * Software Foundation; either version 3 of the License, or (at your option)
 * any later version.
 * 
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 * 
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, see <http://www.gnu.org/licenses/>.
 * 
 */

#include "config.h"
#include "ansidecl.h"
#include "gdb/callback.h"
#include "gdb/remote-sim.h"
#include <sim-config.h>
#include <stdint.h>

#if WITH_HOST_BYTE_ORDER == BIG_ENDIAN
#define HOST_BIG_ENDIAN
#define EBT 0
#else
#define HOST_LITTLE_ENDIAN
#define EBT 3
#endif

#define I_ACC_EXC 1

/* Maximum events in event queue */
#define EVENT_MAX	256

/* Maximum # of floating point queue */
#define FPUQN	1

/* Maximum # of breakpoints */
#define BPT_MAX	256

struct histype {
    unsigned        addr;
    unsigned        time;
};

/* type definitions */

typedef short int int16;	/* 16-bit signed int */
typedef unsigned short int uint16;	/* 16-bit unsigned int */
typedef int     int32;		/* 32-bit signed int */
typedef unsigned int uint32;	/* 32-bit unsigned int */
typedef float   float32;	/* 32-bit float */
typedef double  float64;	/* 64-bit float */

typedef uint64_t uint64; /* 64-bit unsigned int */
typedef int64_t int64;	   /* 64-bit signed int */

struct pstate {

    float64         fd[16];	/* FPU registers */
#ifdef HOST_LITTLE_ENDIAN
    float32         fs[32];
    float32        *fdp;
#else
    float32        *fs;
#endif
    int32          *fsi;
    uint32          fsr;
    int32           fpstate;
    uint32          fpq[FPUQN * 2];
    uint32          fpqn;
    uint32          ftime;
    uint32          flrd;
    uint32          frd;
    uint32          frs1;
    uint32          frs2;
    uint32          fpu_pres;	/* FPU present (0 = No, 1 = Yes) */

    uint32          psr;	/* IU registers */
    uint32          tbr;
    uint32          wim;
    uint32          g[8];
    uint32          r[128];
    uint32          y;
    uint32          asr17;      /* Single vector trapping */
    uint32          pc, npc;


    uint32          trap;	/* Current trap type */
    uint32          annul;	/* Instruction annul */
    uint32          data;	/* Loaded data	     */
    uint32          inst;	/* Current instruction */
    uint32          asi;	/* Current ASI */
    uint32          err_mode;	/* IU error mode */
    uint32          breakpoint;
    uint32          bptnum;
    uint32          bphit;
    uint32          bpts[BPT_MAX];	/* Breakpoints */

    uint32          ltime;	/* Load interlock time */
    uint32          hold;	/* IU hold cycles in current inst */
    uint32          fhold;	/* FPU hold cycles in current inst */
    uint32          icnt;	/* Instruction cycles in curr inst */

    uint32          histlen;	/* Trace history management */
    uint32          histind;
    struct histype *histbuf;
    float32         freq;	/* Simulated processor frequency */


    double          tottime;
    uint64          ninst;
    uint64          fholdt;
    uint64          holdt;
    uint64          icntt;
    uint64          finst;
    uint64          simstart;
    double          starttime;
    uint64          tlimit;	/* Simulation time limit */
    uint64          pwdtime;	/* Cycles in power-down mode */
    uint64          nstore;	/* Number of load instructions */
    uint64          nload;	/* Number of store instructions */
    uint64          nannul;	/* Number of annuled instructions */
    uint64          nbranch;	/* Number of branch instructions */
    uint32          ildreg;	/* Destination of last load instruction */
    uint64          ildtime;	/* Last time point for load dependency */

    int             rett_err;	/* IU in jmpl/restore error state (Rev.0) */
    int             jmpltime;
};

struct evcell {
    void            (*cfunc) ();
    int32           arg;
    uint64          time;
    struct evcell  *nxt;
};

struct estate {
    struct evcell   eq;
    struct evcell  *freeq;
    uint64          simtime;
};

struct irqcell {
    void            (*callback) ();
    int32           arg;
};


#define OK 0
#define TIME_OUT 1
#define BPT_HIT 2
#define ERROR 3
#define CTRL_C 4

/* Prototypes  */

/* erc32.c */
extern void	init_sim (void);
extern void	reset (void);
extern void	error_mode (uint32 pc);
extern void	sim_halt (void);
extern void	exit_sim (void);
extern void	init_stdio (void);
extern void	restore_stdio (void);
extern int	memory_iread (uint32 addr, uint32 *data, int32 *ws);
extern int	memory_read (int32 asi, uint32 addr, uint32 *data,
			     int32 sz, int32 *ws);
extern int	memory_write (int32 asi, uint32 addr, uint32 *data,
			      int32 sz, int32 *ws);
extern int	sis_memory_write (uint32 addr,
				  const unsigned char *data, uint32 length);
extern int	sis_memory_read (uint32 addr, char *data,
				 uint32 length);

/* func.c */
extern struct pstate  sregs;
extern void	set_regi (struct pstate *sregs, int32 reg,
			  uint32 rval);
extern void	get_regi (struct pstate *sregs, int32 reg, char *buf);
extern int	exec_cmd (struct pstate *sregs, const char *cmd);
extern void	reset_stat (struct pstate  *sregs);
extern void	show_stat (struct pstate  *sregs);
extern void	init_bpt (struct pstate  *sregs);
extern void	init_signals (void);

struct disassemble_info;
extern void	dis_mem (uint32 addr, uint32 len,
			 struct disassemble_info *info);
extern void	event (void (*cfunc) (), int32 arg, uint64 delta);
extern void	set_int (int32 level, void (*callback) (), int32 arg);
extern void	advance_time (struct pstate  *sregs);
extern uint32	now (void);
extern int	wait_for_irq (void);
extern int	check_bpt (struct pstate *sregs);
extern void	reset_all (void);
extern void	sys_reset (void);
extern void	sys_halt (void);
extern int	bfd_load (const char *fname);
extern double	get_time (void);

/* exec.c */
extern int	dispatch_instruction (struct pstate *sregs);
extern int	execute_trap (struct pstate *sregs);
extern int	check_interrupts (struct pstate  *sregs);
extern void	init_regs (struct pstate *sregs);

/* interf.c */
extern int	run_sim (struct pstate *sregs,
			 uint64 icount, int dis);

/* float.c */
extern int	get_accex (void);
extern void	clear_accex (void);
extern void	set_fsr (uint32 fsr);

/* help.c */
extern void	usage (void);
extern void	gen_help (void);
Commit	Line	Data
c906108c SS	1	/*
	2	* This file is part of SIS.
	3	*
	4	* ERC32SIM, SPARC instruction simulator. Copyright (C) 1995 Jiri Gaisler,
	5	* European Space Agency
	6	*
	7	* This program is free software; you can redistribute it and/or modify it under
	8	* the terms of the GNU General Public License as published by the Free
3fd725ef	9	* Software Foundation; either version 3 of the License, or (at your option)
c906108c SS	10	* any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful, but WITHOUT
	13	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	14	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	15	* more details.
	16	*
	17	* You should have received a copy of the GNU General Public License along with
51b318de	18	* this program; if not, see <http://www.gnu.org/licenses/>.
c906108c SS	19	*
	20	*/
	21
9a210f30	22	#include "config.h"
c906108c	23	#include "ansidecl.h"
3c25f8c7 AC	24	#include "gdb/callback.h"
3c25f8c7 AC	25	#include "gdb/remote-sim.h"
9c5f41df	26	#include <sim-config.h>
638fcdad JG	27	#include <stdint.h>
638fcdad JG	28
9c5f41df JG	29	#if WITH_HOST_BYTE_ORDER == BIG_ENDIAN
9c5f41df JG	30	#define HOST_BIG_ENDIAN
d3e9b40a	31	#define EBT 0
9c5f41df JG	32	#else
9c5f41df JG	33	#define HOST_LITTLE_ENDIAN
d3e9b40a	34	#define EBT 3
9c5f41df	35	#endif
c906108c SS	36
	37	#define I_ACC_EXC 1
	38
	39	/* Maximum events in event queue */
	40	#define EVENT_MAX 256
	41
	42	/* Maximum # of floating point queue */
	43	#define FPUQN 1
	44
	45	/* Maximum # of breakpoints */
	46	#define BPT_MAX 256
	47
	48	struct histype {
	49	unsigned addr;
	50	unsigned time;
	51	};
	52
	53	/* type definitions */
	54
	55	typedef short int int16; /* 16-bit signed int */
	56	typedef unsigned short int uint16; /* 16-bit unsigned int */
	57	typedef int int32; /* 32-bit signed int */
	58	typedef unsigned int uint32; /* 32-bit unsigned int */
	59	typedef float float32; /* 32-bit float */
	60	typedef double float64; /* 64-bit float */
	61
638fcdad JG	62	typedef uint64_t uint64; /* 64-bit unsigned int */
638fcdad JG	63	typedef int64_t int64; /* 64-bit signed int */
c906108c SS	64
	65	struct pstate {
	66
	67	float64 fd[16]; /* FPU registers */
9c5f41df	68	#ifdef HOST_LITTLE_ENDIAN
c906108c SS	69	float32 fs[32];
	70	float32 *fdp;
	71	#else
	72	float32 *fs;
	73	#endif
	74	int32 *fsi;
	75	uint32 fsr;
	76	int32 fpstate;
	77	uint32 fpq[FPUQN * 2];
	78	uint32 fpqn;
	79	uint32 ftime;
	80	uint32 flrd;
	81	uint32 frd;
	82	uint32 frs1;
	83	uint32 frs2;
	84	uint32 fpu_pres; /* FPU present (0 = No, 1 = Yes) */
	85
	86	uint32 psr; /* IU registers */
	87	uint32 tbr;
	88	uint32 wim;
	89	uint32 g[8];
	90	uint32 r[128];
	91	uint32 y;
	92	uint32 asr17; /* Single vector trapping */
	93	uint32 pc, npc;
	94
	95
	96	uint32 trap; /* Current trap type */
	97	uint32 annul; /* Instruction annul */
	98	uint32 data; /* Loaded data */
	99	uint32 inst; /* Current instruction */
	100	uint32 asi; /* Current ASI */
	101	uint32 err_mode; /* IU error mode */
	102	uint32 breakpoint;
	103	uint32 bptnum;
	104	uint32 bphit;
	105	uint32 bpts[BPT_MAX]; /* Breakpoints */
	106
	107	uint32 ltime; /* Load interlock time */
	108	uint32 hold; /* IU hold cycles in current inst */
	109	uint32 fhold; /* FPU hold cycles in current inst */
	110	uint32 icnt; /* Instruction cycles in curr inst */
	111
	112	uint32 histlen; /* Trace history management */
	113	uint32 histind;
	114	struct histype *histbuf;
	115	float32 freq; /* Simulated processor frequency */
	116
	117
96d67095	118	double tottime;
94110024 JS	119	uint64 ninst;
	120	uint64 fholdt;
	121	uint64 holdt;
	122	uint64 icntt;
	123	uint64 finst;
	124	uint64 simstart;
96d67095	125	double starttime;
94110024 JS	126	uint64 tlimit; /* Simulation time limit */
	127	uint64 pwdtime; /* Cycles in power-down mode */
	128	uint64 nstore; /* Number of load instructions */
	129	uint64 nload; /* Number of store instructions */
	130	uint64 nannul; /* Number of annuled instructions */
	131	uint64 nbranch; /* Number of branch instructions */
c906108c	132	uint32 ildreg; /* Destination of last load instruction */
94110024	133	uint64 ildtime; /* Last time point for load dependency */
c906108c SS	134
	135	int rett_err; /* IU in jmpl/restore error state (Rev.0) */
	136	int jmpltime;
	137	};
	138
	139	struct evcell {
	140	void (*cfunc) ();
	141	int32 arg;
94110024	142	uint64 time;
c906108c SS	143	struct evcell *nxt;
	144	};
	145
	146	struct estate {
	147	struct evcell eq;
	148	struct evcell *freeq;
94110024	149	uint64 simtime;
c906108c SS	150	};
	151
	152	struct irqcell {
	153	void (*callback) ();
	154	int32 arg;
	155	};
	156
	157
	158	#define OK 0
	159	#define TIME_OUT 1
	160	#define BPT_HIT 2
	161	#define ERROR 3
	162	#define CTRL_C 4
	163
	164	/* Prototypes */
	165
	166	/* erc32.c */
bdca5ee4 TT	167	extern void init_sim (void);
	168	extern void reset (void);
	169	extern void error_mode (uint32 pc);
	170	extern void sim_halt (void);
	171	extern void exit_sim (void);
	172	extern void init_stdio (void);
	173	extern void restore_stdio (void);
102b920e	174	extern int memory_iread (uint32 addr, uint32 data, int32 ws);
bdca5ee4 TT	175	extern int memory_read (int32 asi, uint32 addr, uint32 *data,
	176	int32 sz, int32 *ws);
	177	extern int memory_write (int32 asi, uint32 addr, uint32 *data,
	178	int32 sz, int32 *ws);
	179	extern int sis_memory_write (uint32 addr,
	180	const unsigned char *data, uint32 length);
	181	extern int sis_memory_read (uint32 addr, char *data,
	182	uint32 length);
c906108c SS	183
c906108c SS	184	/* func.c */
102b920e	185	extern struct pstate sregs;
bdca5ee4 TT	186	extern void set_regi (struct pstate *sregs, int32 reg,
	187	uint32 rval);
	188	extern void get_regi (struct pstate sregs, int32 reg, char buf);
510d2751	189	extern int exec_cmd (struct pstate sregs, const char cmd);
bdca5ee4 TT	190	extern void reset_stat (struct pstate *sregs);
	191	extern void show_stat (struct pstate *sregs);
	192	extern void init_bpt (struct pstate *sregs);
	193	extern void init_signals (void);
c906108c SS	194
c906108c SS	195	struct disassemble_info;
bdca5ee4 TT	196	extern void dis_mem (uint32 addr, uint32 len,
	197	struct disassemble_info *info);
	198	extern void event (void (*cfunc) (), int32 arg, uint64 delta);
	199	extern void set_int (int32 level, void (*callback) (), int32 arg);
	200	extern void advance_time (struct pstate *sregs);
	201	extern uint32 now (void);
	202	extern int wait_for_irq (void);
	203	extern int check_bpt (struct pstate *sregs);
	204	extern void reset_all (void);
	205	extern void sys_reset (void);
	206	extern void sys_halt (void);
510d2751	207	extern int bfd_load (const char *fname);
96d67095	208	extern double get_time (void);
c906108c SS	209
c906108c SS	210	/* exec.c */
bdca5ee4 TT	211	extern int dispatch_instruction (struct pstate *sregs);
	212	extern int execute_trap (struct pstate *sregs);
	213	extern int check_interrupts (struct pstate *sregs);
	214	extern void init_regs (struct pstate *sregs);
c906108c SS	215
c906108c SS	216	/* interf.c */
bdca5ee4 TT	217	extern int run_sim (struct pstate *sregs,
bdca5ee4 TT	218	uint64 icount, int dis);
c906108c SS	219
c906108c SS	220	/* float.c */
bdca5ee4 TT	221	extern int get_accex (void);
	222	extern void clear_accex (void);
	223	extern void set_fsr (uint32 fsr);
c906108c SS	224
c906108c SS	225	/* help.c */
bdca5ee4 TT	226	extern void usage (void);
bdca5ee4 TT	227	extern void gen_help (void);