projects / deliverable / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| 7a3085c1 AC |
1 | // OBSOLETE /* fr30 simulator support code |
| 2 | // OBSOLETE Copyright (C) 1998, 1999 Free Software Foundation, Inc. | |
| 3 | // OBSOLETE Contributed by Cygnus Solutions. | |
| 4 | // OBSOLETE | |
| 5 | // OBSOLETE This file is part of the GNU simulators. | |
| 6 | // OBSOLETE | |
| 7 | // OBSOLETE This program is free software; you can redistribute it and/or modify | |
| 8 | // OBSOLETE it under the terms of the GNU General Public License as published by | |
| 9 | // OBSOLETE the Free Software Foundation; either version 2, or (at your option) | |
| 10 | // OBSOLETE any later version. | |
| 11 | // OBSOLETE | |
| 12 | // OBSOLETE This program is distributed in the hope that it will be useful, | |
| 13 | // OBSOLETE but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 14 | // OBSOLETE MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 15 | // OBSOLETE GNU General Public License for more details. | |
| 16 | // OBSOLETE | |
| 17 | // OBSOLETE You should have received a copy of the GNU General Public License along | |
| 18 | // OBSOLETE with this program; if not, write to the Free Software Foundation, Inc., | |
| 19 | // OBSOLETE 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ | |
| 20 | // OBSOLETE | |
| 21 | // OBSOLETE #define WANT_CPU | |
| 22 | // OBSOLETE #define WANT_CPU_FR30BF | |
| 23 | // OBSOLETE | |
| 24 | // OBSOLETE #include "sim-main.h" | |
| 25 | // OBSOLETE #include "cgen-mem.h" | |
| 26 | // OBSOLETE #include "cgen-ops.h" | |
| 27 | // OBSOLETE | |
| 28 | // OBSOLETE /* Convert gdb dedicated register number to actual dr reg number. */ | |
| 29 | // OBSOLETE | |
| 30 | // OBSOLETE static int | |
| 31 | // OBSOLETE decode_gdb_dr_regnum (int gdb_regnum) | |
| 32 | // OBSOLETE { | |
| 33 | // OBSOLETE switch (gdb_regnum) | |
| 34 | // OBSOLETE { | |
| 35 | // OBSOLETE case TBR_REGNUM : return H_DR_TBR; | |
| 36 | // OBSOLETE case RP_REGNUM : return H_DR_RP; | |
| 37 | // OBSOLETE case SSP_REGNUM : return H_DR_SSP; | |
| 38 | // OBSOLETE case USP_REGNUM : return H_DR_USP; | |
| 39 | // OBSOLETE case MDH_REGNUM : return H_DR_MDH; | |
| 40 | // OBSOLETE case MDL_REGNUM : return H_DR_MDL; | |
| 41 | // OBSOLETE } | |
| 42 | // OBSOLETE abort (); | |
| 43 | // OBSOLETE } | |
| 44 | // OBSOLETE | |
| 45 | // OBSOLETE /* The contents of BUF are in target byte order. */ | |
| 46 | // OBSOLETE | |
| 47 | // OBSOLETE int | |
| 48 | // OBSOLETE fr30bf_fetch_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len) | |
| 49 | // OBSOLETE { | |
| 50 | // OBSOLETE if (rn < 16) | |
| 51 | // OBSOLETE SETTWI (buf, fr30bf_h_gr_get (current_cpu, rn)); | |
| 52 | // OBSOLETE else | |
| 53 | // OBSOLETE switch (rn) | |
| 54 | // OBSOLETE { | |
| 55 | // OBSOLETE case PC_REGNUM : | |
| 56 | // OBSOLETE SETTWI (buf, fr30bf_h_pc_get (current_cpu)); | |
| 57 | // OBSOLETE break; | |
| 58 | // OBSOLETE case PS_REGNUM : | |
| 59 | // OBSOLETE SETTWI (buf, fr30bf_h_ps_get (current_cpu)); | |
| 60 | // OBSOLETE break; | |
| 61 | // OBSOLETE case TBR_REGNUM : | |
| 62 | // OBSOLETE case RP_REGNUM : | |
| 63 | // OBSOLETE case SSP_REGNUM : | |
| 64 | // OBSOLETE case USP_REGNUM : | |
| 65 | // OBSOLETE case MDH_REGNUM : | |
| 66 | // OBSOLETE case MDL_REGNUM : | |
| 67 | // OBSOLETE SETTWI (buf, fr30bf_h_dr_get (current_cpu, | |
| 68 | // OBSOLETE decode_gdb_dr_regnum (rn))); | |
| 69 | // OBSOLETE break; | |
| 70 | // OBSOLETE default : | |
| 71 | // OBSOLETE return 0; | |
| 72 | // OBSOLETE } | |
| 73 | // OBSOLETE | |
| 74 | // OBSOLETE return -1; /*FIXME*/ | |
| 75 | // OBSOLETE } | |
| 76 | // OBSOLETE | |
| 77 | // OBSOLETE /* The contents of BUF are in target byte order. */ | |
| 78 | // OBSOLETE | |
| 79 | // OBSOLETE int | |
| 80 | // OBSOLETE fr30bf_store_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len) | |
| 81 | // OBSOLETE { | |
| 82 | // OBSOLETE if (rn < 16) | |
| 83 | // OBSOLETE fr30bf_h_gr_set (current_cpu, rn, GETTWI (buf)); | |
| 84 | // OBSOLETE else | |
| 85 | // OBSOLETE switch (rn) | |
| 86 | // OBSOLETE { | |
| 87 | // OBSOLETE case PC_REGNUM : | |
| 88 | // OBSOLETE fr30bf_h_pc_set (current_cpu, GETTWI (buf)); | |
| 89 | // OBSOLETE break; | |
| 90 | // OBSOLETE case PS_REGNUM : | |
| 91 | // OBSOLETE fr30bf_h_ps_set (current_cpu, GETTWI (buf)); | |
| 92 | // OBSOLETE break; | |
| 93 | // OBSOLETE case TBR_REGNUM : | |
| 94 | // OBSOLETE case RP_REGNUM : | |
| 95 | // OBSOLETE case SSP_REGNUM : | |
| 96 | // OBSOLETE case USP_REGNUM : | |
| 97 | // OBSOLETE case MDH_REGNUM : | |
| 98 | // OBSOLETE case MDL_REGNUM : | |
| 99 | // OBSOLETE fr30bf_h_dr_set (current_cpu, | |
| 100 | // OBSOLETE decode_gdb_dr_regnum (rn), | |
| 101 | // OBSOLETE GETTWI (buf)); | |
| 102 | // OBSOLETE break; | |
| 103 | // OBSOLETE default : | |
| 104 | // OBSOLETE return 0; | |
| 105 | // OBSOLETE } | |
| 106 | // OBSOLETE | |
| 107 | // OBSOLETE return -1; /*FIXME*/ | |
| 108 | // OBSOLETE } | |
| 109 | // OBSOLETE \f | |
| 110 | // OBSOLETE /* Cover fns to access the ccr bits. */ | |
| 111 | // OBSOLETE | |
| 112 | // OBSOLETE BI | |
| 113 | // OBSOLETE fr30bf_h_sbit_get_handler (SIM_CPU *current_cpu) | |
| 114 | // OBSOLETE { | |
| 115 | // OBSOLETE return CPU (h_sbit); | |
| 116 | // OBSOLETE } | |
| 117 | // OBSOLETE | |
| 118 | // OBSOLETE void | |
| 119 | // OBSOLETE fr30bf_h_sbit_set_handler (SIM_CPU *current_cpu, BI newval) | |
| 120 | // OBSOLETE { | |
| 121 | // OBSOLETE int old_sbit = CPU (h_sbit); | |
| 122 | // OBSOLETE int new_sbit = (newval != 0); | |
| 123 | // OBSOLETE | |
| 124 | // OBSOLETE CPU (h_sbit) = new_sbit; | |
| 125 | // OBSOLETE | |
| 126 | // OBSOLETE /* When switching stack modes, update the registers. */ | |
| 127 | // OBSOLETE if (old_sbit != new_sbit) | |
| 128 | // OBSOLETE { | |
| 129 | // OBSOLETE if (old_sbit) | |
| 130 | // OBSOLETE { | |
| 131 | // OBSOLETE /* Switching user -> system. */ | |
| 132 | // OBSOLETE CPU (h_dr[H_DR_USP]) = CPU (h_gr[H_GR_SP]); | |
| 133 | // OBSOLETE CPU (h_gr[H_GR_SP]) = CPU (h_dr[H_DR_SSP]); | |
| 134 | // OBSOLETE } | |
| 135 | // OBSOLETE else | |
| 136 | // OBSOLETE { | |
| 137 | // OBSOLETE /* Switching system -> user. */ | |
| 138 | // OBSOLETE CPU (h_dr[H_DR_SSP]) = CPU (h_gr[H_GR_SP]); | |
| 139 | // OBSOLETE CPU (h_gr[H_GR_SP]) = CPU (h_dr[H_DR_USP]); | |
| 140 | // OBSOLETE } | |
| 141 | // OBSOLETE } | |
| 142 | // OBSOLETE | |
| 143 | // OBSOLETE /* TODO: r15 interlock */ | |
| 144 | // OBSOLETE } | |
| 145 | // OBSOLETE \f | |
| 146 | // OBSOLETE /* Cover fns to access the ccr bits. */ | |
| 147 | // OBSOLETE | |
| 148 | // OBSOLETE UQI | |
| 149 | // OBSOLETE fr30bf_h_ccr_get_handler (SIM_CPU *current_cpu) | |
| 150 | // OBSOLETE { | |
| 151 | // OBSOLETE int ccr = ( (GET_H_CBIT () << 0) | |
| 152 | // OBSOLETE | (GET_H_VBIT () << 1) | |
| 153 | // OBSOLETE | (GET_H_ZBIT () << 2) | |
| 154 | // OBSOLETE | (GET_H_NBIT () << 3) | |
| 155 | // OBSOLETE | (GET_H_IBIT () << 4) | |
| 156 | // OBSOLETE | (GET_H_SBIT () << 5)); | |
| 157 | // OBSOLETE | |
| 158 | // OBSOLETE return ccr; | |
| 159 | // OBSOLETE } | |
| 160 | // OBSOLETE | |
| 161 | // OBSOLETE void | |
| 162 | // OBSOLETE fr30bf_h_ccr_set_handler (SIM_CPU *current_cpu, UQI newval) | |
| 163 | // OBSOLETE { | |
| 164 | // OBSOLETE int ccr = newval & 0x3f; | |
| 165 | // OBSOLETE | |
| 166 | // OBSOLETE SET_H_CBIT ((ccr & 1) != 0); | |
| 167 | // OBSOLETE SET_H_VBIT ((ccr & 2) != 0); | |
| 168 | // OBSOLETE SET_H_ZBIT ((ccr & 4) != 0); | |
| 169 | // OBSOLETE SET_H_NBIT ((ccr & 8) != 0); | |
| 170 | // OBSOLETE SET_H_IBIT ((ccr & 0x10) != 0); | |
| 171 | // OBSOLETE SET_H_SBIT ((ccr & 0x20) != 0); | |
| 172 | // OBSOLETE } | |
| 173 | // OBSOLETE \f | |
| 174 | // OBSOLETE /* Cover fns to access the scr bits. */ | |
| 175 | // OBSOLETE | |
| 176 | // OBSOLETE UQI | |
| 177 | // OBSOLETE fr30bf_h_scr_get_handler (SIM_CPU *current_cpu) | |
| 178 | // OBSOLETE { | |
| 179 | // OBSOLETE int scr = ( (GET_H_TBIT () << 0) | |
| 180 | // OBSOLETE | (GET_H_D0BIT () << 1) | |
| 181 | // OBSOLETE | (GET_H_D1BIT () << 2)); | |
| 182 | // OBSOLETE return scr; | |
| 183 | // OBSOLETE } | |
| 184 | // OBSOLETE | |
| 185 | // OBSOLETE void | |
| 186 | // OBSOLETE fr30bf_h_scr_set_handler (SIM_CPU *current_cpu, UQI newval) | |
| 187 | // OBSOLETE { | |
| 188 | // OBSOLETE int scr = newval & 7; | |
| 189 | // OBSOLETE | |
| 190 | // OBSOLETE SET_H_TBIT ((scr & 1) != 0); | |
| 191 | // OBSOLETE SET_H_D0BIT ((scr & 2) != 0); | |
| 192 | // OBSOLETE SET_H_D1BIT ((scr & 4) != 0); | |
| 193 | // OBSOLETE } | |
| 194 | // OBSOLETE \f | |
| 195 | // OBSOLETE /* Cover fns to access the ilm bits. */ | |
| 196 | // OBSOLETE | |
| 197 | // OBSOLETE UQI | |
| 198 | // OBSOLETE fr30bf_h_ilm_get_handler (SIM_CPU *current_cpu) | |
| 199 | // OBSOLETE { | |
| 200 | // OBSOLETE return CPU (h_ilm); | |
| 201 | // OBSOLETE } | |
| 202 | // OBSOLETE | |
| 203 | // OBSOLETE void | |
| 204 | // OBSOLETE fr30bf_h_ilm_set_handler (SIM_CPU *current_cpu, UQI newval) | |
| 205 | // OBSOLETE { | |
| 206 | // OBSOLETE int ilm = newval & 0x1f; | |
| 207 | // OBSOLETE int current_ilm = CPU (h_ilm); | |
| 208 | // OBSOLETE | |
| 209 | // OBSOLETE /* We can only set new ilm values < 16 if the current ilm is < 16. Otherwise | |
| 210 | // OBSOLETE we add 16 to the value we are given. */ | |
| 211 | // OBSOLETE if (current_ilm >= 16 && ilm < 16) | |
| 212 | // OBSOLETE ilm += 16; | |
| 213 | // OBSOLETE | |
| 214 | // OBSOLETE CPU (h_ilm) = ilm; | |
| 215 | // OBSOLETE } | |
| 216 | // OBSOLETE \f | |
| 217 | // OBSOLETE /* Cover fns to access the ps register. */ | |
| 218 | // OBSOLETE | |
| 219 | // OBSOLETE USI | |
| 220 | // OBSOLETE fr30bf_h_ps_get_handler (SIM_CPU *current_cpu) | |
| 221 | // OBSOLETE { | |
| 222 | // OBSOLETE int ccr = GET_H_CCR (); | |
| 223 | // OBSOLETE int scr = GET_H_SCR (); | |
| 224 | // OBSOLETE int ilm = GET_H_ILM (); | |
| 225 | // OBSOLETE | |
| 226 | // OBSOLETE return ccr | (scr << 8) | (ilm << 16); | |
| 227 | // OBSOLETE } | |
| 228 | // OBSOLETE | |
| 229 | // OBSOLETE void | |
| 230 | // OBSOLETE fr30bf_h_ps_set_handler (SIM_CPU *current_cpu, USI newval) | |
| 231 | // OBSOLETE { | |
| 232 | // OBSOLETE int ccr = newval & 0xff; | |
| 233 | // OBSOLETE int scr = (newval >> 8) & 7; | |
| 234 | // OBSOLETE int ilm = (newval >> 16) & 0x1f; | |
| 235 | // OBSOLETE | |
| 236 | // OBSOLETE SET_H_CCR (ccr); | |
| 237 | // OBSOLETE SET_H_SCR (scr); | |
| 238 | // OBSOLETE SET_H_ILM (ilm); | |
| 239 | // OBSOLETE } | |
| 240 | // OBSOLETE \f | |
| 241 | // OBSOLETE /* Cover fns to access the dedicated registers. */ | |
| 242 | // OBSOLETE | |
| 243 | // OBSOLETE SI | |
| 244 | // OBSOLETE fr30bf_h_dr_get_handler (SIM_CPU *current_cpu, UINT dr) | |
| 245 | // OBSOLETE { | |
| 246 | // OBSOLETE switch (dr) | |
| 247 | // OBSOLETE { | |
| 248 | // OBSOLETE case H_DR_SSP : | |
| 249 | // OBSOLETE if (! GET_H_SBIT ()) | |
| 250 | // OBSOLETE return GET_H_GR (H_GR_SP); | |
| 251 | // OBSOLETE else | |
| 252 | // OBSOLETE return CPU (h_dr[H_DR_SSP]); | |
| 253 | // OBSOLETE case H_DR_USP : | |
| 254 | // OBSOLETE if (GET_H_SBIT ()) | |
| 255 | // OBSOLETE return GET_H_GR (H_GR_SP); | |
| 256 | // OBSOLETE else | |
| 257 | // OBSOLETE return CPU (h_dr[H_DR_USP]); | |
| 258 | // OBSOLETE case H_DR_TBR : | |
| 259 | // OBSOLETE case H_DR_RP : | |
| 260 | // OBSOLETE case H_DR_MDH : | |
| 261 | // OBSOLETE case H_DR_MDL : | |
| 262 | // OBSOLETE return CPU (h_dr[dr]); | |
| 263 | // OBSOLETE } | |
| 264 | // OBSOLETE return 0; | |
| 265 | // OBSOLETE } | |
| 266 | // OBSOLETE | |
| 267 | // OBSOLETE void | |
| 268 | // OBSOLETE fr30bf_h_dr_set_handler (SIM_CPU *current_cpu, UINT dr, SI newval) | |
| 269 | // OBSOLETE { | |
| 270 | // OBSOLETE switch (dr) | |
| 271 | // OBSOLETE { | |
| 272 | // OBSOLETE case H_DR_SSP : | |
| 273 | // OBSOLETE if (! GET_H_SBIT ()) | |
| 274 | // OBSOLETE SET_H_GR (H_GR_SP, newval); | |
| 275 | // OBSOLETE else | |
| 276 | // OBSOLETE CPU (h_dr[H_DR_SSP]) = newval; | |
| 277 | // OBSOLETE break; | |
| 278 | // OBSOLETE case H_DR_USP : | |
| 279 | // OBSOLETE if (GET_H_SBIT ()) | |
| 280 | // OBSOLETE SET_H_GR (H_GR_SP, newval); | |
| 281 | // OBSOLETE else | |
| 282 | // OBSOLETE CPU (h_dr[H_DR_USP]) = newval; | |
| 283 | // OBSOLETE break; | |
| 284 | // OBSOLETE case H_DR_TBR : | |
| 285 | // OBSOLETE case H_DR_RP : | |
| 286 | // OBSOLETE case H_DR_MDH : | |
| 287 | // OBSOLETE case H_DR_MDL : | |
| 288 | // OBSOLETE CPU (h_dr[dr]) = newval; | |
| 289 | // OBSOLETE break; | |
| 290 | // OBSOLETE } | |
| 291 | // OBSOLETE } | |
| 292 | // OBSOLETE \f | |
| 293 | // OBSOLETE #if WITH_PROFILE_MODEL_P | |
| 294 | // OBSOLETE | |
| 295 | // OBSOLETE /* FIXME: Some of these should be inline or macros. Later. */ | |
| 296 | // OBSOLETE | |
| 297 | // OBSOLETE /* Initialize cycle counting for an insn. | |
| 298 | // OBSOLETE FIRST_P is non-zero if this is the first insn in a set of parallel | |
| 299 | // OBSOLETE insns. */ | |
| 300 | // OBSOLETE | |
| 301 | // OBSOLETE void | |
| 302 | // OBSOLETE fr30bf_model_insn_before (SIM_CPU *cpu, int first_p) | |
| 303 | // OBSOLETE { | |
| 304 | // OBSOLETE MODEL_FR30_1_DATA *d = CPU_MODEL_DATA (cpu); | |
| 305 | // OBSOLETE d->load_regs_pending = 0; | |
| 306 | // OBSOLETE } | |
| 307 | // OBSOLETE | |
| 308 | // OBSOLETE /* Record the cycles computed for an insn. | |
| 309 | // OBSOLETE LAST_P is non-zero if this is the last insn in a set of parallel insns, | |
| 310 | // OBSOLETE and we update the total cycle count. | |
| 311 | // OBSOLETE CYCLES is the cycle count of the insn. */ | |
| 312 | // OBSOLETE | |
| 313 | // OBSOLETE void | |
| 314 | // OBSOLETE fr30bf_model_insn_after (SIM_CPU *cpu, int last_p, int cycles) | |
| 315 | // OBSOLETE { | |
| 316 | // OBSOLETE PROFILE_DATA *p = CPU_PROFILE_DATA (cpu); | |
| 317 | // OBSOLETE MODEL_FR30_1_DATA *d = CPU_MODEL_DATA (cpu); | |
| 318 | // OBSOLETE | |
| 319 | // OBSOLETE PROFILE_MODEL_TOTAL_CYCLES (p) += cycles; | |
| 320 | // OBSOLETE PROFILE_MODEL_CUR_INSN_CYCLES (p) = cycles; | |
| 321 | // OBSOLETE d->load_regs = d->load_regs_pending; | |
| 322 | // OBSOLETE } | |
| 323 | // OBSOLETE | |
| 324 | // OBSOLETE static INLINE int | |
| 325 | // OBSOLETE check_load_stall (SIM_CPU *cpu, int regno) | |
| 326 | // OBSOLETE { | |
| 327 | // OBSOLETE const MODEL_FR30_1_DATA *d = CPU_MODEL_DATA (cpu); | |
| 328 | // OBSOLETE UINT load_regs = d->load_regs; | |
| 329 | // OBSOLETE | |
| 330 | // OBSOLETE if (regno != -1 | |
| 331 | // OBSOLETE && (load_regs & (1 << regno)) != 0) | |
| 332 | // OBSOLETE { | |
| 333 | // OBSOLETE PROFILE_DATA *p = CPU_PROFILE_DATA (cpu); | |
| 334 | // OBSOLETE ++ PROFILE_MODEL_LOAD_STALL_CYCLES (p); | |
| 335 | // OBSOLETE if (TRACE_INSN_P (cpu)) | |
| 336 | // OBSOLETE cgen_trace_printf (cpu, " ; Load stall."); | |
| 337 | // OBSOLETE return 1; | |
| 338 | // OBSOLETE } | |
| 339 | // OBSOLETE else | |
| 340 | // OBSOLETE return 0; | |
| 341 | // OBSOLETE } | |
| 342 | // OBSOLETE | |
| 343 | // OBSOLETE int | |
| 344 | // OBSOLETE fr30bf_model_fr30_1_u_exec (SIM_CPU *cpu, const IDESC *idesc, | |
| 345 | // OBSOLETE int unit_num, int referenced, | |
| 346 | // OBSOLETE INT in_Ri, INT in_Rj, INT out_Ri) | |
| 347 | // OBSOLETE { | |
| 348 | // OBSOLETE int cycles = idesc->timing->units[unit_num].done; | |
| 349 | // OBSOLETE cycles += check_load_stall (cpu, in_Ri); | |
| 350 | // OBSOLETE cycles += check_load_stall (cpu, in_Rj); | |
| 351 | // OBSOLETE return cycles; | |
| 352 | // OBSOLETE } | |
| 353 | // OBSOLETE | |
| 354 | // OBSOLETE int | |
| 355 | // OBSOLETE fr30bf_model_fr30_1_u_cti (SIM_CPU *cpu, const IDESC *idesc, | |
| 356 | // OBSOLETE int unit_num, int referenced, | |
| 357 | // OBSOLETE INT in_Ri) | |
| 358 | // OBSOLETE { | |
| 359 | // OBSOLETE PROFILE_DATA *p = CPU_PROFILE_DATA (cpu); | |
| 360 | // OBSOLETE /* (1 << 1): The pc is the 2nd element in inputs, outputs. | |
| 361 | // OBSOLETE ??? can be cleaned up */ | |
| 362 | // OBSOLETE int taken_p = (referenced & (1 << 1)) != 0; | |
| 363 | // OBSOLETE int cycles = idesc->timing->units[unit_num].done; | |
| 364 | // OBSOLETE int delay_slot_p = CGEN_ATTR_VALUE (NULL, idesc->attrs, CGEN_INSN_DELAY_SLOT); | |
| 365 | // OBSOLETE | |
| 366 | // OBSOLETE cycles += check_load_stall (cpu, in_Ri); | |
| 367 | // OBSOLETE if (taken_p) | |
| 368 | // OBSOLETE { | |
| 369 | // OBSOLETE /* ??? Handling cti's without delay slots this way will run afoul of | |
| 370 | // OBSOLETE accurate system simulation. Later. */ | |
| 371 | // OBSOLETE if (! delay_slot_p) | |
| 372 | // OBSOLETE { | |
| 373 | // OBSOLETE ++cycles; | |
| 374 | // OBSOLETE ++PROFILE_MODEL_CTI_STALL_CYCLES (p); | |
| 375 | // OBSOLETE } | |
| 376 | // OBSOLETE ++PROFILE_MODEL_TAKEN_COUNT (p); | |
| 377 | // OBSOLETE } | |
| 378 | // OBSOLETE else | |
| 379 | // OBSOLETE ++PROFILE_MODEL_UNTAKEN_COUNT (p); | |
| 380 | // OBSOLETE | |
| 381 | // OBSOLETE return cycles; | |
| 382 | // OBSOLETE } | |
| 383 | // OBSOLETE | |
| 384 | // OBSOLETE int | |
| 385 | // OBSOLETE fr30bf_model_fr30_1_u_load (SIM_CPU *cpu, const IDESC *idesc, | |
| 386 | // OBSOLETE int unit_num, int referenced, | |
| 387 | // OBSOLETE INT in_Rj, INT out_Ri) | |
| 388 | // OBSOLETE { | |
| 389 | // OBSOLETE MODEL_FR30_1_DATA *d = CPU_MODEL_DATA (cpu); | |
| 390 | // OBSOLETE int cycles = idesc->timing->units[unit_num].done; | |
| 391 | // OBSOLETE d->load_regs_pending |= 1 << out_Ri; | |
| 392 | // OBSOLETE cycles += check_load_stall (cpu, in_Rj); | |
| 393 | // OBSOLETE return cycles; | |
| 394 | // OBSOLETE } | |
| 395 | // OBSOLETE | |
| 396 | // OBSOLETE int | |
| 397 | // OBSOLETE fr30bf_model_fr30_1_u_store (SIM_CPU *cpu, const IDESC *idesc, | |
| 398 | // OBSOLETE int unit_num, int referenced, | |
| 399 | // OBSOLETE INT in_Ri, INT in_Rj) | |
| 400 | // OBSOLETE { | |
| 401 | // OBSOLETE int cycles = idesc->timing->units[unit_num].done; | |
| 402 | // OBSOLETE cycles += check_load_stall (cpu, in_Ri); | |
| 403 | // OBSOLETE cycles += check_load_stall (cpu, in_Rj); | |
| 404 | // OBSOLETE return cycles; | |
| 405 | // OBSOLETE } | |
| 406 | // OBSOLETE | |
| 407 | // OBSOLETE int | |
| 408 | // OBSOLETE fr30bf_model_fr30_1_u_ldm (SIM_CPU *cpu, const IDESC *idesc, | |
| 409 | // OBSOLETE int unit_num, int referenced, | |
| 410 | // OBSOLETE INT reglist) | |
| 411 | // OBSOLETE { | |
| 412 | // OBSOLETE return idesc->timing->units[unit_num].done; | |
| 413 | // OBSOLETE } | |
| 414 | // OBSOLETE | |
| 415 | // OBSOLETE int | |
| 416 | // OBSOLETE fr30bf_model_fr30_1_u_stm (SIM_CPU *cpu, const IDESC *idesc, | |
| 417 | // OBSOLETE int unit_num, int referenced, | |
| 418 | // OBSOLETE INT reglist) | |
| 419 | // OBSOLETE { | |
| 420 | // OBSOLETE return idesc->timing->units[unit_num].done; | |
| 421 | // OBSOLETE } | |
| 422 | // OBSOLETE | |
| 423 | // OBSOLETE #endif /* WITH_PROFILE_MODEL_P */ |