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1 | /* collection of junk waiting time to sort out |
2 | Copyright (C) 1998, 1999, 2000, 2001 Free Software Foundation, Inc. | |
3 | Contributed by Red Hat. | |
4 | ||
5 | This file is part of the GNU Simulators. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License along | |
18 | with this program; if not, write to the Free Software Foundation, Inc., | |
19 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ | |
20 | ||
21 | #ifndef FRV_SIM_H | |
22 | #define FRV_SIM_H | |
23 | ||
24 | #include "sim-options.h" | |
25 | ||
26 | /* Not defined in the cgen cpu file for access restriction purposes. */ | |
27 | #define H_SPR_ACC0 1408 | |
28 | #define H_SPR_ACC63 1471 | |
29 | #define H_SPR_ACCG0 1472 | |
30 | #define H_SPR_ACCG63 1535 | |
31 | ||
32 | /* gdb register numbers. */ | |
33 | #define GR_REGNUM_MAX 63 | |
34 | #define FR_REGNUM_MAX 127 | |
35 | #define PC_REGNUM 128 | |
36 | #define LR_REGNUM 145 | |
37 | ||
38 | /* Initialization of the frv cpu. */ | |
39 | void frv_initialize (SIM_CPU *, SIM_DESC); | |
40 | void frv_term (SIM_DESC); | |
41 | void frv_power_on_reset (SIM_CPU *); | |
42 | void frv_hardware_reset (SIM_CPU *); | |
43 | void frv_software_reset (SIM_CPU *); | |
44 | ||
45 | /* The reset register. See FRV LSI section 10.3.1 */ | |
46 | #define RSTR_ADDRESS 0xfeff0500 | |
47 | #define RSTR_INITIAL_VALUE 0x00000400 | |
48 | #define RSTR_HARDWARE_RESET 0x00000200 | |
49 | #define RSTR_SOFTWARE_RESET 0x00000100 | |
50 | ||
51 | #define GET_RSTR_HR(rstr) (((rstr) >> 1) & 1) | |
52 | #define GET_RSTR_SR(rstr) (((rstr) ) & 1) | |
53 | ||
54 | #define SET_RSTR_H(rstr) ((rstr) |= (1 << 9)) | |
55 | #define SET_RSTR_S(rstr) ((rstr) |= (1 << 8)) | |
56 | ||
57 | #define CLEAR_RSTR_P(rstr) ((rstr) &= ~(1 << 10)) | |
58 | #define CLEAR_RSTR_H(rstr) ((rstr) &= ~(1 << 9)) | |
59 | #define CLEAR_RSTR_S(rstr) ((rstr) &= ~(1 << 8)) | |
60 | #define CLEAR_RSTR_HR(rstr) ((rstr) &= ~(1 << 1)) | |
61 | #define CLEAR_RSTR_SR(rstr) ((rstr) &= ~1) | |
62 | ||
63 | /* Cutomized hardware get/set functions. */ | |
64 | extern USI frvbf_h_spr_get_handler (SIM_CPU *, UINT); | |
65 | extern void frvbf_h_spr_set_handler (SIM_CPU *, UINT, USI); | |
66 | extern USI frvbf_h_gr_get_handler (SIM_CPU *, UINT); | |
67 | extern void frvbf_h_gr_set_handler (SIM_CPU *, UINT, USI); | |
68 | extern UHI frvbf_h_gr_hi_get_handler (SIM_CPU *, UINT); | |
69 | extern void frvbf_h_gr_hi_set_handler (SIM_CPU *, UINT, UHI); | |
70 | extern UHI frvbf_h_gr_lo_get_handler (SIM_CPU *, UINT); | |
71 | extern void frvbf_h_gr_lo_set_handler (SIM_CPU *, UINT, UHI); | |
72 | extern DI frvbf_h_gr_double_get_handler (SIM_CPU *, UINT); | |
73 | extern void frvbf_h_gr_double_set_handler (SIM_CPU *, UINT, DI); | |
74 | extern SF frvbf_h_fr_get_handler (SIM_CPU *, UINT); | |
75 | extern void frvbf_h_fr_set_handler (SIM_CPU *, UINT, SF); | |
76 | extern DF frvbf_h_fr_double_get_handler (SIM_CPU *, UINT); | |
77 | extern void frvbf_h_fr_double_set_handler (SIM_CPU *, UINT, DF); | |
78 | extern USI frvbf_h_fr_int_get_handler (SIM_CPU *, UINT); | |
79 | extern void frvbf_h_fr_int_set_handler (SIM_CPU *, UINT, USI); | |
80 | extern DI frvbf_h_cpr_double_get_handler (SIM_CPU *, UINT); | |
81 | extern void frvbf_h_cpr_double_set_handler (SIM_CPU *, UINT, DI); | |
82 | extern void frvbf_h_gr_quad_set_handler (SIM_CPU *, UINT, SI *); | |
83 | extern void frvbf_h_fr_quad_set_handler (SIM_CPU *, UINT, SI *); | |
84 | extern void frvbf_h_cpr_quad_set_handler (SIM_CPU *, UINT, SI *); | |
85 | extern void frvbf_h_psr_s_set_handler (SIM_CPU *, BI); | |
86 | ||
87 | extern USI spr_psr_get_handler (SIM_CPU *); | |
88 | extern void spr_psr_set_handler (SIM_CPU *, USI); | |
89 | extern USI spr_tbr_get_handler (SIM_CPU *); | |
90 | extern void spr_tbr_set_handler (SIM_CPU *, USI); | |
91 | extern USI spr_bpsr_get_handler (SIM_CPU *); | |
92 | extern void spr_bpsr_set_handler (SIM_CPU *, USI); | |
93 | extern USI spr_ccr_get_handler (SIM_CPU *); | |
94 | extern void spr_ccr_set_handler (SIM_CPU *, USI); | |
95 | extern void spr_cccr_set_handler (SIM_CPU *, USI); | |
96 | extern USI spr_cccr_get_handler (SIM_CPU *); | |
97 | extern USI spr_isr_get_handler (SIM_CPU *); | |
98 | extern void spr_isr_set_handler (SIM_CPU *, USI); | |
99 | extern USI spr_sr_get_handler (SIM_CPU *, UINT); | |
100 | extern void spr_sr_set_handler (SIM_CPU *, UINT, USI); | |
101 | ||
102 | extern void frvbf_switch_supervisor_user_context (SIM_CPU *); | |
103 | ||
104 | extern QI frvbf_set_icc_for_shift_left (SIM_CPU *, SI, SI, QI); | |
105 | extern QI frvbf_set_icc_for_shift_right (SIM_CPU *, SI, SI, QI); | |
106 | ||
107 | extern void frvbf_signed_integer_divide (SIM_CPU *, SI, SI, int, int); | |
108 | extern void frvbf_unsigned_integer_divide (SIM_CPU *, USI, USI, int, int); | |
109 | ||
110 | extern void frvbf_clear_accumulators (SIM_CPU *, SI, int); | |
111 | ||
112 | extern SI frvbf_scan_result (SIM_CPU *, SI); | |
113 | extern SI frvbf_cut (SIM_CPU *, SI, SI, SI); | |
114 | extern SI frvbf_media_cut (SIM_CPU *, DI, SI); | |
115 | extern SI frvbf_media_cut_ss (SIM_CPU *, DI, SI); | |
116 | extern void frvbf_media_cop (SIM_CPU *, int); | |
117 | extern UQI frvbf_cr_logic (SIM_CPU *, SI, UQI, UQI); | |
118 | ||
119 | extern void frvbf_set_write_next_vliw_addr_to_LR (SIM_CPU *, int); | |
120 | extern int frvbf_write_next_vliw_addr_to_LR; | |
121 | ||
122 | extern void frvbf_set_ne_index (SIM_CPU *, int); | |
123 | extern void frvbf_force_update (SIM_CPU *); | |
124 | \f | |
125 | #define GETTWI GETTSI | |
126 | #define SETTWI SETTSI | |
127 | #define LEUINT LEUSI | |
128 | \f | |
129 | /* Hardware/device support. | |
130 | ??? Will eventually want to move device stuff to config files. */ | |
131 | ||
132 | /* Support for the MCCR register (Cache Control Register) is needed in order | |
133 | for overlays to work correctly with the scache: cached instructions need | |
134 | to be flushed when the instruction space is changed at runtime. */ | |
135 | ||
136 | /* These were just copied from another port and are necessary to build, but | |
137 | but don't appear to be used. */ | |
138 | #define MCCR_ADDR 0xffffffff | |
139 | #define MCCR_CP 0x80 | |
140 | /* not supported */ | |
141 | #define MCCR_CM0 2 | |
142 | #define MCCR_CM1 1 | |
143 | ||
144 | /* sim_core_attach device argument. */ | |
145 | extern device frv_devices; | |
146 | ||
147 | /* FIXME: Temporary, until device support ready. */ | |
148 | struct _device { int foo; }; | |
149 | ||
150 | /* maintain the address of the start of the previous VLIW insn sequence. */ | |
151 | extern IADDR previous_vliw_pc; | |
152 | ||
153 | /* Hardware status. */ | |
154 | #define GET_HSR0() GET_H_SPR (H_SPR_HSR0) | |
155 | #define SET_HSR0(hsr0) SET_H_SPR (H_SPR_HSR0, (hsr0)) | |
156 | ||
157 | #define GET_HSR0_ICE(hsr0) (((hsr0) >> 31) & 1) | |
158 | #define SET_HSR0_ICE(hsr0) ((hsr0) |= (1 << 31)) | |
159 | #define CLEAR_HSR0_ICE(hsr0) ((hsr0) &= ~(1 << 31)) | |
160 | ||
161 | #define GET_HSR0_DCE(hsr0) (((hsr0) >> 30) & 1) | |
162 | #define SET_HSR0_DCE(hsr0) ((hsr0) |= (1 << 30)) | |
163 | #define CLEAR_HSR0_DCE(hsr0) ((hsr0) &= ~(1 << 30)) | |
164 | ||
165 | #define GET_HSR0_CBM(hsr0) (((hsr0) >> 27) & 1) | |
166 | #define GET_HSR0_RME(hsr0) (((hsr0) >> 22) & 1) | |
167 | #define GET_HSR0_SA(hsr0) (((hsr0) >> 12) & 1) | |
168 | #define GET_HSR0_FRN(hsr0) (((hsr0) >> 11) & 1) | |
169 | #define GET_HSR0_GRN(hsr0) (((hsr0) >> 10) & 1) | |
170 | #define GET_HSR0_FRHE(hsr0) (((hsr0) >> 9) & 1) | |
171 | #define GET_HSR0_FRLE(hsr0) (((hsr0) >> 8) & 1) | |
172 | #define GET_HSR0_GRHE(hsr0) (((hsr0) >> 7) & 1) | |
173 | #define GET_HSR0_GRLE(hsr0) (((hsr0) >> 6) & 1) | |
174 | ||
175 | #define GET_IHSR8() GET_H_SPR (H_SPR_IHSR8) | |
176 | #define GET_IHSR8_NBC(ihsr8) ((ihsr8) & 1) | |
177 | ||
178 | void frvbf_insn_cache_preload (SIM_CPU *, SI, USI, int); | |
179 | void frvbf_data_cache_preload (SIM_CPU *, SI, USI, int); | |
180 | void frvbf_insn_cache_unlock (SIM_CPU *, SI); | |
181 | void frvbf_data_cache_unlock (SIM_CPU *, SI); | |
182 | void frvbf_insn_cache_invalidate (SIM_CPU *, SI, int); | |
183 | void frvbf_data_cache_invalidate (SIM_CPU *, SI, int); | |
184 | void frvbf_data_cache_flush (SIM_CPU *, SI, int); | |
185 | ||
186 | /* FR-V Interrupt classes. | |
187 | These are declared in order of increasing priority. */ | |
188 | enum frv_interrupt_class | |
189 | { | |
190 | FRV_EXTERNAL_INTERRUPT, | |
191 | FRV_SOFTWARE_INTERRUPT, | |
192 | FRV_PROGRAM_INTERRUPT, | |
193 | FRV_BREAK_INTERRUPT, | |
194 | FRV_RESET_INTERRUPT, | |
195 | NUM_FRV_INTERRUPT_CLASSES | |
196 | }; | |
197 | ||
198 | /* FR-V Interrupt kinds. | |
199 | These are declared in order of increasing priority. */ | |
200 | enum frv_interrupt_kind | |
201 | { | |
202 | /* External interrupts */ | |
203 | FRV_INTERRUPT_LEVEL_1, | |
204 | FRV_INTERRUPT_LEVEL_2, | |
205 | FRV_INTERRUPT_LEVEL_3, | |
206 | FRV_INTERRUPT_LEVEL_4, | |
207 | FRV_INTERRUPT_LEVEL_5, | |
208 | FRV_INTERRUPT_LEVEL_6, | |
209 | FRV_INTERRUPT_LEVEL_7, | |
210 | FRV_INTERRUPT_LEVEL_8, | |
211 | FRV_INTERRUPT_LEVEL_9, | |
212 | FRV_INTERRUPT_LEVEL_10, | |
213 | FRV_INTERRUPT_LEVEL_11, | |
214 | FRV_INTERRUPT_LEVEL_12, | |
215 | FRV_INTERRUPT_LEVEL_13, | |
216 | FRV_INTERRUPT_LEVEL_14, | |
217 | FRV_INTERRUPT_LEVEL_15, | |
218 | /* Software interrupt */ | |
219 | FRV_TRAP_INSTRUCTION, | |
220 | /* Program interrupts */ | |
221 | FRV_COMMIT_EXCEPTION, | |
222 | FRV_DIVISION_EXCEPTION, | |
223 | FRV_DATA_STORE_ERROR, | |
224 | FRV_DATA_ACCESS_EXCEPTION, | |
225 | FRV_DATA_ACCESS_MMU_MISS, | |
226 | FRV_DATA_ACCESS_ERROR, | |
227 | FRV_MP_EXCEPTION, | |
228 | FRV_FP_EXCEPTION, | |
229 | FRV_MEM_ADDRESS_NOT_ALIGNED, | |
230 | FRV_REGISTER_EXCEPTION, | |
231 | FRV_MP_DISABLED, | |
232 | FRV_FP_DISABLED, | |
233 | FRV_PRIVILEGED_INSTRUCTION, | |
234 | FRV_ILLEGAL_INSTRUCTION, | |
235 | FRV_INSTRUCTION_ACCESS_EXCEPTION, | |
236 | FRV_INSTRUCTION_ACCESS_ERROR, | |
237 | FRV_INSTRUCTION_ACCESS_MMU_MISS, | |
238 | FRV_COMPOUND_EXCEPTION, | |
239 | /* Break interrupt */ | |
240 | FRV_BREAK_EXCEPTION, | |
241 | /* Reset interrupt */ | |
242 | FRV_RESET, | |
243 | NUM_FRV_INTERRUPT_KINDS | |
244 | }; | |
245 | ||
246 | /* FRV interrupt exception codes */ | |
247 | enum frv_ec | |
248 | { | |
249 | FRV_EC_DATA_STORE_ERROR = 0x00, | |
250 | FRV_EC_INSTRUCTION_ACCESS_MMU_MISS = 0x01, | |
251 | FRV_EC_INSTRUCTION_ACCESS_ERROR = 0x02, | |
252 | FRV_EC_INSTRUCTION_ACCESS_EXCEPTION = 0x03, | |
253 | FRV_EC_PRIVILEGED_INSTRUCTION = 0x04, | |
254 | FRV_EC_ILLEGAL_INSTRUCTION = 0x05, | |
255 | FRV_EC_FP_DISABLED = 0x06, | |
256 | FRV_EC_MP_DISABLED = 0x07, | |
257 | FRV_EC_MEM_ADDRESS_NOT_ALIGNED = 0x0b, | |
258 | FRV_EC_REGISTER_EXCEPTION = 0x0c, | |
259 | FRV_EC_FP_EXCEPTION = 0x0d, | |
260 | FRV_EC_MP_EXCEPTION = 0x0e, | |
261 | FRV_EC_DATA_ACCESS_ERROR = 0x10, | |
262 | FRV_EC_DATA_ACCESS_MMU_MISS = 0x11, | |
263 | FRV_EC_DATA_ACCESS_EXCEPTION = 0x12, | |
264 | FRV_EC_DIVISION_EXCEPTION = 0x13, | |
265 | FRV_EC_COMMIT_EXCEPTION = 0x14, | |
266 | FRV_EC_NOT_EXECUTED = 0x1f, | |
267 | FRV_EC_INTERRUPT_LEVEL_1 = FRV_EC_NOT_EXECUTED, | |
268 | FRV_EC_INTERRUPT_LEVEL_2 = FRV_EC_NOT_EXECUTED, | |
269 | FRV_EC_INTERRUPT_LEVEL_3 = FRV_EC_NOT_EXECUTED, | |
270 | FRV_EC_INTERRUPT_LEVEL_4 = FRV_EC_NOT_EXECUTED, | |
271 | FRV_EC_INTERRUPT_LEVEL_5 = FRV_EC_NOT_EXECUTED, | |
272 | FRV_EC_INTERRUPT_LEVEL_6 = FRV_EC_NOT_EXECUTED, | |
273 | FRV_EC_INTERRUPT_LEVEL_7 = FRV_EC_NOT_EXECUTED, | |
274 | FRV_EC_INTERRUPT_LEVEL_8 = FRV_EC_NOT_EXECUTED, | |
275 | FRV_EC_INTERRUPT_LEVEL_9 = FRV_EC_NOT_EXECUTED, | |
276 | FRV_EC_INTERRUPT_LEVEL_10 = FRV_EC_NOT_EXECUTED, | |
277 | FRV_EC_INTERRUPT_LEVEL_11 = FRV_EC_NOT_EXECUTED, | |
278 | FRV_EC_INTERRUPT_LEVEL_12 = FRV_EC_NOT_EXECUTED, | |
279 | FRV_EC_INTERRUPT_LEVEL_13 = FRV_EC_NOT_EXECUTED, | |
280 | FRV_EC_INTERRUPT_LEVEL_14 = FRV_EC_NOT_EXECUTED, | |
281 | FRV_EC_INTERRUPT_LEVEL_15 = FRV_EC_NOT_EXECUTED, | |
282 | FRV_EC_TRAP_INSTRUCTION = FRV_EC_NOT_EXECUTED, | |
283 | FRV_EC_COMPOUND_EXCEPTION = FRV_EC_NOT_EXECUTED, | |
284 | FRV_EC_BREAK_EXCEPTION = FRV_EC_NOT_EXECUTED, | |
285 | FRV_EC_RESET = FRV_EC_NOT_EXECUTED | |
286 | }; | |
287 | ||
288 | /* FR-V Interrupt. | |
289 | This struct contains enough information to describe a particular interrupt | |
290 | occurance. */ | |
291 | struct frv_interrupt | |
292 | { | |
293 | enum frv_interrupt_kind kind; | |
294 | enum frv_ec ec; | |
295 | enum frv_interrupt_class iclass; | |
296 | unsigned char deferred; | |
297 | unsigned char precise; | |
298 | unsigned char handler_offset; | |
299 | }; | |
300 | ||
301 | /* FR-V Interrupt table. | |
302 | Describes the interrupts supported by the FR-V. */ | |
303 | extern struct frv_interrupt frv_interrupt_table[]; | |
304 | ||
305 | /* FR-V Interrupt State. | |
306 | Interrupts are queued during execution of parallel insns and the interupt(s) | |
307 | to be handled determined by analysing the queue after each VLIW insn. */ | |
308 | #define FRV_INTERRUPT_QUEUE_SIZE (4 * 4) /* 4 interrupts x 4 insns for now. */ | |
309 | ||
310 | /* register_exception codes */ | |
311 | enum frv_rec | |
312 | { | |
313 | FRV_REC_UNIMPLEMENTED = 0, | |
314 | FRV_REC_UNALIGNED = 1 | |
315 | }; | |
316 | ||
317 | /* instruction_access_exception codes */ | |
318 | enum frv_iaec | |
319 | { | |
320 | FRV_IAEC_PROTECT_VIOLATION = 1 | |
321 | }; | |
322 | ||
323 | /* data_access_exception codes */ | |
324 | enum frv_daec | |
325 | { | |
326 | FRV_DAEC_PROTECT_VIOLATION = 1 | |
327 | }; | |
328 | ||
329 | /* division_exception ISR codes */ | |
330 | enum frv_dtt | |
331 | { | |
332 | FRV_DTT_NO_EXCEPTION = 0, | |
333 | FRV_DTT_DIVISION_BY_ZERO = 1, | |
334 | FRV_DTT_OVERFLOW = 2, | |
335 | FRV_DTT_BOTH = 3 | |
336 | }; | |
337 | ||
338 | /* data written during an insn causing an interrupt */ | |
339 | struct frv_data_written | |
340 | { | |
341 | USI words[4]; /* Actual data in words */ | |
342 | int length; /* length of data written */ | |
343 | }; | |
344 | ||
345 | /* fp_exception info */ | |
346 | /* Trap codes for FSR0 and FQ registers. */ | |
347 | enum frv_fsr_traps | |
348 | { | |
349 | FSR_INVALID_OPERATION = 0x20, | |
350 | FSR_OVERFLOW = 0x10, | |
351 | FSR_UNDERFLOW = 0x08, | |
352 | FSR_DIVISION_BY_ZERO = 0x04, | |
353 | FSR_INEXACT = 0x02, | |
354 | FSR_DENORMAL_INPUT = 0x01, | |
355 | FSR_NO_EXCEPTION = 0 | |
356 | }; | |
357 | ||
358 | /* Floating point trap types for FSR. */ | |
359 | enum frv_fsr_ftt | |
360 | { | |
361 | FTT_NONE = 0, | |
362 | FTT_IEEE_754_EXCEPTION = 1, | |
363 | FTT_UNIMPLEMENTED_FPOP = 3, | |
364 | FTT_SEQUENCE_ERROR = 4, | |
365 | FTT_INVALID_FR = 6, | |
366 | FTT_DENORMAL_INPUT = 7 | |
367 | }; | |
368 | ||
369 | struct frv_fp_exception_info | |
370 | { | |
371 | enum frv_fsr_traps fsr_mask; /* interrupt code for FSR */ | |
372 | enum frv_fsr_ftt ftt; /* floating point trap type */ | |
373 | }; | |
374 | ||
375 | struct frv_interrupt_queue_element | |
376 | { | |
377 | enum frv_interrupt_kind kind; /* kind of interrupt */ | |
378 | IADDR vpc; /* address of insn causing interrupt */ | |
379 | int slot; /* VLIW slot containing the insn. */ | |
380 | USI eaddress; /* address of data access */ | |
381 | union { | |
382 | enum frv_rec rec; /* register exception code */ | |
383 | enum frv_iaec iaec; /* insn access exception code */ | |
384 | enum frv_daec daec; /* data access exception code */ | |
385 | enum frv_dtt dtt; /* division exception code */ | |
386 | struct frv_fp_exception_info fp_info; | |
387 | struct frv_data_written data_written; | |
388 | } u; | |
389 | }; | |
390 | ||
391 | struct frv_interrupt_timer | |
392 | { | |
393 | int enabled; | |
394 | unsigned value; | |
395 | unsigned current; | |
396 | enum frv_interrupt_kind interrupt; | |
397 | }; | |
398 | ||
399 | struct frv_interrupt_state | |
400 | { | |
401 | /* The interrupt queue */ | |
402 | struct frv_interrupt_queue_element queue[FRV_INTERRUPT_QUEUE_SIZE]; | |
403 | int queue_index; | |
404 | ||
405 | /* interrupt queue element causing imprecise interrupt. */ | |
406 | struct frv_interrupt_queue_element *imprecise_interrupt; | |
407 | ||
408 | /* interrupt timer. */ | |
409 | struct frv_interrupt_timer timer; | |
410 | ||
411 | /* The last data written stored as an array of words. */ | |
412 | struct frv_data_written data_written; | |
413 | ||
414 | /* The vliw slot of the insn causing the interrupt. */ | |
415 | int slot; | |
416 | ||
417 | /* target register index for non excepting insns. */ | |
418 | #define NE_NOFLAG (-1) | |
419 | int ne_index; | |
420 | ||
421 | /* Accumulated NE flags for non excepting floating point insns. */ | |
422 | SI f_ne_flags[2]; | |
423 | }; | |
424 | ||
425 | extern struct frv_interrupt_state frv_interrupt_state; | |
426 | ||
427 | /* Macros to manipulate the PSR. */ | |
428 | #define GET_PSR() GET_H_SPR (H_SPR_PSR) | |
429 | ||
430 | #define SET_PSR_ET(psr, et) ( \ | |
431 | (psr) = ((psr) & ~0x1) | ((et) & 0x1) \ | |
432 | ) | |
433 | ||
434 | #define GET_PSR_PS(psr) (((psr) >> 1) & 1) | |
435 | ||
436 | #define SET_PSR_S(psr, s) ( \ | |
437 | (psr) = ((psr) & ~(0x1 << 2)) | (((s) & 0x1) << 2) \ | |
438 | ) | |
439 | ||
440 | /* Macros to handle the ISR register. */ | |
441 | #define GET_ISR() GET_H_SPR (H_SPR_ISR) | |
442 | #define SET_ISR(isr) SET_H_SPR (H_SPR_ISR, (isr)) | |
443 | ||
444 | #define GET_ISR_EDE(isr) (((isr) >> 5) & 1) | |
445 | ||
446 | #define GET_ISR_DTT(isr) (((isr) >> 3) & 3) | |
447 | #define SET_ISR_DTT(isr, dtt) ( \ | |
448 | (isr) = ((isr) & ~(0x3 << 3)) | (((dtt) & 0x3) << 3) \ | |
449 | ) | |
450 | ||
451 | #define SET_ISR_AEXC(isr) ((isr) |= (1 << 2)) | |
452 | ||
453 | #define GET_ISR_EMAM(isr) ((isr) & 1) | |
454 | ||
455 | /* Macros to handle exception status registers. | |
456 | Get and set the hardware directly, since we may be getting/setting fields | |
457 | which are not accessible to the user. */ | |
458 | #define GET_ESR(index) \ | |
459 | (CPU (h_spr[H_SPR_ESR0 + (index)])) | |
460 | #define SET_ESR(index, esr) \ | |
461 | (CPU (h_spr[H_SPR_ESR0 + (index)]) = (esr)) | |
462 | ||
463 | #define SET_ESR_VALID(esr) ((esr) |= 1) | |
464 | #define CLEAR_ESR_VALID(esr) ((esr) &= ~1) | |
465 | ||
466 | #define SET_ESR_EC(esr, ec) ( \ | |
467 | (esr) = ((esr) & ~(0x1f << 1)) | (((ec) & 0x1f) << 1) \ | |
468 | ) | |
469 | ||
470 | #define SET_ESR_REC(esr, rec) ( \ | |
471 | (esr) = ((esr) & ~(0x3 << 6)) | (((rec) & 0x3) << 6) \ | |
472 | ) | |
473 | ||
474 | #define SET_ESR_IAEC(esr, iaec) ( \ | |
475 | (esr) = ((esr) & ~(0x1 << 8)) | (((iaec) & 0x1) << 8) \ | |
476 | ) | |
477 | ||
478 | #define SET_ESR_DAEC(esr, daec) ( \ | |
479 | (esr) = ((esr) & ~(0x1 << 9)) | (((daec) & 0x1) << 9) \ | |
480 | ) | |
481 | ||
482 | #define SET_ESR_EAV(esr) ((esr) |= (1 << 11)) | |
483 | #define CLEAR_ESR_EAV(esr) ((esr) &= ~(1 << 11)) | |
484 | ||
485 | #define GET_ESR_EDV(esr) (((esr) >> 12) & 1) | |
486 | #define SET_ESR_EDV(esr) ((esr) |= (1 << 12)) | |
487 | #define CLEAR_ESR_EDV(esr) ((esr) &= ~(1 << 12)) | |
488 | ||
489 | #define GET_ESR_EDN(esr) ( \ | |
490 | ((esr) >> 13) & 0xf \ | |
491 | ) | |
492 | #define SET_ESR_EDN(esr, edn) ( \ | |
493 | (esr) = ((esr) & ~(0xf << 13)) | (((edn) & 0xf) << 13) \ | |
494 | ) | |
495 | ||
496 | #define SET_EPCR(index, address) \ | |
497 | (CPU (h_spr[H_SPR_EPCR0 + (index)]) = (address)) | |
498 | ||
499 | #define SET_EAR(index, address) \ | |
500 | (CPU (h_spr[H_SPR_EAR0 + (index)]) = (address)) | |
501 | ||
502 | #define SET_EDR(index, edr) \ | |
503 | (CPU (h_spr[H_SPR_EDR0 + (index)]) = (edr)) | |
504 | ||
505 | #define GET_ESFR(index) \ | |
506 | (CPU (h_spr[H_SPR_ESFR0 + (index)])) | |
507 | #define SET_ESFR(index, esfr) \ | |
508 | (CPU (h_spr[H_SPR_ESFR0 + (index)]) = (esfr)) | |
509 | ||
510 | #define GET_ESFR_FLAG(findex) ( \ | |
511 | (findex) > 31 ? \ | |
512 | ((CPU (h_spr[H_SPR_ESFR0]) >> ((findex)-32)) & 1) \ | |
513 | : \ | |
514 | ((CPU (h_spr[H_SPR_ESFR1]) >> (findex)) & 1) \ | |
515 | ) | |
516 | #define SET_ESFR_FLAG(findex) ( \ | |
517 | (findex) > 31 ? \ | |
518 | (CPU (h_spr[H_SPR_ESFR0]) = \ | |
519 | (CPU (h_spr[H_SPR_ESFR0]) | (1 << ((findex)-32))) \ | |
520 | ) : \ | |
521 | (CPU (h_spr[H_SPR_ESFR1]) = \ | |
522 | (CPU (h_spr[H_SPR_ESFR1]) | (1 << (findex))) \ | |
523 | ) \ | |
524 | ) | |
525 | ||
526 | /* The FSR registers. | |
527 | Get and set the hardware directly, since we may be getting/setting fields | |
528 | which are not accessible to the user. */ | |
529 | #define GET_FSR(index) \ | |
530 | (CPU (h_spr[H_SPR_FSR0 + (index)])) | |
531 | #define SET_FSR(index, fsr) \ | |
532 | (CPU (h_spr[H_SPR_FSR0 + (index)]) = (fsr)) | |
533 | ||
534 | #define GET_FSR_TEM(fsr) ( \ | |
535 | ((fsr) >> 24) & 0x3f \ | |
536 | ) | |
537 | ||
538 | #define SET_FSR_QNE(fsr) ((fsr) |= (1 << 20)) | |
539 | #define GET_FSR_QNE(fsr) (((fsr) >> 20) & 1) | |
540 | ||
541 | #define SET_FSR_FTT(fsr, ftt) ( \ | |
542 | (fsr) = ((fsr) & ~(0x7 << 17)) | (((ftt) & 0x7) << 17) \ | |
543 | ) | |
544 | ||
545 | #define GET_FSR_AEXC(fsr) ( \ | |
546 | ((fsr) >> 10) & 0x3f \ | |
547 | ) | |
548 | #define SET_FSR_AEXC(fsr, aexc) ( \ | |
549 | (fsr) = ((fsr) & ~(0x3f << 10)) | (((aexc) & 0x3f) << 10) \ | |
550 | ) | |
551 | ||
552 | /* SIMD instruction exception codes for FQ. */ | |
553 | enum frv_sie | |
554 | { | |
555 | SIE_NIL = 0, | |
556 | SIE_FRi = 1, | |
557 | SIE_FRi_1 = 2 | |
558 | }; | |
559 | ||
560 | /* MIV field of FQ. */ | |
561 | enum frv_miv | |
562 | { | |
563 | MIV_FLOAT = 0, | |
564 | MIV_MEDIA = 1 | |
565 | }; | |
566 | ||
567 | /* The FQ registers are 64 bits wide and are implemented as 32 bit pairs. The | |
568 | index here refers to the low order 32 bit element. | |
569 | Get and set the hardware directly, since we may be getting/setting fields | |
570 | which are not accessible to the user. */ | |
571 | #define GET_FQ(index) \ | |
572 | (CPU (h_spr[H_SPR_FQST0 + 2 * (index)])) | |
573 | #define SET_FQ(index, fq) \ | |
574 | (CPU (h_spr[H_SPR_FQST0 + 2 * (index)]) = (fq)) | |
575 | ||
576 | #define SET_FQ_MIV(fq, miv) ( \ | |
577 | (fq) = ((fq) & ~(0x1 << 31)) | (((miv) & 0x1) << 31) \ | |
578 | ) | |
579 | ||
580 | #define SET_FQ_SIE(fq, sie) ( \ | |
581 | (fq) = ((fq) & ~(0x3 << 15)) | (((sie) & 0x3) << 15) \ | |
582 | ) | |
583 | ||
584 | #define SET_FQ_FTT(fq, ftt) ( \ | |
585 | (fq) = ((fq) & ~(0x7 << 7)) | (((ftt) & 0x7) << 7) \ | |
586 | ) | |
587 | ||
588 | #define SET_FQ_CEXC(fq, cexc) ( \ | |
589 | (fq) = ((fq) & ~(0x3f << 1)) | (((cexc) & 0x3f) << 1) \ | |
590 | ) | |
591 | ||
592 | #define GET_FQ_VALID(fq) ((fq) & 1) | |
593 | #define SET_FQ_VALID(fq) ((fq) |= 1) | |
594 | ||
595 | #define SET_FQ_OPC(index, insn) \ | |
596 | (CPU (h_spr[H_SPR_FQOP0 + 2 * (index)]) = (insn)) | |
597 | ||
598 | /* mp_exception support. */ | |
599 | /* Media trap types for MSR. */ | |
600 | enum frv_msr_mtt | |
601 | { | |
602 | MTT_NONE = 0, | |
603 | MTT_OVERFLOW = 1, | |
604 | MTT_ACC_NOT_ALIGNED = 2, | |
605 | MTT_ACC_NOT_IMPLEMENTED = 2, /* Yes -- same value as MTT_ACC_NOT_ALIGNED. */ | |
606 | MTT_CR_NOT_ALIGNED = 3, | |
607 | MTT_UNIMPLEMENTED_MPOP = 5, | |
608 | MTT_INVALID_FR = 6 | |
609 | }; | |
610 | ||
611 | /* Media status registers. | |
612 | Get and set the hardware directly, since we may be getting/setting fields | |
613 | which are not accessible to the user. */ | |
614 | #define GET_MSR(index) \ | |
615 | (CPU (h_spr[H_SPR_MSR0 + (index)])) | |
616 | #define SET_MSR(index, msr) \ | |
617 | (CPU (h_spr[H_SPR_MSR0 + (index)]) = (msr)) | |
618 | ||
619 | #define GET_MSR_AOVF(msr) ((msr) & 1) | |
620 | #define SET_MSR_AOVF(msr) ((msr) |= 1) | |
621 | ||
622 | #define GET_MSR_OVF(msr) ( \ | |
623 | ((msr) >> 1) & 0x1 \ | |
624 | ) | |
625 | #define SET_MSR_OVF(msr) ( \ | |
626 | (msr) |= (1 << 1) \ | |
627 | ) | |
628 | #define CLEAR_MSR_OVF(msr) ( \ | |
629 | (msr) &= ~(1 << 1) \ | |
630 | ) | |
631 | ||
632 | #define OR_MSR_SIE(msr, sie) ( \ | |
633 | (msr) |= (((sie) & 0xf) << 2) \ | |
634 | ) | |
635 | #define CLEAR_MSR_SIE(msr) ( \ | |
636 | (msr) &= ~(0xf << 2) \ | |
637 | ) | |
638 | ||
639 | #define GET_MSR_MTT(msr) ( \ | |
640 | ((msr) >> 12) & 0x7 \ | |
641 | ) | |
642 | #define SET_MSR_MTT(msr, mtt) ( \ | |
643 | (msr) = ((msr) & ~(0x7 << 12)) | (((mtt) & 0x7) << 12) \ | |
644 | ) | |
645 | #define GET_MSR_EMCI(msr) ( \ | |
646 | ((msr) >> 24) & 0x1 \ | |
647 | ) | |
648 | #define GET_MSR_SRDAV(msr) ( \ | |
649 | ((msr) >> 28) & 0x1 \ | |
650 | ) | |
651 | #define GET_MSR_RDAV(msr) ( \ | |
652 | ((msr) >> 29) & 0x1 \ | |
653 | ) | |
654 | #define GET_MSR_RD(msr) ( \ | |
655 | ((msr) >> 30) & 0x3 \ | |
656 | ) | |
657 | ||
658 | void frvbf_media_register_not_aligned (SIM_CPU *); | |
659 | void frvbf_media_acc_not_aligned (SIM_CPU *); | |
660 | void frvbf_media_cr_not_aligned (SIM_CPU *); | |
661 | void frvbf_media_overflow (SIM_CPU *, int); | |
662 | ||
663 | /* Functions for queuing and processing interrupts. */ | |
664 | struct frv_interrupt_queue_element * | |
665 | frv_queue_break_interrupt (SIM_CPU *); | |
666 | ||
667 | struct frv_interrupt_queue_element * | |
668 | frv_queue_software_interrupt (SIM_CPU *, SI); | |
669 | ||
670 | struct frv_interrupt_queue_element * | |
671 | frv_queue_program_interrupt (SIM_CPU *, enum frv_interrupt_kind); | |
672 | ||
673 | struct frv_interrupt_queue_element * | |
674 | frv_queue_external_interrupt (SIM_CPU *, enum frv_interrupt_kind); | |
675 | ||
676 | struct frv_interrupt_queue_element * | |
677 | frv_queue_illegal_instruction_interrupt (SIM_CPU *, const CGEN_INSN *); | |
678 | ||
679 | struct frv_interrupt_queue_element * | |
680 | frv_queue_non_implemented_instruction_interrupt (SIM_CPU *, const CGEN_INSN *); | |
681 | ||
682 | struct frv_interrupt_queue_element * | |
683 | frv_queue_register_exception_interrupt (SIM_CPU *, enum frv_rec); | |
684 | ||
685 | struct frv_interrupt_queue_element * | |
686 | frv_queue_mem_address_not_aligned_interrupt (SIM_CPU *, USI); | |
687 | ||
688 | struct frv_interrupt_queue_element * | |
689 | frv_queue_data_access_error_interrupt (SIM_CPU *, USI); | |
690 | ||
691 | struct frv_interrupt_queue_element * | |
692 | frv_queue_instruction_access_error_interrupt (SIM_CPU *); | |
693 | ||
694 | struct frv_interrupt_queue_element * | |
695 | frv_queue_instruction_access_exception_interrupt (SIM_CPU *); | |
696 | ||
697 | struct frv_interrupt_queue_element * | |
698 | frv_queue_fp_exception_interrupt (SIM_CPU *, struct frv_fp_exception_info *); | |
699 | ||
700 | enum frv_dtt frvbf_division_exception (SIM_CPU *, enum frv_dtt, int, int); | |
701 | ||
702 | struct frv_interrupt_queue_element * | |
703 | frv_queue_interrupt (SIM_CPU *, enum frv_interrupt_kind); | |
704 | ||
705 | void | |
706 | frv_set_interrupt_queue_slot (SIM_CPU *, struct frv_interrupt_queue_element *); | |
707 | ||
708 | void frv_set_mp_exception_registers (SIM_CPU *, enum frv_msr_mtt, int); | |
709 | void frv_detect_insn_access_interrupts (SIM_CPU *, SCACHE *); | |
710 | ||
711 | void frv_process_interrupts (SIM_CPU *); | |
712 | ||
713 | void frv_break_interrupt (SIM_CPU *, struct frv_interrupt *, IADDR); | |
714 | void frv_non_operating_interrupt (SIM_CPU *, enum frv_interrupt_kind, IADDR); | |
715 | void frv_program_interrupt ( | |
716 | SIM_CPU *, struct frv_interrupt_queue_element *, IADDR | |
717 | ); | |
718 | void frv_software_interrupt ( | |
719 | SIM_CPU *, struct frv_interrupt_queue_element *, IADDR | |
720 | ); | |
721 | void frv_external_interrupt ( | |
722 | SIM_CPU *, struct frv_interrupt_queue_element *, IADDR | |
723 | ); | |
724 | void frv_program_or_software_interrupt ( | |
725 | SIM_CPU *, struct frv_interrupt *, IADDR | |
726 | ); | |
727 | void frv_clear_interrupt_classes ( | |
728 | enum frv_interrupt_class, enum frv_interrupt_class | |
729 | ); | |
730 | ||
731 | void | |
732 | frv_save_data_written_for_interrupts (SIM_CPU *, CGEN_WRITE_QUEUE_ELEMENT *); | |
733 | ||
734 | /* Special purpose traps. */ | |
735 | #define TRAP_SYSCALL 0x80 | |
736 | #define TRAP_BREAKPOINT 0x81 | |
737 | #define TRAP_REGDUMP1 0x82 | |
738 | #define TRAP_REGDUMP2 0x83 | |
739 | ||
740 | /* Handle the trap insns */ | |
741 | void frv_itrap (SIM_CPU *, PCADDR, USI, int); | |
742 | void frv_mtrap (SIM_CPU *); | |
743 | /* Handle the break insn. */ | |
744 | void frv_break (SIM_CPU *); | |
745 | /* Handle the rett insn. */ | |
746 | USI frv_rett (SIM_CPU *current_cpu, PCADDR pc, BI debug_field); | |
747 | ||
748 | /* Parallel write queue flags. */ | |
749 | #define FRV_WRITE_QUEUE_FORCE_WRITE 1 | |
750 | ||
751 | #define CGEN_WRITE_QUEUE_ELEMENT_PIPE(element) CGEN_WRITE_QUEUE_ELEMENT_WORD1 (element) | |
752 | ||
753 | /* Functions and macros for handling non-excepting instruction side effects. | |
754 | Get and set the hardware directly, since we may be getting/setting fields | |
755 | which are not accessible to the user. */ | |
756 | #define GET_NECR() (GET_H_SPR (H_SPR_NECR)) | |
757 | #define GET_NECR_ELOS(necr) (((necr) >> 6) & 1) | |
758 | #define GET_NECR_NEN(necr) (((necr) >> 1) & 0x1f) | |
759 | #define GET_NECR_VALID(necr) (((necr) ) & 1) | |
760 | ||
761 | #define NO_NESR (-1) | |
762 | /* NESR field values. See Tables 30-33 in section 4.4.2.1 of the FRV | |
763 | Architecture volume 1. */ | |
764 | #define NESR_MEM_ADDRESS_NOT_ALIGNED 0x0b | |
765 | #define NESR_REGISTER_NOT_ALIGNED 0x1 | |
766 | #define NESR_UQI_SIZE 0 | |
767 | #define NESR_QI_SIZE 1 | |
768 | #define NESR_UHI_SIZE 2 | |
769 | #define NESR_HI_SIZE 3 | |
770 | #define NESR_SI_SIZE 4 | |
771 | #define NESR_DI_SIZE 5 | |
772 | #define NESR_XI_SIZE 6 | |
773 | ||
774 | #define GET_NESR(index) GET_H_SPR (H_SPR_NESR0 + (index)) | |
775 | #define SET_NESR(index, value) ( \ | |
776 | sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, \ | |
777 | H_SPR_NESR0 + (index), (value)), \ | |
778 | frvbf_force_update (current_cpu) \ | |
779 | ) | |
780 | #define GET_NESR_VALID(nesr) ((nesr) & 1) | |
781 | #define SET_NESR_VALID(nesr) ((nesr) |= 1) | |
782 | ||
783 | #define SET_NESR_EAV(nesr) ((nesr) |= (1 << 31)) | |
784 | ||
785 | #define GET_NESR_FR(nesr) (((nesr) >> 30) & 1) | |
786 | #define SET_NESR_FR(nesr) ((nesr) |= (1 << 30)) | |
787 | #define CLEAR_NESR_FR(nesr) ((nesr) &= ~(1 << 30)) | |
788 | ||
789 | #define GET_NESR_DRN(nesr) (((nesr) >> 24) & 0x3f) | |
790 | #define SET_NESR_DRN(nesr, drn) ( \ | |
791 | (nesr) = ((nesr) & ~(0x3f << 24)) | (((drn) & 0x3f) << 24) \ | |
792 | ) | |
793 | ||
794 | #define SET_NESR_SIZE(nesr, data_size) ( \ | |
795 | (nesr) = ((nesr) & ~(0x7 << 21)) | (((data_size) & 0x7) << 21) \ | |
796 | ) | |
797 | ||
798 | #define SET_NESR_NEAN(nesr, index) ( \ | |
799 | (nesr) = ((nesr) & ~(0x1f << 10)) | (((index) & 0x1f) << 10) \ | |
800 | ) | |
801 | ||
802 | #define GET_NESR_DAEC(nesr) (((nesr) >> 9) & 1) | |
803 | #define SET_NESR_DAEC(nesr, daec) ( \ | |
804 | (nesr) = ((nesr) & ~(1 << 9)) | (((daec) & 1) << 9) \ | |
805 | ) | |
806 | ||
807 | #define GET_NESR_REC(nesr) (((nesr) >> 6) & 3) | |
808 | #define SET_NESR_REC(nesr, rec) ( \ | |
809 | (nesr) = ((nesr) & ~(3 << 6)) | (((rec) & 3) << 6) \ | |
810 | ) | |
811 | ||
812 | #define GET_NESR_EC(nesr) (((nesr) >> 1) & 0x1f) | |
813 | #define SET_NESR_EC(nesr, ec) ( \ | |
814 | (nesr) = ((nesr) & ~(0x1f << 1)) | (((ec) & 0x1f) << 1) \ | |
815 | ) | |
816 | ||
817 | #define SET_NEEAR(index, address) ( \ | |
818 | sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, \ | |
819 | H_SPR_NEEAR0 + (index), (address)), \ | |
820 | frvbf_force_update (current_cpu) \ | |
821 | ) | |
822 | ||
823 | #define GET_NE_FLAGS(flags, NE_base) ( \ | |
824 | (flags)[0] = GET_H_SPR ((NE_base)), \ | |
825 | (flags)[1] = GET_H_SPR ((NE_base) + 1) \ | |
826 | ) | |
827 | #define SET_NE_FLAGS(NE_base, flags) ( \ | |
828 | sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, (NE_base), \ | |
829 | (flags)[0]), \ | |
830 | frvbf_force_update (current_cpu), \ | |
831 | sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, (NE_base) + 1, \ | |
832 | (flags)[1]), \ | |
833 | frvbf_force_update (current_cpu) \ | |
834 | ) | |
835 | ||
836 | #define GET_NE_FLAG(flags, index) ( \ | |
837 | (index) > 31 ? \ | |
838 | ((flags[0] >> ((index) - 32)) & 1) \ | |
839 | : \ | |
840 | ((flags[1] >> (index)) & 1) \ | |
841 | ) | |
842 | #define SET_NE_FLAG(flags, index) ( \ | |
843 | (index) > 31 ? \ | |
844 | ((flags)[0] |= (1 << ((index) - 32))) \ | |
845 | : \ | |
846 | ((flags)[1] |= (1 << (index))) \ | |
847 | ) | |
848 | #define CLEAR_NE_FLAG(flags, index) ( \ | |
849 | (index) > 31 ? \ | |
850 | ((flags)[0] &= ~(1 << ((index) - 32))) \ | |
851 | : \ | |
852 | ((flags)[1] &= ~(1 << (index))) \ | |
853 | ) | |
854 | ||
855 | BI frvbf_check_non_excepting_load (SIM_CPU *, SI, SI, SI, SI, QI, BI); | |
856 | void frvbf_check_recovering_store (SIM_CPU *, PCADDR, SI, int, int); | |
857 | ||
858 | void frvbf_clear_ne_flags (SIM_CPU *, SI, BI); | |
859 | void frvbf_commit (SIM_CPU *, SI, BI); | |
860 | ||
861 | void frvbf_fpu_error (CGEN_FPU *, int); | |
862 | ||
863 | void frv_vliw_setup_insn (SIM_CPU *, const CGEN_INSN *); | |
864 | ||
865 | extern int insns_in_slot[]; | |
866 | ||
867 | #define COUNT_INSNS_IN_SLOT(slot) \ | |
868 | { \ | |
869 | if (WITH_PROFILE_MODEL_P) \ | |
870 | ++insns_in_slot[slot]; \ | |
871 | } | |
872 | ||
873 | #define INSNS_IN_SLOT(slot) (insns_in_slot[slot]) | |
874 | ||
875 | /* Multiple loads and stores. */ | |
876 | void frvbf_load_multiple_GR (SIM_CPU *, PCADDR, SI, SI, int); | |
877 | void frvbf_load_multiple_FRint (SIM_CPU *, PCADDR, SI, SI, int); | |
878 | void frvbf_load_multiple_CPR (SIM_CPU *, PCADDR, SI, SI, int); | |
879 | void frvbf_store_multiple_GR (SIM_CPU *, PCADDR, SI, SI, int); | |
880 | void frvbf_store_multiple_FRint (SIM_CPU *, PCADDR, SI, SI, int); | |
881 | void frvbf_store_multiple_CPR (SIM_CPU *, PCADDR, SI, SI, int); | |
882 | ||
883 | /* Memory and cache support. */ | |
884 | QI frvbf_read_mem_QI (SIM_CPU *, IADDR, SI); | |
885 | UQI frvbf_read_mem_UQI (SIM_CPU *, IADDR, SI); | |
886 | HI frvbf_read_mem_HI (SIM_CPU *, IADDR, SI); | |
887 | UHI frvbf_read_mem_UHI (SIM_CPU *, IADDR, SI); | |
888 | SI frvbf_read_mem_SI (SIM_CPU *, IADDR, SI); | |
889 | SI frvbf_read_mem_WI (SIM_CPU *, IADDR, SI); | |
890 | DI frvbf_read_mem_DI (SIM_CPU *, IADDR, SI); | |
891 | DF frvbf_read_mem_DF (SIM_CPU *, IADDR, SI); | |
892 | ||
893 | USI frvbf_read_imem_USI (SIM_CPU *, PCADDR); | |
894 | ||
895 | void frvbf_write_mem_QI (SIM_CPU *, IADDR, SI, QI); | |
896 | void frvbf_write_mem_UQI (SIM_CPU *, IADDR, SI, UQI); | |
897 | void frvbf_write_mem_HI (SIM_CPU *, IADDR, SI, HI); | |
898 | void frvbf_write_mem_UHI (SIM_CPU *, IADDR, SI, UHI); | |
899 | void frvbf_write_mem_SI (SIM_CPU *, IADDR, SI, SI); | |
900 | void frvbf_write_mem_WI (SIM_CPU *, IADDR, SI, SI); | |
901 | void frvbf_write_mem_DI (SIM_CPU *, IADDR, SI, DI); | |
902 | void frvbf_write_mem_DF (SIM_CPU *, IADDR, SI, DF); | |
903 | ||
904 | void frvbf_mem_set_QI (SIM_CPU *, IADDR, SI, QI); | |
905 | void frvbf_mem_set_HI (SIM_CPU *, IADDR, SI, HI); | |
906 | void frvbf_mem_set_SI (SIM_CPU *, IADDR, SI, SI); | |
907 | void frvbf_mem_set_DI (SIM_CPU *, IADDR, SI, DI); | |
908 | void frvbf_mem_set_DF (SIM_CPU *, IADDR, SI, DF); | |
909 | void frvbf_mem_set_XI (SIM_CPU *, IADDR, SI, SI *); | |
910 | ||
911 | void frv_set_write_queue_slot (SIM_CPU *current_cpu); | |
912 | ||
913 | /* FRV specific options. */ | |
914 | extern const OPTION frv_options[]; | |
915 | ||
916 | #endif /* FRV_SIM_H */ |