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b34f6357 DB |
1 | /* frv simulator fr400 dependent profiling code. |
2 | ||
7b6bb8da JB |
3 | Copyright (C) 2001, 2007, 2008, 2009, 2010, 2011 |
4 | Free Software Foundation, Inc. | |
b34f6357 DB |
5 | Contributed by Red Hat |
6 | ||
7 | This file is part of the GNU simulators. | |
8 | ||
9 | This program is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
4744ac1b JB |
11 | the Free Software Foundation; either version 3 of the License, or |
12 | (at your option) any later version. | |
b34f6357 DB |
13 | |
14 | This program is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
4744ac1b JB |
19 | You should have received a copy of the GNU General Public License |
20 | along with this program. If not, see <http://www.gnu.org/licenses/>. | |
b34f6357 DB |
21 | |
22 | */ | |
23 | #define WANT_CPU | |
24 | #define WANT_CPU_FRVBF | |
25 | ||
26 | #include "sim-main.h" | |
27 | #include "bfd.h" | |
28 | ||
29 | #if WITH_PROFILE_MODEL_P | |
30 | ||
31 | #include "profile.h" | |
32 | #include "profile-fr400.h" | |
33 | ||
34 | /* These functions get and set flags representing the use of | |
35 | registers/resources. */ | |
36 | static void set_use_not_fp_load (SIM_CPU *, INT); | |
37 | static void set_use_not_media_p4 (SIM_CPU *, INT); | |
38 | static void set_use_not_media_p6 (SIM_CPU *, INT); | |
39 | ||
40 | static void set_acc_use_not_media_p2 (SIM_CPU *, INT); | |
41 | static void set_acc_use_not_media_p4 (SIM_CPU *, INT); | |
42 | ||
43 | void | |
44 | fr400_reset_gr_flags (SIM_CPU *cpu, INT fr) | |
45 | { | |
46 | set_use_not_gr_complex (cpu, fr); | |
47 | } | |
48 | ||
49 | void | |
50 | fr400_reset_fr_flags (SIM_CPU *cpu, INT fr) | |
51 | { | |
52 | set_use_not_fp_load (cpu, fr); | |
53 | set_use_not_media_p4 (cpu, fr); | |
54 | set_use_not_media_p6 (cpu, fr); | |
55 | } | |
56 | ||
57 | void | |
58 | fr400_reset_acc_flags (SIM_CPU *cpu, INT acc) | |
59 | { | |
60 | set_acc_use_not_media_p2 (cpu, acc); | |
61 | set_acc_use_not_media_p4 (cpu, acc); | |
62 | } | |
63 | ||
64 | static void | |
65 | set_use_is_fp_load (SIM_CPU *cpu, INT fr, INT fr_double) | |
66 | { | |
67 | MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); | |
68 | if (fr != -1) | |
69 | { | |
70 | fr400_reset_fr_flags (cpu, fr); | |
71 | d->cur_fp_load |= (((DI)1) << fr); | |
72 | } | |
73 | if (fr_double != -1) | |
74 | { | |
75 | fr400_reset_fr_flags (cpu, fr_double); | |
76 | d->cur_fp_load |= (((DI)1) << fr_double); | |
77 | if (fr_double < 63) | |
78 | { | |
79 | fr400_reset_fr_flags (cpu, fr_double + 1); | |
80 | d->cur_fp_load |= (((DI)1) << (fr_double + 1)); | |
81 | } | |
82 | } | |
83 | ||
84 | } | |
85 | ||
86 | static void | |
87 | set_use_not_fp_load (SIM_CPU *cpu, INT fr) | |
88 | { | |
89 | MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); | |
90 | if (fr != -1) | |
91 | d->cur_fp_load &= ~(((DI)1) << fr); | |
92 | } | |
93 | ||
94 | static int | |
95 | use_is_fp_load (SIM_CPU *cpu, INT fr) | |
96 | { | |
97 | MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); | |
98 | if (fr != -1) | |
99 | return (d->prev_fp_load >> fr) & 1; | |
100 | return 0; | |
101 | } | |
102 | ||
103 | static void | |
104 | set_acc_use_is_media_p2 (SIM_CPU *cpu, INT acc) | |
105 | { | |
106 | MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); | |
107 | if (acc != -1) | |
108 | { | |
109 | fr400_reset_acc_flags (cpu, acc); | |
110 | d->cur_acc_p2 |= (((DI)1) << acc); | |
111 | } | |
112 | } | |
113 | ||
114 | static void | |
115 | set_acc_use_not_media_p2 (SIM_CPU *cpu, INT acc) | |
116 | { | |
117 | MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); | |
118 | if (acc != -1) | |
119 | d->cur_acc_p2 &= ~(((DI)1) << acc); | |
120 | } | |
121 | ||
122 | static int | |
123 | acc_use_is_media_p2 (SIM_CPU *cpu, INT acc) | |
124 | { | |
125 | MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); | |
126 | if (acc != -1) | |
127 | return d->cur_acc_p2 & (((DI)1) << acc); | |
128 | return 0; | |
129 | } | |
130 | ||
131 | static void | |
132 | set_use_is_media_p4 (SIM_CPU *cpu, INT fr) | |
133 | { | |
134 | MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); | |
135 | if (fr != -1) | |
136 | { | |
137 | fr400_reset_fr_flags (cpu, fr); | |
138 | d->cur_fr_p4 |= (((DI)1) << fr); | |
139 | } | |
140 | } | |
141 | ||
142 | static void | |
143 | set_use_not_media_p4 (SIM_CPU *cpu, INT fr) | |
144 | { | |
145 | MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); | |
146 | if (fr != -1) | |
147 | d->cur_fr_p4 &= ~(((DI)1) << fr); | |
148 | } | |
149 | ||
150 | static int | |
151 | use_is_media_p4 (SIM_CPU *cpu, INT fr) | |
152 | { | |
153 | MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); | |
154 | if (fr != -1) | |
155 | return d->cur_fr_p4 & (((DI)1) << fr); | |
156 | return 0; | |
157 | } | |
158 | ||
159 | static void | |
160 | set_acc_use_is_media_p4 (SIM_CPU *cpu, INT acc) | |
161 | { | |
162 | MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); | |
163 | if (acc != -1) | |
164 | { | |
165 | fr400_reset_acc_flags (cpu, acc); | |
166 | d->cur_acc_p4 |= (((DI)1) << acc); | |
167 | } | |
168 | } | |
169 | ||
170 | static void | |
171 | set_acc_use_not_media_p4 (SIM_CPU *cpu, INT acc) | |
172 | { | |
173 | MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); | |
174 | if (acc != -1) | |
175 | d->cur_acc_p4 &= ~(((DI)1) << acc); | |
176 | } | |
177 | ||
178 | static int | |
179 | acc_use_is_media_p4 (SIM_CPU *cpu, INT acc) | |
180 | { | |
181 | MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); | |
182 | if (acc != -1) | |
183 | return d->cur_acc_p4 & (((DI)1) << acc); | |
184 | return 0; | |
185 | } | |
186 | ||
187 | static void | |
188 | set_use_is_media_p6 (SIM_CPU *cpu, INT fr) | |
189 | { | |
190 | MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); | |
191 | if (fr != -1) | |
192 | { | |
193 | fr400_reset_fr_flags (cpu, fr); | |
194 | d->cur_fr_p6 |= (((DI)1) << fr); | |
195 | } | |
196 | } | |
197 | ||
198 | static void | |
199 | set_use_not_media_p6 (SIM_CPU *cpu, INT fr) | |
200 | { | |
201 | MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); | |
202 | if (fr != -1) | |
203 | d->cur_fr_p6 &= ~(((DI)1) << fr); | |
204 | } | |
205 | ||
206 | static int | |
207 | use_is_media_p6 (SIM_CPU *cpu, INT fr) | |
208 | { | |
209 | MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); | |
210 | if (fr != -1) | |
211 | return d->cur_fr_p6 & (((DI)1) << fr); | |
212 | return 0; | |
213 | } | |
214 | ||
215 | /* Initialize cycle counting for an insn. | |
216 | FIRST_P is non-zero if this is the first insn in a set of parallel | |
217 | insns. */ | |
218 | void | |
219 | fr400_model_insn_before (SIM_CPU *cpu, int first_p) | |
220 | { | |
221 | if (first_p) | |
222 | { | |
223 | MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); | |
224 | FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); | |
225 | ps->cur_gr_complex = ps->prev_gr_complex; | |
226 | d->cur_fp_load = d->prev_fp_load; | |
227 | d->cur_fr_p4 = d->prev_fr_p4; | |
228 | d->cur_fr_p6 = d->prev_fr_p6; | |
229 | d->cur_acc_p2 = d->prev_acc_p2; | |
230 | d->cur_acc_p4 = d->prev_acc_p4; | |
231 | } | |
232 | } | |
233 | ||
234 | /* Record the cycles computed for an insn. | |
235 | LAST_P is non-zero if this is the last insn in a set of parallel insns, | |
236 | and we update the total cycle count. | |
237 | CYCLES is the cycle count of the insn. */ | |
238 | void | |
239 | fr400_model_insn_after (SIM_CPU *cpu, int last_p, int cycles) | |
240 | { | |
241 | if (last_p) | |
242 | { | |
243 | MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); | |
244 | FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); | |
245 | ps->prev_gr_complex = ps->cur_gr_complex; | |
246 | d->prev_fp_load = d->cur_fp_load; | |
247 | d->prev_fr_p4 = d->cur_fr_p4; | |
248 | d->prev_fr_p6 = d->cur_fr_p6; | |
249 | d->prev_acc_p2 = d->cur_acc_p2; | |
250 | d->prev_acc_p4 = d->cur_acc_p4; | |
251 | } | |
252 | } | |
253 | ||
254 | int | |
255 | frvbf_model_fr400_u_exec (SIM_CPU *cpu, const IDESC *idesc, | |
256 | int unit_num, int referenced) | |
257 | { | |
258 | return idesc->timing->units[unit_num].done; | |
259 | } | |
260 | ||
261 | int | |
262 | frvbf_model_fr400_u_integer (SIM_CPU *cpu, const IDESC *idesc, | |
263 | int unit_num, int referenced, | |
264 | INT in_GRi, INT in_GRj, INT out_GRk, | |
265 | INT out_ICCi_1) | |
266 | { | |
267 | /* Modelling for this unit is the same as for fr500. */ | |
268 | return frvbf_model_fr500_u_integer (cpu, idesc, unit_num, referenced, | |
269 | in_GRi, in_GRj, out_GRk, out_ICCi_1); | |
270 | } | |
271 | ||
272 | int | |
273 | frvbf_model_fr400_u_imul (SIM_CPU *cpu, const IDESC *idesc, | |
274 | int unit_num, int referenced, | |
275 | INT in_GRi, INT in_GRj, INT out_GRk, INT out_ICCi_1) | |
276 | { | |
277 | /* Modelling for this unit is the same as for fr500. */ | |
278 | return frvbf_model_fr500_u_imul (cpu, idesc, unit_num, referenced, | |
279 | in_GRi, in_GRj, out_GRk, out_ICCi_1); | |
280 | } | |
281 | ||
282 | int | |
283 | frvbf_model_fr400_u_idiv (SIM_CPU *cpu, const IDESC *idesc, | |
284 | int unit_num, int referenced, | |
285 | INT in_GRi, INT in_GRj, INT out_GRk, INT out_ICCi_1) | |
286 | { | |
287 | int cycles; | |
288 | FRV_VLIW *vliw; | |
289 | int slot; | |
290 | ||
291 | /* icc0-icc4 are the upper 4 fields of the CCR. */ | |
292 | if (out_ICCi_1 >= 0) | |
293 | out_ICCi_1 += 4; | |
294 | ||
295 | vliw = CPU_VLIW (cpu); | |
296 | slot = vliw->next_slot - 1; | |
297 | slot = (*vliw->current_vliw)[slot] - UNIT_I0; | |
298 | ||
299 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
300 | { | |
301 | /* The entire VLIW insn must wait if there is a dependency on a register | |
302 | which is not ready yet. | |
303 | The latency of the registers may be less than previously recorded, | |
304 | depending on how they were used previously. | |
305 | See Table 13-8 in the LSI. */ | |
306 | if (in_GRi != out_GRk && in_GRi >= 0) | |
307 | { | |
308 | if (use_is_gr_complex (cpu, in_GRi)) | |
309 | decrease_GR_busy (cpu, in_GRi, 1); | |
310 | } | |
311 | if (in_GRj != out_GRk && in_GRj != in_GRi && in_GRj >= 0) | |
312 | { | |
313 | if (use_is_gr_complex (cpu, in_GRj)) | |
314 | decrease_GR_busy (cpu, in_GRj, 1); | |
315 | } | |
316 | vliw_wait_for_GR (cpu, in_GRi); | |
317 | vliw_wait_for_GR (cpu, in_GRj); | |
318 | vliw_wait_for_GR (cpu, out_GRk); | |
319 | vliw_wait_for_CCR (cpu, out_ICCi_1); | |
320 | vliw_wait_for_idiv_resource (cpu, slot); | |
321 | handle_resource_wait (cpu); | |
322 | load_wait_for_GR (cpu, in_GRi); | |
323 | load_wait_for_GR (cpu, in_GRj); | |
324 | load_wait_for_GR (cpu, out_GRk); | |
325 | trace_vliw_wait_cycles (cpu); | |
326 | return 0; | |
327 | } | |
328 | ||
329 | /* GRk has a latency of 19 cycles! */ | |
330 | cycles = idesc->timing->units[unit_num].done; | |
331 | update_GR_latency (cpu, out_GRk, cycles + 19); | |
332 | set_use_is_gr_complex (cpu, out_GRk); | |
333 | ||
334 | /* ICCi_1 has a latency of 18 cycles. */ | |
335 | update_CCR_latency (cpu, out_ICCi_1, cycles + 18); | |
336 | ||
337 | /* the idiv resource has a latency of 18 cycles! */ | |
338 | update_idiv_resource_latency (cpu, slot, cycles + 18); | |
339 | ||
340 | return cycles; | |
341 | } | |
342 | ||
343 | int | |
344 | frvbf_model_fr400_u_branch (SIM_CPU *cpu, const IDESC *idesc, | |
345 | int unit_num, int referenced, | |
346 | INT in_GRi, INT in_GRj, | |
347 | INT in_ICCi_2, INT in_ICCi_3) | |
348 | { | |
349 | #define BRANCH_PREDICTED(ps) ((ps)->branch_hint & 2) | |
350 | FRV_PROFILE_STATE *ps; | |
351 | int cycles; | |
352 | ||
353 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
354 | { | |
355 | /* Modelling for this unit is the same as for fr500 in pass 1. */ | |
356 | return frvbf_model_fr500_u_branch (cpu, idesc, unit_num, referenced, | |
357 | in_GRi, in_GRj, in_ICCi_2, in_ICCi_3); | |
358 | } | |
359 | ||
360 | cycles = idesc->timing->units[unit_num].done; | |
361 | ||
362 | /* Compute the branch penalty, based on the the prediction and the out | |
363 | come. When counting branches taken or not taken, don't consider branches | |
364 | after the first taken branch in a vliw insn. */ | |
365 | ps = CPU_PROFILE_STATE (cpu); | |
366 | if (! ps->vliw_branch_taken) | |
367 | { | |
368 | int penalty; | |
369 | /* (1 << 4): The pc is the 5th element in inputs, outputs. | |
370 | ??? can be cleaned up */ | |
371 | PROFILE_DATA *p = CPU_PROFILE_DATA (cpu); | |
372 | int taken = (referenced & (1 << 4)) != 0; | |
373 | if (taken) | |
374 | { | |
375 | ++PROFILE_MODEL_TAKEN_COUNT (p); | |
376 | ps->vliw_branch_taken = 1; | |
377 | if (BRANCH_PREDICTED (ps)) | |
378 | penalty = 1; | |
379 | else | |
380 | penalty = 3; | |
381 | } | |
382 | else | |
383 | { | |
384 | ++PROFILE_MODEL_UNTAKEN_COUNT (p); | |
385 | if (BRANCH_PREDICTED (ps)) | |
386 | penalty = 3; | |
387 | else | |
388 | penalty = 0; | |
389 | } | |
390 | if (penalty > 0) | |
391 | { | |
392 | /* Additional 1 cycle penalty if the branch address is not 8 byte | |
393 | aligned. */ | |
394 | if (ps->branch_address & 7) | |
395 | ++penalty; | |
396 | update_branch_penalty (cpu, penalty); | |
397 | PROFILE_MODEL_CTI_STALL_CYCLES (p) += penalty; | |
398 | } | |
399 | } | |
400 | ||
401 | return cycles; | |
402 | } | |
403 | ||
404 | int | |
405 | frvbf_model_fr400_u_trap (SIM_CPU *cpu, const IDESC *idesc, | |
406 | int unit_num, int referenced, | |
407 | INT in_GRi, INT in_GRj, | |
408 | INT in_ICCi_2, INT in_FCCi_2) | |
409 | { | |
410 | /* Modelling for this unit is the same as for fr500. */ | |
411 | return frvbf_model_fr500_u_trap (cpu, idesc, unit_num, referenced, | |
412 | in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); | |
413 | } | |
414 | ||
415 | int | |
416 | frvbf_model_fr400_u_check (SIM_CPU *cpu, const IDESC *idesc, | |
417 | int unit_num, int referenced, | |
418 | INT in_ICCi_3, INT in_FCCi_3) | |
419 | { | |
420 | /* Modelling for this unit is the same as for fr500. */ | |
421 | return frvbf_model_fr500_u_check (cpu, idesc, unit_num, referenced, | |
422 | in_ICCi_3, in_FCCi_3); | |
423 | } | |
424 | ||
425 | int | |
426 | frvbf_model_fr400_u_set_hilo (SIM_CPU *cpu, const IDESC *idesc, | |
427 | int unit_num, int referenced, | |
428 | INT out_GRkhi, INT out_GRklo) | |
429 | { | |
430 | /* Modelling for this unit is the same as for fr500. */ | |
431 | return frvbf_model_fr500_u_set_hilo (cpu, idesc, unit_num, referenced, | |
432 | out_GRkhi, out_GRklo); | |
433 | } | |
434 | ||
435 | int | |
436 | frvbf_model_fr400_u_gr_load (SIM_CPU *cpu, const IDESC *idesc, | |
437 | int unit_num, int referenced, | |
438 | INT in_GRi, INT in_GRj, | |
439 | INT out_GRk, INT out_GRdoublek) | |
440 | { | |
441 | /* Modelling for this unit is the same as for fr500. */ | |
442 | return frvbf_model_fr500_u_gr_load (cpu, idesc, unit_num, referenced, | |
443 | in_GRi, in_GRj, out_GRk, out_GRdoublek); | |
444 | } | |
445 | ||
446 | int | |
447 | frvbf_model_fr400_u_gr_store (SIM_CPU *cpu, const IDESC *idesc, | |
448 | int unit_num, int referenced, | |
449 | INT in_GRi, INT in_GRj, | |
450 | INT in_GRk, INT in_GRdoublek) | |
451 | { | |
452 | /* Modelling for this unit is the same as for fr500. */ | |
453 | return frvbf_model_fr500_u_gr_store (cpu, idesc, unit_num, referenced, | |
454 | in_GRi, in_GRj, in_GRk, in_GRdoublek); | |
455 | } | |
456 | ||
457 | int | |
458 | frvbf_model_fr400_u_fr_load (SIM_CPU *cpu, const IDESC *idesc, | |
459 | int unit_num, int referenced, | |
460 | INT in_GRi, INT in_GRj, | |
461 | INT out_FRk, INT out_FRdoublek) | |
462 | { | |
463 | int cycles; | |
464 | ||
465 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
466 | { | |
467 | /* Pass 1 is the same as for fr500. */ | |
468 | return frvbf_model_fr500_u_fr_load (cpu, idesc, unit_num, referenced, | |
469 | in_GRi, in_GRj, out_FRk, | |
470 | out_FRdoublek); | |
471 | } | |
472 | ||
473 | cycles = idesc->timing->units[unit_num].done; | |
474 | ||
475 | /* The latency of FRk for a load will depend on how long it takes to retrieve | |
476 | the the data from the cache or memory. */ | |
477 | update_FR_latency_for_load (cpu, out_FRk, cycles); | |
478 | update_FRdouble_latency_for_load (cpu, out_FRdoublek, cycles); | |
479 | ||
480 | set_use_is_fp_load (cpu, out_FRk, out_FRdoublek); | |
481 | ||
482 | return cycles; | |
483 | } | |
484 | ||
485 | int | |
486 | frvbf_model_fr400_u_fr_store (SIM_CPU *cpu, const IDESC *idesc, | |
487 | int unit_num, int referenced, | |
488 | INT in_GRi, INT in_GRj, | |
489 | INT in_FRk, INT in_FRdoublek) | |
490 | { | |
491 | int cycles; | |
492 | ||
493 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
494 | { | |
495 | /* The entire VLIW insn must wait if there is a dependency on a register | |
496 | which is not ready yet. | |
497 | The latency of the registers may be less than previously recorded, | |
498 | depending on how they were used previously. | |
499 | See Table 13-8 in the LSI. */ | |
500 | if (in_GRi >= 0) | |
501 | { | |
502 | if (use_is_gr_complex (cpu, in_GRi)) | |
503 | decrease_GR_busy (cpu, in_GRi, 1); | |
504 | } | |
505 | if (in_GRj != in_GRi && in_GRj >= 0) | |
506 | { | |
507 | if (use_is_gr_complex (cpu, in_GRj)) | |
508 | decrease_GR_busy (cpu, in_GRj, 1); | |
509 | } | |
510 | if (in_FRk >= 0) | |
511 | { | |
512 | if (use_is_media_p4 (cpu, in_FRk) || use_is_media_p6 (cpu, in_FRk)) | |
513 | decrease_FR_busy (cpu, in_FRk, 1); | |
514 | else | |
515 | enforce_full_fr_latency (cpu, in_FRk); | |
516 | } | |
517 | vliw_wait_for_GR (cpu, in_GRi); | |
518 | vliw_wait_for_GR (cpu, in_GRj); | |
519 | vliw_wait_for_FR (cpu, in_FRk); | |
520 | vliw_wait_for_FRdouble (cpu, in_FRdoublek); | |
521 | handle_resource_wait (cpu); | |
522 | load_wait_for_GR (cpu, in_GRi); | |
523 | load_wait_for_GR (cpu, in_GRj); | |
524 | load_wait_for_FR (cpu, in_FRk); | |
525 | load_wait_for_FRdouble (cpu, in_FRdoublek); | |
526 | trace_vliw_wait_cycles (cpu); | |
527 | return 0; | |
528 | } | |
529 | ||
530 | cycles = idesc->timing->units[unit_num].done; | |
531 | ||
532 | return cycles; | |
533 | } | |
534 | ||
535 | int | |
536 | frvbf_model_fr400_u_swap (SIM_CPU *cpu, const IDESC *idesc, | |
537 | int unit_num, int referenced, | |
538 | INT in_GRi, INT in_GRj, INT out_GRk) | |
539 | { | |
540 | /* Modelling for this unit is the same as for fr500. */ | |
541 | return frvbf_model_fr500_u_swap (cpu, idesc, unit_num, referenced, | |
542 | in_GRi, in_GRj, out_GRk); | |
543 | } | |
544 | ||
545 | int | |
546 | frvbf_model_fr400_u_fr2gr (SIM_CPU *cpu, const IDESC *idesc, | |
547 | int unit_num, int referenced, | |
548 | INT in_FRk, INT out_GRj) | |
549 | { | |
550 | int cycles; | |
551 | ||
552 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
553 | { | |
554 | /* The entire VLIW insn must wait if there is a dependency on a register | |
555 | which is not ready yet. | |
556 | The latency of the registers may be less than previously recorded, | |
557 | depending on how they were used previously. | |
558 | See Table 13-8 in the LSI. */ | |
559 | if (in_FRk >= 0) | |
560 | { | |
561 | if (use_is_media_p4 (cpu, in_FRk) || use_is_media_p6 (cpu, in_FRk)) | |
562 | decrease_FR_busy (cpu, in_FRk, 1); | |
563 | else | |
564 | enforce_full_fr_latency (cpu, in_FRk); | |
565 | } | |
566 | vliw_wait_for_FR (cpu, in_FRk); | |
567 | vliw_wait_for_GR (cpu, out_GRj); | |
568 | handle_resource_wait (cpu); | |
569 | load_wait_for_FR (cpu, in_FRk); | |
570 | load_wait_for_GR (cpu, out_GRj); | |
571 | trace_vliw_wait_cycles (cpu); | |
572 | return 0; | |
573 | } | |
574 | ||
575 | /* The latency of GRj is 2 cycles. */ | |
576 | cycles = idesc->timing->units[unit_num].done; | |
577 | update_GR_latency (cpu, out_GRj, cycles + 2); | |
578 | set_use_is_gr_complex (cpu, out_GRj); | |
579 | ||
580 | return cycles; | |
581 | } | |
582 | ||
583 | int | |
584 | frvbf_model_fr400_u_spr2gr (SIM_CPU *cpu, const IDESC *idesc, | |
585 | int unit_num, int referenced, | |
586 | INT in_spr, INT out_GRj) | |
587 | { | |
588 | /* Modelling for this unit is the same as for fr500. */ | |
589 | return frvbf_model_fr500_u_spr2gr (cpu, idesc, unit_num, referenced, | |
590 | in_spr, out_GRj); | |
591 | } | |
592 | ||
593 | int | |
594 | frvbf_model_fr400_u_gr2fr (SIM_CPU *cpu, const IDESC *idesc, | |
595 | int unit_num, int referenced, | |
596 | INT in_GRj, INT out_FRk) | |
597 | { | |
598 | int cycles; | |
599 | ||
600 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
601 | { | |
602 | /* Pass 1 is the same as for fr500. */ | |
603 | frvbf_model_fr500_u_gr2fr (cpu, idesc, unit_num, referenced, | |
604 | in_GRj, out_FRk); | |
605 | } | |
606 | ||
607 | /* The latency of FRk is 1 cycles. */ | |
608 | cycles = idesc->timing->units[unit_num].done; | |
609 | update_FR_latency (cpu, out_FRk, cycles + 1); | |
610 | ||
611 | return cycles; | |
612 | } | |
613 | ||
614 | int | |
615 | frvbf_model_fr400_u_gr2spr (SIM_CPU *cpu, const IDESC *idesc, | |
616 | int unit_num, int referenced, | |
617 | INT in_GRj, INT out_spr) | |
618 | { | |
619 | /* Modelling for this unit is the same as for fr500. */ | |
620 | return frvbf_model_fr500_u_gr2spr (cpu, idesc, unit_num, referenced, | |
621 | in_GRj, out_spr); | |
622 | } | |
623 | ||
b34f6357 DB |
624 | int |
625 | frvbf_model_fr400_u_media_1 (SIM_CPU *cpu, const IDESC *idesc, | |
626 | int unit_num, int referenced, | |
627 | INT in_FRi, INT in_FRj, | |
628 | INT out_FRk) | |
629 | { | |
630 | int cycles; | |
631 | FRV_PROFILE_STATE *ps; | |
632 | const CGEN_INSN *insn; | |
633 | int busy_adjustment[] = {0, 0}; | |
634 | int *fr; | |
635 | ||
636 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
637 | return 0; | |
638 | ||
639 | /* The preprocessing can execute right away. */ | |
640 | cycles = idesc->timing->units[unit_num].done; | |
641 | ||
642 | ps = CPU_PROFILE_STATE (cpu); | |
643 | insn = idesc->idata; | |
644 | ||
645 | /* The latency of the registers may be less than previously recorded, | |
646 | depending on how they were used previously. | |
647 | See Table 13-8 in the LSI. */ | |
648 | if (in_FRi >= 0) | |
649 | { | |
650 | if (use_is_fp_load (cpu, in_FRi)) | |
651 | { | |
652 | busy_adjustment[0] = 1; | |
653 | decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]); | |
654 | } | |
655 | else | |
656 | enforce_full_fr_latency (cpu, in_FRi); | |
657 | } | |
658 | if (in_FRj >= 0 && in_FRj != in_FRi) | |
659 | { | |
660 | if (use_is_fp_load (cpu, in_FRj)) | |
661 | { | |
662 | busy_adjustment[1] = 1; | |
663 | decrease_FR_busy (cpu, in_FRj, busy_adjustment[1]); | |
664 | } | |
665 | else | |
666 | enforce_full_fr_latency (cpu, in_FRj); | |
667 | } | |
668 | ||
669 | /* The post processing must wait if there is a dependency on a FR | |
670 | which is not ready yet. */ | |
671 | ps->post_wait = cycles; | |
672 | post_wait_for_FR (cpu, in_FRi); | |
673 | post_wait_for_FR (cpu, in_FRj); | |
674 | post_wait_for_FR (cpu, out_FRk); | |
675 | ||
676 | /* Restore the busy cycles of the registers we used. */ | |
677 | fr = ps->fr_busy; | |
678 | if (in_FRi >= 0) | |
679 | fr[in_FRi] += busy_adjustment[0]; | |
680 | if (in_FRj >= 0) | |
681 | fr[in_FRj] += busy_adjustment[1]; | |
682 | ||
683 | /* The latency of the output register will be at least the latency of the | |
684 | other inputs. Once initiated, post-processing has no latency. */ | |
685 | if (out_FRk >= 0) | |
686 | { | |
687 | update_FR_latency (cpu, out_FRk, ps->post_wait); | |
688 | update_FR_ptime (cpu, out_FRk, 0); | |
689 | } | |
690 | ||
691 | return cycles; | |
692 | } | |
693 | ||
694 | int | |
695 | frvbf_model_fr400_u_media_1_quad (SIM_CPU *cpu, const IDESC *idesc, | |
696 | int unit_num, int referenced, | |
697 | INT in_FRi, INT in_FRj, | |
698 | INT out_FRk) | |
699 | { | |
700 | int cycles; | |
701 | INT dual_FRi; | |
702 | INT dual_FRj; | |
703 | INT dual_FRk; | |
704 | FRV_PROFILE_STATE *ps; | |
705 | int busy_adjustment[] = {0, 0, 0, 0}; | |
706 | int *fr; | |
707 | ||
708 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
709 | return 0; | |
710 | ||
711 | /* The preprocessing can execute right away. */ | |
712 | cycles = idesc->timing->units[unit_num].done; | |
713 | ||
714 | ps = CPU_PROFILE_STATE (cpu); | |
715 | dual_FRi = DUAL_REG (in_FRi); | |
716 | dual_FRj = DUAL_REG (in_FRj); | |
717 | dual_FRk = DUAL_REG (out_FRk); | |
718 | ||
719 | /* The latency of the registers may be less than previously recorded, | |
720 | depending on how they were used previously. | |
721 | See Table 13-8 in the LSI. */ | |
722 | if (use_is_fp_load (cpu, in_FRi)) | |
723 | { | |
724 | busy_adjustment[0] = 1; | |
725 | decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]); | |
726 | } | |
727 | else | |
728 | enforce_full_fr_latency (cpu, in_FRi); | |
729 | if (dual_FRi >= 0 && use_is_fp_load (cpu, dual_FRi)) | |
730 | { | |
731 | busy_adjustment[1] = 1; | |
732 | decrease_FR_busy (cpu, dual_FRi, busy_adjustment[1]); | |
733 | } | |
734 | else | |
735 | enforce_full_fr_latency (cpu, dual_FRi); | |
736 | if (in_FRj != in_FRi) | |
737 | { | |
738 | if (use_is_fp_load (cpu, in_FRj)) | |
739 | { | |
740 | busy_adjustment[2] = 1; | |
741 | decrease_FR_busy (cpu, in_FRj, busy_adjustment[2]); | |
742 | } | |
743 | else | |
744 | enforce_full_fr_latency (cpu, in_FRj); | |
745 | if (dual_FRj >= 0 && use_is_fp_load (cpu, dual_FRj)) | |
746 | { | |
747 | busy_adjustment[3] = 1; | |
748 | decrease_FR_busy (cpu, dual_FRj, busy_adjustment[3]); | |
749 | } | |
750 | else | |
751 | enforce_full_fr_latency (cpu, dual_FRj); | |
752 | } | |
753 | ||
754 | /* The post processing must wait if there is a dependency on a FR | |
755 | which is not ready yet. */ | |
756 | ps->post_wait = cycles; | |
757 | post_wait_for_FR (cpu, in_FRi); | |
758 | post_wait_for_FR (cpu, dual_FRi); | |
759 | post_wait_for_FR (cpu, in_FRj); | |
760 | post_wait_for_FR (cpu, dual_FRj); | |
761 | post_wait_for_FR (cpu, out_FRk); | |
762 | post_wait_for_FR (cpu, dual_FRk); | |
763 | ||
764 | /* Restore the busy cycles of the registers we used. */ | |
765 | fr = ps->fr_busy; | |
766 | fr[in_FRi] += busy_adjustment[0]; | |
767 | if (dual_FRi >= 0) | |
768 | fr[dual_FRi] += busy_adjustment[1]; | |
769 | fr[in_FRj] += busy_adjustment[2]; | |
770 | if (dual_FRj >= 0) | |
771 | fr[dual_FRj] += busy_adjustment[3]; | |
772 | ||
773 | /* The latency of the output register will be at least the latency of the | |
774 | other inputs. */ | |
775 | update_FR_latency (cpu, out_FRk, ps->post_wait); | |
776 | ||
777 | /* Once initiated, post-processing has no latency. */ | |
778 | update_FR_ptime (cpu, out_FRk, 0); | |
779 | ||
780 | if (dual_FRk >= 0) | |
781 | { | |
782 | update_FR_latency (cpu, dual_FRk, ps->post_wait); | |
783 | update_FR_ptime (cpu, dual_FRk, 0); | |
784 | } | |
785 | ||
786 | return cycles; | |
787 | } | |
788 | ||
789 | int | |
790 | frvbf_model_fr400_u_media_hilo (SIM_CPU *cpu, const IDESC *idesc, | |
791 | int unit_num, int referenced, | |
792 | INT out_FRkhi, INT out_FRklo) | |
793 | { | |
794 | int cycles; | |
795 | FRV_PROFILE_STATE *ps; | |
796 | ||
797 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
798 | return 0; | |
799 | ||
800 | /* The preprocessing can execute right away. */ | |
801 | cycles = idesc->timing->units[unit_num].done; | |
802 | ||
803 | ps = CPU_PROFILE_STATE (cpu); | |
804 | ||
805 | /* The post processing must wait if there is a dependency on a FR | |
806 | which is not ready yet. */ | |
807 | ps->post_wait = cycles; | |
808 | post_wait_for_FR (cpu, out_FRkhi); | |
809 | post_wait_for_FR (cpu, out_FRklo); | |
810 | ||
811 | /* The latency of the output register will be at least the latency of the | |
812 | other inputs. Once initiated, post-processing has no latency. */ | |
813 | if (out_FRkhi >= 0) | |
814 | { | |
815 | update_FR_latency (cpu, out_FRkhi, ps->post_wait); | |
816 | update_FR_ptime (cpu, out_FRkhi, 0); | |
817 | } | |
818 | if (out_FRklo >= 0) | |
819 | { | |
820 | update_FR_latency (cpu, out_FRklo, ps->post_wait); | |
821 | update_FR_ptime (cpu, out_FRklo, 0); | |
822 | } | |
823 | ||
824 | return cycles; | |
825 | } | |
826 | ||
827 | int | |
828 | frvbf_model_fr400_u_media_2 (SIM_CPU *cpu, const IDESC *idesc, | |
829 | int unit_num, int referenced, | |
830 | INT in_FRi, INT in_FRj, | |
831 | INT out_ACC40Sk, INT out_ACC40Uk) | |
832 | { | |
833 | int cycles; | |
834 | INT dual_ACC40Sk; | |
835 | INT dual_ACC40Uk; | |
836 | FRV_PROFILE_STATE *ps; | |
837 | int busy_adjustment[] = {0, 0, 0, 0, 0, 0}; | |
838 | int *fr; | |
839 | int *acc; | |
840 | ||
841 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
842 | return 0; | |
843 | ||
844 | /* The preprocessing can execute right away. */ | |
845 | cycles = idesc->timing->units[unit_num].done; | |
846 | ||
847 | ps = CPU_PROFILE_STATE (cpu); | |
848 | dual_ACC40Sk = DUAL_REG (out_ACC40Sk); | |
849 | dual_ACC40Uk = DUAL_REG (out_ACC40Uk); | |
850 | ||
851 | /* The latency of the registers may be less than previously recorded, | |
852 | depending on how they were used previously. | |
853 | See Table 13-8 in the LSI. */ | |
854 | if (in_FRi >= 0) | |
855 | { | |
856 | if (use_is_fp_load (cpu, in_FRi)) | |
857 | { | |
858 | busy_adjustment[0] = 1; | |
859 | decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]); | |
860 | } | |
861 | else | |
862 | enforce_full_fr_latency (cpu, in_FRi); | |
863 | } | |
864 | if (in_FRj >= 0 && in_FRj != in_FRi) | |
865 | { | |
866 | if (use_is_fp_load (cpu, in_FRj)) | |
867 | { | |
868 | busy_adjustment[1] = 1; | |
869 | decrease_FR_busy (cpu, in_FRj, busy_adjustment[1]); | |
870 | } | |
871 | else | |
872 | enforce_full_fr_latency (cpu, in_FRj); | |
873 | } | |
874 | if (out_ACC40Sk >= 0) | |
875 | { | |
876 | if (acc_use_is_media_p2 (cpu, out_ACC40Sk)) | |
877 | { | |
878 | busy_adjustment[2] = 1; | |
879 | decrease_ACC_busy (cpu, out_ACC40Sk, busy_adjustment[2]); | |
880 | } | |
881 | } | |
882 | if (dual_ACC40Sk >= 0) | |
883 | { | |
884 | if (acc_use_is_media_p2 (cpu, dual_ACC40Sk)) | |
885 | { | |
886 | busy_adjustment[3] = 1; | |
887 | decrease_ACC_busy (cpu, dual_ACC40Sk, busy_adjustment[3]); | |
888 | } | |
889 | } | |
890 | if (out_ACC40Uk >= 0) | |
891 | { | |
892 | if (acc_use_is_media_p2 (cpu, out_ACC40Uk)) | |
893 | { | |
894 | busy_adjustment[4] = 1; | |
895 | decrease_ACC_busy (cpu, out_ACC40Uk, busy_adjustment[4]); | |
896 | } | |
897 | } | |
898 | if (dual_ACC40Uk >= 0) | |
899 | { | |
900 | if (acc_use_is_media_p2 (cpu, dual_ACC40Uk)) | |
901 | { | |
902 | busy_adjustment[5] = 1; | |
903 | decrease_ACC_busy (cpu, dual_ACC40Uk, busy_adjustment[5]); | |
904 | } | |
905 | } | |
906 | ||
907 | /* The post processing must wait if there is a dependency on a FR | |
908 | which is not ready yet. */ | |
909 | ps->post_wait = cycles; | |
910 | post_wait_for_FR (cpu, in_FRi); | |
911 | post_wait_for_FR (cpu, in_FRj); | |
912 | post_wait_for_ACC (cpu, out_ACC40Sk); | |
913 | post_wait_for_ACC (cpu, dual_ACC40Sk); | |
914 | post_wait_for_ACC (cpu, out_ACC40Uk); | |
915 | post_wait_for_ACC (cpu, dual_ACC40Uk); | |
916 | ||
917 | /* Restore the busy cycles of the registers we used. */ | |
918 | fr = ps->fr_busy; | |
919 | acc = ps->acc_busy; | |
920 | fr[in_FRi] += busy_adjustment[0]; | |
921 | fr[in_FRj] += busy_adjustment[1]; | |
922 | if (out_ACC40Sk >= 0) | |
923 | acc[out_ACC40Sk] += busy_adjustment[2]; | |
924 | if (dual_ACC40Sk >= 0) | |
925 | acc[dual_ACC40Sk] += busy_adjustment[3]; | |
926 | if (out_ACC40Uk >= 0) | |
927 | acc[out_ACC40Uk] += busy_adjustment[4]; | |
928 | if (dual_ACC40Uk >= 0) | |
929 | acc[dual_ACC40Uk] += busy_adjustment[5]; | |
930 | ||
931 | /* The latency of the output register will be at least the latency of the | |
932 | other inputs. Once initiated, post-processing will take 1 cycles. */ | |
933 | if (out_ACC40Sk >= 0) | |
934 | { | |
935 | update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1); | |
936 | set_acc_use_is_media_p2 (cpu, out_ACC40Sk); | |
937 | } | |
938 | if (dual_ACC40Sk >= 0) | |
939 | { | |
940 | update_ACC_latency (cpu, dual_ACC40Sk, ps->post_wait + 1); | |
941 | set_acc_use_is_media_p2 (cpu, dual_ACC40Sk); | |
942 | } | |
943 | if (out_ACC40Uk >= 0) | |
944 | { | |
945 | update_ACC_latency (cpu, out_ACC40Uk, ps->post_wait + 1); | |
946 | set_acc_use_is_media_p2 (cpu, out_ACC40Uk); | |
947 | } | |
948 | if (dual_ACC40Uk >= 0) | |
949 | { | |
950 | update_ACC_latency (cpu, dual_ACC40Uk, ps->post_wait + 1); | |
951 | set_acc_use_is_media_p2 (cpu, dual_ACC40Uk); | |
952 | } | |
953 | ||
954 | return cycles; | |
955 | } | |
956 | ||
957 | int | |
958 | frvbf_model_fr400_u_media_2_quad (SIM_CPU *cpu, const IDESC *idesc, | |
959 | int unit_num, int referenced, | |
960 | INT in_FRi, INT in_FRj, | |
961 | INT out_ACC40Sk, INT out_ACC40Uk) | |
962 | { | |
963 | int cycles; | |
964 | INT dual_FRi; | |
965 | INT dual_FRj; | |
966 | INT ACC40Sk_1; | |
967 | INT ACC40Sk_2; | |
968 | INT ACC40Sk_3; | |
969 | INT ACC40Uk_1; | |
970 | INT ACC40Uk_2; | |
971 | INT ACC40Uk_3; | |
972 | FRV_PROFILE_STATE *ps; | |
973 | int busy_adjustment[] = {0, 0, 0, 0, 0, 0, 0 ,0}; | |
974 | int *fr; | |
975 | int *acc; | |
976 | ||
977 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
978 | return 0; | |
979 | ||
980 | /* The preprocessing can execute right away. */ | |
981 | cycles = idesc->timing->units[unit_num].done; | |
982 | ||
983 | dual_FRi = DUAL_REG (in_FRi); | |
984 | dual_FRj = DUAL_REG (in_FRj); | |
985 | ACC40Sk_1 = DUAL_REG (out_ACC40Sk); | |
986 | ACC40Sk_2 = DUAL_REG (ACC40Sk_1); | |
987 | ACC40Sk_3 = DUAL_REG (ACC40Sk_2); | |
988 | ACC40Uk_1 = DUAL_REG (out_ACC40Uk); | |
989 | ACC40Uk_2 = DUAL_REG (ACC40Uk_1); | |
990 | ACC40Uk_3 = DUAL_REG (ACC40Uk_2); | |
991 | ||
992 | ps = CPU_PROFILE_STATE (cpu); | |
993 | /* The latency of the registers may be less than previously recorded, | |
994 | depending on how they were used previously. | |
995 | See Table 13-8 in the LSI. */ | |
996 | if (use_is_fp_load (cpu, in_FRi)) | |
997 | { | |
998 | busy_adjustment[0] = 1; | |
999 | decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]); | |
1000 | } | |
1001 | else | |
1002 | enforce_full_fr_latency (cpu, in_FRi); | |
1003 | if (dual_FRi >= 0 && use_is_fp_load (cpu, dual_FRi)) | |
1004 | { | |
1005 | busy_adjustment[1] = 1; | |
1006 | decrease_FR_busy (cpu, dual_FRi, busy_adjustment[1]); | |
1007 | } | |
1008 | else | |
1009 | enforce_full_fr_latency (cpu, dual_FRi); | |
1010 | if (in_FRj != in_FRi) | |
1011 | { | |
1012 | if (use_is_fp_load (cpu, in_FRj)) | |
1013 | { | |
1014 | busy_adjustment[2] = 1; | |
1015 | decrease_FR_busy (cpu, in_FRj, busy_adjustment[2]); | |
1016 | } | |
1017 | else | |
1018 | enforce_full_fr_latency (cpu, in_FRj); | |
1019 | if (dual_FRj >= 0 && use_is_fp_load (cpu, dual_FRj)) | |
1020 | { | |
1021 | busy_adjustment[3] = 1; | |
1022 | decrease_FR_busy (cpu, dual_FRj, busy_adjustment[3]); | |
1023 | } | |
1024 | else | |
1025 | enforce_full_fr_latency (cpu, dual_FRj); | |
1026 | } | |
1027 | if (out_ACC40Sk >= 0) | |
1028 | { | |
1029 | if (acc_use_is_media_p2 (cpu, out_ACC40Sk)) | |
1030 | { | |
1031 | busy_adjustment[4] = 1; | |
1032 | decrease_ACC_busy (cpu, out_ACC40Sk, busy_adjustment[4]); | |
1033 | } | |
1034 | if (ACC40Sk_1 >= 0) | |
1035 | { | |
1036 | if (acc_use_is_media_p2 (cpu, ACC40Sk_1)) | |
1037 | { | |
1038 | busy_adjustment[5] = 1; | |
1039 | decrease_ACC_busy (cpu, ACC40Sk_1, busy_adjustment[5]); | |
1040 | } | |
1041 | } | |
1042 | if (ACC40Sk_2 >= 0) | |
1043 | { | |
1044 | if (acc_use_is_media_p2 (cpu, ACC40Sk_2)) | |
1045 | { | |
1046 | busy_adjustment[6] = 1; | |
1047 | decrease_ACC_busy (cpu, ACC40Sk_2, busy_adjustment[6]); | |
1048 | } | |
1049 | } | |
1050 | if (ACC40Sk_3 >= 0) | |
1051 | { | |
1052 | if (acc_use_is_media_p2 (cpu, ACC40Sk_3)) | |
1053 | { | |
1054 | busy_adjustment[7] = 1; | |
1055 | decrease_ACC_busy (cpu, ACC40Sk_3, busy_adjustment[7]); | |
1056 | } | |
1057 | } | |
1058 | } | |
1059 | else if (out_ACC40Uk >= 0) | |
1060 | { | |
1061 | if (acc_use_is_media_p2 (cpu, out_ACC40Uk)) | |
1062 | { | |
1063 | busy_adjustment[4] = 1; | |
1064 | decrease_ACC_busy (cpu, out_ACC40Uk, busy_adjustment[4]); | |
1065 | } | |
1066 | if (ACC40Uk_1 >= 0) | |
1067 | { | |
1068 | if (acc_use_is_media_p2 (cpu, ACC40Uk_1)) | |
1069 | { | |
1070 | busy_adjustment[5] = 1; | |
1071 | decrease_ACC_busy (cpu, ACC40Uk_1, busy_adjustment[5]); | |
1072 | } | |
1073 | } | |
1074 | if (ACC40Uk_2 >= 0) | |
1075 | { | |
1076 | if (acc_use_is_media_p2 (cpu, ACC40Uk_2)) | |
1077 | { | |
1078 | busy_adjustment[6] = 1; | |
1079 | decrease_ACC_busy (cpu, ACC40Uk_2, busy_adjustment[6]); | |
1080 | } | |
1081 | } | |
1082 | if (ACC40Uk_3 >= 0) | |
1083 | { | |
1084 | if (acc_use_is_media_p2 (cpu, ACC40Uk_3)) | |
1085 | { | |
1086 | busy_adjustment[7] = 1; | |
1087 | decrease_ACC_busy (cpu, ACC40Uk_3, busy_adjustment[7]); | |
1088 | } | |
1089 | } | |
1090 | } | |
1091 | ||
1092 | /* The post processing must wait if there is a dependency on a FR | |
1093 | which is not ready yet. */ | |
1094 | ps->post_wait = cycles; | |
1095 | post_wait_for_FR (cpu, in_FRi); | |
1096 | post_wait_for_FR (cpu, dual_FRi); | |
1097 | post_wait_for_FR (cpu, in_FRj); | |
1098 | post_wait_for_FR (cpu, dual_FRj); | |
1099 | post_wait_for_ACC (cpu, out_ACC40Sk); | |
1100 | post_wait_for_ACC (cpu, ACC40Sk_1); | |
1101 | post_wait_for_ACC (cpu, ACC40Sk_2); | |
1102 | post_wait_for_ACC (cpu, ACC40Sk_3); | |
1103 | post_wait_for_ACC (cpu, out_ACC40Uk); | |
1104 | post_wait_for_ACC (cpu, ACC40Uk_1); | |
1105 | post_wait_for_ACC (cpu, ACC40Uk_2); | |
1106 | post_wait_for_ACC (cpu, ACC40Uk_3); | |
1107 | ||
1108 | /* Restore the busy cycles of the registers we used. */ | |
1109 | fr = ps->fr_busy; | |
1110 | acc = ps->acc_busy; | |
1111 | fr[in_FRi] += busy_adjustment[0]; | |
1112 | if (dual_FRi >= 0) | |
1113 | fr[dual_FRi] += busy_adjustment[1]; | |
1114 | fr[in_FRj] += busy_adjustment[2]; | |
1115 | if (dual_FRj > 0) | |
1116 | fr[dual_FRj] += busy_adjustment[3]; | |
1117 | if (out_ACC40Sk >= 0) | |
1118 | { | |
1119 | acc[out_ACC40Sk] += busy_adjustment[4]; | |
1120 | if (ACC40Sk_1 >= 0) | |
1121 | acc[ACC40Sk_1] += busy_adjustment[5]; | |
1122 | if (ACC40Sk_2 >= 0) | |
1123 | acc[ACC40Sk_2] += busy_adjustment[6]; | |
1124 | if (ACC40Sk_3 >= 0) | |
1125 | acc[ACC40Sk_3] += busy_adjustment[7]; | |
1126 | } | |
1127 | else if (out_ACC40Uk >= 0) | |
1128 | { | |
1129 | acc[out_ACC40Uk] += busy_adjustment[4]; | |
1130 | if (ACC40Uk_1 >= 0) | |
1131 | acc[ACC40Uk_1] += busy_adjustment[5]; | |
1132 | if (ACC40Uk_2 >= 0) | |
1133 | acc[ACC40Uk_2] += busy_adjustment[6]; | |
1134 | if (ACC40Uk_3 >= 0) | |
1135 | acc[ACC40Uk_3] += busy_adjustment[7]; | |
1136 | } | |
1137 | ||
1138 | /* The latency of the output register will be at least the latency of the | |
1139 | other inputs. Once initiated, post-processing will take 1 cycle. */ | |
1140 | if (out_ACC40Sk >= 0) | |
1141 | { | |
1142 | update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1); | |
1143 | ||
1144 | set_acc_use_is_media_p2 (cpu, out_ACC40Sk); | |
1145 | if (ACC40Sk_1 >= 0) | |
1146 | { | |
1147 | update_ACC_latency (cpu, ACC40Sk_1, ps->post_wait + 1); | |
1148 | ||
1149 | set_acc_use_is_media_p2 (cpu, ACC40Sk_1); | |
1150 | } | |
1151 | if (ACC40Sk_2 >= 0) | |
1152 | { | |
1153 | update_ACC_latency (cpu, ACC40Sk_2, ps->post_wait + 1); | |
1154 | ||
1155 | set_acc_use_is_media_p2 (cpu, ACC40Sk_2); | |
1156 | } | |
1157 | if (ACC40Sk_3 >= 0) | |
1158 | { | |
1159 | update_ACC_latency (cpu, ACC40Sk_3, ps->post_wait + 1); | |
1160 | ||
1161 | set_acc_use_is_media_p2 (cpu, ACC40Sk_3); | |
1162 | } | |
1163 | } | |
1164 | else if (out_ACC40Uk >= 0) | |
1165 | { | |
1166 | update_ACC_latency (cpu, out_ACC40Uk, ps->post_wait + 1); | |
1167 | ||
1168 | set_acc_use_is_media_p2 (cpu, out_ACC40Uk); | |
1169 | if (ACC40Uk_1 >= 0) | |
1170 | { | |
1171 | update_ACC_latency (cpu, ACC40Uk_1, ps->post_wait + 1); | |
1172 | ||
1173 | set_acc_use_is_media_p2 (cpu, ACC40Uk_1); | |
1174 | } | |
1175 | if (ACC40Uk_2 >= 0) | |
1176 | { | |
1177 | update_ACC_latency (cpu, ACC40Uk_2, ps->post_wait + 1); | |
1178 | ||
1179 | set_acc_use_is_media_p2 (cpu, ACC40Uk_2); | |
1180 | } | |
1181 | if (ACC40Uk_3 >= 0) | |
1182 | { | |
1183 | update_ACC_latency (cpu, ACC40Uk_3, ps->post_wait + 1); | |
1184 | ||
1185 | set_acc_use_is_media_p2 (cpu, ACC40Uk_3); | |
1186 | } | |
1187 | } | |
1188 | ||
1189 | return cycles; | |
1190 | } | |
1191 | ||
1192 | int | |
1193 | frvbf_model_fr400_u_media_2_acc (SIM_CPU *cpu, const IDESC *idesc, | |
1194 | int unit_num, int referenced, | |
1195 | INT in_ACC40Si, INT out_ACC40Sk) | |
1196 | { | |
1197 | int cycles; | |
1198 | INT ACC40Si_1; | |
1199 | FRV_PROFILE_STATE *ps; | |
1200 | int busy_adjustment[] = {0, 0, 0}; | |
1201 | int *acc; | |
1202 | ||
1203 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
1204 | return 0; | |
1205 | ||
1206 | /* The preprocessing can execute right away. */ | |
1207 | cycles = idesc->timing->units[unit_num].done; | |
1208 | ||
1209 | ACC40Si_1 = DUAL_REG (in_ACC40Si); | |
1210 | ||
1211 | ps = CPU_PROFILE_STATE (cpu); | |
1212 | /* The latency of the registers may be less than previously recorded, | |
1213 | depending on how they were used previously. | |
1214 | See Table 13-8 in the LSI. */ | |
1215 | if (acc_use_is_media_p2 (cpu, in_ACC40Si)) | |
1216 | { | |
1217 | busy_adjustment[0] = 1; | |
1218 | decrease_ACC_busy (cpu, in_ACC40Si, busy_adjustment[0]); | |
1219 | } | |
1220 | if (ACC40Si_1 >= 0 && acc_use_is_media_p2 (cpu, ACC40Si_1)) | |
1221 | { | |
1222 | busy_adjustment[1] = 1; | |
1223 | decrease_ACC_busy (cpu, ACC40Si_1, busy_adjustment[1]); | |
1224 | } | |
1225 | if (out_ACC40Sk != in_ACC40Si && out_ACC40Sk != ACC40Si_1 | |
1226 | && acc_use_is_media_p2 (cpu, out_ACC40Sk)) | |
1227 | { | |
1228 | busy_adjustment[2] = 1; | |
1229 | decrease_ACC_busy (cpu, out_ACC40Sk, busy_adjustment[2]); | |
1230 | } | |
1231 | ||
1232 | /* The post processing must wait if there is a dependency on a register | |
1233 | which is not ready yet. */ | |
1234 | ps->post_wait = cycles; | |
1235 | post_wait_for_ACC (cpu, in_ACC40Si); | |
1236 | post_wait_for_ACC (cpu, ACC40Si_1); | |
1237 | post_wait_for_ACC (cpu, out_ACC40Sk); | |
1238 | ||
1239 | /* Restore the busy cycles of the registers we used. */ | |
1240 | acc = ps->acc_busy; | |
1241 | acc[in_ACC40Si] += busy_adjustment[0]; | |
1242 | if (ACC40Si_1 >= 0) | |
1243 | acc[ACC40Si_1] += busy_adjustment[1]; | |
1244 | acc[out_ACC40Sk] += busy_adjustment[2]; | |
1245 | ||
1246 | /* The latency of the output register will be at least the latency of the | |
1247 | other inputs. Once initiated, post-processing will take 1 cycle. */ | |
1248 | update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1); | |
1249 | set_acc_use_is_media_p2 (cpu, out_ACC40Sk); | |
1250 | ||
1251 | return cycles; | |
1252 | } | |
1253 | ||
1254 | int | |
1255 | frvbf_model_fr400_u_media_2_acc_dual (SIM_CPU *cpu, const IDESC *idesc, | |
1256 | int unit_num, int referenced, | |
1257 | INT in_ACC40Si, INT out_ACC40Sk) | |
1258 | { | |
1259 | int cycles; | |
1260 | INT ACC40Si_1; | |
1261 | INT ACC40Si_2; | |
1262 | INT ACC40Si_3; | |
1263 | INT ACC40Sk_1; | |
1264 | FRV_PROFILE_STATE *ps; | |
1265 | int busy_adjustment[] = {0, 0, 0, 0, 0, 0}; | |
1266 | int *acc; | |
1267 | ||
1268 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
1269 | return 0; | |
1270 | ||
1271 | /* The preprocessing can execute right away. */ | |
1272 | cycles = idesc->timing->units[unit_num].done; | |
1273 | ||
1274 | ACC40Si_1 = DUAL_REG (in_ACC40Si); | |
1275 | ACC40Si_2 = DUAL_REG (ACC40Si_1); | |
1276 | ACC40Si_3 = DUAL_REG (ACC40Si_2); | |
1277 | ACC40Sk_1 = DUAL_REG (out_ACC40Sk); | |
1278 | ||
1279 | ps = CPU_PROFILE_STATE (cpu); | |
1280 | /* The latency of the registers may be less than previously recorded, | |
1281 | depending on how they were used previously. | |
1282 | See Table 13-8 in the LSI. */ | |
1283 | if (acc_use_is_media_p2 (cpu, in_ACC40Si)) | |
1284 | { | |
1285 | busy_adjustment[0] = 1; | |
1286 | decrease_ACC_busy (cpu, in_ACC40Si, busy_adjustment[0]); | |
1287 | } | |
1288 | if (ACC40Si_1 >= 0 && acc_use_is_media_p2 (cpu, ACC40Si_1)) | |
1289 | { | |
1290 | busy_adjustment[1] = 1; | |
1291 | decrease_ACC_busy (cpu, ACC40Si_1, busy_adjustment[1]); | |
1292 | } | |
1293 | if (ACC40Si_2 >= 0 && acc_use_is_media_p2 (cpu, ACC40Si_2)) | |
1294 | { | |
1295 | busy_adjustment[2] = 1; | |
1296 | decrease_ACC_busy (cpu, ACC40Si_2, busy_adjustment[2]); | |
1297 | } | |
1298 | if (ACC40Si_3 >= 0 && acc_use_is_media_p2 (cpu, ACC40Si_3)) | |
1299 | { | |
1300 | busy_adjustment[3] = 1; | |
1301 | decrease_ACC_busy (cpu, ACC40Si_3, busy_adjustment[3]); | |
1302 | } | |
1303 | if (out_ACC40Sk != in_ACC40Si && out_ACC40Sk != ACC40Si_1 | |
1304 | && out_ACC40Sk != ACC40Si_2 && out_ACC40Sk != ACC40Si_3) | |
1305 | { | |
1306 | if (acc_use_is_media_p2 (cpu, out_ACC40Sk)) | |
1307 | { | |
1308 | busy_adjustment[4] = 1; | |
1309 | decrease_ACC_busy (cpu, out_ACC40Sk, busy_adjustment[4]); | |
1310 | } | |
1311 | } | |
1312 | if (ACC40Sk_1 != in_ACC40Si && ACC40Sk_1 != ACC40Si_1 | |
1313 | && ACC40Sk_1 != ACC40Si_2 && ACC40Sk_1 != ACC40Si_3) | |
1314 | { | |
1315 | if (acc_use_is_media_p2 (cpu, ACC40Sk_1)) | |
1316 | { | |
1317 | busy_adjustment[5] = 1; | |
1318 | decrease_ACC_busy (cpu, ACC40Sk_1, busy_adjustment[5]); | |
1319 | } | |
1320 | } | |
1321 | ||
1322 | /* The post processing must wait if there is a dependency on a register | |
1323 | which is not ready yet. */ | |
1324 | ps->post_wait = cycles; | |
1325 | post_wait_for_ACC (cpu, in_ACC40Si); | |
1326 | post_wait_for_ACC (cpu, ACC40Si_1); | |
1327 | post_wait_for_ACC (cpu, ACC40Si_2); | |
1328 | post_wait_for_ACC (cpu, ACC40Si_3); | |
1329 | post_wait_for_ACC (cpu, out_ACC40Sk); | |
1330 | post_wait_for_ACC (cpu, ACC40Sk_1); | |
1331 | ||
1332 | /* Restore the busy cycles of the registers we used. */ | |
1333 | acc = ps->acc_busy; | |
1334 | acc[in_ACC40Si] += busy_adjustment[0]; | |
1335 | if (ACC40Si_1 >= 0) | |
1336 | acc[ACC40Si_1] += busy_adjustment[1]; | |
1337 | if (ACC40Si_2 >= 0) | |
1338 | acc[ACC40Si_2] += busy_adjustment[2]; | |
1339 | if (ACC40Si_3 >= 0) | |
1340 | acc[ACC40Si_3] += busy_adjustment[3]; | |
1341 | acc[out_ACC40Sk] += busy_adjustment[4]; | |
1342 | if (ACC40Sk_1 >= 0) | |
1343 | acc[ACC40Sk_1] += busy_adjustment[5]; | |
1344 | ||
1345 | /* The latency of the output register will be at least the latency of the | |
1346 | other inputs. Once initiated, post-processing will take 1 cycle. */ | |
1347 | update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1); | |
1348 | set_acc_use_is_media_p2 (cpu, out_ACC40Sk); | |
1349 | if (ACC40Sk_1 >= 0) | |
1350 | { | |
1351 | update_ACC_latency (cpu, ACC40Sk_1, ps->post_wait + 1); | |
1352 | set_acc_use_is_media_p2 (cpu, ACC40Sk_1); | |
1353 | } | |
1354 | ||
1355 | return cycles; | |
1356 | } | |
1357 | ||
1358 | int | |
1359 | frvbf_model_fr400_u_media_2_add_sub (SIM_CPU *cpu, const IDESC *idesc, | |
1360 | int unit_num, int referenced, | |
1361 | INT in_ACC40Si, INT out_ACC40Sk) | |
1362 | { | |
1363 | int cycles; | |
1364 | INT ACC40Si_1; | |
1365 | INT ACC40Sk_1; | |
1366 | FRV_PROFILE_STATE *ps; | |
1367 | int busy_adjustment[] = {0, 0, 0, 0}; | |
1368 | int *acc; | |
1369 | ||
1370 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
1371 | return 0; | |
1372 | ||
1373 | /* The preprocessing can execute right away. */ | |
1374 | cycles = idesc->timing->units[unit_num].done; | |
1375 | ||
1376 | ACC40Si_1 = DUAL_REG (in_ACC40Si); | |
1377 | ACC40Sk_1 = DUAL_REG (out_ACC40Sk); | |
1378 | ||
1379 | ps = CPU_PROFILE_STATE (cpu); | |
1380 | /* The latency of the registers may be less than previously recorded, | |
1381 | depending on how they were used previously. | |
1382 | See Table 13-8 in the LSI. */ | |
1383 | if (acc_use_is_media_p2 (cpu, in_ACC40Si)) | |
1384 | { | |
1385 | busy_adjustment[0] = 1; | |
1386 | decrease_ACC_busy (cpu, in_ACC40Si, busy_adjustment[0]); | |
1387 | } | |
1388 | if (ACC40Si_1 >= 0 && acc_use_is_media_p2 (cpu, ACC40Si_1)) | |
1389 | { | |
1390 | busy_adjustment[1] = 1; | |
1391 | decrease_ACC_busy (cpu, ACC40Si_1, busy_adjustment[1]); | |
1392 | } | |
1393 | if (out_ACC40Sk != in_ACC40Si && out_ACC40Sk != ACC40Si_1) | |
1394 | { | |
1395 | if (acc_use_is_media_p2 (cpu, out_ACC40Sk)) | |
1396 | { | |
1397 | busy_adjustment[2] = 1; | |
1398 | decrease_ACC_busy (cpu, out_ACC40Sk, busy_adjustment[2]); | |
1399 | } | |
1400 | } | |
1401 | if (ACC40Sk_1 != in_ACC40Si && ACC40Sk_1 != ACC40Si_1) | |
1402 | { | |
1403 | if (acc_use_is_media_p2 (cpu, ACC40Sk_1)) | |
1404 | { | |
1405 | busy_adjustment[3] = 1; | |
1406 | decrease_ACC_busy (cpu, ACC40Sk_1, busy_adjustment[3]); | |
1407 | } | |
1408 | } | |
1409 | ||
1410 | /* The post processing must wait if there is a dependency on a register | |
1411 | which is not ready yet. */ | |
1412 | ps->post_wait = cycles; | |
1413 | post_wait_for_ACC (cpu, in_ACC40Si); | |
1414 | post_wait_for_ACC (cpu, ACC40Si_1); | |
1415 | post_wait_for_ACC (cpu, out_ACC40Sk); | |
1416 | post_wait_for_ACC (cpu, ACC40Sk_1); | |
1417 | ||
1418 | /* Restore the busy cycles of the registers we used. */ | |
1419 | acc = ps->acc_busy; | |
1420 | acc[in_ACC40Si] += busy_adjustment[0]; | |
1421 | if (ACC40Si_1 >= 0) | |
1422 | acc[ACC40Si_1] += busy_adjustment[1]; | |
1423 | acc[out_ACC40Sk] += busy_adjustment[2]; | |
1424 | if (ACC40Sk_1 >= 0) | |
1425 | acc[ACC40Sk_1] += busy_adjustment[3]; | |
1426 | ||
1427 | /* The latency of the output register will be at least the latency of the | |
1428 | other inputs. Once initiated, post-processing will take 1 cycle. */ | |
1429 | update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1); | |
1430 | set_acc_use_is_media_p2 (cpu, out_ACC40Sk); | |
1431 | if (ACC40Sk_1 >= 0) | |
1432 | { | |
1433 | update_ACC_latency (cpu, ACC40Sk_1, ps->post_wait + 1); | |
1434 | set_acc_use_is_media_p2 (cpu, ACC40Sk_1); | |
1435 | } | |
1436 | ||
1437 | return cycles; | |
1438 | } | |
1439 | ||
1440 | int | |
1441 | frvbf_model_fr400_u_media_2_add_sub_dual (SIM_CPU *cpu, const IDESC *idesc, | |
1442 | int unit_num, int referenced, | |
1443 | INT in_ACC40Si, INT out_ACC40Sk) | |
1444 | { | |
1445 | int cycles; | |
1446 | INT ACC40Si_1; | |
1447 | INT ACC40Si_2; | |
1448 | INT ACC40Si_3; | |
1449 | INT ACC40Sk_1; | |
1450 | INT ACC40Sk_2; | |
1451 | INT ACC40Sk_3; | |
1452 | FRV_PROFILE_STATE *ps; | |
1453 | int busy_adjustment[] = {0, 0, 0, 0, 0, 0, 0, 0}; | |
1454 | int *acc; | |
1455 | ||
1456 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
1457 | return 0; | |
1458 | ||
1459 | /* The preprocessing can execute right away. */ | |
1460 | cycles = idesc->timing->units[unit_num].done; | |
1461 | ||
1462 | ACC40Si_1 = DUAL_REG (in_ACC40Si); | |
1463 | ACC40Si_2 = DUAL_REG (ACC40Si_1); | |
1464 | ACC40Si_3 = DUAL_REG (ACC40Si_2); | |
1465 | ACC40Sk_1 = DUAL_REG (out_ACC40Sk); | |
1466 | ACC40Sk_2 = DUAL_REG (ACC40Sk_1); | |
1467 | ACC40Sk_3 = DUAL_REG (ACC40Sk_2); | |
1468 | ||
1469 | ps = CPU_PROFILE_STATE (cpu); | |
1470 | /* The latency of the registers may be less than previously recorded, | |
1471 | depending on how they were used previously. | |
1472 | See Table 13-8 in the LSI. */ | |
1473 | if (acc_use_is_media_p2 (cpu, in_ACC40Si)) | |
1474 | { | |
1475 | busy_adjustment[0] = 1; | |
1476 | decrease_ACC_busy (cpu, in_ACC40Si, busy_adjustment[0]); | |
1477 | } | |
1478 | if (ACC40Si_1 >= 0 && acc_use_is_media_p2 (cpu, ACC40Si_1)) | |
1479 | { | |
1480 | busy_adjustment[1] = 1; | |
1481 | decrease_ACC_busy (cpu, ACC40Si_1, busy_adjustment[1]); | |
1482 | } | |
1483 | if (ACC40Si_2 >= 0 && acc_use_is_media_p2 (cpu, ACC40Si_2)) | |
1484 | { | |
1485 | busy_adjustment[2] = 1; | |
1486 | decrease_ACC_busy (cpu, ACC40Si_2, busy_adjustment[2]); | |
1487 | } | |
1488 | if (ACC40Si_3 >= 0 && acc_use_is_media_p2 (cpu, ACC40Si_3)) | |
1489 | { | |
1490 | busy_adjustment[3] = 1; | |
1491 | decrease_ACC_busy (cpu, ACC40Si_3, busy_adjustment[3]); | |
1492 | } | |
1493 | if (out_ACC40Sk != in_ACC40Si && out_ACC40Sk != ACC40Si_1 | |
1494 | && out_ACC40Sk != ACC40Si_2 && out_ACC40Sk != ACC40Si_3) | |
1495 | { | |
1496 | if (acc_use_is_media_p2 (cpu, out_ACC40Sk)) | |
1497 | { | |
1498 | busy_adjustment[4] = 1; | |
1499 | decrease_ACC_busy (cpu, out_ACC40Sk, busy_adjustment[4]); | |
1500 | } | |
1501 | } | |
1502 | if (ACC40Sk_1 != in_ACC40Si && ACC40Sk_1 != ACC40Si_1 | |
1503 | && ACC40Sk_1 != ACC40Si_2 && ACC40Sk_1 != ACC40Si_3) | |
1504 | { | |
1505 | if (acc_use_is_media_p2 (cpu, ACC40Sk_1)) | |
1506 | { | |
1507 | busy_adjustment[5] = 1; | |
1508 | decrease_ACC_busy (cpu, ACC40Sk_1, busy_adjustment[5]); | |
1509 | } | |
1510 | } | |
1511 | if (ACC40Sk_2 != in_ACC40Si && ACC40Sk_2 != ACC40Si_1 | |
1512 | && ACC40Sk_2 != ACC40Si_2 && ACC40Sk_2 != ACC40Si_3) | |
1513 | { | |
1514 | if (acc_use_is_media_p2 (cpu, ACC40Sk_2)) | |
1515 | { | |
1516 | busy_adjustment[6] = 1; | |
1517 | decrease_ACC_busy (cpu, ACC40Sk_2, busy_adjustment[6]); | |
1518 | } | |
1519 | } | |
1520 | if (ACC40Sk_3 != in_ACC40Si && ACC40Sk_3 != ACC40Si_1 | |
1521 | && ACC40Sk_3 != ACC40Si_2 && ACC40Sk_3 != ACC40Si_3) | |
1522 | { | |
1523 | if (acc_use_is_media_p2 (cpu, ACC40Sk_3)) | |
1524 | { | |
1525 | busy_adjustment[7] = 1; | |
1526 | decrease_ACC_busy (cpu, ACC40Sk_3, busy_adjustment[7]); | |
1527 | } | |
1528 | } | |
1529 | ||
1530 | /* The post processing must wait if there is a dependency on a register | |
1531 | which is not ready yet. */ | |
1532 | ps->post_wait = cycles; | |
1533 | post_wait_for_ACC (cpu, in_ACC40Si); | |
1534 | post_wait_for_ACC (cpu, ACC40Si_1); | |
1535 | post_wait_for_ACC (cpu, ACC40Si_2); | |
1536 | post_wait_for_ACC (cpu, ACC40Si_3); | |
1537 | post_wait_for_ACC (cpu, out_ACC40Sk); | |
1538 | post_wait_for_ACC (cpu, ACC40Sk_1); | |
1539 | post_wait_for_ACC (cpu, ACC40Sk_2); | |
1540 | post_wait_for_ACC (cpu, ACC40Sk_3); | |
1541 | ||
1542 | /* Restore the busy cycles of the registers we used. */ | |
1543 | acc = ps->acc_busy; | |
1544 | acc[in_ACC40Si] += busy_adjustment[0]; | |
1545 | if (ACC40Si_1 >= 0) | |
1546 | acc[ACC40Si_1] += busy_adjustment[1]; | |
1547 | if (ACC40Si_2 >= 0) | |
1548 | acc[ACC40Si_2] += busy_adjustment[2]; | |
1549 | if (ACC40Si_3 >= 0) | |
1550 | acc[ACC40Si_3] += busy_adjustment[3]; | |
1551 | acc[out_ACC40Sk] += busy_adjustment[4]; | |
1552 | if (ACC40Sk_1 >= 0) | |
1553 | acc[ACC40Sk_1] += busy_adjustment[5]; | |
1554 | if (ACC40Sk_2 >= 0) | |
1555 | acc[ACC40Sk_2] += busy_adjustment[6]; | |
1556 | if (ACC40Sk_3 >= 0) | |
1557 | acc[ACC40Sk_3] += busy_adjustment[7]; | |
1558 | ||
1559 | /* The latency of the output register will be at least the latency of the | |
1560 | other inputs. Once initiated, post-processing will take 1 cycle. */ | |
1561 | update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1); | |
1562 | set_acc_use_is_media_p2 (cpu, out_ACC40Sk); | |
1563 | if (ACC40Sk_1 >= 0) | |
1564 | { | |
1565 | update_ACC_latency (cpu, ACC40Sk_1, ps->post_wait + 1); | |
1566 | set_acc_use_is_media_p2 (cpu, ACC40Sk_1); | |
1567 | } | |
1568 | if (ACC40Sk_2 >= 0) | |
1569 | { | |
1570 | update_ACC_latency (cpu, ACC40Sk_2, ps->post_wait + 1); | |
1571 | set_acc_use_is_media_p2 (cpu, ACC40Sk_2); | |
1572 | } | |
1573 | if (ACC40Sk_3 >= 0) | |
1574 | { | |
1575 | update_ACC_latency (cpu, ACC40Sk_3, ps->post_wait + 1); | |
1576 | set_acc_use_is_media_p2 (cpu, ACC40Sk_3); | |
1577 | } | |
1578 | ||
1579 | return cycles; | |
1580 | } | |
1581 | ||
1582 | int | |
1583 | frvbf_model_fr400_u_media_3 (SIM_CPU *cpu, const IDESC *idesc, | |
1584 | int unit_num, int referenced, | |
1585 | INT in_FRi, INT in_FRj, | |
1586 | INT out_FRk) | |
1587 | { | |
1588 | /* Modelling is the same as media unit 1. */ | |
1589 | return frvbf_model_fr400_u_media_1 (cpu, idesc, unit_num, referenced, | |
1590 | in_FRi, in_FRj, out_FRk); | |
1591 | } | |
1592 | ||
1593 | int | |
1594 | frvbf_model_fr400_u_media_3_dual (SIM_CPU *cpu, const IDESC *idesc, | |
1595 | int unit_num, int referenced, | |
1596 | INT in_FRi, INT out_FRk) | |
1597 | { | |
1598 | int cycles; | |
1599 | INT dual_FRi; | |
1600 | FRV_PROFILE_STATE *ps; | |
1601 | int busy_adjustment[] = {0, 0}; | |
1602 | int *fr; | |
1603 | ||
1604 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
1605 | return 0; | |
1606 | ||
1607 | /* The preprocessing can execute right away. */ | |
1608 | cycles = idesc->timing->units[unit_num].done; | |
1609 | ||
1610 | ps = CPU_PROFILE_STATE (cpu); | |
1611 | dual_FRi = DUAL_REG (in_FRi); | |
1612 | ||
1613 | /* The latency of the registers may be less than previously recorded, | |
1614 | depending on how they were used previously. | |
1615 | See Table 13-8 in the LSI. */ | |
1616 | if (use_is_fp_load (cpu, in_FRi)) | |
1617 | { | |
1618 | busy_adjustment[0] = 1; | |
1619 | decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]); | |
1620 | } | |
1621 | else | |
1622 | enforce_full_fr_latency (cpu, in_FRi); | |
1623 | if (dual_FRi >= 0 && use_is_fp_load (cpu, dual_FRi)) | |
1624 | { | |
1625 | busy_adjustment[1] = 1; | |
1626 | decrease_FR_busy (cpu, dual_FRi, busy_adjustment[1]); | |
1627 | } | |
1628 | else | |
1629 | enforce_full_fr_latency (cpu, dual_FRi); | |
1630 | ||
1631 | /* The post processing must wait if there is a dependency on a FR | |
1632 | which is not ready yet. */ | |
1633 | ps->post_wait = cycles; | |
1634 | post_wait_for_FR (cpu, in_FRi); | |
1635 | post_wait_for_FR (cpu, dual_FRi); | |
1636 | post_wait_for_FR (cpu, out_FRk); | |
1637 | ||
1638 | /* Restore the busy cycles of the registers we used. */ | |
1639 | fr = ps->fr_busy; | |
1640 | fr[in_FRi] += busy_adjustment[0]; | |
1641 | if (dual_FRi >= 0) | |
1642 | fr[dual_FRi] += busy_adjustment[1]; | |
1643 | ||
1644 | /* The latency of the output register will be at least the latency of the | |
1645 | other inputs. */ | |
1646 | update_FR_latency (cpu, out_FRk, ps->post_wait); | |
1647 | ||
1648 | /* Once initiated, post-processing has no latency. */ | |
1649 | update_FR_ptime (cpu, out_FRk, 0); | |
1650 | ||
1651 | return cycles; | |
1652 | } | |
1653 | ||
1654 | int | |
1655 | frvbf_model_fr400_u_media_3_quad (SIM_CPU *cpu, const IDESC *idesc, | |
1656 | int unit_num, int referenced, | |
1657 | INT in_FRi, INT in_FRj, | |
1658 | INT out_FRk) | |
1659 | { | |
1660 | /* Modelling is the same as media unit 1. */ | |
1661 | return frvbf_model_fr400_u_media_1_quad (cpu, idesc, unit_num, referenced, | |
1662 | in_FRi, in_FRj, out_FRk); | |
1663 | } | |
1664 | ||
1665 | int | |
1666 | frvbf_model_fr400_u_media_4 (SIM_CPU *cpu, const IDESC *idesc, | |
1667 | int unit_num, int referenced, | |
1668 | INT in_ACC40Si, INT in_FRj, | |
1669 | INT out_ACC40Sk, INT out_FRk) | |
1670 | { | |
1671 | int cycles; | |
1672 | FRV_PROFILE_STATE *ps; | |
1673 | const CGEN_INSN *insn; | |
1674 | int busy_adjustment[] = {0}; | |
1675 | int *fr; | |
1676 | ||
1677 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
1678 | return 0; | |
1679 | ||
1680 | /* The preprocessing can execute right away. */ | |
1681 | cycles = idesc->timing->units[unit_num].done; | |
1682 | ||
1683 | ps = CPU_PROFILE_STATE (cpu); | |
1684 | insn = idesc->idata; | |
1685 | ||
1686 | /* The latency of the registers may be less than previously recorded, | |
1687 | depending on how they were used previously. | |
1688 | See Table 13-8 in the LSI. */ | |
1689 | if (in_FRj >= 0) | |
1690 | { | |
1691 | if (use_is_fp_load (cpu, in_FRj)) | |
1692 | { | |
1693 | busy_adjustment[0] = 1; | |
1694 | decrease_FR_busy (cpu, in_FRj, busy_adjustment[0]); | |
1695 | } | |
1696 | else | |
1697 | enforce_full_fr_latency (cpu, in_FRj); | |
1698 | } | |
1699 | ||
1700 | /* The post processing must wait if there is a dependency on a FR | |
1701 | which is not ready yet. */ | |
1702 | ps->post_wait = cycles; | |
1703 | post_wait_for_ACC (cpu, in_ACC40Si); | |
1704 | post_wait_for_ACC (cpu, out_ACC40Sk); | |
1705 | post_wait_for_FR (cpu, in_FRj); | |
1706 | post_wait_for_FR (cpu, out_FRk); | |
1707 | ||
1708 | /* Restore the busy cycles of the registers we used. */ | |
1709 | fr = ps->fr_busy; | |
1710 | ||
1711 | /* The latency of the output register will be at least the latency of the | |
1712 | other inputs. Once initiated, post-processing will take 1 cycle. */ | |
1713 | if (out_FRk >= 0) | |
1714 | { | |
1715 | update_FR_latency (cpu, out_FRk, ps->post_wait); | |
1716 | update_FR_ptime (cpu, out_FRk, 1); | |
1717 | /* Mark this use of the register as media unit 4. */ | |
1718 | set_use_is_media_p4 (cpu, out_FRk); | |
1719 | } | |
1720 | else if (out_ACC40Sk >= 0) | |
1721 | { | |
1722 | update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait); | |
1723 | update_ACC_ptime (cpu, out_ACC40Sk, 1); | |
1724 | /* Mark this use of the register as media unit 4. */ | |
1725 | set_acc_use_is_media_p4 (cpu, out_ACC40Sk); | |
1726 | } | |
1727 | ||
1728 | return cycles; | |
1729 | } | |
1730 | ||
1731 | int | |
1732 | frvbf_model_fr400_u_media_4_accg (SIM_CPU *cpu, const IDESC *idesc, | |
1733 | int unit_num, int referenced, | |
1734 | INT in_ACCGi, INT in_FRinti, | |
1735 | INT out_ACCGk, INT out_FRintk) | |
1736 | { | |
1737 | /* Modelling is the same as media-4 unit except use accumulator guards | |
1738 | as input instead of accumulators. */ | |
1739 | return frvbf_model_fr400_u_media_4 (cpu, idesc, unit_num, referenced, | |
1740 | in_ACCGi, in_FRinti, | |
1741 | out_ACCGk, out_FRintk); | |
1742 | } | |
1743 | ||
1744 | int | |
1745 | frvbf_model_fr400_u_media_4_acc_dual (SIM_CPU *cpu, const IDESC *idesc, | |
1746 | int unit_num, int referenced, | |
1747 | INT in_ACC40Si, INT out_FRk) | |
1748 | { | |
1749 | int cycles; | |
1750 | FRV_PROFILE_STATE *ps; | |
1751 | const CGEN_INSN *insn; | |
1752 | INT ACC40Si_1; | |
1753 | INT FRk_1; | |
1754 | ||
1755 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
1756 | return 0; | |
1757 | ||
1758 | /* The preprocessing can execute right away. */ | |
1759 | cycles = idesc->timing->units[unit_num].done; | |
1760 | ||
1761 | ps = CPU_PROFILE_STATE (cpu); | |
1762 | ACC40Si_1 = DUAL_REG (in_ACC40Si); | |
1763 | FRk_1 = DUAL_REG (out_FRk); | |
1764 | ||
1765 | insn = idesc->idata; | |
1766 | ||
1767 | /* The post processing must wait if there is a dependency on a FR | |
1768 | which is not ready yet. */ | |
1769 | ps->post_wait = cycles; | |
1770 | post_wait_for_ACC (cpu, in_ACC40Si); | |
1771 | post_wait_for_ACC (cpu, ACC40Si_1); | |
1772 | post_wait_for_FR (cpu, out_FRk); | |
1773 | post_wait_for_FR (cpu, FRk_1); | |
1774 | ||
1775 | /* The latency of the output register will be at least the latency of the | |
1776 | other inputs. Once initiated, post-processing will take 1 cycle. */ | |
1777 | if (out_FRk >= 0) | |
1778 | { | |
1779 | update_FR_latency (cpu, out_FRk, ps->post_wait); | |
1780 | update_FR_ptime (cpu, out_FRk, 1); | |
1781 | /* Mark this use of the register as media unit 4. */ | |
1782 | set_use_is_media_p4 (cpu, out_FRk); | |
1783 | } | |
1784 | if (FRk_1 >= 0) | |
1785 | { | |
1786 | update_FR_latency (cpu, FRk_1, ps->post_wait); | |
1787 | update_FR_ptime (cpu, FRk_1, 1); | |
1788 | /* Mark this use of the register as media unit 4. */ | |
1789 | set_use_is_media_p4 (cpu, FRk_1); | |
1790 | } | |
1791 | ||
1792 | return cycles; | |
1793 | } | |
1794 | ||
1795 | int | |
1796 | frvbf_model_fr400_u_media_6 (SIM_CPU *cpu, const IDESC *idesc, | |
1797 | int unit_num, int referenced, | |
1798 | INT in_FRi, INT out_FRk) | |
1799 | { | |
1800 | int cycles; | |
1801 | FRV_PROFILE_STATE *ps; | |
1802 | const CGEN_INSN *insn; | |
1803 | int busy_adjustment[] = {0}; | |
1804 | int *fr; | |
1805 | ||
1806 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
1807 | return 0; | |
1808 | ||
1809 | /* The preprocessing can execute right away. */ | |
1810 | cycles = idesc->timing->units[unit_num].done; | |
1811 | ||
1812 | ps = CPU_PROFILE_STATE (cpu); | |
1813 | insn = idesc->idata; | |
1814 | ||
1815 | /* The latency of the registers may be less than previously recorded, | |
1816 | depending on how they were used previously. | |
1817 | See Table 13-8 in the LSI. */ | |
1818 | if (in_FRi >= 0) | |
1819 | { | |
1820 | if (use_is_fp_load (cpu, in_FRi)) | |
1821 | { | |
1822 | busy_adjustment[0] = 1; | |
1823 | decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]); | |
1824 | } | |
1825 | else | |
1826 | enforce_full_fr_latency (cpu, in_FRi); | |
1827 | } | |
1828 | ||
1829 | /* The post processing must wait if there is a dependency on a FR | |
1830 | which is not ready yet. */ | |
1831 | ps->post_wait = cycles; | |
1832 | post_wait_for_FR (cpu, in_FRi); | |
1833 | post_wait_for_FR (cpu, out_FRk); | |
1834 | ||
1835 | /* Restore the busy cycles of the registers we used. */ | |
1836 | fr = ps->fr_busy; | |
1837 | if (in_FRi >= 0) | |
1838 | fr[in_FRi] += busy_adjustment[0]; | |
1839 | ||
1840 | /* The latency of the output register will be at least the latency of the | |
1841 | other inputs. Once initiated, post-processing will take 1 cycle. */ | |
1842 | if (out_FRk >= 0) | |
1843 | { | |
1844 | update_FR_latency (cpu, out_FRk, ps->post_wait); | |
1845 | update_FR_ptime (cpu, out_FRk, 1); | |
1846 | ||
1847 | /* Mark this use of the register as media unit 1. */ | |
1848 | set_use_is_media_p6 (cpu, out_FRk); | |
1849 | } | |
1850 | ||
1851 | return cycles; | |
1852 | } | |
1853 | ||
1854 | int | |
1855 | frvbf_model_fr400_u_media_7 (SIM_CPU *cpu, const IDESC *idesc, | |
1856 | int unit_num, int referenced, | |
1857 | INT in_FRinti, INT in_FRintj, | |
1858 | INT out_FCCk) | |
1859 | { | |
1860 | int cycles; | |
1861 | FRV_PROFILE_STATE *ps; | |
1862 | int busy_adjustment[] = {0, 0}; | |
1863 | int *fr; | |
1864 | ||
1865 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
1866 | return 0; | |
1867 | ||
1868 | /* The preprocessing can execute right away. */ | |
1869 | cycles = idesc->timing->units[unit_num].done; | |
1870 | ||
1871 | /* The post processing must wait if there is a dependency on a FR | |
1872 | which is not ready yet. */ | |
1873 | ps = CPU_PROFILE_STATE (cpu); | |
1874 | ||
1875 | /* The latency of the registers may be less than previously recorded, | |
1876 | depending on how they were used previously. | |
1877 | See Table 13-8 in the LSI. */ | |
1878 | if (in_FRinti >= 0) | |
1879 | { | |
1880 | if (use_is_fp_load (cpu, in_FRinti)) | |
1881 | { | |
1882 | busy_adjustment[0] = 1; | |
1883 | decrease_FR_busy (cpu, in_FRinti, busy_adjustment[0]); | |
1884 | } | |
1885 | else | |
1886 | enforce_full_fr_latency (cpu, in_FRinti); | |
1887 | } | |
1888 | if (in_FRintj >= 0 && in_FRintj != in_FRinti) | |
1889 | { | |
1890 | if (use_is_fp_load (cpu, in_FRintj)) | |
1891 | { | |
1892 | busy_adjustment[1] = 1; | |
1893 | decrease_FR_busy (cpu, in_FRintj, busy_adjustment[1]); | |
1894 | } | |
1895 | else | |
1896 | enforce_full_fr_latency (cpu, in_FRintj); | |
1897 | } | |
1898 | ||
1899 | ps->post_wait = cycles; | |
1900 | post_wait_for_FR (cpu, in_FRinti); | |
1901 | post_wait_for_FR (cpu, in_FRintj); | |
1902 | post_wait_for_CCR (cpu, out_FCCk); | |
1903 | ||
1904 | /* Restore the busy cycles of the registers we used. */ | |
1905 | fr = ps->fr_busy; | |
1906 | if (in_FRinti >= 0) | |
1907 | fr[in_FRinti] += busy_adjustment[0]; | |
1908 | if (in_FRintj >= 0) | |
1909 | fr[in_FRintj] += busy_adjustment[1]; | |
1910 | ||
1911 | /* The latency of FCCi_2 will be the latency of the other inputs plus 1 | |
1912 | cycle. */ | |
1913 | update_CCR_latency (cpu, out_FCCk, ps->post_wait + 1); | |
1914 | ||
1915 | return cycles; | |
1916 | } | |
1917 | ||
1918 | int | |
1919 | frvbf_model_fr400_u_media_dual_expand (SIM_CPU *cpu, const IDESC *idesc, | |
1920 | int unit_num, int referenced, | |
1921 | INT in_FRi, | |
1922 | INT out_FRk) | |
1923 | { | |
1924 | /* Insns using this unit are media-3 class insns, with a dual FRk output. */ | |
1925 | int cycles; | |
1926 | INT dual_FRk; | |
1927 | FRV_PROFILE_STATE *ps; | |
1928 | int busy_adjustment[] = {0}; | |
1929 | int *fr; | |
1930 | ||
1931 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
1932 | return 0; | |
1933 | ||
1934 | /* The preprocessing can execute right away. */ | |
1935 | cycles = idesc->timing->units[unit_num].done; | |
1936 | ||
1937 | /* If the previous use of the registers was a media op, | |
1938 | then their latency will be less than previously recorded. | |
1939 | See Table 13-13 in the LSI. */ | |
1940 | dual_FRk = DUAL_REG (out_FRk); | |
1941 | ps = CPU_PROFILE_STATE (cpu); | |
1942 | if (use_is_fp_load (cpu, in_FRi)) | |
1943 | { | |
1944 | busy_adjustment[0] = 1; | |
1945 | decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]); | |
1946 | } | |
1947 | else | |
1948 | enforce_full_fr_latency (cpu, in_FRi); | |
1949 | ||
1950 | /* The post processing must wait if there is a dependency on a FR | |
1951 | which is not ready yet. */ | |
1952 | ps->post_wait = cycles; | |
1953 | post_wait_for_FR (cpu, in_FRi); | |
1954 | post_wait_for_FR (cpu, out_FRk); | |
1955 | post_wait_for_FR (cpu, dual_FRk); | |
1956 | ||
1957 | /* Restore the busy cycles of the registers we used. */ | |
1958 | fr = ps->fr_busy; | |
1959 | fr[in_FRi] += busy_adjustment[0]; | |
1960 | ||
1961 | /* The latency of the output register will be at least the latency of the | |
1962 | other inputs. Once initiated, post-processing has no latency. */ | |
1963 | update_FR_latency (cpu, out_FRk, ps->post_wait); | |
1964 | update_FR_ptime (cpu, out_FRk, 0); | |
1965 | ||
1966 | if (dual_FRk >= 0) | |
1967 | { | |
1968 | update_FR_latency (cpu, dual_FRk, ps->post_wait); | |
1969 | update_FR_ptime (cpu, dual_FRk, 0); | |
1970 | } | |
1971 | ||
1972 | return cycles; | |
1973 | } | |
1974 | ||
1975 | int | |
1976 | frvbf_model_fr400_u_media_dual_htob (SIM_CPU *cpu, const IDESC *idesc, | |
1977 | int unit_num, int referenced, | |
1978 | INT in_FRj, | |
1979 | INT out_FRk) | |
1980 | { | |
1981 | /* Insns using this unit are media-3 class insns, with a dual FRj input. */ | |
1982 | int cycles; | |
1983 | INT dual_FRj; | |
1984 | FRV_PROFILE_STATE *ps; | |
1985 | int busy_adjustment[] = {0, 0}; | |
1986 | int *fr; | |
1987 | ||
1988 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
1989 | return 0; | |
1990 | ||
1991 | /* The preprocessing can execute right away. */ | |
1992 | cycles = idesc->timing->units[unit_num].done; | |
1993 | ||
1994 | /* If the previous use of the registers was a media op, | |
1995 | then their latency will be less than previously recorded. | |
1996 | See Table 13-13 in the LSI. */ | |
1997 | dual_FRj = DUAL_REG (in_FRj); | |
1998 | ps = CPU_PROFILE_STATE (cpu); | |
1999 | if (use_is_fp_load (cpu, in_FRj)) | |
2000 | { | |
2001 | busy_adjustment[0] = 1; | |
2002 | decrease_FR_busy (cpu, in_FRj, busy_adjustment[0]); | |
2003 | } | |
2004 | else | |
2005 | enforce_full_fr_latency (cpu, in_FRj); | |
2006 | if (dual_FRj >= 0) | |
2007 | { | |
2008 | if (use_is_fp_load (cpu, dual_FRj)) | |
2009 | { | |
2010 | busy_adjustment[1] = 1; | |
2011 | decrease_FR_busy (cpu, dual_FRj, busy_adjustment[1]); | |
2012 | } | |
2013 | else | |
2014 | enforce_full_fr_latency (cpu, dual_FRj); | |
2015 | } | |
2016 | ||
2017 | /* The post processing must wait if there is a dependency on a FR | |
2018 | which is not ready yet. */ | |
2019 | ps->post_wait = cycles; | |
2020 | post_wait_for_FR (cpu, in_FRj); | |
2021 | post_wait_for_FR (cpu, dual_FRj); | |
2022 | post_wait_for_FR (cpu, out_FRk); | |
2023 | ||
2024 | /* Restore the busy cycles of the registers we used. */ | |
2025 | fr = ps->fr_busy; | |
2026 | fr[in_FRj] += busy_adjustment[0]; | |
2027 | if (dual_FRj >= 0) | |
2028 | fr[dual_FRj] += busy_adjustment[1]; | |
2029 | ||
2030 | /* The latency of the output register will be at least the latency of the | |
2031 | other inputs. */ | |
2032 | update_FR_latency (cpu, out_FRk, ps->post_wait); | |
2033 | ||
2034 | /* Once initiated, post-processing has no latency. */ | |
2035 | update_FR_ptime (cpu, out_FRk, 0); | |
2036 | ||
2037 | return cycles; | |
2038 | } | |
2039 | ||
2040 | int | |
2041 | frvbf_model_fr400_u_ici (SIM_CPU *cpu, const IDESC *idesc, | |
2042 | int unit_num, int referenced, | |
2043 | INT in_GRi, INT in_GRj) | |
2044 | { | |
2045 | /* Modelling for this unit is the same as for fr500. */ | |
2046 | return frvbf_model_fr500_u_ici (cpu, idesc, unit_num, referenced, | |
2047 | in_GRi, in_GRj); | |
2048 | } | |
2049 | ||
2050 | int | |
2051 | frvbf_model_fr400_u_dci (SIM_CPU *cpu, const IDESC *idesc, | |
2052 | int unit_num, int referenced, | |
2053 | INT in_GRi, INT in_GRj) | |
2054 | { | |
2055 | /* Modelling for this unit is the same as for fr500. */ | |
2056 | return frvbf_model_fr500_u_dci (cpu, idesc, unit_num, referenced, | |
2057 | in_GRi, in_GRj); | |
2058 | } | |
2059 | ||
2060 | int | |
2061 | frvbf_model_fr400_u_dcf (SIM_CPU *cpu, const IDESC *idesc, | |
2062 | int unit_num, int referenced, | |
2063 | INT in_GRi, INT in_GRj) | |
2064 | { | |
2065 | /* Modelling for this unit is the same as for fr500. */ | |
2066 | return frvbf_model_fr500_u_dcf (cpu, idesc, unit_num, referenced, | |
2067 | in_GRi, in_GRj); | |
2068 | } | |
2069 | ||
2070 | int | |
2071 | frvbf_model_fr400_u_icpl (SIM_CPU *cpu, const IDESC *idesc, | |
2072 | int unit_num, int referenced, | |
2073 | INT in_GRi, INT in_GRj) | |
2074 | { | |
2075 | /* Modelling for this unit is the same as for fr500. */ | |
2076 | return frvbf_model_fr500_u_icpl (cpu, idesc, unit_num, referenced, | |
2077 | in_GRi, in_GRj); | |
2078 | } | |
2079 | ||
2080 | int | |
2081 | frvbf_model_fr400_u_dcpl (SIM_CPU *cpu, const IDESC *idesc, | |
2082 | int unit_num, int referenced, | |
2083 | INT in_GRi, INT in_GRj) | |
2084 | { | |
2085 | /* Modelling for this unit is the same as for fr500. */ | |
2086 | return frvbf_model_fr500_u_dcpl (cpu, idesc, unit_num, referenced, | |
2087 | in_GRi, in_GRj); | |
2088 | } | |
2089 | ||
2090 | int | |
2091 | frvbf_model_fr400_u_icul (SIM_CPU *cpu, const IDESC *idesc, | |
2092 | int unit_num, int referenced, | |
2093 | INT in_GRi, INT in_GRj) | |
2094 | { | |
2095 | /* Modelling for this unit is the same as for fr500. */ | |
2096 | return frvbf_model_fr500_u_icul (cpu, idesc, unit_num, referenced, | |
2097 | in_GRi, in_GRj); | |
2098 | } | |
2099 | ||
2100 | int | |
2101 | frvbf_model_fr400_u_dcul (SIM_CPU *cpu, const IDESC *idesc, | |
2102 | int unit_num, int referenced, | |
2103 | INT in_GRi, INT in_GRj) | |
2104 | { | |
2105 | /* Modelling for this unit is the same as for fr500. */ | |
2106 | return frvbf_model_fr500_u_dcul (cpu, idesc, unit_num, referenced, | |
2107 | in_GRi, in_GRj); | |
2108 | } | |
2109 | ||
2110 | int | |
2111 | frvbf_model_fr400_u_barrier (SIM_CPU *cpu, const IDESC *idesc, | |
2112 | int unit_num, int referenced) | |
2113 | { | |
2114 | /* Modelling for this unit is the same as for fr500. */ | |
2115 | return frvbf_model_fr500_u_barrier (cpu, idesc, unit_num, referenced); | |
2116 | } | |
2117 | ||
2118 | int | |
2119 | frvbf_model_fr400_u_membar (SIM_CPU *cpu, const IDESC *idesc, | |
2120 | int unit_num, int referenced) | |
2121 | { | |
2122 | /* Modelling for this unit is the same as for fr500. */ | |
2123 | return frvbf_model_fr500_u_membar (cpu, idesc, unit_num, referenced); | |
2124 | } | |
2125 | ||
2126 | #endif /* WITH_PROFILE_MODEL_P */ |