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b34f6357 DB |
1 | /* frv simulator fr400 dependent profiling code. |
2 | ||
32d0add0 | 3 | Copyright (C) 2001-2015 Free Software Foundation, Inc. |
b34f6357 DB |
4 | Contributed by Red Hat |
5 | ||
6 | This file is part of the GNU simulators. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
4744ac1b JB |
10 | the Free Software Foundation; either version 3 of the License, or |
11 | (at your option) any later version. | |
b34f6357 DB |
12 | |
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
4744ac1b JB |
18 | You should have received a copy of the GNU General Public License |
19 | along with this program. If not, see <http://www.gnu.org/licenses/>. | |
b34f6357 DB |
20 | |
21 | */ | |
22 | #define WANT_CPU | |
23 | #define WANT_CPU_FRVBF | |
24 | ||
25 | #include "sim-main.h" | |
26 | #include "bfd.h" | |
27 | ||
28 | #if WITH_PROFILE_MODEL_P | |
29 | ||
30 | #include "profile.h" | |
31 | #include "profile-fr400.h" | |
32 | ||
33 | /* These functions get and set flags representing the use of | |
34 | registers/resources. */ | |
35 | static void set_use_not_fp_load (SIM_CPU *, INT); | |
36 | static void set_use_not_media_p4 (SIM_CPU *, INT); | |
37 | static void set_use_not_media_p6 (SIM_CPU *, INT); | |
38 | ||
39 | static void set_acc_use_not_media_p2 (SIM_CPU *, INT); | |
40 | static void set_acc_use_not_media_p4 (SIM_CPU *, INT); | |
41 | ||
42 | void | |
43 | fr400_reset_gr_flags (SIM_CPU *cpu, INT fr) | |
44 | { | |
45 | set_use_not_gr_complex (cpu, fr); | |
46 | } | |
47 | ||
48 | void | |
49 | fr400_reset_fr_flags (SIM_CPU *cpu, INT fr) | |
50 | { | |
51 | set_use_not_fp_load (cpu, fr); | |
52 | set_use_not_media_p4 (cpu, fr); | |
53 | set_use_not_media_p6 (cpu, fr); | |
54 | } | |
55 | ||
56 | void | |
57 | fr400_reset_acc_flags (SIM_CPU *cpu, INT acc) | |
58 | { | |
59 | set_acc_use_not_media_p2 (cpu, acc); | |
60 | set_acc_use_not_media_p4 (cpu, acc); | |
61 | } | |
62 | ||
63 | static void | |
64 | set_use_is_fp_load (SIM_CPU *cpu, INT fr, INT fr_double) | |
65 | { | |
66 | MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); | |
67 | if (fr != -1) | |
68 | { | |
69 | fr400_reset_fr_flags (cpu, fr); | |
70 | d->cur_fp_load |= (((DI)1) << fr); | |
71 | } | |
72 | if (fr_double != -1) | |
73 | { | |
74 | fr400_reset_fr_flags (cpu, fr_double); | |
75 | d->cur_fp_load |= (((DI)1) << fr_double); | |
76 | if (fr_double < 63) | |
77 | { | |
78 | fr400_reset_fr_flags (cpu, fr_double + 1); | |
79 | d->cur_fp_load |= (((DI)1) << (fr_double + 1)); | |
80 | } | |
81 | } | |
82 | ||
83 | } | |
84 | ||
85 | static void | |
86 | set_use_not_fp_load (SIM_CPU *cpu, INT fr) | |
87 | { | |
88 | MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); | |
89 | if (fr != -1) | |
90 | d->cur_fp_load &= ~(((DI)1) << fr); | |
91 | } | |
92 | ||
93 | static int | |
94 | use_is_fp_load (SIM_CPU *cpu, INT fr) | |
95 | { | |
96 | MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); | |
97 | if (fr != -1) | |
98 | return (d->prev_fp_load >> fr) & 1; | |
99 | return 0; | |
100 | } | |
101 | ||
102 | static void | |
103 | set_acc_use_is_media_p2 (SIM_CPU *cpu, INT acc) | |
104 | { | |
105 | MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); | |
106 | if (acc != -1) | |
107 | { | |
108 | fr400_reset_acc_flags (cpu, acc); | |
109 | d->cur_acc_p2 |= (((DI)1) << acc); | |
110 | } | |
111 | } | |
112 | ||
113 | static void | |
114 | set_acc_use_not_media_p2 (SIM_CPU *cpu, INT acc) | |
115 | { | |
116 | MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); | |
117 | if (acc != -1) | |
118 | d->cur_acc_p2 &= ~(((DI)1) << acc); | |
119 | } | |
120 | ||
121 | static int | |
122 | acc_use_is_media_p2 (SIM_CPU *cpu, INT acc) | |
123 | { | |
124 | MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); | |
125 | if (acc != -1) | |
126 | return d->cur_acc_p2 & (((DI)1) << acc); | |
127 | return 0; | |
128 | } | |
129 | ||
130 | static void | |
131 | set_use_is_media_p4 (SIM_CPU *cpu, INT fr) | |
132 | { | |
133 | MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); | |
134 | if (fr != -1) | |
135 | { | |
136 | fr400_reset_fr_flags (cpu, fr); | |
137 | d->cur_fr_p4 |= (((DI)1) << fr); | |
138 | } | |
139 | } | |
140 | ||
141 | static void | |
142 | set_use_not_media_p4 (SIM_CPU *cpu, INT fr) | |
143 | { | |
144 | MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); | |
145 | if (fr != -1) | |
146 | d->cur_fr_p4 &= ~(((DI)1) << fr); | |
147 | } | |
148 | ||
149 | static int | |
150 | use_is_media_p4 (SIM_CPU *cpu, INT fr) | |
151 | { | |
152 | MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); | |
153 | if (fr != -1) | |
154 | return d->cur_fr_p4 & (((DI)1) << fr); | |
155 | return 0; | |
156 | } | |
157 | ||
158 | static void | |
159 | set_acc_use_is_media_p4 (SIM_CPU *cpu, INT acc) | |
160 | { | |
161 | MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); | |
162 | if (acc != -1) | |
163 | { | |
164 | fr400_reset_acc_flags (cpu, acc); | |
165 | d->cur_acc_p4 |= (((DI)1) << acc); | |
166 | } | |
167 | } | |
168 | ||
169 | static void | |
170 | set_acc_use_not_media_p4 (SIM_CPU *cpu, INT acc) | |
171 | { | |
172 | MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); | |
173 | if (acc != -1) | |
174 | d->cur_acc_p4 &= ~(((DI)1) << acc); | |
175 | } | |
176 | ||
177 | static int | |
178 | acc_use_is_media_p4 (SIM_CPU *cpu, INT acc) | |
179 | { | |
180 | MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); | |
181 | if (acc != -1) | |
182 | return d->cur_acc_p4 & (((DI)1) << acc); | |
183 | return 0; | |
184 | } | |
185 | ||
186 | static void | |
187 | set_use_is_media_p6 (SIM_CPU *cpu, INT fr) | |
188 | { | |
189 | MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); | |
190 | if (fr != -1) | |
191 | { | |
192 | fr400_reset_fr_flags (cpu, fr); | |
193 | d->cur_fr_p6 |= (((DI)1) << fr); | |
194 | } | |
195 | } | |
196 | ||
197 | static void | |
198 | set_use_not_media_p6 (SIM_CPU *cpu, INT fr) | |
199 | { | |
200 | MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); | |
201 | if (fr != -1) | |
202 | d->cur_fr_p6 &= ~(((DI)1) << fr); | |
203 | } | |
204 | ||
205 | static int | |
206 | use_is_media_p6 (SIM_CPU *cpu, INT fr) | |
207 | { | |
208 | MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); | |
209 | if (fr != -1) | |
210 | return d->cur_fr_p6 & (((DI)1) << fr); | |
211 | return 0; | |
212 | } | |
213 | ||
214 | /* Initialize cycle counting for an insn. | |
215 | FIRST_P is non-zero if this is the first insn in a set of parallel | |
216 | insns. */ | |
217 | void | |
218 | fr400_model_insn_before (SIM_CPU *cpu, int first_p) | |
219 | { | |
220 | if (first_p) | |
221 | { | |
222 | MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); | |
223 | FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); | |
224 | ps->cur_gr_complex = ps->prev_gr_complex; | |
225 | d->cur_fp_load = d->prev_fp_load; | |
226 | d->cur_fr_p4 = d->prev_fr_p4; | |
227 | d->cur_fr_p6 = d->prev_fr_p6; | |
228 | d->cur_acc_p2 = d->prev_acc_p2; | |
229 | d->cur_acc_p4 = d->prev_acc_p4; | |
230 | } | |
231 | } | |
232 | ||
233 | /* Record the cycles computed for an insn. | |
234 | LAST_P is non-zero if this is the last insn in a set of parallel insns, | |
235 | and we update the total cycle count. | |
236 | CYCLES is the cycle count of the insn. */ | |
237 | void | |
238 | fr400_model_insn_after (SIM_CPU *cpu, int last_p, int cycles) | |
239 | { | |
240 | if (last_p) | |
241 | { | |
242 | MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); | |
243 | FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); | |
244 | ps->prev_gr_complex = ps->cur_gr_complex; | |
245 | d->prev_fp_load = d->cur_fp_load; | |
246 | d->prev_fr_p4 = d->cur_fr_p4; | |
247 | d->prev_fr_p6 = d->cur_fr_p6; | |
248 | d->prev_acc_p2 = d->cur_acc_p2; | |
249 | d->prev_acc_p4 = d->cur_acc_p4; | |
250 | } | |
251 | } | |
252 | ||
253 | int | |
254 | frvbf_model_fr400_u_exec (SIM_CPU *cpu, const IDESC *idesc, | |
255 | int unit_num, int referenced) | |
256 | { | |
257 | return idesc->timing->units[unit_num].done; | |
258 | } | |
259 | ||
260 | int | |
261 | frvbf_model_fr400_u_integer (SIM_CPU *cpu, const IDESC *idesc, | |
262 | int unit_num, int referenced, | |
263 | INT in_GRi, INT in_GRj, INT out_GRk, | |
264 | INT out_ICCi_1) | |
265 | { | |
266 | /* Modelling for this unit is the same as for fr500. */ | |
267 | return frvbf_model_fr500_u_integer (cpu, idesc, unit_num, referenced, | |
268 | in_GRi, in_GRj, out_GRk, out_ICCi_1); | |
269 | } | |
270 | ||
271 | int | |
272 | frvbf_model_fr400_u_imul (SIM_CPU *cpu, const IDESC *idesc, | |
273 | int unit_num, int referenced, | |
274 | INT in_GRi, INT in_GRj, INT out_GRk, INT out_ICCi_1) | |
275 | { | |
276 | /* Modelling for this unit is the same as for fr500. */ | |
277 | return frvbf_model_fr500_u_imul (cpu, idesc, unit_num, referenced, | |
278 | in_GRi, in_GRj, out_GRk, out_ICCi_1); | |
279 | } | |
280 | ||
281 | int | |
282 | frvbf_model_fr400_u_idiv (SIM_CPU *cpu, const IDESC *idesc, | |
283 | int unit_num, int referenced, | |
284 | INT in_GRi, INT in_GRj, INT out_GRk, INT out_ICCi_1) | |
285 | { | |
286 | int cycles; | |
287 | FRV_VLIW *vliw; | |
288 | int slot; | |
289 | ||
290 | /* icc0-icc4 are the upper 4 fields of the CCR. */ | |
291 | if (out_ICCi_1 >= 0) | |
292 | out_ICCi_1 += 4; | |
293 | ||
294 | vliw = CPU_VLIW (cpu); | |
295 | slot = vliw->next_slot - 1; | |
296 | slot = (*vliw->current_vliw)[slot] - UNIT_I0; | |
297 | ||
298 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
299 | { | |
300 | /* The entire VLIW insn must wait if there is a dependency on a register | |
301 | which is not ready yet. | |
302 | The latency of the registers may be less than previously recorded, | |
303 | depending on how they were used previously. | |
304 | See Table 13-8 in the LSI. */ | |
305 | if (in_GRi != out_GRk && in_GRi >= 0) | |
306 | { | |
307 | if (use_is_gr_complex (cpu, in_GRi)) | |
308 | decrease_GR_busy (cpu, in_GRi, 1); | |
309 | } | |
310 | if (in_GRj != out_GRk && in_GRj != in_GRi && in_GRj >= 0) | |
311 | { | |
312 | if (use_is_gr_complex (cpu, in_GRj)) | |
313 | decrease_GR_busy (cpu, in_GRj, 1); | |
314 | } | |
315 | vliw_wait_for_GR (cpu, in_GRi); | |
316 | vliw_wait_for_GR (cpu, in_GRj); | |
317 | vliw_wait_for_GR (cpu, out_GRk); | |
318 | vliw_wait_for_CCR (cpu, out_ICCi_1); | |
319 | vliw_wait_for_idiv_resource (cpu, slot); | |
320 | handle_resource_wait (cpu); | |
321 | load_wait_for_GR (cpu, in_GRi); | |
322 | load_wait_for_GR (cpu, in_GRj); | |
323 | load_wait_for_GR (cpu, out_GRk); | |
324 | trace_vliw_wait_cycles (cpu); | |
325 | return 0; | |
326 | } | |
327 | ||
328 | /* GRk has a latency of 19 cycles! */ | |
329 | cycles = idesc->timing->units[unit_num].done; | |
330 | update_GR_latency (cpu, out_GRk, cycles + 19); | |
331 | set_use_is_gr_complex (cpu, out_GRk); | |
332 | ||
333 | /* ICCi_1 has a latency of 18 cycles. */ | |
334 | update_CCR_latency (cpu, out_ICCi_1, cycles + 18); | |
335 | ||
336 | /* the idiv resource has a latency of 18 cycles! */ | |
337 | update_idiv_resource_latency (cpu, slot, cycles + 18); | |
338 | ||
339 | return cycles; | |
340 | } | |
341 | ||
342 | int | |
343 | frvbf_model_fr400_u_branch (SIM_CPU *cpu, const IDESC *idesc, | |
344 | int unit_num, int referenced, | |
345 | INT in_GRi, INT in_GRj, | |
346 | INT in_ICCi_2, INT in_ICCi_3) | |
347 | { | |
348 | #define BRANCH_PREDICTED(ps) ((ps)->branch_hint & 2) | |
349 | FRV_PROFILE_STATE *ps; | |
350 | int cycles; | |
351 | ||
352 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
353 | { | |
354 | /* Modelling for this unit is the same as for fr500 in pass 1. */ | |
355 | return frvbf_model_fr500_u_branch (cpu, idesc, unit_num, referenced, | |
356 | in_GRi, in_GRj, in_ICCi_2, in_ICCi_3); | |
357 | } | |
358 | ||
359 | cycles = idesc->timing->units[unit_num].done; | |
360 | ||
361 | /* Compute the branch penalty, based on the the prediction and the out | |
362 | come. When counting branches taken or not taken, don't consider branches | |
363 | after the first taken branch in a vliw insn. */ | |
364 | ps = CPU_PROFILE_STATE (cpu); | |
365 | if (! ps->vliw_branch_taken) | |
366 | { | |
367 | int penalty; | |
368 | /* (1 << 4): The pc is the 5th element in inputs, outputs. | |
369 | ??? can be cleaned up */ | |
370 | PROFILE_DATA *p = CPU_PROFILE_DATA (cpu); | |
371 | int taken = (referenced & (1 << 4)) != 0; | |
372 | if (taken) | |
373 | { | |
374 | ++PROFILE_MODEL_TAKEN_COUNT (p); | |
375 | ps->vliw_branch_taken = 1; | |
376 | if (BRANCH_PREDICTED (ps)) | |
377 | penalty = 1; | |
378 | else | |
379 | penalty = 3; | |
380 | } | |
381 | else | |
382 | { | |
383 | ++PROFILE_MODEL_UNTAKEN_COUNT (p); | |
384 | if (BRANCH_PREDICTED (ps)) | |
385 | penalty = 3; | |
386 | else | |
387 | penalty = 0; | |
388 | } | |
389 | if (penalty > 0) | |
390 | { | |
391 | /* Additional 1 cycle penalty if the branch address is not 8 byte | |
392 | aligned. */ | |
393 | if (ps->branch_address & 7) | |
394 | ++penalty; | |
395 | update_branch_penalty (cpu, penalty); | |
396 | PROFILE_MODEL_CTI_STALL_CYCLES (p) += penalty; | |
397 | } | |
398 | } | |
399 | ||
400 | return cycles; | |
401 | } | |
402 | ||
403 | int | |
404 | frvbf_model_fr400_u_trap (SIM_CPU *cpu, const IDESC *idesc, | |
405 | int unit_num, int referenced, | |
406 | INT in_GRi, INT in_GRj, | |
407 | INT in_ICCi_2, INT in_FCCi_2) | |
408 | { | |
409 | /* Modelling for this unit is the same as for fr500. */ | |
410 | return frvbf_model_fr500_u_trap (cpu, idesc, unit_num, referenced, | |
411 | in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); | |
412 | } | |
413 | ||
414 | int | |
415 | frvbf_model_fr400_u_check (SIM_CPU *cpu, const IDESC *idesc, | |
416 | int unit_num, int referenced, | |
417 | INT in_ICCi_3, INT in_FCCi_3) | |
418 | { | |
419 | /* Modelling for this unit is the same as for fr500. */ | |
420 | return frvbf_model_fr500_u_check (cpu, idesc, unit_num, referenced, | |
421 | in_ICCi_3, in_FCCi_3); | |
422 | } | |
423 | ||
424 | int | |
425 | frvbf_model_fr400_u_set_hilo (SIM_CPU *cpu, const IDESC *idesc, | |
426 | int unit_num, int referenced, | |
427 | INT out_GRkhi, INT out_GRklo) | |
428 | { | |
429 | /* Modelling for this unit is the same as for fr500. */ | |
430 | return frvbf_model_fr500_u_set_hilo (cpu, idesc, unit_num, referenced, | |
431 | out_GRkhi, out_GRklo); | |
432 | } | |
433 | ||
434 | int | |
435 | frvbf_model_fr400_u_gr_load (SIM_CPU *cpu, const IDESC *idesc, | |
436 | int unit_num, int referenced, | |
437 | INT in_GRi, INT in_GRj, | |
438 | INT out_GRk, INT out_GRdoublek) | |
439 | { | |
440 | /* Modelling for this unit is the same as for fr500. */ | |
441 | return frvbf_model_fr500_u_gr_load (cpu, idesc, unit_num, referenced, | |
442 | in_GRi, in_GRj, out_GRk, out_GRdoublek); | |
443 | } | |
444 | ||
445 | int | |
446 | frvbf_model_fr400_u_gr_store (SIM_CPU *cpu, const IDESC *idesc, | |
447 | int unit_num, int referenced, | |
448 | INT in_GRi, INT in_GRj, | |
449 | INT in_GRk, INT in_GRdoublek) | |
450 | { | |
451 | /* Modelling for this unit is the same as for fr500. */ | |
452 | return frvbf_model_fr500_u_gr_store (cpu, idesc, unit_num, referenced, | |
453 | in_GRi, in_GRj, in_GRk, in_GRdoublek); | |
454 | } | |
455 | ||
456 | int | |
457 | frvbf_model_fr400_u_fr_load (SIM_CPU *cpu, const IDESC *idesc, | |
458 | int unit_num, int referenced, | |
459 | INT in_GRi, INT in_GRj, | |
460 | INT out_FRk, INT out_FRdoublek) | |
461 | { | |
462 | int cycles; | |
463 | ||
464 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
465 | { | |
466 | /* Pass 1 is the same as for fr500. */ | |
467 | return frvbf_model_fr500_u_fr_load (cpu, idesc, unit_num, referenced, | |
468 | in_GRi, in_GRj, out_FRk, | |
469 | out_FRdoublek); | |
470 | } | |
471 | ||
472 | cycles = idesc->timing->units[unit_num].done; | |
473 | ||
474 | /* The latency of FRk for a load will depend on how long it takes to retrieve | |
475 | the the data from the cache or memory. */ | |
476 | update_FR_latency_for_load (cpu, out_FRk, cycles); | |
477 | update_FRdouble_latency_for_load (cpu, out_FRdoublek, cycles); | |
478 | ||
479 | set_use_is_fp_load (cpu, out_FRk, out_FRdoublek); | |
480 | ||
481 | return cycles; | |
482 | } | |
483 | ||
484 | int | |
485 | frvbf_model_fr400_u_fr_store (SIM_CPU *cpu, const IDESC *idesc, | |
486 | int unit_num, int referenced, | |
487 | INT in_GRi, INT in_GRj, | |
488 | INT in_FRk, INT in_FRdoublek) | |
489 | { | |
490 | int cycles; | |
491 | ||
492 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
493 | { | |
494 | /* The entire VLIW insn must wait if there is a dependency on a register | |
495 | which is not ready yet. | |
496 | The latency of the registers may be less than previously recorded, | |
497 | depending on how they were used previously. | |
498 | See Table 13-8 in the LSI. */ | |
499 | if (in_GRi >= 0) | |
500 | { | |
501 | if (use_is_gr_complex (cpu, in_GRi)) | |
502 | decrease_GR_busy (cpu, in_GRi, 1); | |
503 | } | |
504 | if (in_GRj != in_GRi && in_GRj >= 0) | |
505 | { | |
506 | if (use_is_gr_complex (cpu, in_GRj)) | |
507 | decrease_GR_busy (cpu, in_GRj, 1); | |
508 | } | |
509 | if (in_FRk >= 0) | |
510 | { | |
511 | if (use_is_media_p4 (cpu, in_FRk) || use_is_media_p6 (cpu, in_FRk)) | |
512 | decrease_FR_busy (cpu, in_FRk, 1); | |
513 | else | |
514 | enforce_full_fr_latency (cpu, in_FRk); | |
515 | } | |
516 | vliw_wait_for_GR (cpu, in_GRi); | |
517 | vliw_wait_for_GR (cpu, in_GRj); | |
518 | vliw_wait_for_FR (cpu, in_FRk); | |
519 | vliw_wait_for_FRdouble (cpu, in_FRdoublek); | |
520 | handle_resource_wait (cpu); | |
521 | load_wait_for_GR (cpu, in_GRi); | |
522 | load_wait_for_GR (cpu, in_GRj); | |
523 | load_wait_for_FR (cpu, in_FRk); | |
524 | load_wait_for_FRdouble (cpu, in_FRdoublek); | |
525 | trace_vliw_wait_cycles (cpu); | |
526 | return 0; | |
527 | } | |
528 | ||
529 | cycles = idesc->timing->units[unit_num].done; | |
530 | ||
531 | return cycles; | |
532 | } | |
533 | ||
534 | int | |
535 | frvbf_model_fr400_u_swap (SIM_CPU *cpu, const IDESC *idesc, | |
536 | int unit_num, int referenced, | |
537 | INT in_GRi, INT in_GRj, INT out_GRk) | |
538 | { | |
539 | /* Modelling for this unit is the same as for fr500. */ | |
540 | return frvbf_model_fr500_u_swap (cpu, idesc, unit_num, referenced, | |
541 | in_GRi, in_GRj, out_GRk); | |
542 | } | |
543 | ||
544 | int | |
545 | frvbf_model_fr400_u_fr2gr (SIM_CPU *cpu, const IDESC *idesc, | |
546 | int unit_num, int referenced, | |
547 | INT in_FRk, INT out_GRj) | |
548 | { | |
549 | int cycles; | |
550 | ||
551 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
552 | { | |
553 | /* The entire VLIW insn must wait if there is a dependency on a register | |
554 | which is not ready yet. | |
555 | The latency of the registers may be less than previously recorded, | |
556 | depending on how they were used previously. | |
557 | See Table 13-8 in the LSI. */ | |
558 | if (in_FRk >= 0) | |
559 | { | |
560 | if (use_is_media_p4 (cpu, in_FRk) || use_is_media_p6 (cpu, in_FRk)) | |
561 | decrease_FR_busy (cpu, in_FRk, 1); | |
562 | else | |
563 | enforce_full_fr_latency (cpu, in_FRk); | |
564 | } | |
565 | vliw_wait_for_FR (cpu, in_FRk); | |
566 | vliw_wait_for_GR (cpu, out_GRj); | |
567 | handle_resource_wait (cpu); | |
568 | load_wait_for_FR (cpu, in_FRk); | |
569 | load_wait_for_GR (cpu, out_GRj); | |
570 | trace_vliw_wait_cycles (cpu); | |
571 | return 0; | |
572 | } | |
573 | ||
574 | /* The latency of GRj is 2 cycles. */ | |
575 | cycles = idesc->timing->units[unit_num].done; | |
576 | update_GR_latency (cpu, out_GRj, cycles + 2); | |
577 | set_use_is_gr_complex (cpu, out_GRj); | |
578 | ||
579 | return cycles; | |
580 | } | |
581 | ||
582 | int | |
583 | frvbf_model_fr400_u_spr2gr (SIM_CPU *cpu, const IDESC *idesc, | |
584 | int unit_num, int referenced, | |
585 | INT in_spr, INT out_GRj) | |
586 | { | |
587 | /* Modelling for this unit is the same as for fr500. */ | |
588 | return frvbf_model_fr500_u_spr2gr (cpu, idesc, unit_num, referenced, | |
589 | in_spr, out_GRj); | |
590 | } | |
591 | ||
592 | int | |
593 | frvbf_model_fr400_u_gr2fr (SIM_CPU *cpu, const IDESC *idesc, | |
594 | int unit_num, int referenced, | |
595 | INT in_GRj, INT out_FRk) | |
596 | { | |
597 | int cycles; | |
598 | ||
599 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
600 | { | |
601 | /* Pass 1 is the same as for fr500. */ | |
602 | frvbf_model_fr500_u_gr2fr (cpu, idesc, unit_num, referenced, | |
603 | in_GRj, out_FRk); | |
604 | } | |
605 | ||
606 | /* The latency of FRk is 1 cycles. */ | |
607 | cycles = idesc->timing->units[unit_num].done; | |
608 | update_FR_latency (cpu, out_FRk, cycles + 1); | |
609 | ||
610 | return cycles; | |
611 | } | |
612 | ||
613 | int | |
614 | frvbf_model_fr400_u_gr2spr (SIM_CPU *cpu, const IDESC *idesc, | |
615 | int unit_num, int referenced, | |
616 | INT in_GRj, INT out_spr) | |
617 | { | |
618 | /* Modelling for this unit is the same as for fr500. */ | |
619 | return frvbf_model_fr500_u_gr2spr (cpu, idesc, unit_num, referenced, | |
620 | in_GRj, out_spr); | |
621 | } | |
622 | ||
b34f6357 DB |
623 | int |
624 | frvbf_model_fr400_u_media_1 (SIM_CPU *cpu, const IDESC *idesc, | |
625 | int unit_num, int referenced, | |
626 | INT in_FRi, INT in_FRj, | |
627 | INT out_FRk) | |
628 | { | |
629 | int cycles; | |
630 | FRV_PROFILE_STATE *ps; | |
631 | const CGEN_INSN *insn; | |
632 | int busy_adjustment[] = {0, 0}; | |
633 | int *fr; | |
634 | ||
635 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
636 | return 0; | |
637 | ||
638 | /* The preprocessing can execute right away. */ | |
639 | cycles = idesc->timing->units[unit_num].done; | |
640 | ||
641 | ps = CPU_PROFILE_STATE (cpu); | |
642 | insn = idesc->idata; | |
643 | ||
644 | /* The latency of the registers may be less than previously recorded, | |
645 | depending on how they were used previously. | |
646 | See Table 13-8 in the LSI. */ | |
647 | if (in_FRi >= 0) | |
648 | { | |
649 | if (use_is_fp_load (cpu, in_FRi)) | |
650 | { | |
651 | busy_adjustment[0] = 1; | |
652 | decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]); | |
653 | } | |
654 | else | |
655 | enforce_full_fr_latency (cpu, in_FRi); | |
656 | } | |
657 | if (in_FRj >= 0 && in_FRj != in_FRi) | |
658 | { | |
659 | if (use_is_fp_load (cpu, in_FRj)) | |
660 | { | |
661 | busy_adjustment[1] = 1; | |
662 | decrease_FR_busy (cpu, in_FRj, busy_adjustment[1]); | |
663 | } | |
664 | else | |
665 | enforce_full_fr_latency (cpu, in_FRj); | |
666 | } | |
667 | ||
668 | /* The post processing must wait if there is a dependency on a FR | |
669 | which is not ready yet. */ | |
670 | ps->post_wait = cycles; | |
671 | post_wait_for_FR (cpu, in_FRi); | |
672 | post_wait_for_FR (cpu, in_FRj); | |
673 | post_wait_for_FR (cpu, out_FRk); | |
674 | ||
675 | /* Restore the busy cycles of the registers we used. */ | |
676 | fr = ps->fr_busy; | |
677 | if (in_FRi >= 0) | |
678 | fr[in_FRi] += busy_adjustment[0]; | |
679 | if (in_FRj >= 0) | |
680 | fr[in_FRj] += busy_adjustment[1]; | |
681 | ||
682 | /* The latency of the output register will be at least the latency of the | |
683 | other inputs. Once initiated, post-processing has no latency. */ | |
684 | if (out_FRk >= 0) | |
685 | { | |
686 | update_FR_latency (cpu, out_FRk, ps->post_wait); | |
687 | update_FR_ptime (cpu, out_FRk, 0); | |
688 | } | |
689 | ||
690 | return cycles; | |
691 | } | |
692 | ||
693 | int | |
694 | frvbf_model_fr400_u_media_1_quad (SIM_CPU *cpu, const IDESC *idesc, | |
695 | int unit_num, int referenced, | |
696 | INT in_FRi, INT in_FRj, | |
697 | INT out_FRk) | |
698 | { | |
699 | int cycles; | |
700 | INT dual_FRi; | |
701 | INT dual_FRj; | |
702 | INT dual_FRk; | |
703 | FRV_PROFILE_STATE *ps; | |
704 | int busy_adjustment[] = {0, 0, 0, 0}; | |
705 | int *fr; | |
706 | ||
707 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
708 | return 0; | |
709 | ||
710 | /* The preprocessing can execute right away. */ | |
711 | cycles = idesc->timing->units[unit_num].done; | |
712 | ||
713 | ps = CPU_PROFILE_STATE (cpu); | |
714 | dual_FRi = DUAL_REG (in_FRi); | |
715 | dual_FRj = DUAL_REG (in_FRj); | |
716 | dual_FRk = DUAL_REG (out_FRk); | |
717 | ||
718 | /* The latency of the registers may be less than previously recorded, | |
719 | depending on how they were used previously. | |
720 | See Table 13-8 in the LSI. */ | |
721 | if (use_is_fp_load (cpu, in_FRi)) | |
722 | { | |
723 | busy_adjustment[0] = 1; | |
724 | decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]); | |
725 | } | |
726 | else | |
727 | enforce_full_fr_latency (cpu, in_FRi); | |
728 | if (dual_FRi >= 0 && use_is_fp_load (cpu, dual_FRi)) | |
729 | { | |
730 | busy_adjustment[1] = 1; | |
731 | decrease_FR_busy (cpu, dual_FRi, busy_adjustment[1]); | |
732 | } | |
733 | else | |
734 | enforce_full_fr_latency (cpu, dual_FRi); | |
735 | if (in_FRj != in_FRi) | |
736 | { | |
737 | if (use_is_fp_load (cpu, in_FRj)) | |
738 | { | |
739 | busy_adjustment[2] = 1; | |
740 | decrease_FR_busy (cpu, in_FRj, busy_adjustment[2]); | |
741 | } | |
742 | else | |
743 | enforce_full_fr_latency (cpu, in_FRj); | |
744 | if (dual_FRj >= 0 && use_is_fp_load (cpu, dual_FRj)) | |
745 | { | |
746 | busy_adjustment[3] = 1; | |
747 | decrease_FR_busy (cpu, dual_FRj, busy_adjustment[3]); | |
748 | } | |
749 | else | |
750 | enforce_full_fr_latency (cpu, dual_FRj); | |
751 | } | |
752 | ||
753 | /* The post processing must wait if there is a dependency on a FR | |
754 | which is not ready yet. */ | |
755 | ps->post_wait = cycles; | |
756 | post_wait_for_FR (cpu, in_FRi); | |
757 | post_wait_for_FR (cpu, dual_FRi); | |
758 | post_wait_for_FR (cpu, in_FRj); | |
759 | post_wait_for_FR (cpu, dual_FRj); | |
760 | post_wait_for_FR (cpu, out_FRk); | |
761 | post_wait_for_FR (cpu, dual_FRk); | |
762 | ||
763 | /* Restore the busy cycles of the registers we used. */ | |
764 | fr = ps->fr_busy; | |
765 | fr[in_FRi] += busy_adjustment[0]; | |
766 | if (dual_FRi >= 0) | |
767 | fr[dual_FRi] += busy_adjustment[1]; | |
768 | fr[in_FRj] += busy_adjustment[2]; | |
769 | if (dual_FRj >= 0) | |
770 | fr[dual_FRj] += busy_adjustment[3]; | |
771 | ||
772 | /* The latency of the output register will be at least the latency of the | |
773 | other inputs. */ | |
774 | update_FR_latency (cpu, out_FRk, ps->post_wait); | |
775 | ||
776 | /* Once initiated, post-processing has no latency. */ | |
777 | update_FR_ptime (cpu, out_FRk, 0); | |
778 | ||
779 | if (dual_FRk >= 0) | |
780 | { | |
781 | update_FR_latency (cpu, dual_FRk, ps->post_wait); | |
782 | update_FR_ptime (cpu, dual_FRk, 0); | |
783 | } | |
784 | ||
785 | return cycles; | |
786 | } | |
787 | ||
788 | int | |
789 | frvbf_model_fr400_u_media_hilo (SIM_CPU *cpu, const IDESC *idesc, | |
790 | int unit_num, int referenced, | |
791 | INT out_FRkhi, INT out_FRklo) | |
792 | { | |
793 | int cycles; | |
794 | FRV_PROFILE_STATE *ps; | |
795 | ||
796 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
797 | return 0; | |
798 | ||
799 | /* The preprocessing can execute right away. */ | |
800 | cycles = idesc->timing->units[unit_num].done; | |
801 | ||
802 | ps = CPU_PROFILE_STATE (cpu); | |
803 | ||
804 | /* The post processing must wait if there is a dependency on a FR | |
805 | which is not ready yet. */ | |
806 | ps->post_wait = cycles; | |
807 | post_wait_for_FR (cpu, out_FRkhi); | |
808 | post_wait_for_FR (cpu, out_FRklo); | |
809 | ||
810 | /* The latency of the output register will be at least the latency of the | |
811 | other inputs. Once initiated, post-processing has no latency. */ | |
812 | if (out_FRkhi >= 0) | |
813 | { | |
814 | update_FR_latency (cpu, out_FRkhi, ps->post_wait); | |
815 | update_FR_ptime (cpu, out_FRkhi, 0); | |
816 | } | |
817 | if (out_FRklo >= 0) | |
818 | { | |
819 | update_FR_latency (cpu, out_FRklo, ps->post_wait); | |
820 | update_FR_ptime (cpu, out_FRklo, 0); | |
821 | } | |
822 | ||
823 | return cycles; | |
824 | } | |
825 | ||
826 | int | |
827 | frvbf_model_fr400_u_media_2 (SIM_CPU *cpu, const IDESC *idesc, | |
828 | int unit_num, int referenced, | |
829 | INT in_FRi, INT in_FRj, | |
830 | INT out_ACC40Sk, INT out_ACC40Uk) | |
831 | { | |
832 | int cycles; | |
833 | INT dual_ACC40Sk; | |
834 | INT dual_ACC40Uk; | |
835 | FRV_PROFILE_STATE *ps; | |
836 | int busy_adjustment[] = {0, 0, 0, 0, 0, 0}; | |
837 | int *fr; | |
838 | int *acc; | |
839 | ||
840 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
841 | return 0; | |
842 | ||
843 | /* The preprocessing can execute right away. */ | |
844 | cycles = idesc->timing->units[unit_num].done; | |
845 | ||
846 | ps = CPU_PROFILE_STATE (cpu); | |
847 | dual_ACC40Sk = DUAL_REG (out_ACC40Sk); | |
848 | dual_ACC40Uk = DUAL_REG (out_ACC40Uk); | |
849 | ||
850 | /* The latency of the registers may be less than previously recorded, | |
851 | depending on how they were used previously. | |
852 | See Table 13-8 in the LSI. */ | |
853 | if (in_FRi >= 0) | |
854 | { | |
855 | if (use_is_fp_load (cpu, in_FRi)) | |
856 | { | |
857 | busy_adjustment[0] = 1; | |
858 | decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]); | |
859 | } | |
860 | else | |
861 | enforce_full_fr_latency (cpu, in_FRi); | |
862 | } | |
863 | if (in_FRj >= 0 && in_FRj != in_FRi) | |
864 | { | |
865 | if (use_is_fp_load (cpu, in_FRj)) | |
866 | { | |
867 | busy_adjustment[1] = 1; | |
868 | decrease_FR_busy (cpu, in_FRj, busy_adjustment[1]); | |
869 | } | |
870 | else | |
871 | enforce_full_fr_latency (cpu, in_FRj); | |
872 | } | |
873 | if (out_ACC40Sk >= 0) | |
874 | { | |
875 | if (acc_use_is_media_p2 (cpu, out_ACC40Sk)) | |
876 | { | |
877 | busy_adjustment[2] = 1; | |
878 | decrease_ACC_busy (cpu, out_ACC40Sk, busy_adjustment[2]); | |
879 | } | |
880 | } | |
881 | if (dual_ACC40Sk >= 0) | |
882 | { | |
883 | if (acc_use_is_media_p2 (cpu, dual_ACC40Sk)) | |
884 | { | |
885 | busy_adjustment[3] = 1; | |
886 | decrease_ACC_busy (cpu, dual_ACC40Sk, busy_adjustment[3]); | |
887 | } | |
888 | } | |
889 | if (out_ACC40Uk >= 0) | |
890 | { | |
891 | if (acc_use_is_media_p2 (cpu, out_ACC40Uk)) | |
892 | { | |
893 | busy_adjustment[4] = 1; | |
894 | decrease_ACC_busy (cpu, out_ACC40Uk, busy_adjustment[4]); | |
895 | } | |
896 | } | |
897 | if (dual_ACC40Uk >= 0) | |
898 | { | |
899 | if (acc_use_is_media_p2 (cpu, dual_ACC40Uk)) | |
900 | { | |
901 | busy_adjustment[5] = 1; | |
902 | decrease_ACC_busy (cpu, dual_ACC40Uk, busy_adjustment[5]); | |
903 | } | |
904 | } | |
905 | ||
906 | /* The post processing must wait if there is a dependency on a FR | |
907 | which is not ready yet. */ | |
908 | ps->post_wait = cycles; | |
909 | post_wait_for_FR (cpu, in_FRi); | |
910 | post_wait_for_FR (cpu, in_FRj); | |
911 | post_wait_for_ACC (cpu, out_ACC40Sk); | |
912 | post_wait_for_ACC (cpu, dual_ACC40Sk); | |
913 | post_wait_for_ACC (cpu, out_ACC40Uk); | |
914 | post_wait_for_ACC (cpu, dual_ACC40Uk); | |
915 | ||
916 | /* Restore the busy cycles of the registers we used. */ | |
917 | fr = ps->fr_busy; | |
918 | acc = ps->acc_busy; | |
919 | fr[in_FRi] += busy_adjustment[0]; | |
920 | fr[in_FRj] += busy_adjustment[1]; | |
921 | if (out_ACC40Sk >= 0) | |
922 | acc[out_ACC40Sk] += busy_adjustment[2]; | |
923 | if (dual_ACC40Sk >= 0) | |
924 | acc[dual_ACC40Sk] += busy_adjustment[3]; | |
925 | if (out_ACC40Uk >= 0) | |
926 | acc[out_ACC40Uk] += busy_adjustment[4]; | |
927 | if (dual_ACC40Uk >= 0) | |
928 | acc[dual_ACC40Uk] += busy_adjustment[5]; | |
929 | ||
930 | /* The latency of the output register will be at least the latency of the | |
931 | other inputs. Once initiated, post-processing will take 1 cycles. */ | |
932 | if (out_ACC40Sk >= 0) | |
933 | { | |
934 | update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1); | |
935 | set_acc_use_is_media_p2 (cpu, out_ACC40Sk); | |
936 | } | |
937 | if (dual_ACC40Sk >= 0) | |
938 | { | |
939 | update_ACC_latency (cpu, dual_ACC40Sk, ps->post_wait + 1); | |
940 | set_acc_use_is_media_p2 (cpu, dual_ACC40Sk); | |
941 | } | |
942 | if (out_ACC40Uk >= 0) | |
943 | { | |
944 | update_ACC_latency (cpu, out_ACC40Uk, ps->post_wait + 1); | |
945 | set_acc_use_is_media_p2 (cpu, out_ACC40Uk); | |
946 | } | |
947 | if (dual_ACC40Uk >= 0) | |
948 | { | |
949 | update_ACC_latency (cpu, dual_ACC40Uk, ps->post_wait + 1); | |
950 | set_acc_use_is_media_p2 (cpu, dual_ACC40Uk); | |
951 | } | |
952 | ||
953 | return cycles; | |
954 | } | |
955 | ||
956 | int | |
957 | frvbf_model_fr400_u_media_2_quad (SIM_CPU *cpu, const IDESC *idesc, | |
958 | int unit_num, int referenced, | |
959 | INT in_FRi, INT in_FRj, | |
960 | INT out_ACC40Sk, INT out_ACC40Uk) | |
961 | { | |
962 | int cycles; | |
963 | INT dual_FRi; | |
964 | INT dual_FRj; | |
965 | INT ACC40Sk_1; | |
966 | INT ACC40Sk_2; | |
967 | INT ACC40Sk_3; | |
968 | INT ACC40Uk_1; | |
969 | INT ACC40Uk_2; | |
970 | INT ACC40Uk_3; | |
971 | FRV_PROFILE_STATE *ps; | |
972 | int busy_adjustment[] = {0, 0, 0, 0, 0, 0, 0 ,0}; | |
973 | int *fr; | |
974 | int *acc; | |
975 | ||
976 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
977 | return 0; | |
978 | ||
979 | /* The preprocessing can execute right away. */ | |
980 | cycles = idesc->timing->units[unit_num].done; | |
981 | ||
982 | dual_FRi = DUAL_REG (in_FRi); | |
983 | dual_FRj = DUAL_REG (in_FRj); | |
984 | ACC40Sk_1 = DUAL_REG (out_ACC40Sk); | |
985 | ACC40Sk_2 = DUAL_REG (ACC40Sk_1); | |
986 | ACC40Sk_3 = DUAL_REG (ACC40Sk_2); | |
987 | ACC40Uk_1 = DUAL_REG (out_ACC40Uk); | |
988 | ACC40Uk_2 = DUAL_REG (ACC40Uk_1); | |
989 | ACC40Uk_3 = DUAL_REG (ACC40Uk_2); | |
990 | ||
991 | ps = CPU_PROFILE_STATE (cpu); | |
992 | /* The latency of the registers may be less than previously recorded, | |
993 | depending on how they were used previously. | |
994 | See Table 13-8 in the LSI. */ | |
995 | if (use_is_fp_load (cpu, in_FRi)) | |
996 | { | |
997 | busy_adjustment[0] = 1; | |
998 | decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]); | |
999 | } | |
1000 | else | |
1001 | enforce_full_fr_latency (cpu, in_FRi); | |
1002 | if (dual_FRi >= 0 && use_is_fp_load (cpu, dual_FRi)) | |
1003 | { | |
1004 | busy_adjustment[1] = 1; | |
1005 | decrease_FR_busy (cpu, dual_FRi, busy_adjustment[1]); | |
1006 | } | |
1007 | else | |
1008 | enforce_full_fr_latency (cpu, dual_FRi); | |
1009 | if (in_FRj != in_FRi) | |
1010 | { | |
1011 | if (use_is_fp_load (cpu, in_FRj)) | |
1012 | { | |
1013 | busy_adjustment[2] = 1; | |
1014 | decrease_FR_busy (cpu, in_FRj, busy_adjustment[2]); | |
1015 | } | |
1016 | else | |
1017 | enforce_full_fr_latency (cpu, in_FRj); | |
1018 | if (dual_FRj >= 0 && use_is_fp_load (cpu, dual_FRj)) | |
1019 | { | |
1020 | busy_adjustment[3] = 1; | |
1021 | decrease_FR_busy (cpu, dual_FRj, busy_adjustment[3]); | |
1022 | } | |
1023 | else | |
1024 | enforce_full_fr_latency (cpu, dual_FRj); | |
1025 | } | |
1026 | if (out_ACC40Sk >= 0) | |
1027 | { | |
1028 | if (acc_use_is_media_p2 (cpu, out_ACC40Sk)) | |
1029 | { | |
1030 | busy_adjustment[4] = 1; | |
1031 | decrease_ACC_busy (cpu, out_ACC40Sk, busy_adjustment[4]); | |
1032 | } | |
1033 | if (ACC40Sk_1 >= 0) | |
1034 | { | |
1035 | if (acc_use_is_media_p2 (cpu, ACC40Sk_1)) | |
1036 | { | |
1037 | busy_adjustment[5] = 1; | |
1038 | decrease_ACC_busy (cpu, ACC40Sk_1, busy_adjustment[5]); | |
1039 | } | |
1040 | } | |
1041 | if (ACC40Sk_2 >= 0) | |
1042 | { | |
1043 | if (acc_use_is_media_p2 (cpu, ACC40Sk_2)) | |
1044 | { | |
1045 | busy_adjustment[6] = 1; | |
1046 | decrease_ACC_busy (cpu, ACC40Sk_2, busy_adjustment[6]); | |
1047 | } | |
1048 | } | |
1049 | if (ACC40Sk_3 >= 0) | |
1050 | { | |
1051 | if (acc_use_is_media_p2 (cpu, ACC40Sk_3)) | |
1052 | { | |
1053 | busy_adjustment[7] = 1; | |
1054 | decrease_ACC_busy (cpu, ACC40Sk_3, busy_adjustment[7]); | |
1055 | } | |
1056 | } | |
1057 | } | |
1058 | else if (out_ACC40Uk >= 0) | |
1059 | { | |
1060 | if (acc_use_is_media_p2 (cpu, out_ACC40Uk)) | |
1061 | { | |
1062 | busy_adjustment[4] = 1; | |
1063 | decrease_ACC_busy (cpu, out_ACC40Uk, busy_adjustment[4]); | |
1064 | } | |
1065 | if (ACC40Uk_1 >= 0) | |
1066 | { | |
1067 | if (acc_use_is_media_p2 (cpu, ACC40Uk_1)) | |
1068 | { | |
1069 | busy_adjustment[5] = 1; | |
1070 | decrease_ACC_busy (cpu, ACC40Uk_1, busy_adjustment[5]); | |
1071 | } | |
1072 | } | |
1073 | if (ACC40Uk_2 >= 0) | |
1074 | { | |
1075 | if (acc_use_is_media_p2 (cpu, ACC40Uk_2)) | |
1076 | { | |
1077 | busy_adjustment[6] = 1; | |
1078 | decrease_ACC_busy (cpu, ACC40Uk_2, busy_adjustment[6]); | |
1079 | } | |
1080 | } | |
1081 | if (ACC40Uk_3 >= 0) | |
1082 | { | |
1083 | if (acc_use_is_media_p2 (cpu, ACC40Uk_3)) | |
1084 | { | |
1085 | busy_adjustment[7] = 1; | |
1086 | decrease_ACC_busy (cpu, ACC40Uk_3, busy_adjustment[7]); | |
1087 | } | |
1088 | } | |
1089 | } | |
1090 | ||
1091 | /* The post processing must wait if there is a dependency on a FR | |
1092 | which is not ready yet. */ | |
1093 | ps->post_wait = cycles; | |
1094 | post_wait_for_FR (cpu, in_FRi); | |
1095 | post_wait_for_FR (cpu, dual_FRi); | |
1096 | post_wait_for_FR (cpu, in_FRj); | |
1097 | post_wait_for_FR (cpu, dual_FRj); | |
1098 | post_wait_for_ACC (cpu, out_ACC40Sk); | |
1099 | post_wait_for_ACC (cpu, ACC40Sk_1); | |
1100 | post_wait_for_ACC (cpu, ACC40Sk_2); | |
1101 | post_wait_for_ACC (cpu, ACC40Sk_3); | |
1102 | post_wait_for_ACC (cpu, out_ACC40Uk); | |
1103 | post_wait_for_ACC (cpu, ACC40Uk_1); | |
1104 | post_wait_for_ACC (cpu, ACC40Uk_2); | |
1105 | post_wait_for_ACC (cpu, ACC40Uk_3); | |
1106 | ||
1107 | /* Restore the busy cycles of the registers we used. */ | |
1108 | fr = ps->fr_busy; | |
1109 | acc = ps->acc_busy; | |
1110 | fr[in_FRi] += busy_adjustment[0]; | |
1111 | if (dual_FRi >= 0) | |
1112 | fr[dual_FRi] += busy_adjustment[1]; | |
1113 | fr[in_FRj] += busy_adjustment[2]; | |
1114 | if (dual_FRj > 0) | |
1115 | fr[dual_FRj] += busy_adjustment[3]; | |
1116 | if (out_ACC40Sk >= 0) | |
1117 | { | |
1118 | acc[out_ACC40Sk] += busy_adjustment[4]; | |
1119 | if (ACC40Sk_1 >= 0) | |
1120 | acc[ACC40Sk_1] += busy_adjustment[5]; | |
1121 | if (ACC40Sk_2 >= 0) | |
1122 | acc[ACC40Sk_2] += busy_adjustment[6]; | |
1123 | if (ACC40Sk_3 >= 0) | |
1124 | acc[ACC40Sk_3] += busy_adjustment[7]; | |
1125 | } | |
1126 | else if (out_ACC40Uk >= 0) | |
1127 | { | |
1128 | acc[out_ACC40Uk] += busy_adjustment[4]; | |
1129 | if (ACC40Uk_1 >= 0) | |
1130 | acc[ACC40Uk_1] += busy_adjustment[5]; | |
1131 | if (ACC40Uk_2 >= 0) | |
1132 | acc[ACC40Uk_2] += busy_adjustment[6]; | |
1133 | if (ACC40Uk_3 >= 0) | |
1134 | acc[ACC40Uk_3] += busy_adjustment[7]; | |
1135 | } | |
1136 | ||
1137 | /* The latency of the output register will be at least the latency of the | |
1138 | other inputs. Once initiated, post-processing will take 1 cycle. */ | |
1139 | if (out_ACC40Sk >= 0) | |
1140 | { | |
1141 | update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1); | |
1142 | ||
1143 | set_acc_use_is_media_p2 (cpu, out_ACC40Sk); | |
1144 | if (ACC40Sk_1 >= 0) | |
1145 | { | |
1146 | update_ACC_latency (cpu, ACC40Sk_1, ps->post_wait + 1); | |
1147 | ||
1148 | set_acc_use_is_media_p2 (cpu, ACC40Sk_1); | |
1149 | } | |
1150 | if (ACC40Sk_2 >= 0) | |
1151 | { | |
1152 | update_ACC_latency (cpu, ACC40Sk_2, ps->post_wait + 1); | |
1153 | ||
1154 | set_acc_use_is_media_p2 (cpu, ACC40Sk_2); | |
1155 | } | |
1156 | if (ACC40Sk_3 >= 0) | |
1157 | { | |
1158 | update_ACC_latency (cpu, ACC40Sk_3, ps->post_wait + 1); | |
1159 | ||
1160 | set_acc_use_is_media_p2 (cpu, ACC40Sk_3); | |
1161 | } | |
1162 | } | |
1163 | else if (out_ACC40Uk >= 0) | |
1164 | { | |
1165 | update_ACC_latency (cpu, out_ACC40Uk, ps->post_wait + 1); | |
1166 | ||
1167 | set_acc_use_is_media_p2 (cpu, out_ACC40Uk); | |
1168 | if (ACC40Uk_1 >= 0) | |
1169 | { | |
1170 | update_ACC_latency (cpu, ACC40Uk_1, ps->post_wait + 1); | |
1171 | ||
1172 | set_acc_use_is_media_p2 (cpu, ACC40Uk_1); | |
1173 | } | |
1174 | if (ACC40Uk_2 >= 0) | |
1175 | { | |
1176 | update_ACC_latency (cpu, ACC40Uk_2, ps->post_wait + 1); | |
1177 | ||
1178 | set_acc_use_is_media_p2 (cpu, ACC40Uk_2); | |
1179 | } | |
1180 | if (ACC40Uk_3 >= 0) | |
1181 | { | |
1182 | update_ACC_latency (cpu, ACC40Uk_3, ps->post_wait + 1); | |
1183 | ||
1184 | set_acc_use_is_media_p2 (cpu, ACC40Uk_3); | |
1185 | } | |
1186 | } | |
1187 | ||
1188 | return cycles; | |
1189 | } | |
1190 | ||
1191 | int | |
1192 | frvbf_model_fr400_u_media_2_acc (SIM_CPU *cpu, const IDESC *idesc, | |
1193 | int unit_num, int referenced, | |
1194 | INT in_ACC40Si, INT out_ACC40Sk) | |
1195 | { | |
1196 | int cycles; | |
1197 | INT ACC40Si_1; | |
1198 | FRV_PROFILE_STATE *ps; | |
1199 | int busy_adjustment[] = {0, 0, 0}; | |
1200 | int *acc; | |
1201 | ||
1202 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
1203 | return 0; | |
1204 | ||
1205 | /* The preprocessing can execute right away. */ | |
1206 | cycles = idesc->timing->units[unit_num].done; | |
1207 | ||
1208 | ACC40Si_1 = DUAL_REG (in_ACC40Si); | |
1209 | ||
1210 | ps = CPU_PROFILE_STATE (cpu); | |
1211 | /* The latency of the registers may be less than previously recorded, | |
1212 | depending on how they were used previously. | |
1213 | See Table 13-8 in the LSI. */ | |
1214 | if (acc_use_is_media_p2 (cpu, in_ACC40Si)) | |
1215 | { | |
1216 | busy_adjustment[0] = 1; | |
1217 | decrease_ACC_busy (cpu, in_ACC40Si, busy_adjustment[0]); | |
1218 | } | |
1219 | if (ACC40Si_1 >= 0 && acc_use_is_media_p2 (cpu, ACC40Si_1)) | |
1220 | { | |
1221 | busy_adjustment[1] = 1; | |
1222 | decrease_ACC_busy (cpu, ACC40Si_1, busy_adjustment[1]); | |
1223 | } | |
1224 | if (out_ACC40Sk != in_ACC40Si && out_ACC40Sk != ACC40Si_1 | |
1225 | && acc_use_is_media_p2 (cpu, out_ACC40Sk)) | |
1226 | { | |
1227 | busy_adjustment[2] = 1; | |
1228 | decrease_ACC_busy (cpu, out_ACC40Sk, busy_adjustment[2]); | |
1229 | } | |
1230 | ||
1231 | /* The post processing must wait if there is a dependency on a register | |
1232 | which is not ready yet. */ | |
1233 | ps->post_wait = cycles; | |
1234 | post_wait_for_ACC (cpu, in_ACC40Si); | |
1235 | post_wait_for_ACC (cpu, ACC40Si_1); | |
1236 | post_wait_for_ACC (cpu, out_ACC40Sk); | |
1237 | ||
1238 | /* Restore the busy cycles of the registers we used. */ | |
1239 | acc = ps->acc_busy; | |
1240 | acc[in_ACC40Si] += busy_adjustment[0]; | |
1241 | if (ACC40Si_1 >= 0) | |
1242 | acc[ACC40Si_1] += busy_adjustment[1]; | |
1243 | acc[out_ACC40Sk] += busy_adjustment[2]; | |
1244 | ||
1245 | /* The latency of the output register will be at least the latency of the | |
1246 | other inputs. Once initiated, post-processing will take 1 cycle. */ | |
1247 | update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1); | |
1248 | set_acc_use_is_media_p2 (cpu, out_ACC40Sk); | |
1249 | ||
1250 | return cycles; | |
1251 | } | |
1252 | ||
1253 | int | |
1254 | frvbf_model_fr400_u_media_2_acc_dual (SIM_CPU *cpu, const IDESC *idesc, | |
1255 | int unit_num, int referenced, | |
1256 | INT in_ACC40Si, INT out_ACC40Sk) | |
1257 | { | |
1258 | int cycles; | |
1259 | INT ACC40Si_1; | |
1260 | INT ACC40Si_2; | |
1261 | INT ACC40Si_3; | |
1262 | INT ACC40Sk_1; | |
1263 | FRV_PROFILE_STATE *ps; | |
1264 | int busy_adjustment[] = {0, 0, 0, 0, 0, 0}; | |
1265 | int *acc; | |
1266 | ||
1267 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
1268 | return 0; | |
1269 | ||
1270 | /* The preprocessing can execute right away. */ | |
1271 | cycles = idesc->timing->units[unit_num].done; | |
1272 | ||
1273 | ACC40Si_1 = DUAL_REG (in_ACC40Si); | |
1274 | ACC40Si_2 = DUAL_REG (ACC40Si_1); | |
1275 | ACC40Si_3 = DUAL_REG (ACC40Si_2); | |
1276 | ACC40Sk_1 = DUAL_REG (out_ACC40Sk); | |
1277 | ||
1278 | ps = CPU_PROFILE_STATE (cpu); | |
1279 | /* The latency of the registers may be less than previously recorded, | |
1280 | depending on how they were used previously. | |
1281 | See Table 13-8 in the LSI. */ | |
1282 | if (acc_use_is_media_p2 (cpu, in_ACC40Si)) | |
1283 | { | |
1284 | busy_adjustment[0] = 1; | |
1285 | decrease_ACC_busy (cpu, in_ACC40Si, busy_adjustment[0]); | |
1286 | } | |
1287 | if (ACC40Si_1 >= 0 && acc_use_is_media_p2 (cpu, ACC40Si_1)) | |
1288 | { | |
1289 | busy_adjustment[1] = 1; | |
1290 | decrease_ACC_busy (cpu, ACC40Si_1, busy_adjustment[1]); | |
1291 | } | |
1292 | if (ACC40Si_2 >= 0 && acc_use_is_media_p2 (cpu, ACC40Si_2)) | |
1293 | { | |
1294 | busy_adjustment[2] = 1; | |
1295 | decrease_ACC_busy (cpu, ACC40Si_2, busy_adjustment[2]); | |
1296 | } | |
1297 | if (ACC40Si_3 >= 0 && acc_use_is_media_p2 (cpu, ACC40Si_3)) | |
1298 | { | |
1299 | busy_adjustment[3] = 1; | |
1300 | decrease_ACC_busy (cpu, ACC40Si_3, busy_adjustment[3]); | |
1301 | } | |
1302 | if (out_ACC40Sk != in_ACC40Si && out_ACC40Sk != ACC40Si_1 | |
1303 | && out_ACC40Sk != ACC40Si_2 && out_ACC40Sk != ACC40Si_3) | |
1304 | { | |
1305 | if (acc_use_is_media_p2 (cpu, out_ACC40Sk)) | |
1306 | { | |
1307 | busy_adjustment[4] = 1; | |
1308 | decrease_ACC_busy (cpu, out_ACC40Sk, busy_adjustment[4]); | |
1309 | } | |
1310 | } | |
1311 | if (ACC40Sk_1 != in_ACC40Si && ACC40Sk_1 != ACC40Si_1 | |
1312 | && ACC40Sk_1 != ACC40Si_2 && ACC40Sk_1 != ACC40Si_3) | |
1313 | { | |
1314 | if (acc_use_is_media_p2 (cpu, ACC40Sk_1)) | |
1315 | { | |
1316 | busy_adjustment[5] = 1; | |
1317 | decrease_ACC_busy (cpu, ACC40Sk_1, busy_adjustment[5]); | |
1318 | } | |
1319 | } | |
1320 | ||
1321 | /* The post processing must wait if there is a dependency on a register | |
1322 | which is not ready yet. */ | |
1323 | ps->post_wait = cycles; | |
1324 | post_wait_for_ACC (cpu, in_ACC40Si); | |
1325 | post_wait_for_ACC (cpu, ACC40Si_1); | |
1326 | post_wait_for_ACC (cpu, ACC40Si_2); | |
1327 | post_wait_for_ACC (cpu, ACC40Si_3); | |
1328 | post_wait_for_ACC (cpu, out_ACC40Sk); | |
1329 | post_wait_for_ACC (cpu, ACC40Sk_1); | |
1330 | ||
1331 | /* Restore the busy cycles of the registers we used. */ | |
1332 | acc = ps->acc_busy; | |
1333 | acc[in_ACC40Si] += busy_adjustment[0]; | |
1334 | if (ACC40Si_1 >= 0) | |
1335 | acc[ACC40Si_1] += busy_adjustment[1]; | |
1336 | if (ACC40Si_2 >= 0) | |
1337 | acc[ACC40Si_2] += busy_adjustment[2]; | |
1338 | if (ACC40Si_3 >= 0) | |
1339 | acc[ACC40Si_3] += busy_adjustment[3]; | |
1340 | acc[out_ACC40Sk] += busy_adjustment[4]; | |
1341 | if (ACC40Sk_1 >= 0) | |
1342 | acc[ACC40Sk_1] += busy_adjustment[5]; | |
1343 | ||
1344 | /* The latency of the output register will be at least the latency of the | |
1345 | other inputs. Once initiated, post-processing will take 1 cycle. */ | |
1346 | update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1); | |
1347 | set_acc_use_is_media_p2 (cpu, out_ACC40Sk); | |
1348 | if (ACC40Sk_1 >= 0) | |
1349 | { | |
1350 | update_ACC_latency (cpu, ACC40Sk_1, ps->post_wait + 1); | |
1351 | set_acc_use_is_media_p2 (cpu, ACC40Sk_1); | |
1352 | } | |
1353 | ||
1354 | return cycles; | |
1355 | } | |
1356 | ||
1357 | int | |
1358 | frvbf_model_fr400_u_media_2_add_sub (SIM_CPU *cpu, const IDESC *idesc, | |
1359 | int unit_num, int referenced, | |
1360 | INT in_ACC40Si, INT out_ACC40Sk) | |
1361 | { | |
1362 | int cycles; | |
1363 | INT ACC40Si_1; | |
1364 | INT ACC40Sk_1; | |
1365 | FRV_PROFILE_STATE *ps; | |
1366 | int busy_adjustment[] = {0, 0, 0, 0}; | |
1367 | int *acc; | |
1368 | ||
1369 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
1370 | return 0; | |
1371 | ||
1372 | /* The preprocessing can execute right away. */ | |
1373 | cycles = idesc->timing->units[unit_num].done; | |
1374 | ||
1375 | ACC40Si_1 = DUAL_REG (in_ACC40Si); | |
1376 | ACC40Sk_1 = DUAL_REG (out_ACC40Sk); | |
1377 | ||
1378 | ps = CPU_PROFILE_STATE (cpu); | |
1379 | /* The latency of the registers may be less than previously recorded, | |
1380 | depending on how they were used previously. | |
1381 | See Table 13-8 in the LSI. */ | |
1382 | if (acc_use_is_media_p2 (cpu, in_ACC40Si)) | |
1383 | { | |
1384 | busy_adjustment[0] = 1; | |
1385 | decrease_ACC_busy (cpu, in_ACC40Si, busy_adjustment[0]); | |
1386 | } | |
1387 | if (ACC40Si_1 >= 0 && acc_use_is_media_p2 (cpu, ACC40Si_1)) | |
1388 | { | |
1389 | busy_adjustment[1] = 1; | |
1390 | decrease_ACC_busy (cpu, ACC40Si_1, busy_adjustment[1]); | |
1391 | } | |
1392 | if (out_ACC40Sk != in_ACC40Si && out_ACC40Sk != ACC40Si_1) | |
1393 | { | |
1394 | if (acc_use_is_media_p2 (cpu, out_ACC40Sk)) | |
1395 | { | |
1396 | busy_adjustment[2] = 1; | |
1397 | decrease_ACC_busy (cpu, out_ACC40Sk, busy_adjustment[2]); | |
1398 | } | |
1399 | } | |
1400 | if (ACC40Sk_1 != in_ACC40Si && ACC40Sk_1 != ACC40Si_1) | |
1401 | { | |
1402 | if (acc_use_is_media_p2 (cpu, ACC40Sk_1)) | |
1403 | { | |
1404 | busy_adjustment[3] = 1; | |
1405 | decrease_ACC_busy (cpu, ACC40Sk_1, busy_adjustment[3]); | |
1406 | } | |
1407 | } | |
1408 | ||
1409 | /* The post processing must wait if there is a dependency on a register | |
1410 | which is not ready yet. */ | |
1411 | ps->post_wait = cycles; | |
1412 | post_wait_for_ACC (cpu, in_ACC40Si); | |
1413 | post_wait_for_ACC (cpu, ACC40Si_1); | |
1414 | post_wait_for_ACC (cpu, out_ACC40Sk); | |
1415 | post_wait_for_ACC (cpu, ACC40Sk_1); | |
1416 | ||
1417 | /* Restore the busy cycles of the registers we used. */ | |
1418 | acc = ps->acc_busy; | |
1419 | acc[in_ACC40Si] += busy_adjustment[0]; | |
1420 | if (ACC40Si_1 >= 0) | |
1421 | acc[ACC40Si_1] += busy_adjustment[1]; | |
1422 | acc[out_ACC40Sk] += busy_adjustment[2]; | |
1423 | if (ACC40Sk_1 >= 0) | |
1424 | acc[ACC40Sk_1] += busy_adjustment[3]; | |
1425 | ||
1426 | /* The latency of the output register will be at least the latency of the | |
1427 | other inputs. Once initiated, post-processing will take 1 cycle. */ | |
1428 | update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1); | |
1429 | set_acc_use_is_media_p2 (cpu, out_ACC40Sk); | |
1430 | if (ACC40Sk_1 >= 0) | |
1431 | { | |
1432 | update_ACC_latency (cpu, ACC40Sk_1, ps->post_wait + 1); | |
1433 | set_acc_use_is_media_p2 (cpu, ACC40Sk_1); | |
1434 | } | |
1435 | ||
1436 | return cycles; | |
1437 | } | |
1438 | ||
1439 | int | |
1440 | frvbf_model_fr400_u_media_2_add_sub_dual (SIM_CPU *cpu, const IDESC *idesc, | |
1441 | int unit_num, int referenced, | |
1442 | INT in_ACC40Si, INT out_ACC40Sk) | |
1443 | { | |
1444 | int cycles; | |
1445 | INT ACC40Si_1; | |
1446 | INT ACC40Si_2; | |
1447 | INT ACC40Si_3; | |
1448 | INT ACC40Sk_1; | |
1449 | INT ACC40Sk_2; | |
1450 | INT ACC40Sk_3; | |
1451 | FRV_PROFILE_STATE *ps; | |
1452 | int busy_adjustment[] = {0, 0, 0, 0, 0, 0, 0, 0}; | |
1453 | int *acc; | |
1454 | ||
1455 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
1456 | return 0; | |
1457 | ||
1458 | /* The preprocessing can execute right away. */ | |
1459 | cycles = idesc->timing->units[unit_num].done; | |
1460 | ||
1461 | ACC40Si_1 = DUAL_REG (in_ACC40Si); | |
1462 | ACC40Si_2 = DUAL_REG (ACC40Si_1); | |
1463 | ACC40Si_3 = DUAL_REG (ACC40Si_2); | |
1464 | ACC40Sk_1 = DUAL_REG (out_ACC40Sk); | |
1465 | ACC40Sk_2 = DUAL_REG (ACC40Sk_1); | |
1466 | ACC40Sk_3 = DUAL_REG (ACC40Sk_2); | |
1467 | ||
1468 | ps = CPU_PROFILE_STATE (cpu); | |
1469 | /* The latency of the registers may be less than previously recorded, | |
1470 | depending on how they were used previously. | |
1471 | See Table 13-8 in the LSI. */ | |
1472 | if (acc_use_is_media_p2 (cpu, in_ACC40Si)) | |
1473 | { | |
1474 | busy_adjustment[0] = 1; | |
1475 | decrease_ACC_busy (cpu, in_ACC40Si, busy_adjustment[0]); | |
1476 | } | |
1477 | if (ACC40Si_1 >= 0 && acc_use_is_media_p2 (cpu, ACC40Si_1)) | |
1478 | { | |
1479 | busy_adjustment[1] = 1; | |
1480 | decrease_ACC_busy (cpu, ACC40Si_1, busy_adjustment[1]); | |
1481 | } | |
1482 | if (ACC40Si_2 >= 0 && acc_use_is_media_p2 (cpu, ACC40Si_2)) | |
1483 | { | |
1484 | busy_adjustment[2] = 1; | |
1485 | decrease_ACC_busy (cpu, ACC40Si_2, busy_adjustment[2]); | |
1486 | } | |
1487 | if (ACC40Si_3 >= 0 && acc_use_is_media_p2 (cpu, ACC40Si_3)) | |
1488 | { | |
1489 | busy_adjustment[3] = 1; | |
1490 | decrease_ACC_busy (cpu, ACC40Si_3, busy_adjustment[3]); | |
1491 | } | |
1492 | if (out_ACC40Sk != in_ACC40Si && out_ACC40Sk != ACC40Si_1 | |
1493 | && out_ACC40Sk != ACC40Si_2 && out_ACC40Sk != ACC40Si_3) | |
1494 | { | |
1495 | if (acc_use_is_media_p2 (cpu, out_ACC40Sk)) | |
1496 | { | |
1497 | busy_adjustment[4] = 1; | |
1498 | decrease_ACC_busy (cpu, out_ACC40Sk, busy_adjustment[4]); | |
1499 | } | |
1500 | } | |
1501 | if (ACC40Sk_1 != in_ACC40Si && ACC40Sk_1 != ACC40Si_1 | |
1502 | && ACC40Sk_1 != ACC40Si_2 && ACC40Sk_1 != ACC40Si_3) | |
1503 | { | |
1504 | if (acc_use_is_media_p2 (cpu, ACC40Sk_1)) | |
1505 | { | |
1506 | busy_adjustment[5] = 1; | |
1507 | decrease_ACC_busy (cpu, ACC40Sk_1, busy_adjustment[5]); | |
1508 | } | |
1509 | } | |
1510 | if (ACC40Sk_2 != in_ACC40Si && ACC40Sk_2 != ACC40Si_1 | |
1511 | && ACC40Sk_2 != ACC40Si_2 && ACC40Sk_2 != ACC40Si_3) | |
1512 | { | |
1513 | if (acc_use_is_media_p2 (cpu, ACC40Sk_2)) | |
1514 | { | |
1515 | busy_adjustment[6] = 1; | |
1516 | decrease_ACC_busy (cpu, ACC40Sk_2, busy_adjustment[6]); | |
1517 | } | |
1518 | } | |
1519 | if (ACC40Sk_3 != in_ACC40Si && ACC40Sk_3 != ACC40Si_1 | |
1520 | && ACC40Sk_3 != ACC40Si_2 && ACC40Sk_3 != ACC40Si_3) | |
1521 | { | |
1522 | if (acc_use_is_media_p2 (cpu, ACC40Sk_3)) | |
1523 | { | |
1524 | busy_adjustment[7] = 1; | |
1525 | decrease_ACC_busy (cpu, ACC40Sk_3, busy_adjustment[7]); | |
1526 | } | |
1527 | } | |
1528 | ||
1529 | /* The post processing must wait if there is a dependency on a register | |
1530 | which is not ready yet. */ | |
1531 | ps->post_wait = cycles; | |
1532 | post_wait_for_ACC (cpu, in_ACC40Si); | |
1533 | post_wait_for_ACC (cpu, ACC40Si_1); | |
1534 | post_wait_for_ACC (cpu, ACC40Si_2); | |
1535 | post_wait_for_ACC (cpu, ACC40Si_3); | |
1536 | post_wait_for_ACC (cpu, out_ACC40Sk); | |
1537 | post_wait_for_ACC (cpu, ACC40Sk_1); | |
1538 | post_wait_for_ACC (cpu, ACC40Sk_2); | |
1539 | post_wait_for_ACC (cpu, ACC40Sk_3); | |
1540 | ||
1541 | /* Restore the busy cycles of the registers we used. */ | |
1542 | acc = ps->acc_busy; | |
1543 | acc[in_ACC40Si] += busy_adjustment[0]; | |
1544 | if (ACC40Si_1 >= 0) | |
1545 | acc[ACC40Si_1] += busy_adjustment[1]; | |
1546 | if (ACC40Si_2 >= 0) | |
1547 | acc[ACC40Si_2] += busy_adjustment[2]; | |
1548 | if (ACC40Si_3 >= 0) | |
1549 | acc[ACC40Si_3] += busy_adjustment[3]; | |
1550 | acc[out_ACC40Sk] += busy_adjustment[4]; | |
1551 | if (ACC40Sk_1 >= 0) | |
1552 | acc[ACC40Sk_1] += busy_adjustment[5]; | |
1553 | if (ACC40Sk_2 >= 0) | |
1554 | acc[ACC40Sk_2] += busy_adjustment[6]; | |
1555 | if (ACC40Sk_3 >= 0) | |
1556 | acc[ACC40Sk_3] += busy_adjustment[7]; | |
1557 | ||
1558 | /* The latency of the output register will be at least the latency of the | |
1559 | other inputs. Once initiated, post-processing will take 1 cycle. */ | |
1560 | update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1); | |
1561 | set_acc_use_is_media_p2 (cpu, out_ACC40Sk); | |
1562 | if (ACC40Sk_1 >= 0) | |
1563 | { | |
1564 | update_ACC_latency (cpu, ACC40Sk_1, ps->post_wait + 1); | |
1565 | set_acc_use_is_media_p2 (cpu, ACC40Sk_1); | |
1566 | } | |
1567 | if (ACC40Sk_2 >= 0) | |
1568 | { | |
1569 | update_ACC_latency (cpu, ACC40Sk_2, ps->post_wait + 1); | |
1570 | set_acc_use_is_media_p2 (cpu, ACC40Sk_2); | |
1571 | } | |
1572 | if (ACC40Sk_3 >= 0) | |
1573 | { | |
1574 | update_ACC_latency (cpu, ACC40Sk_3, ps->post_wait + 1); | |
1575 | set_acc_use_is_media_p2 (cpu, ACC40Sk_3); | |
1576 | } | |
1577 | ||
1578 | return cycles; | |
1579 | } | |
1580 | ||
1581 | int | |
1582 | frvbf_model_fr400_u_media_3 (SIM_CPU *cpu, const IDESC *idesc, | |
1583 | int unit_num, int referenced, | |
1584 | INT in_FRi, INT in_FRj, | |
1585 | INT out_FRk) | |
1586 | { | |
1587 | /* Modelling is the same as media unit 1. */ | |
1588 | return frvbf_model_fr400_u_media_1 (cpu, idesc, unit_num, referenced, | |
1589 | in_FRi, in_FRj, out_FRk); | |
1590 | } | |
1591 | ||
1592 | int | |
1593 | frvbf_model_fr400_u_media_3_dual (SIM_CPU *cpu, const IDESC *idesc, | |
1594 | int unit_num, int referenced, | |
1595 | INT in_FRi, INT out_FRk) | |
1596 | { | |
1597 | int cycles; | |
1598 | INT dual_FRi; | |
1599 | FRV_PROFILE_STATE *ps; | |
1600 | int busy_adjustment[] = {0, 0}; | |
1601 | int *fr; | |
1602 | ||
1603 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
1604 | return 0; | |
1605 | ||
1606 | /* The preprocessing can execute right away. */ | |
1607 | cycles = idesc->timing->units[unit_num].done; | |
1608 | ||
1609 | ps = CPU_PROFILE_STATE (cpu); | |
1610 | dual_FRi = DUAL_REG (in_FRi); | |
1611 | ||
1612 | /* The latency of the registers may be less than previously recorded, | |
1613 | depending on how they were used previously. | |
1614 | See Table 13-8 in the LSI. */ | |
1615 | if (use_is_fp_load (cpu, in_FRi)) | |
1616 | { | |
1617 | busy_adjustment[0] = 1; | |
1618 | decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]); | |
1619 | } | |
1620 | else | |
1621 | enforce_full_fr_latency (cpu, in_FRi); | |
1622 | if (dual_FRi >= 0 && use_is_fp_load (cpu, dual_FRi)) | |
1623 | { | |
1624 | busy_adjustment[1] = 1; | |
1625 | decrease_FR_busy (cpu, dual_FRi, busy_adjustment[1]); | |
1626 | } | |
1627 | else | |
1628 | enforce_full_fr_latency (cpu, dual_FRi); | |
1629 | ||
1630 | /* The post processing must wait if there is a dependency on a FR | |
1631 | which is not ready yet. */ | |
1632 | ps->post_wait = cycles; | |
1633 | post_wait_for_FR (cpu, in_FRi); | |
1634 | post_wait_for_FR (cpu, dual_FRi); | |
1635 | post_wait_for_FR (cpu, out_FRk); | |
1636 | ||
1637 | /* Restore the busy cycles of the registers we used. */ | |
1638 | fr = ps->fr_busy; | |
1639 | fr[in_FRi] += busy_adjustment[0]; | |
1640 | if (dual_FRi >= 0) | |
1641 | fr[dual_FRi] += busy_adjustment[1]; | |
1642 | ||
1643 | /* The latency of the output register will be at least the latency of the | |
1644 | other inputs. */ | |
1645 | update_FR_latency (cpu, out_FRk, ps->post_wait); | |
1646 | ||
1647 | /* Once initiated, post-processing has no latency. */ | |
1648 | update_FR_ptime (cpu, out_FRk, 0); | |
1649 | ||
1650 | return cycles; | |
1651 | } | |
1652 | ||
1653 | int | |
1654 | frvbf_model_fr400_u_media_3_quad (SIM_CPU *cpu, const IDESC *idesc, | |
1655 | int unit_num, int referenced, | |
1656 | INT in_FRi, INT in_FRj, | |
1657 | INT out_FRk) | |
1658 | { | |
1659 | /* Modelling is the same as media unit 1. */ | |
1660 | return frvbf_model_fr400_u_media_1_quad (cpu, idesc, unit_num, referenced, | |
1661 | in_FRi, in_FRj, out_FRk); | |
1662 | } | |
1663 | ||
1664 | int | |
1665 | frvbf_model_fr400_u_media_4 (SIM_CPU *cpu, const IDESC *idesc, | |
1666 | int unit_num, int referenced, | |
1667 | INT in_ACC40Si, INT in_FRj, | |
1668 | INT out_ACC40Sk, INT out_FRk) | |
1669 | { | |
1670 | int cycles; | |
1671 | FRV_PROFILE_STATE *ps; | |
1672 | const CGEN_INSN *insn; | |
1673 | int busy_adjustment[] = {0}; | |
1674 | int *fr; | |
1675 | ||
1676 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
1677 | return 0; | |
1678 | ||
1679 | /* The preprocessing can execute right away. */ | |
1680 | cycles = idesc->timing->units[unit_num].done; | |
1681 | ||
1682 | ps = CPU_PROFILE_STATE (cpu); | |
1683 | insn = idesc->idata; | |
1684 | ||
1685 | /* The latency of the registers may be less than previously recorded, | |
1686 | depending on how they were used previously. | |
1687 | See Table 13-8 in the LSI. */ | |
1688 | if (in_FRj >= 0) | |
1689 | { | |
1690 | if (use_is_fp_load (cpu, in_FRj)) | |
1691 | { | |
1692 | busy_adjustment[0] = 1; | |
1693 | decrease_FR_busy (cpu, in_FRj, busy_adjustment[0]); | |
1694 | } | |
1695 | else | |
1696 | enforce_full_fr_latency (cpu, in_FRj); | |
1697 | } | |
1698 | ||
1699 | /* The post processing must wait if there is a dependency on a FR | |
1700 | which is not ready yet. */ | |
1701 | ps->post_wait = cycles; | |
1702 | post_wait_for_ACC (cpu, in_ACC40Si); | |
1703 | post_wait_for_ACC (cpu, out_ACC40Sk); | |
1704 | post_wait_for_FR (cpu, in_FRj); | |
1705 | post_wait_for_FR (cpu, out_FRk); | |
1706 | ||
1707 | /* Restore the busy cycles of the registers we used. */ | |
1708 | fr = ps->fr_busy; | |
1709 | ||
1710 | /* The latency of the output register will be at least the latency of the | |
1711 | other inputs. Once initiated, post-processing will take 1 cycle. */ | |
1712 | if (out_FRk >= 0) | |
1713 | { | |
1714 | update_FR_latency (cpu, out_FRk, ps->post_wait); | |
1715 | update_FR_ptime (cpu, out_FRk, 1); | |
1716 | /* Mark this use of the register as media unit 4. */ | |
1717 | set_use_is_media_p4 (cpu, out_FRk); | |
1718 | } | |
1719 | else if (out_ACC40Sk >= 0) | |
1720 | { | |
1721 | update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait); | |
1722 | update_ACC_ptime (cpu, out_ACC40Sk, 1); | |
1723 | /* Mark this use of the register as media unit 4. */ | |
1724 | set_acc_use_is_media_p4 (cpu, out_ACC40Sk); | |
1725 | } | |
1726 | ||
1727 | return cycles; | |
1728 | } | |
1729 | ||
1730 | int | |
1731 | frvbf_model_fr400_u_media_4_accg (SIM_CPU *cpu, const IDESC *idesc, | |
1732 | int unit_num, int referenced, | |
1733 | INT in_ACCGi, INT in_FRinti, | |
1734 | INT out_ACCGk, INT out_FRintk) | |
1735 | { | |
1736 | /* Modelling is the same as media-4 unit except use accumulator guards | |
1737 | as input instead of accumulators. */ | |
1738 | return frvbf_model_fr400_u_media_4 (cpu, idesc, unit_num, referenced, | |
1739 | in_ACCGi, in_FRinti, | |
1740 | out_ACCGk, out_FRintk); | |
1741 | } | |
1742 | ||
1743 | int | |
1744 | frvbf_model_fr400_u_media_4_acc_dual (SIM_CPU *cpu, const IDESC *idesc, | |
1745 | int unit_num, int referenced, | |
1746 | INT in_ACC40Si, INT out_FRk) | |
1747 | { | |
1748 | int cycles; | |
1749 | FRV_PROFILE_STATE *ps; | |
1750 | const CGEN_INSN *insn; | |
1751 | INT ACC40Si_1; | |
1752 | INT FRk_1; | |
1753 | ||
1754 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
1755 | return 0; | |
1756 | ||
1757 | /* The preprocessing can execute right away. */ | |
1758 | cycles = idesc->timing->units[unit_num].done; | |
1759 | ||
1760 | ps = CPU_PROFILE_STATE (cpu); | |
1761 | ACC40Si_1 = DUAL_REG (in_ACC40Si); | |
1762 | FRk_1 = DUAL_REG (out_FRk); | |
1763 | ||
1764 | insn = idesc->idata; | |
1765 | ||
1766 | /* The post processing must wait if there is a dependency on a FR | |
1767 | which is not ready yet. */ | |
1768 | ps->post_wait = cycles; | |
1769 | post_wait_for_ACC (cpu, in_ACC40Si); | |
1770 | post_wait_for_ACC (cpu, ACC40Si_1); | |
1771 | post_wait_for_FR (cpu, out_FRk); | |
1772 | post_wait_for_FR (cpu, FRk_1); | |
1773 | ||
1774 | /* The latency of the output register will be at least the latency of the | |
1775 | other inputs. Once initiated, post-processing will take 1 cycle. */ | |
1776 | if (out_FRk >= 0) | |
1777 | { | |
1778 | update_FR_latency (cpu, out_FRk, ps->post_wait); | |
1779 | update_FR_ptime (cpu, out_FRk, 1); | |
1780 | /* Mark this use of the register as media unit 4. */ | |
1781 | set_use_is_media_p4 (cpu, out_FRk); | |
1782 | } | |
1783 | if (FRk_1 >= 0) | |
1784 | { | |
1785 | update_FR_latency (cpu, FRk_1, ps->post_wait); | |
1786 | update_FR_ptime (cpu, FRk_1, 1); | |
1787 | /* Mark this use of the register as media unit 4. */ | |
1788 | set_use_is_media_p4 (cpu, FRk_1); | |
1789 | } | |
1790 | ||
1791 | return cycles; | |
1792 | } | |
1793 | ||
1794 | int | |
1795 | frvbf_model_fr400_u_media_6 (SIM_CPU *cpu, const IDESC *idesc, | |
1796 | int unit_num, int referenced, | |
1797 | INT in_FRi, INT out_FRk) | |
1798 | { | |
1799 | int cycles; | |
1800 | FRV_PROFILE_STATE *ps; | |
1801 | const CGEN_INSN *insn; | |
1802 | int busy_adjustment[] = {0}; | |
1803 | int *fr; | |
1804 | ||
1805 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
1806 | return 0; | |
1807 | ||
1808 | /* The preprocessing can execute right away. */ | |
1809 | cycles = idesc->timing->units[unit_num].done; | |
1810 | ||
1811 | ps = CPU_PROFILE_STATE (cpu); | |
1812 | insn = idesc->idata; | |
1813 | ||
1814 | /* The latency of the registers may be less than previously recorded, | |
1815 | depending on how they were used previously. | |
1816 | See Table 13-8 in the LSI. */ | |
1817 | if (in_FRi >= 0) | |
1818 | { | |
1819 | if (use_is_fp_load (cpu, in_FRi)) | |
1820 | { | |
1821 | busy_adjustment[0] = 1; | |
1822 | decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]); | |
1823 | } | |
1824 | else | |
1825 | enforce_full_fr_latency (cpu, in_FRi); | |
1826 | } | |
1827 | ||
1828 | /* The post processing must wait if there is a dependency on a FR | |
1829 | which is not ready yet. */ | |
1830 | ps->post_wait = cycles; | |
1831 | post_wait_for_FR (cpu, in_FRi); | |
1832 | post_wait_for_FR (cpu, out_FRk); | |
1833 | ||
1834 | /* Restore the busy cycles of the registers we used. */ | |
1835 | fr = ps->fr_busy; | |
1836 | if (in_FRi >= 0) | |
1837 | fr[in_FRi] += busy_adjustment[0]; | |
1838 | ||
1839 | /* The latency of the output register will be at least the latency of the | |
1840 | other inputs. Once initiated, post-processing will take 1 cycle. */ | |
1841 | if (out_FRk >= 0) | |
1842 | { | |
1843 | update_FR_latency (cpu, out_FRk, ps->post_wait); | |
1844 | update_FR_ptime (cpu, out_FRk, 1); | |
1845 | ||
1846 | /* Mark this use of the register as media unit 1. */ | |
1847 | set_use_is_media_p6 (cpu, out_FRk); | |
1848 | } | |
1849 | ||
1850 | return cycles; | |
1851 | } | |
1852 | ||
1853 | int | |
1854 | frvbf_model_fr400_u_media_7 (SIM_CPU *cpu, const IDESC *idesc, | |
1855 | int unit_num, int referenced, | |
1856 | INT in_FRinti, INT in_FRintj, | |
1857 | INT out_FCCk) | |
1858 | { | |
1859 | int cycles; | |
1860 | FRV_PROFILE_STATE *ps; | |
1861 | int busy_adjustment[] = {0, 0}; | |
1862 | int *fr; | |
1863 | ||
1864 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
1865 | return 0; | |
1866 | ||
1867 | /* The preprocessing can execute right away. */ | |
1868 | cycles = idesc->timing->units[unit_num].done; | |
1869 | ||
1870 | /* The post processing must wait if there is a dependency on a FR | |
1871 | which is not ready yet. */ | |
1872 | ps = CPU_PROFILE_STATE (cpu); | |
1873 | ||
1874 | /* The latency of the registers may be less than previously recorded, | |
1875 | depending on how they were used previously. | |
1876 | See Table 13-8 in the LSI. */ | |
1877 | if (in_FRinti >= 0) | |
1878 | { | |
1879 | if (use_is_fp_load (cpu, in_FRinti)) | |
1880 | { | |
1881 | busy_adjustment[0] = 1; | |
1882 | decrease_FR_busy (cpu, in_FRinti, busy_adjustment[0]); | |
1883 | } | |
1884 | else | |
1885 | enforce_full_fr_latency (cpu, in_FRinti); | |
1886 | } | |
1887 | if (in_FRintj >= 0 && in_FRintj != in_FRinti) | |
1888 | { | |
1889 | if (use_is_fp_load (cpu, in_FRintj)) | |
1890 | { | |
1891 | busy_adjustment[1] = 1; | |
1892 | decrease_FR_busy (cpu, in_FRintj, busy_adjustment[1]); | |
1893 | } | |
1894 | else | |
1895 | enforce_full_fr_latency (cpu, in_FRintj); | |
1896 | } | |
1897 | ||
1898 | ps->post_wait = cycles; | |
1899 | post_wait_for_FR (cpu, in_FRinti); | |
1900 | post_wait_for_FR (cpu, in_FRintj); | |
1901 | post_wait_for_CCR (cpu, out_FCCk); | |
1902 | ||
1903 | /* Restore the busy cycles of the registers we used. */ | |
1904 | fr = ps->fr_busy; | |
1905 | if (in_FRinti >= 0) | |
1906 | fr[in_FRinti] += busy_adjustment[0]; | |
1907 | if (in_FRintj >= 0) | |
1908 | fr[in_FRintj] += busy_adjustment[1]; | |
1909 | ||
1910 | /* The latency of FCCi_2 will be the latency of the other inputs plus 1 | |
1911 | cycle. */ | |
1912 | update_CCR_latency (cpu, out_FCCk, ps->post_wait + 1); | |
1913 | ||
1914 | return cycles; | |
1915 | } | |
1916 | ||
1917 | int | |
1918 | frvbf_model_fr400_u_media_dual_expand (SIM_CPU *cpu, const IDESC *idesc, | |
1919 | int unit_num, int referenced, | |
1920 | INT in_FRi, | |
1921 | INT out_FRk) | |
1922 | { | |
1923 | /* Insns using this unit are media-3 class insns, with a dual FRk output. */ | |
1924 | int cycles; | |
1925 | INT dual_FRk; | |
1926 | FRV_PROFILE_STATE *ps; | |
1927 | int busy_adjustment[] = {0}; | |
1928 | int *fr; | |
1929 | ||
1930 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
1931 | return 0; | |
1932 | ||
1933 | /* The preprocessing can execute right away. */ | |
1934 | cycles = idesc->timing->units[unit_num].done; | |
1935 | ||
1936 | /* If the previous use of the registers was a media op, | |
1937 | then their latency will be less than previously recorded. | |
1938 | See Table 13-13 in the LSI. */ | |
1939 | dual_FRk = DUAL_REG (out_FRk); | |
1940 | ps = CPU_PROFILE_STATE (cpu); | |
1941 | if (use_is_fp_load (cpu, in_FRi)) | |
1942 | { | |
1943 | busy_adjustment[0] = 1; | |
1944 | decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]); | |
1945 | } | |
1946 | else | |
1947 | enforce_full_fr_latency (cpu, in_FRi); | |
1948 | ||
1949 | /* The post processing must wait if there is a dependency on a FR | |
1950 | which is not ready yet. */ | |
1951 | ps->post_wait = cycles; | |
1952 | post_wait_for_FR (cpu, in_FRi); | |
1953 | post_wait_for_FR (cpu, out_FRk); | |
1954 | post_wait_for_FR (cpu, dual_FRk); | |
1955 | ||
1956 | /* Restore the busy cycles of the registers we used. */ | |
1957 | fr = ps->fr_busy; | |
1958 | fr[in_FRi] += busy_adjustment[0]; | |
1959 | ||
1960 | /* The latency of the output register will be at least the latency of the | |
1961 | other inputs. Once initiated, post-processing has no latency. */ | |
1962 | update_FR_latency (cpu, out_FRk, ps->post_wait); | |
1963 | update_FR_ptime (cpu, out_FRk, 0); | |
1964 | ||
1965 | if (dual_FRk >= 0) | |
1966 | { | |
1967 | update_FR_latency (cpu, dual_FRk, ps->post_wait); | |
1968 | update_FR_ptime (cpu, dual_FRk, 0); | |
1969 | } | |
1970 | ||
1971 | return cycles; | |
1972 | } | |
1973 | ||
1974 | int | |
1975 | frvbf_model_fr400_u_media_dual_htob (SIM_CPU *cpu, const IDESC *idesc, | |
1976 | int unit_num, int referenced, | |
1977 | INT in_FRj, | |
1978 | INT out_FRk) | |
1979 | { | |
1980 | /* Insns using this unit are media-3 class insns, with a dual FRj input. */ | |
1981 | int cycles; | |
1982 | INT dual_FRj; | |
1983 | FRV_PROFILE_STATE *ps; | |
1984 | int busy_adjustment[] = {0, 0}; | |
1985 | int *fr; | |
1986 | ||
1987 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
1988 | return 0; | |
1989 | ||
1990 | /* The preprocessing can execute right away. */ | |
1991 | cycles = idesc->timing->units[unit_num].done; | |
1992 | ||
1993 | /* If the previous use of the registers was a media op, | |
1994 | then their latency will be less than previously recorded. | |
1995 | See Table 13-13 in the LSI. */ | |
1996 | dual_FRj = DUAL_REG (in_FRj); | |
1997 | ps = CPU_PROFILE_STATE (cpu); | |
1998 | if (use_is_fp_load (cpu, in_FRj)) | |
1999 | { | |
2000 | busy_adjustment[0] = 1; | |
2001 | decrease_FR_busy (cpu, in_FRj, busy_adjustment[0]); | |
2002 | } | |
2003 | else | |
2004 | enforce_full_fr_latency (cpu, in_FRj); | |
2005 | if (dual_FRj >= 0) | |
2006 | { | |
2007 | if (use_is_fp_load (cpu, dual_FRj)) | |
2008 | { | |
2009 | busy_adjustment[1] = 1; | |
2010 | decrease_FR_busy (cpu, dual_FRj, busy_adjustment[1]); | |
2011 | } | |
2012 | else | |
2013 | enforce_full_fr_latency (cpu, dual_FRj); | |
2014 | } | |
2015 | ||
2016 | /* The post processing must wait if there is a dependency on a FR | |
2017 | which is not ready yet. */ | |
2018 | ps->post_wait = cycles; | |
2019 | post_wait_for_FR (cpu, in_FRj); | |
2020 | post_wait_for_FR (cpu, dual_FRj); | |
2021 | post_wait_for_FR (cpu, out_FRk); | |
2022 | ||
2023 | /* Restore the busy cycles of the registers we used. */ | |
2024 | fr = ps->fr_busy; | |
2025 | fr[in_FRj] += busy_adjustment[0]; | |
2026 | if (dual_FRj >= 0) | |
2027 | fr[dual_FRj] += busy_adjustment[1]; | |
2028 | ||
2029 | /* The latency of the output register will be at least the latency of the | |
2030 | other inputs. */ | |
2031 | update_FR_latency (cpu, out_FRk, ps->post_wait); | |
2032 | ||
2033 | /* Once initiated, post-processing has no latency. */ | |
2034 | update_FR_ptime (cpu, out_FRk, 0); | |
2035 | ||
2036 | return cycles; | |
2037 | } | |
2038 | ||
2039 | int | |
2040 | frvbf_model_fr400_u_ici (SIM_CPU *cpu, const IDESC *idesc, | |
2041 | int unit_num, int referenced, | |
2042 | INT in_GRi, INT in_GRj) | |
2043 | { | |
2044 | /* Modelling for this unit is the same as for fr500. */ | |
2045 | return frvbf_model_fr500_u_ici (cpu, idesc, unit_num, referenced, | |
2046 | in_GRi, in_GRj); | |
2047 | } | |
2048 | ||
2049 | int | |
2050 | frvbf_model_fr400_u_dci (SIM_CPU *cpu, const IDESC *idesc, | |
2051 | int unit_num, int referenced, | |
2052 | INT in_GRi, INT in_GRj) | |
2053 | { | |
2054 | /* Modelling for this unit is the same as for fr500. */ | |
2055 | return frvbf_model_fr500_u_dci (cpu, idesc, unit_num, referenced, | |
2056 | in_GRi, in_GRj); | |
2057 | } | |
2058 | ||
2059 | int | |
2060 | frvbf_model_fr400_u_dcf (SIM_CPU *cpu, const IDESC *idesc, | |
2061 | int unit_num, int referenced, | |
2062 | INT in_GRi, INT in_GRj) | |
2063 | { | |
2064 | /* Modelling for this unit is the same as for fr500. */ | |
2065 | return frvbf_model_fr500_u_dcf (cpu, idesc, unit_num, referenced, | |
2066 | in_GRi, in_GRj); | |
2067 | } | |
2068 | ||
2069 | int | |
2070 | frvbf_model_fr400_u_icpl (SIM_CPU *cpu, const IDESC *idesc, | |
2071 | int unit_num, int referenced, | |
2072 | INT in_GRi, INT in_GRj) | |
2073 | { | |
2074 | /* Modelling for this unit is the same as for fr500. */ | |
2075 | return frvbf_model_fr500_u_icpl (cpu, idesc, unit_num, referenced, | |
2076 | in_GRi, in_GRj); | |
2077 | } | |
2078 | ||
2079 | int | |
2080 | frvbf_model_fr400_u_dcpl (SIM_CPU *cpu, const IDESC *idesc, | |
2081 | int unit_num, int referenced, | |
2082 | INT in_GRi, INT in_GRj) | |
2083 | { | |
2084 | /* Modelling for this unit is the same as for fr500. */ | |
2085 | return frvbf_model_fr500_u_dcpl (cpu, idesc, unit_num, referenced, | |
2086 | in_GRi, in_GRj); | |
2087 | } | |
2088 | ||
2089 | int | |
2090 | frvbf_model_fr400_u_icul (SIM_CPU *cpu, const IDESC *idesc, | |
2091 | int unit_num, int referenced, | |
2092 | INT in_GRi, INT in_GRj) | |
2093 | { | |
2094 | /* Modelling for this unit is the same as for fr500. */ | |
2095 | return frvbf_model_fr500_u_icul (cpu, idesc, unit_num, referenced, | |
2096 | in_GRi, in_GRj); | |
2097 | } | |
2098 | ||
2099 | int | |
2100 | frvbf_model_fr400_u_dcul (SIM_CPU *cpu, const IDESC *idesc, | |
2101 | int unit_num, int referenced, | |
2102 | INT in_GRi, INT in_GRj) | |
2103 | { | |
2104 | /* Modelling for this unit is the same as for fr500. */ | |
2105 | return frvbf_model_fr500_u_dcul (cpu, idesc, unit_num, referenced, | |
2106 | in_GRi, in_GRj); | |
2107 | } | |
2108 | ||
2109 | int | |
2110 | frvbf_model_fr400_u_barrier (SIM_CPU *cpu, const IDESC *idesc, | |
2111 | int unit_num, int referenced) | |
2112 | { | |
2113 | /* Modelling for this unit is the same as for fr500. */ | |
2114 | return frvbf_model_fr500_u_barrier (cpu, idesc, unit_num, referenced); | |
2115 | } | |
2116 | ||
2117 | int | |
2118 | frvbf_model_fr400_u_membar (SIM_CPU *cpu, const IDESC *idesc, | |
2119 | int unit_num, int referenced) | |
2120 | { | |
2121 | /* Modelling for this unit is the same as for fr500. */ | |
2122 | return frvbf_model_fr500_u_membar (cpu, idesc, unit_num, referenced); | |
2123 | } | |
2124 | ||
2125 | #endif /* WITH_PROFILE_MODEL_P */ |