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676a64f4 RS |
1 | /* frv simulator fr450 dependent profiling code. |
2 | ||
32d0add0 | 3 | Copyright (C) 2001-2015 Free Software Foundation, Inc. |
676a64f4 RS |
4 | Contributed by Red Hat |
5 | ||
6 | This file is part of the GNU simulators. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
4744ac1b JB |
10 | the Free Software Foundation; either version 3 of the License, or |
11 | (at your option) any later version. | |
676a64f4 RS |
12 | |
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
4744ac1b JB |
18 | You should have received a copy of the GNU General Public License |
19 | along with this program. If not, see <http://www.gnu.org/licenses/>. | |
676a64f4 RS |
20 | |
21 | */ | |
22 | #define WANT_CPU | |
23 | #define WANT_CPU_FRVBF | |
24 | ||
25 | #include "sim-main.h" | |
26 | #include "bfd.h" | |
27 | ||
28 | #if WITH_PROFILE_MODEL_P | |
29 | ||
30 | #include "profile.h" | |
31 | #include "profile-fr400.h" | |
32 | ||
33 | int | |
34 | frvbf_model_fr450_u_exec (SIM_CPU *cpu, const IDESC *idesc, | |
35 | int unit_num, int referenced) | |
36 | { | |
37 | return idesc->timing->units[unit_num].done; | |
38 | } | |
39 | ||
40 | int | |
41 | frvbf_model_fr450_u_integer (SIM_CPU *cpu, const IDESC *idesc, | |
42 | int unit_num, int referenced, | |
43 | INT in_GRi, INT in_GRj, INT out_GRk, | |
44 | INT out_ICCi_1) | |
45 | { | |
46 | /* Modelling for this unit is the same as for fr500. */ | |
47 | return frvbf_model_fr500_u_integer (cpu, idesc, unit_num, referenced, | |
48 | in_GRi, in_GRj, out_GRk, out_ICCi_1); | |
49 | } | |
50 | ||
51 | int | |
52 | frvbf_model_fr450_u_imul (SIM_CPU *cpu, const IDESC *idesc, | |
53 | int unit_num, int referenced, | |
54 | INT in_GRi, INT in_GRj, INT out_GRk, INT out_ICCi_1) | |
55 | { | |
56 | int cycles; | |
57 | ||
58 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
59 | { | |
60 | /* Pass 1 is the same as for fr500. */ | |
61 | return frvbf_model_fr500_u_imul (cpu, idesc, unit_num, referenced, | |
62 | in_GRi, in_GRj, out_GRk, out_ICCi_1); | |
63 | } | |
64 | ||
65 | /* icc0-icc4 are the upper 4 fields of the CCR. */ | |
66 | if (out_ICCi_1 >= 0) | |
67 | out_ICCi_1 += 4; | |
68 | ||
69 | /* GRk and IACCi_1 have a latency of 1 cycle. */ | |
70 | cycles = idesc->timing->units[unit_num].done; | |
71 | update_GRdouble_latency (cpu, out_GRk, cycles + 1); | |
72 | update_CCR_latency (cpu, out_ICCi_1, cycles + 1); | |
73 | ||
74 | return cycles; | |
75 | } | |
76 | ||
77 | int | |
78 | frvbf_model_fr450_u_idiv (SIM_CPU *cpu, const IDESC *idesc, | |
79 | int unit_num, int referenced, | |
80 | INT in_GRi, INT in_GRj, INT out_GRk, INT out_ICCi_1) | |
81 | { | |
82 | int cycles; | |
83 | ||
84 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
85 | { | |
86 | /* Pass 1 is the same as for fr500. */ | |
87 | return frvbf_model_fr500_u_idiv (cpu, idesc, unit_num, referenced, | |
88 | in_GRi, in_GRj, out_GRk, out_ICCi_1); | |
89 | } | |
90 | ||
91 | /* icc0-icc4 are the upper 4 fields of the CCR. */ | |
92 | if (out_ICCi_1 >= 0) | |
93 | out_ICCi_1 += 4; | |
94 | ||
95 | /* GRk, ICCi_1 and the divider have a latency of 18 cycles */ | |
96 | cycles = idesc->timing->units[unit_num].done; | |
97 | update_GR_latency (cpu, out_GRk, cycles + 18); | |
98 | update_CCR_latency (cpu, out_ICCi_1, cycles + 18); | |
99 | update_idiv_resource_latency (cpu, 0, cycles + 18); | |
100 | ||
101 | return cycles; | |
102 | } | |
103 | ||
104 | int | |
105 | frvbf_model_fr450_u_branch (SIM_CPU *cpu, const IDESC *idesc, | |
106 | int unit_num, int referenced, | |
107 | INT in_GRi, INT in_GRj, | |
108 | INT in_ICCi_2, INT in_ICCi_3) | |
109 | { | |
110 | /* Modelling for this unit is the same as for fr400. */ | |
111 | return frvbf_model_fr400_u_branch (cpu, idesc, unit_num, referenced, | |
112 | in_GRi, in_GRj, in_ICCi_2, in_ICCi_3); | |
113 | } | |
114 | ||
115 | int | |
116 | frvbf_model_fr450_u_trap (SIM_CPU *cpu, const IDESC *idesc, | |
117 | int unit_num, int referenced, | |
118 | INT in_GRi, INT in_GRj, | |
119 | INT in_ICCi_2, INT in_FCCi_2) | |
120 | { | |
121 | /* Modelling for this unit is the same as for fr500. */ | |
122 | return frvbf_model_fr500_u_trap (cpu, idesc, unit_num, referenced, | |
123 | in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); | |
124 | } | |
125 | ||
126 | int | |
127 | frvbf_model_fr450_u_check (SIM_CPU *cpu, const IDESC *idesc, | |
128 | int unit_num, int referenced, | |
129 | INT in_ICCi_3, INT in_FCCi_3) | |
130 | { | |
131 | /* Modelling for this unit is the same as for fr500. */ | |
132 | return frvbf_model_fr500_u_check (cpu, idesc, unit_num, referenced, | |
133 | in_ICCi_3, in_FCCi_3); | |
134 | } | |
135 | ||
136 | int | |
137 | frvbf_model_fr450_u_set_hilo (SIM_CPU *cpu, const IDESC *idesc, | |
138 | int unit_num, int referenced, | |
139 | INT out_GRkhi, INT out_GRklo) | |
140 | { | |
141 | /* Modelling for this unit is the same as for fr500. */ | |
142 | return frvbf_model_fr500_u_set_hilo (cpu, idesc, unit_num, referenced, | |
143 | out_GRkhi, out_GRklo); | |
144 | } | |
145 | ||
146 | int | |
147 | frvbf_model_fr450_u_gr_load (SIM_CPU *cpu, const IDESC *idesc, | |
148 | int unit_num, int referenced, | |
149 | INT in_GRi, INT in_GRj, | |
150 | INT out_GRk, INT out_GRdoublek) | |
151 | { | |
152 | int cycles; | |
153 | ||
154 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
155 | { | |
156 | /* Pass 1 is the same as for fr500. */ | |
157 | return frvbf_model_fr500_u_fr_load (cpu, idesc, unit_num, referenced, | |
158 | in_GRi, in_GRj, out_GRk, | |
159 | out_GRdoublek); | |
160 | } | |
161 | ||
162 | cycles = idesc->timing->units[unit_num].done; | |
163 | ||
164 | /* The latency of GRk for a load will depend on how long it takes to retrieve | |
165 | the the data from the cache or memory. */ | |
166 | update_GR_latency_for_load (cpu, out_GRk, cycles); | |
167 | update_GRdouble_latency_for_load (cpu, out_GRdoublek, cycles); | |
168 | ||
169 | if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) | |
170 | { | |
171 | /* GNER has a latency of 2 cycles. */ | |
172 | update_SPR_latency (cpu, GNER_FOR_GR (out_GRk), cycles + 2); | |
173 | update_SPR_latency (cpu, GNER_FOR_GR (out_GRdoublek), cycles + 2); | |
174 | } | |
175 | ||
176 | return cycles; | |
177 | } | |
178 | ||
179 | int | |
180 | frvbf_model_fr450_u_gr_store (SIM_CPU *cpu, const IDESC *idesc, | |
181 | int unit_num, int referenced, | |
182 | INT in_GRi, INT in_GRj, | |
183 | INT in_GRk, INT in_GRdoublek) | |
184 | { | |
185 | /* Modelling for this unit is the same as for fr500. */ | |
186 | return frvbf_model_fr500_u_gr_store (cpu, idesc, unit_num, referenced, | |
187 | in_GRi, in_GRj, in_GRk, in_GRdoublek); | |
188 | } | |
189 | ||
190 | int | |
191 | frvbf_model_fr450_u_fr_load (SIM_CPU *cpu, const IDESC *idesc, | |
192 | int unit_num, int referenced, | |
193 | INT in_GRi, INT in_GRj, | |
194 | INT out_FRk, INT out_FRdoublek) | |
195 | { | |
196 | /* Modelling for this unit is the same as for fr400. */ | |
197 | return frvbf_model_fr400_u_fr_load (cpu, idesc, unit_num, referenced, | |
198 | in_GRi, in_GRj, out_FRk, out_FRdoublek); | |
199 | } | |
200 | ||
201 | int | |
202 | frvbf_model_fr450_u_fr_store (SIM_CPU *cpu, const IDESC *idesc, | |
203 | int unit_num, int referenced, | |
204 | INT in_GRi, INT in_GRj, | |
205 | INT in_FRk, INT in_FRdoublek) | |
206 | { | |
207 | /* Modelling for this unit is the same as for fr400. */ | |
208 | return frvbf_model_fr400_u_fr_load (cpu, idesc, unit_num, referenced, | |
209 | in_GRi, in_GRj, in_FRk, in_FRdoublek); | |
210 | } | |
211 | ||
212 | int | |
213 | frvbf_model_fr450_u_swap (SIM_CPU *cpu, const IDESC *idesc, | |
214 | int unit_num, int referenced, | |
215 | INT in_GRi, INT in_GRj, INT out_GRk) | |
216 | { | |
217 | /* Modelling for this unit is the same as for fr500. */ | |
218 | return frvbf_model_fr500_u_swap (cpu, idesc, unit_num, referenced, | |
219 | in_GRi, in_GRj, out_GRk); | |
220 | } | |
221 | ||
222 | int | |
223 | frvbf_model_fr450_u_fr2gr (SIM_CPU *cpu, const IDESC *idesc, | |
224 | int unit_num, int referenced, | |
225 | INT in_FRk, INT out_GRj) | |
226 | { | |
227 | int cycles; | |
228 | ||
229 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
230 | { | |
231 | /* Pass 1 is the same as for fr400. */ | |
232 | return frvbf_model_fr500_u_fr2gr (cpu, idesc, unit_num, referenced, | |
233 | in_FRk, out_GRj); | |
234 | } | |
235 | ||
236 | /* The latency of GRj is 1 cycle. */ | |
237 | cycles = idesc->timing->units[unit_num].done; | |
238 | update_GR_latency (cpu, out_GRj, cycles + 1); | |
239 | ||
240 | return cycles; | |
241 | } | |
242 | ||
243 | int | |
244 | frvbf_model_fr450_u_spr2gr (SIM_CPU *cpu, const IDESC *idesc, | |
245 | int unit_num, int referenced, | |
246 | INT in_spr, INT out_GRj) | |
247 | { | |
248 | /* Modelling for this unit is the same as for fr500. */ | |
249 | return frvbf_model_fr500_u_spr2gr (cpu, idesc, unit_num, referenced, | |
250 | in_spr, out_GRj); | |
251 | } | |
252 | ||
253 | int | |
254 | frvbf_model_fr450_u_gr2fr (SIM_CPU *cpu, const IDESC *idesc, | |
255 | int unit_num, int referenced, | |
256 | INT in_GRj, INT out_FRk) | |
257 | { | |
258 | /* Modelling for this unit is the same as for fr400. */ | |
259 | return frvbf_model_fr400_u_gr2fr (cpu, idesc, unit_num, referenced, | |
260 | in_GRj, out_FRk); | |
261 | } | |
262 | ||
263 | int | |
264 | frvbf_model_fr450_u_gr2spr (SIM_CPU *cpu, const IDESC *idesc, | |
265 | int unit_num, int referenced, | |
266 | INT in_GRj, INT out_spr) | |
267 | { | |
268 | /* Modelling for this unit is the same as for fr500. */ | |
269 | return frvbf_model_fr500_u_gr2spr (cpu, idesc, unit_num, referenced, | |
270 | in_GRj, out_spr); | |
271 | } | |
272 | ||
273 | int | |
274 | frvbf_model_fr450_u_media_1 (SIM_CPU *cpu, const IDESC *idesc, | |
275 | int unit_num, int referenced, | |
276 | INT in_FRi, INT in_FRj, | |
277 | INT out_FRk) | |
278 | { | |
279 | /* Modelling for this unit is the same as for fr400. */ | |
280 | return frvbf_model_fr400_u_media_1 (cpu, idesc, unit_num, referenced, | |
281 | in_FRi, in_FRj, out_FRk); | |
282 | } | |
283 | ||
284 | int | |
285 | frvbf_model_fr450_u_media_1_quad (SIM_CPU *cpu, const IDESC *idesc, | |
286 | int unit_num, int referenced, | |
287 | INT in_FRi, INT in_FRj, | |
288 | INT out_FRk) | |
289 | { | |
290 | /* Modelling for this unit is the same as for fr400. */ | |
291 | return frvbf_model_fr400_u_media_1_quad (cpu, idesc, unit_num, referenced, | |
292 | in_FRi, in_FRj, out_FRk); | |
293 | } | |
294 | ||
295 | int | |
296 | frvbf_model_fr450_u_media_hilo (SIM_CPU *cpu, const IDESC *idesc, | |
297 | int unit_num, int referenced, | |
298 | INT out_FRkhi, INT out_FRklo) | |
299 | { | |
300 | /* Modelling for this unit is the same as for fr400. */ | |
301 | return frvbf_model_fr400_u_media_hilo (cpu, idesc, unit_num, referenced, | |
302 | out_FRkhi, out_FRklo); | |
303 | } | |
304 | ||
305 | int | |
306 | frvbf_model_fr450_u_media_2 (SIM_CPU *cpu, const IDESC *idesc, | |
307 | int unit_num, int referenced, | |
308 | INT in_FRi, INT in_FRj, | |
309 | INT out_ACC40Sk, INT out_ACC40Uk) | |
310 | { | |
311 | /* Modelling for this unit is the same as for fr400. */ | |
312 | return frvbf_model_fr400_u_media_2 (cpu, idesc, unit_num, referenced, | |
313 | in_FRi, in_FRj, out_ACC40Sk, | |
314 | out_ACC40Uk); | |
315 | } | |
316 | ||
317 | int | |
318 | frvbf_model_fr450_u_media_2_quad (SIM_CPU *cpu, const IDESC *idesc, | |
319 | int unit_num, int referenced, | |
320 | INT in_FRi, INT in_FRj, | |
321 | INT out_ACC40Sk, INT out_ACC40Uk) | |
322 | { | |
323 | /* Modelling for this unit is the same as for fr400. */ | |
324 | return frvbf_model_fr400_u_media_2_quad (cpu, idesc, unit_num, referenced, | |
325 | in_FRi, in_FRj, out_ACC40Sk, | |
326 | out_ACC40Uk); | |
327 | } | |
328 | ||
329 | int | |
330 | frvbf_model_fr450_u_media_2_acc (SIM_CPU *cpu, const IDESC *idesc, | |
331 | int unit_num, int referenced, | |
332 | INT in_ACC40Si, INT out_ACC40Sk) | |
333 | { | |
334 | /* Modelling for this unit is the same as for fr400. */ | |
335 | return frvbf_model_fr400_u_media_2_acc (cpu, idesc, unit_num, referenced, | |
336 | in_ACC40Si, out_ACC40Sk); | |
337 | } | |
338 | ||
339 | int | |
340 | frvbf_model_fr450_u_media_2_acc_dual (SIM_CPU *cpu, const IDESC *idesc, | |
341 | int unit_num, int referenced, | |
342 | INT in_ACC40Si, INT out_ACC40Sk) | |
343 | { | |
344 | /* Modelling for this unit is the same as for fr400. */ | |
345 | return frvbf_model_fr400_u_media_2_acc_dual (cpu, idesc, unit_num, | |
346 | referenced, in_ACC40Si, | |
347 | out_ACC40Sk); | |
348 | } | |
349 | ||
350 | int | |
351 | frvbf_model_fr450_u_media_2_add_sub (SIM_CPU *cpu, const IDESC *idesc, | |
352 | int unit_num, int referenced, | |
353 | INT in_ACC40Si, INT out_ACC40Sk) | |
354 | { | |
355 | /* Modelling for this unit is the same as for fr400. */ | |
356 | return frvbf_model_fr400_u_media_2_add_sub (cpu, idesc, unit_num, | |
357 | referenced, in_ACC40Si, | |
358 | out_ACC40Sk); | |
359 | } | |
360 | ||
361 | int | |
362 | frvbf_model_fr450_u_media_2_add_sub_dual (SIM_CPU *cpu, const IDESC *idesc, | |
363 | int unit_num, int referenced, | |
364 | INT in_ACC40Si, INT out_ACC40Sk) | |
365 | { | |
366 | /* Modelling for this unit is the same as for fr400. */ | |
367 | return frvbf_model_fr400_u_media_2_add_sub_dual (cpu, idesc, unit_num, | |
368 | referenced, in_ACC40Si, | |
369 | out_ACC40Sk); | |
370 | } | |
371 | ||
372 | int | |
373 | frvbf_model_fr450_u_media_3 (SIM_CPU *cpu, const IDESC *idesc, | |
374 | int unit_num, int referenced, | |
375 | INT in_FRi, INT in_FRj, | |
376 | INT out_FRk) | |
377 | { | |
378 | /* Modelling is the same as media unit 1. */ | |
379 | return frvbf_model_fr450_u_media_1 (cpu, idesc, unit_num, referenced, | |
380 | in_FRi, in_FRj, out_FRk); | |
381 | } | |
382 | ||
383 | int | |
384 | frvbf_model_fr450_u_media_3_dual (SIM_CPU *cpu, const IDESC *idesc, | |
385 | int unit_num, int referenced, | |
386 | INT in_FRi, INT out_FRk) | |
387 | { | |
388 | /* Modelling for this unit is the same as for fr400. */ | |
389 | return frvbf_model_fr400_u_media_3_dual (cpu, idesc, unit_num, referenced, | |
390 | in_FRi, out_FRk); | |
391 | } | |
392 | ||
393 | int | |
394 | frvbf_model_fr450_u_media_3_quad (SIM_CPU *cpu, const IDESC *idesc, | |
395 | int unit_num, int referenced, | |
396 | INT in_FRi, INT in_FRj, | |
397 | INT out_FRk) | |
398 | { | |
399 | /* Modelling is the same as media unit 1. */ | |
400 | return frvbf_model_fr450_u_media_1_quad (cpu, idesc, unit_num, referenced, | |
401 | in_FRi, in_FRj, out_FRk); | |
402 | } | |
403 | ||
404 | int | |
405 | frvbf_model_fr450_u_media_4 (SIM_CPU *cpu, const IDESC *idesc, | |
406 | int unit_num, int referenced, | |
407 | INT in_ACC40Si, INT in_FRj, | |
408 | INT out_ACC40Sk, INT out_FRk) | |
409 | { | |
410 | /* Modelling for this unit is the same as for fr400. */ | |
411 | return frvbf_model_fr400_u_media_4 (cpu, idesc, unit_num, referenced, | |
412 | in_ACC40Si, in_FRj, | |
413 | out_ACC40Sk, out_FRk); | |
414 | } | |
415 | ||
416 | int | |
417 | frvbf_model_fr450_u_media_4_accg (SIM_CPU *cpu, const IDESC *idesc, | |
418 | int unit_num, int referenced, | |
419 | INT in_ACCGi, INT in_FRinti, | |
420 | INT out_ACCGk, INT out_FRintk) | |
421 | { | |
422 | /* Modelling is the same as media-4 unit except use accumulator guards | |
423 | as input instead of accumulators. */ | |
424 | return frvbf_model_fr450_u_media_4 (cpu, idesc, unit_num, referenced, | |
425 | in_ACCGi, in_FRinti, | |
426 | out_ACCGk, out_FRintk); | |
427 | } | |
428 | ||
429 | int | |
430 | frvbf_model_fr450_u_media_4_acc_dual (SIM_CPU *cpu, const IDESC *idesc, | |
431 | int unit_num, int referenced, | |
432 | INT in_ACC40Si, INT out_FRk) | |
433 | { | |
434 | /* Modelling for this unit is the same as for fr400. */ | |
435 | return frvbf_model_fr400_u_media_4_acc_dual (cpu, idesc, unit_num, | |
436 | referenced, in_ACC40Si, | |
437 | out_FRk); | |
438 | } | |
439 | ||
440 | int | |
441 | frvbf_model_fr450_u_media_4_mclracca (SIM_CPU *cpu, const IDESC *idesc, | |
442 | int unit_num, int referenced) | |
443 | { | |
444 | int cycles; | |
445 | int acc; | |
446 | FRV_PROFILE_STATE *ps; | |
447 | ||
448 | if (model_insn == FRV_INSN_MODEL_PASS_1) | |
449 | return 0; | |
450 | ||
451 | /* The preprocessing can execute right away. */ | |
452 | cycles = idesc->timing->units[unit_num].done; | |
453 | ||
454 | ps = CPU_PROFILE_STATE (cpu); | |
455 | ||
456 | /* The post processing must wait for any pending ACC writes. */ | |
457 | ps->post_wait = cycles; | |
458 | for (acc = 0; acc < 4; acc++) | |
459 | post_wait_for_ACC (cpu, acc); | |
460 | for (acc = 8; acc < 12; acc++) | |
461 | post_wait_for_ACC (cpu, acc); | |
462 | ||
463 | for (acc = 0; acc < 4; acc++) | |
464 | { | |
465 | update_ACC_latency (cpu, acc, ps->post_wait); | |
466 | update_ACC_ptime (cpu, acc, 2); | |
467 | } | |
468 | for (acc = 8; acc < 12; acc++) | |
469 | { | |
470 | update_ACC_latency (cpu, acc, ps->post_wait); | |
471 | update_ACC_ptime (cpu, acc, 2); | |
472 | } | |
473 | ||
474 | return cycles; | |
475 | } | |
476 | ||
477 | int | |
478 | frvbf_model_fr450_u_media_6 (SIM_CPU *cpu, const IDESC *idesc, | |
479 | int unit_num, int referenced, | |
480 | INT in_FRi, INT out_FRk) | |
481 | { | |
482 | /* Modelling for this unit is the same as for fr400. */ | |
483 | return frvbf_model_fr400_u_media_6 (cpu, idesc, unit_num, referenced, | |
484 | in_FRi, out_FRk); | |
485 | } | |
486 | ||
487 | int | |
488 | frvbf_model_fr450_u_media_7 (SIM_CPU *cpu, const IDESC *idesc, | |
489 | int unit_num, int referenced, | |
490 | INT in_FRinti, INT in_FRintj, | |
491 | INT out_FCCk) | |
492 | { | |
493 | /* Modelling for this unit is the same as for fr400. */ | |
494 | return frvbf_model_fr400_u_media_7 (cpu, idesc, unit_num, referenced, | |
495 | in_FRinti, in_FRintj, out_FCCk); | |
496 | } | |
497 | ||
498 | int | |
499 | frvbf_model_fr450_u_media_dual_expand (SIM_CPU *cpu, const IDESC *idesc, | |
500 | int unit_num, int referenced, | |
501 | INT in_FRi, | |
502 | INT out_FRk) | |
503 | { | |
504 | /* Modelling for this unit is the same as for fr400. */ | |
505 | return frvbf_model_fr400_u_media_dual_expand (cpu, idesc, unit_num, | |
506 | referenced, in_FRi, out_FRk); | |
507 | } | |
508 | ||
509 | int | |
510 | frvbf_model_fr450_u_media_dual_htob (SIM_CPU *cpu, const IDESC *idesc, | |
511 | int unit_num, int referenced, | |
512 | INT in_FRj, | |
513 | INT out_FRk) | |
514 | { | |
515 | /* Modelling for this unit is the same as for fr400. */ | |
516 | return frvbf_model_fr400_u_media_dual_htob (cpu, idesc, unit_num, | |
517 | referenced, in_FRj, out_FRk); | |
518 | } | |
519 | ||
520 | int | |
521 | frvbf_model_fr450_u_ici (SIM_CPU *cpu, const IDESC *idesc, | |
522 | int unit_num, int referenced, | |
523 | INT in_GRi, INT in_GRj) | |
524 | { | |
525 | /* Modelling for this unit is the same as for fr500. */ | |
526 | return frvbf_model_fr500_u_ici (cpu, idesc, unit_num, referenced, | |
527 | in_GRi, in_GRj); | |
528 | } | |
529 | ||
530 | int | |
531 | frvbf_model_fr450_u_dci (SIM_CPU *cpu, const IDESC *idesc, | |
532 | int unit_num, int referenced, | |
533 | INT in_GRi, INT in_GRj) | |
534 | { | |
535 | /* Modelling for this unit is the same as for fr500. */ | |
536 | return frvbf_model_fr500_u_dci (cpu, idesc, unit_num, referenced, | |
537 | in_GRi, in_GRj); | |
538 | } | |
539 | ||
540 | int | |
541 | frvbf_model_fr450_u_dcf (SIM_CPU *cpu, const IDESC *idesc, | |
542 | int unit_num, int referenced, | |
543 | INT in_GRi, INT in_GRj) | |
544 | { | |
545 | /* Modelling for this unit is the same as for fr500. */ | |
546 | return frvbf_model_fr500_u_dcf (cpu, idesc, unit_num, referenced, | |
547 | in_GRi, in_GRj); | |
548 | } | |
549 | ||
550 | int | |
551 | frvbf_model_fr450_u_icpl (SIM_CPU *cpu, const IDESC *idesc, | |
552 | int unit_num, int referenced, | |
553 | INT in_GRi, INT in_GRj) | |
554 | { | |
555 | /* Modelling for this unit is the same as for fr500. */ | |
556 | return frvbf_model_fr500_u_icpl (cpu, idesc, unit_num, referenced, | |
557 | in_GRi, in_GRj); | |
558 | } | |
559 | ||
560 | int | |
561 | frvbf_model_fr450_u_dcpl (SIM_CPU *cpu, const IDESC *idesc, | |
562 | int unit_num, int referenced, | |
563 | INT in_GRi, INT in_GRj) | |
564 | { | |
565 | /* Modelling for this unit is the same as for fr500. */ | |
566 | return frvbf_model_fr500_u_dcpl (cpu, idesc, unit_num, referenced, | |
567 | in_GRi, in_GRj); | |
568 | } | |
569 | ||
570 | int | |
571 | frvbf_model_fr450_u_icul (SIM_CPU *cpu, const IDESC *idesc, | |
572 | int unit_num, int referenced, | |
573 | INT in_GRi, INT in_GRj) | |
574 | { | |
575 | /* Modelling for this unit is the same as for fr500. */ | |
576 | return frvbf_model_fr500_u_icul (cpu, idesc, unit_num, referenced, | |
577 | in_GRi, in_GRj); | |
578 | } | |
579 | ||
580 | int | |
581 | frvbf_model_fr450_u_dcul (SIM_CPU *cpu, const IDESC *idesc, | |
582 | int unit_num, int referenced, | |
583 | INT in_GRi, INT in_GRj) | |
584 | { | |
585 | /* Modelling for this unit is the same as for fr500. */ | |
586 | return frvbf_model_fr500_u_dcul (cpu, idesc, unit_num, referenced, | |
587 | in_GRi, in_GRj); | |
588 | } | |
589 | ||
590 | int | |
591 | frvbf_model_fr450_u_barrier (SIM_CPU *cpu, const IDESC *idesc, | |
592 | int unit_num, int referenced) | |
593 | { | |
594 | /* Modelling for this unit is the same as for fr500. */ | |
595 | return frvbf_model_fr500_u_barrier (cpu, idesc, unit_num, referenced); | |
596 | } | |
597 | ||
598 | int | |
599 | frvbf_model_fr450_u_membar (SIM_CPU *cpu, const IDESC *idesc, | |
600 | int unit_num, int referenced) | |
601 | { | |
602 | /* Modelling for this unit is the same as for fr500. */ | |
603 | return frvbf_model_fr500_u_membar (cpu, idesc, unit_num, referenced); | |
604 | } | |
605 | ||
606 | #endif /* WITH_PROFILE_MODEL_P */ |