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1 | /* frv simulator support code |
2 | Copyright (C) 1999, 2000, 2001 Free Software Foundation, Inc. | |
3 | Contributed by Red Hat. | |
4 | ||
5 | This file is part of the GNU simulators. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License along | |
18 | with this program; if not, write to the Free Software Foundation, Inc., | |
19 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ | |
20 | ||
21 | #define WANT_CPU | |
22 | #define WANT_CPU_FRVBF | |
23 | ||
24 | #include "sim-main.h" | |
25 | #include "bfd.h" | |
26 | ||
27 | /* Initialize the frv simulator. */ | |
28 | void | |
29 | frv_initialize (SIM_CPU *current_cpu, SIM_DESC sd) | |
30 | { | |
31 | FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (current_cpu); | |
32 | PROFILE_DATA *p = CPU_PROFILE_DATA (current_cpu); | |
33 | FRV_CACHE *insn_cache = CPU_INSN_CACHE (current_cpu); | |
34 | FRV_CACHE *data_cache = CPU_DATA_CACHE (current_cpu); | |
35 | int insn_cache_enabled = CACHE_INITIALIZED (insn_cache); | |
36 | int data_cache_enabled = CACHE_INITIALIZED (data_cache); | |
37 | USI hsr0; | |
38 | ||
39 | /* We need to ensure that the caches are initialized even if they are not | |
40 | initially enabled (via commandline) because they can be enabled by | |
41 | software. */ | |
42 | if (! insn_cache_enabled) | |
43 | frv_cache_init (current_cpu, CPU_INSN_CACHE (current_cpu)); | |
44 | if (! data_cache_enabled) | |
45 | frv_cache_init (current_cpu, CPU_DATA_CACHE (current_cpu)); | |
46 | ||
47 | /* Set the default cpu frequency if it has not been set on the command | |
48 | line. */ | |
49 | if (PROFILE_CPU_FREQ (p) == 0) | |
50 | PROFILE_CPU_FREQ (p) = 266000000; /* 266MHz */ | |
51 | ||
52 | /* Allocate one cache line of memory containing the address of the reset | |
53 | register Use the largest of the insn cache line size and the data cache | |
54 | line size. */ | |
55 | { | |
56 | int addr = RSTR_ADDRESS; | |
57 | void *aligned_buffer; | |
58 | int bytes; | |
59 | ||
60 | if (CPU_INSN_CACHE (current_cpu)->line_size | |
61 | > CPU_DATA_CACHE (current_cpu)->line_size) | |
62 | bytes = CPU_INSN_CACHE (current_cpu)->line_size; | |
63 | else | |
64 | bytes = CPU_DATA_CACHE (current_cpu)->line_size; | |
65 | ||
66 | /* 'bytes' is a power of 2. Calculate the starting address of the | |
67 | cache line. */ | |
68 | addr &= ~(bytes - 1); | |
69 | aligned_buffer = zalloc (bytes); /* clear */ | |
70 | sim_core_attach (sd, NULL, 0, access_read_write, 0, addr, bytes, | |
71 | 0, NULL, aligned_buffer); | |
72 | } | |
73 | ||
74 | PROFILE_INFO_CPU_CALLBACK(p) = frv_profile_info; | |
75 | ps->insn_fetch_address = -1; | |
76 | ps->branch_address = -1; | |
77 | ||
78 | cgen_init_accurate_fpu (current_cpu, CGEN_CPU_FPU (current_cpu), | |
79 | frvbf_fpu_error); | |
80 | ||
81 | /* Initialize the register control information. */ | |
82 | frv_register_control_init (current_cpu); | |
83 | ||
84 | /* Now perform power-on reset. */ | |
85 | frv_power_on_reset (current_cpu); | |
86 | ||
87 | /* Make sure that HSR0.ICE and HSR0.DCE are set properly. */ | |
88 | hsr0 = GET_HSR0 (); | |
89 | if (insn_cache_enabled) | |
90 | SET_HSR0_ICE (hsr0); | |
91 | else | |
92 | CLEAR_HSR0_ICE (hsr0); | |
93 | if (data_cache_enabled) | |
94 | SET_HSR0_DCE (hsr0); | |
95 | else | |
96 | CLEAR_HSR0_DCE (hsr0); | |
97 | SET_HSR0 (hsr0); | |
98 | } | |
99 | ||
100 | /* Initialize the frv simulator. */ | |
101 | void | |
102 | frv_term (SIM_DESC sd) | |
103 | { | |
104 | /* If the timer is enabled, and model profiling was not originally enabled, | |
105 | then turn it off again. This is the only place we can currently gain | |
106 | control to do this. */ | |
107 | if (frv_interrupt_state.timer.enabled && ! frv_save_profile_model_p) | |
108 | sim_profile_set_option (current_state, "-model", PROFILE_MODEL_IDX, "0"); | |
109 | } | |
110 | ||
111 | /* Perform a power on reset. */ | |
112 | void | |
113 | frv_power_on_reset (SIM_CPU *cpu) | |
114 | { | |
115 | /* GR, FR and CPR registers are undefined at initialization time. */ | |
116 | frv_initialize_spr (cpu); | |
117 | /* Initialize the RSTR register (in memory). */ | |
118 | if (frv_cache_enabled (CPU_DATA_CACHE (cpu))) | |
119 | frvbf_mem_set_SI (cpu, CPU_PC_GET (cpu), RSTR_ADDRESS, RSTR_INITIAL_VALUE); | |
120 | else | |
121 | SETMEMSI (cpu, CPU_PC_GET (cpu), RSTR_ADDRESS, RSTR_INITIAL_VALUE); | |
122 | } | |
123 | ||
124 | /* Perform a hardware reset. */ | |
125 | void | |
126 | frv_hardware_reset (SIM_CPU *cpu) | |
127 | { | |
128 | /* GR, FR and CPR registers are undefined at hardware reset. */ | |
129 | frv_initialize_spr (cpu); | |
130 | /* Reset the RSTR register (in memory). */ | |
131 | if (frv_cache_enabled (CPU_DATA_CACHE (cpu))) | |
132 | frvbf_mem_set_SI (cpu, CPU_PC_GET (cpu), RSTR_ADDRESS, RSTR_HARDWARE_RESET); | |
133 | else | |
134 | SETMEMSI (cpu, CPU_PC_GET (cpu), RSTR_ADDRESS, RSTR_HARDWARE_RESET); | |
135 | /* Reset the insn and data caches. */ | |
136 | frv_cache_invalidate_all (CPU_INSN_CACHE (cpu), 0/* no flush */); | |
137 | frv_cache_invalidate_all (CPU_DATA_CACHE (cpu), 0/* no flush */); | |
138 | } | |
139 | ||
140 | /* Perform a software reset. */ | |
141 | void | |
142 | frv_software_reset (SIM_CPU *cpu) | |
143 | { | |
144 | /* GR, FR and CPR registers are undefined at software reset. */ | |
145 | frv_reset_spr (cpu); | |
146 | /* Reset the RSTR register (in memory). */ | |
147 | if (frv_cache_enabled (CPU_DATA_CACHE (cpu))) | |
148 | frvbf_mem_set_SI (cpu, CPU_PC_GET (cpu), RSTR_ADDRESS, RSTR_SOFTWARE_RESET); | |
149 | else | |
150 | SETMEMSI (cpu, CPU_PC_GET (cpu), RSTR_ADDRESS, RSTR_SOFTWARE_RESET); | |
151 | } |