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b34f6357 | 1 | /* frv trap support |
ecd75fc8 | 2 | Copyright (C) 1999-2014 Free Software Foundation, Inc. |
b34f6357 DB |
3 | Contributed by Red Hat. |
4 | ||
5 | This file is part of the GNU simulators. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
4744ac1b JB |
9 | the Free Software Foundation; either version 3 of the License, or |
10 | (at your option) any later version. | |
b34f6357 DB |
11 | |
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
4744ac1b JB |
17 | You should have received a copy of the GNU General Public License |
18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
b34f6357 DB |
19 | |
20 | #define WANT_CPU frvbf | |
21 | #define WANT_CPU_FRVBF | |
22 | ||
23 | #include "sim-main.h" | |
24 | #include "targ-vals.h" | |
25 | #include "cgen-engine.h" | |
26 | #include "cgen-par.h" | |
27 | #include "sim-fpu.h" | |
28 | ||
29 | #include "bfd.h" | |
30 | #include "libiberty.h" | |
31 | ||
79e59fe6 | 32 | CGEN_ATTR_VALUE_ENUM_TYPE frv_current_fm_slot; |
e930b1f5 | 33 | |
b34f6357 DB |
34 | /* The semantic code invokes this for invalid (unrecognized) instructions. */ |
35 | ||
36 | SEM_PC | |
37 | sim_engine_invalid_insn (SIM_CPU *current_cpu, IADDR cia, SEM_PC vpc) | |
38 | { | |
39 | frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION); | |
40 | return vpc; | |
41 | } | |
42 | ||
43 | /* Process an address exception. */ | |
44 | ||
45 | void | |
46 | frv_core_signal (SIM_DESC sd, SIM_CPU *current_cpu, sim_cia cia, | |
47 | unsigned int map, int nr_bytes, address_word addr, | |
48 | transfer_type transfer, sim_core_signals sig) | |
49 | { | |
50 | if (sig == sim_core_unaligned_signal) | |
51 | { | |
676a64f4 RS |
52 | if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400 |
53 | || STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr450) | |
b34f6357 DB |
54 | frv_queue_data_access_error_interrupt (current_cpu, addr); |
55 | else | |
56 | frv_queue_mem_address_not_aligned_interrupt (current_cpu, addr); | |
57 | } | |
58 | ||
59 | frv_term (sd); | |
60 | sim_core_signal (sd, current_cpu, cia, map, nr_bytes, addr, transfer, sig); | |
61 | } | |
62 | ||
63 | void | |
64 | frv_sim_engine_halt_hook (SIM_DESC sd, SIM_CPU *current_cpu, sim_cia cia) | |
65 | { | |
66 | int i; | |
67 | if (current_cpu != NULL) | |
68 | CIA_SET (current_cpu, cia); | |
69 | ||
70 | /* Invalidate the insn and data caches of all cpus. */ | |
71 | for (i = 0; i < MAX_NR_PROCESSORS; ++i) | |
72 | { | |
73 | current_cpu = STATE_CPU (sd, i); | |
74 | frv_cache_invalidate_all (CPU_INSN_CACHE (current_cpu), 0); | |
75 | frv_cache_invalidate_all (CPU_DATA_CACHE (current_cpu), 1); | |
76 | } | |
77 | frv_term (sd); | |
78 | } | |
79 | \f | |
80 | /* Read/write functions for system call interface. */ | |
81 | ||
82 | static int | |
83 | syscall_read_mem (host_callback *cb, struct cb_syscall *sc, | |
84 | unsigned long taddr, char *buf, int bytes) | |
85 | { | |
86 | SIM_DESC sd = (SIM_DESC) sc->p1; | |
87 | SIM_CPU *cpu = (SIM_CPU *) sc->p2; | |
88 | ||
89 | frv_cache_invalidate_all (CPU_DATA_CACHE (cpu), 1); | |
90 | return sim_core_read_buffer (sd, cpu, read_map, buf, taddr, bytes); | |
91 | } | |
92 | ||
93 | static int | |
94 | syscall_write_mem (host_callback *cb, struct cb_syscall *sc, | |
95 | unsigned long taddr, const char *buf, int bytes) | |
96 | { | |
97 | SIM_DESC sd = (SIM_DESC) sc->p1; | |
98 | SIM_CPU *cpu = (SIM_CPU *) sc->p2; | |
99 | ||
100 | frv_cache_invalidate_all (CPU_INSN_CACHE (cpu), 0); | |
101 | frv_cache_invalidate_all (CPU_DATA_CACHE (cpu), 1); | |
102 | return sim_core_write_buffer (sd, cpu, write_map, buf, taddr, bytes); | |
103 | } | |
104 | ||
105 | /* Handle TRA and TIRA insns. */ | |
106 | void | |
107 | frv_itrap (SIM_CPU *current_cpu, PCADDR pc, USI base, SI offset) | |
108 | { | |
109 | SIM_DESC sd = CPU_STATE (current_cpu); | |
110 | host_callback *cb = STATE_CALLBACK (sd); | |
111 | USI num = ((base + offset) & 0x7f) + 0x80; | |
112 | ||
113 | #ifdef SIM_HAVE_BREAKPOINTS | |
114 | /* Check for breakpoints "owned" by the simulator first, regardless | |
115 | of --environment. */ | |
116 | if (num == TRAP_BREAKPOINT) | |
117 | { | |
118 | /* First try sim-break.c. If it's a breakpoint the simulator "owns" | |
119 | it doesn't return. Otherwise it returns and let's us try. */ | |
120 | sim_handle_breakpoint (sd, current_cpu, pc); | |
121 | /* Fall through. */ | |
122 | } | |
123 | #endif | |
124 | ||
125 | if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT) | |
126 | { | |
127 | frv_queue_software_interrupt (current_cpu, num); | |
128 | return; | |
129 | } | |
130 | ||
131 | switch (num) | |
132 | { | |
133 | case TRAP_SYSCALL : | |
134 | { | |
135 | CB_SYSCALL s; | |
136 | CB_SYSCALL_INIT (&s); | |
137 | s.func = GET_H_GR (7); | |
138 | s.arg1 = GET_H_GR (8); | |
139 | s.arg2 = GET_H_GR (9); | |
140 | s.arg3 = GET_H_GR (10); | |
141 | ||
142 | if (s.func == TARGET_SYS_exit) | |
143 | { | |
144 | sim_engine_halt (sd, current_cpu, NULL, pc, sim_exited, s.arg1); | |
145 | } | |
146 | ||
147 | s.p1 = (PTR) sd; | |
148 | s.p2 = (PTR) current_cpu; | |
149 | s.read_mem = syscall_read_mem; | |
150 | s.write_mem = syscall_write_mem; | |
151 | cb_syscall (cb, &s); | |
152 | SET_H_GR (8, s.result); | |
153 | SET_H_GR (9, s.result2); | |
154 | SET_H_GR (10, s.errcode); | |
155 | break; | |
156 | } | |
157 | ||
158 | case TRAP_BREAKPOINT: | |
159 | sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGTRAP); | |
160 | break; | |
161 | ||
162 | /* Add support for dumping registers, either at fixed traps, or all | |
163 | unknown traps if configured with --enable-sim-trapdump. */ | |
164 | default: | |
165 | #if !TRAPDUMP | |
166 | frv_queue_software_interrupt (current_cpu, num); | |
167 | return; | |
168 | #endif | |
169 | ||
170 | #ifdef TRAP_REGDUMP1 | |
171 | case TRAP_REGDUMP1: | |
172 | #endif | |
173 | ||
174 | #ifdef TRAP_REGDUMP2 | |
175 | case TRAP_REGDUMP2: | |
176 | #endif | |
177 | ||
178 | #if TRAPDUMP || (defined (TRAP_REGDUMP1)) || (defined (TRAP_REGDUMP2)) | |
179 | { | |
180 | char buf[256]; | |
181 | int i, j; | |
182 | ||
183 | buf[0] = 0; | |
184 | if (STATE_TEXT_SECTION (sd) | |
185 | && pc >= STATE_TEXT_START (sd) | |
186 | && pc < STATE_TEXT_END (sd)) | |
187 | { | |
188 | const char *pc_filename = (const char *)0; | |
189 | const char *pc_function = (const char *)0; | |
190 | unsigned int pc_linenum = 0; | |
191 | ||
192 | if (bfd_find_nearest_line (STATE_PROG_BFD (sd), | |
193 | STATE_TEXT_SECTION (sd), | |
fc0a2244 | 194 | (struct bfd_symbol **) 0, |
b34f6357 DB |
195 | pc - STATE_TEXT_START (sd), |
196 | &pc_filename, &pc_function, &pc_linenum) | |
197 | && (pc_function || pc_filename)) | |
198 | { | |
199 | char *p = buf+2; | |
200 | buf[0] = ' '; | |
201 | buf[1] = '('; | |
202 | if (pc_function) | |
203 | { | |
204 | strcpy (p, pc_function); | |
205 | p += strlen (p); | |
206 | } | |
207 | else | |
208 | { | |
209 | char *q = (char *) strrchr (pc_filename, '/'); | |
210 | strcpy (p, (q) ? q+1 : pc_filename); | |
211 | p += strlen (p); | |
212 | } | |
213 | ||
214 | if (pc_linenum) | |
215 | { | |
216 | sprintf (p, " line %d", pc_linenum); | |
217 | p += strlen (p); | |
218 | } | |
219 | ||
220 | p[0] = ')'; | |
221 | p[1] = '\0'; | |
222 | if ((p+1) - buf > sizeof (buf)) | |
223 | abort (); | |
224 | } | |
225 | } | |
226 | ||
227 | sim_io_printf (sd, | |
228 | "\nRegister dump, pc = 0x%.8x%s, base = %u, offset = %d\n", | |
229 | (unsigned)pc, buf, (unsigned)base, (int)offset); | |
230 | ||
231 | for (i = 0; i < 64; i += 8) | |
232 | { | |
233 | long g0 = (long)GET_H_GR (i); | |
234 | long g1 = (long)GET_H_GR (i+1); | |
235 | long g2 = (long)GET_H_GR (i+2); | |
236 | long g3 = (long)GET_H_GR (i+3); | |
237 | long g4 = (long)GET_H_GR (i+4); | |
238 | long g5 = (long)GET_H_GR (i+5); | |
239 | long g6 = (long)GET_H_GR (i+6); | |
240 | long g7 = (long)GET_H_GR (i+7); | |
241 | ||
242 | if ((g0 | g1 | g2 | g3 | g4 | g5 | g6 | g7) != 0) | |
243 | sim_io_printf (sd, | |
244 | "\tgr%02d - gr%02d: 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx\n", | |
245 | i, i+7, g0, g1, g2, g3, g4, g5, g6, g7); | |
246 | } | |
247 | ||
248 | for (i = 0; i < 64; i += 8) | |
249 | { | |
250 | long f0 = (long)GET_H_FR (i); | |
251 | long f1 = (long)GET_H_FR (i+1); | |
252 | long f2 = (long)GET_H_FR (i+2); | |
253 | long f3 = (long)GET_H_FR (i+3); | |
254 | long f4 = (long)GET_H_FR (i+4); | |
255 | long f5 = (long)GET_H_FR (i+5); | |
256 | long f6 = (long)GET_H_FR (i+6); | |
257 | long f7 = (long)GET_H_FR (i+7); | |
258 | ||
259 | if ((f0 | f1 | f2 | f3 | f4 | f5 | f6 | f7) != 0) | |
260 | sim_io_printf (sd, | |
261 | "\tfr%02d - fr%02d: 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx\n", | |
262 | i, i+7, f0, f1, f2, f3, f4, f5, f6, f7); | |
263 | } | |
264 | ||
265 | sim_io_printf (sd, | |
266 | "\tlr/lcr/cc/ccc: 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx\n", | |
267 | (long)GET_H_SPR (272), | |
268 | (long)GET_H_SPR (273), | |
269 | (long)GET_H_SPR (256), | |
270 | (long)GET_H_SPR (263)); | |
271 | } | |
272 | break; | |
273 | #endif | |
274 | } | |
275 | } | |
276 | ||
277 | /* Handle the MTRAP insn. */ | |
278 | void | |
279 | frv_mtrap (SIM_CPU *current_cpu) | |
280 | { | |
e930b1f5 DB |
281 | SIM_DESC sd = CPU_STATE (current_cpu); |
282 | ||
b34f6357 DB |
283 | /* Check the status of media exceptions in MSR0. */ |
284 | SI msr = GET_MSR (0); | |
e930b1f5 | 285 | if (GET_MSR_AOVF (msr) || GET_MSR_MTT (msr) && STATE_ARCHITECTURE (sd)->mach != bfd_mach_fr550) |
b34f6357 DB |
286 | frv_queue_program_interrupt (current_cpu, FRV_MP_EXCEPTION); |
287 | } | |
288 | ||
289 | /* Handle the BREAK insn. */ | |
290 | void | |
291 | frv_break (SIM_CPU *current_cpu) | |
292 | { | |
293 | IADDR pc; | |
294 | SIM_DESC sd = CPU_STATE (current_cpu); | |
295 | ||
296 | #ifdef SIM_HAVE_BREAKPOINTS | |
297 | /* First try sim-break.c. If it's a breakpoint the simulator "owns" | |
298 | it doesn't return. Otherwise it returns and let's us try. */ | |
299 | pc = GET_H_PC (); | |
300 | sim_handle_breakpoint (sd, current_cpu, pc); | |
301 | /* Fall through. */ | |
302 | #endif | |
303 | ||
304 | if (STATE_ENVIRONMENT (sd) != OPERATING_ENVIRONMENT) | |
305 | { | |
306 | /* Invalidate the insn cache because the debugger will presumably | |
307 | replace the breakpoint insn with the real one. */ | |
308 | #ifndef SIM_HAVE_BREAKPOINTS | |
309 | pc = GET_H_PC (); | |
310 | #endif | |
311 | sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGTRAP); | |
312 | } | |
313 | ||
314 | frv_queue_break_interrupt (current_cpu); | |
315 | } | |
316 | ||
317 | /* Return from trap. */ | |
318 | USI | |
319 | frv_rett (SIM_CPU *current_cpu, PCADDR pc, BI debug_field) | |
320 | { | |
321 | USI new_pc; | |
322 | /* if (normal running mode and debug_field==0 | |
323 | PC=PCSR | |
324 | PSR.ET=1 | |
325 | PSR.S=PSR.PS | |
326 | else if (debug running mode and debug_field==1) | |
327 | PC=(BPCSR) | |
328 | PSR.ET=BPSR.BET | |
329 | PSR.S=BPSR.BS | |
330 | change to normal running mode | |
331 | */ | |
332 | int psr_s = GET_H_PSR_S (); | |
333 | int psr_et = GET_H_PSR_ET (); | |
334 | ||
335 | /* Check for exceptions in the priority order listed in the FRV Architecture | |
336 | Volume 2. */ | |
337 | if (! psr_s) | |
338 | { | |
339 | /* Halt if PSR.ET is not set. See chapter 6 of the LSI. */ | |
340 | if (! psr_et) | |
341 | { | |
342 | SIM_DESC sd = CPU_STATE (current_cpu); | |
343 | sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGTRAP); | |
344 | } | |
345 | ||
346 | /* privileged_instruction interrupt will have already been queued by | |
347 | frv_detect_insn_access_interrupts. */ | |
348 | new_pc = pc + 4; | |
349 | } | |
350 | else if (psr_et) | |
351 | { | |
352 | /* Halt if PSR.S is set. See chapter 6 of the LSI. */ | |
353 | if (psr_s) | |
354 | { | |
355 | SIM_DESC sd = CPU_STATE (current_cpu); | |
356 | sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGTRAP); | |
357 | } | |
358 | ||
359 | frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION); | |
360 | new_pc = pc + 4; | |
361 | } | |
362 | else if (! CPU_DEBUG_STATE (current_cpu) && debug_field == 0) | |
363 | { | |
364 | USI psr = GET_PSR (); | |
365 | /* Return from normal running state. */ | |
366 | new_pc = GET_H_SPR (H_SPR_PCSR); | |
367 | SET_PSR_ET (psr, 1); | |
368 | SET_PSR_S (psr, GET_PSR_PS (psr)); | |
369 | sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, H_SPR_PSR, psr); | |
370 | } | |
371 | else if (CPU_DEBUG_STATE (current_cpu) && debug_field == 1) | |
372 | { | |
373 | USI psr = GET_PSR (); | |
374 | /* Return from debug state. */ | |
375 | new_pc = GET_H_SPR (H_SPR_BPCSR); | |
376 | SET_PSR_ET (psr, GET_H_BPSR_BET ()); | |
377 | SET_PSR_S (psr, GET_H_BPSR_BS ()); | |
378 | sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, H_SPR_PSR, psr); | |
379 | CPU_DEBUG_STATE (current_cpu) = 0; | |
380 | } | |
381 | else | |
382 | new_pc = pc + 4; | |
383 | ||
384 | return new_pc; | |
385 | } | |
386 | \f | |
387 | /* Functions for handling non-excepting instruction side effects. */ | |
388 | static SI next_available_nesr (SIM_CPU *current_cpu, SI current_index) | |
389 | { | |
390 | FRV_REGISTER_CONTROL *control = CPU_REGISTER_CONTROL (current_cpu); | |
391 | if (control->spr[H_SPR_NECR].implemented) | |
392 | { | |
393 | int limit; | |
394 | USI necr = GET_NECR (); | |
395 | ||
396 | /* See if any NESRs are implemented. First need to check the validity of | |
397 | the NECR. */ | |
398 | if (! GET_NECR_VALID (necr)) | |
399 | return NO_NESR; | |
400 | ||
401 | limit = GET_NECR_NEN (necr); | |
402 | for (++current_index; current_index < limit; ++current_index) | |
403 | { | |
404 | SI nesr = GET_NESR (current_index); | |
405 | if (! GET_NESR_VALID (nesr)) | |
406 | return current_index; | |
407 | } | |
408 | } | |
409 | return NO_NESR; | |
410 | } | |
411 | ||
412 | static SI next_valid_nesr (SIM_CPU *current_cpu, SI current_index) | |
413 | { | |
414 | FRV_REGISTER_CONTROL *control = CPU_REGISTER_CONTROL (current_cpu); | |
415 | if (control->spr[H_SPR_NECR].implemented) | |
416 | { | |
417 | int limit; | |
418 | USI necr = GET_NECR (); | |
419 | ||
420 | /* See if any NESRs are implemented. First need to check the validity of | |
421 | the NECR. */ | |
422 | if (! GET_NECR_VALID (necr)) | |
423 | return NO_NESR; | |
424 | ||
425 | limit = GET_NECR_NEN (necr); | |
426 | for (++current_index; current_index < limit; ++current_index) | |
427 | { | |
428 | SI nesr = GET_NESR (current_index); | |
429 | if (GET_NESR_VALID (nesr)) | |
430 | return current_index; | |
431 | } | |
432 | } | |
433 | return NO_NESR; | |
434 | } | |
435 | ||
436 | BI | |
437 | frvbf_check_non_excepting_load ( | |
438 | SIM_CPU *current_cpu, SI base_index, SI disp_index, SI target_index, | |
439 | SI immediate_disp, QI data_size, BI is_float | |
440 | ) | |
441 | { | |
442 | BI rc = 1; /* perform the load. */ | |
443 | SIM_DESC sd = CPU_STATE (current_cpu); | |
444 | int daec = 0; | |
445 | int rec = 0; | |
446 | int ec = 0; | |
447 | USI necr; | |
448 | int do_elos; | |
449 | SI NE_flags[2]; | |
450 | SI NE_base; | |
451 | SI nesr; | |
452 | SI ne_index; | |
453 | FRV_REGISTER_CONTROL *control; | |
454 | ||
455 | SI address = GET_H_GR (base_index); | |
456 | if (disp_index >= 0) | |
457 | address += GET_H_GR (disp_index); | |
458 | else | |
459 | address += immediate_disp; | |
460 | ||
461 | /* Check for interrupt factors. */ | |
462 | switch (data_size) | |
463 | { | |
464 | case NESR_UQI_SIZE: | |
465 | case NESR_QI_SIZE: | |
466 | break; | |
467 | case NESR_UHI_SIZE: | |
468 | case NESR_HI_SIZE: | |
469 | if (address & 1) | |
470 | ec = 1; | |
471 | break; | |
472 | case NESR_SI_SIZE: | |
473 | if (address & 3) | |
474 | ec = 1; | |
475 | break; | |
476 | case NESR_DI_SIZE: | |
477 | if (address & 7) | |
478 | ec = 1; | |
479 | if (target_index & 1) | |
480 | rec = 1; | |
481 | break; | |
482 | case NESR_XI_SIZE: | |
483 | if (address & 0xf) | |
484 | ec = 1; | |
485 | if (target_index & 3) | |
486 | rec = 1; | |
487 | break; | |
488 | default: | |
489 | { | |
490 | IADDR pc = GET_H_PC (); | |
491 | sim_engine_abort (sd, current_cpu, pc, | |
492 | "check_non_excepting_load: Incorrect data_size\n"); | |
493 | break; | |
494 | } | |
495 | } | |
496 | ||
497 | control = CPU_REGISTER_CONTROL (current_cpu); | |
498 | if (control->spr[H_SPR_NECR].implemented) | |
499 | { | |
500 | necr = GET_NECR (); | |
501 | do_elos = GET_NECR_VALID (necr) && GET_NECR_ELOS (necr); | |
502 | } | |
503 | else | |
504 | do_elos = 0; | |
505 | ||
506 | /* NECR, NESR, NEEAR are only implemented for the full frv machine. */ | |
507 | if (do_elos) | |
508 | { | |
509 | ne_index = next_available_nesr (current_cpu, NO_NESR); | |
510 | if (ne_index == NO_NESR) | |
511 | { | |
512 | IADDR pc = GET_H_PC (); | |
513 | sim_engine_abort (sd, current_cpu, pc, | |
514 | "No available NESR register\n"); | |
515 | } | |
516 | ||
517 | /* Fill in the basic fields of the NESR. */ | |
518 | nesr = GET_NESR (ne_index); | |
519 | SET_NESR_VALID (nesr); | |
520 | SET_NESR_EAV (nesr); | |
521 | SET_NESR_DRN (nesr, target_index); | |
522 | SET_NESR_SIZE (nesr, data_size); | |
523 | SET_NESR_NEAN (nesr, ne_index); | |
524 | if (is_float) | |
525 | SET_NESR_FR (nesr); | |
526 | else | |
527 | CLEAR_NESR_FR (nesr); | |
528 | ||
529 | /* Set the corresponding NEEAR. */ | |
530 | SET_NEEAR (ne_index, address); | |
531 | ||
532 | SET_NESR_DAEC (nesr, 0); | |
533 | SET_NESR_REC (nesr, 0); | |
534 | SET_NESR_EC (nesr, 0); | |
535 | } | |
536 | ||
537 | /* Set the NE flag corresponding to the target register if an interrupt | |
538 | factor was detected. | |
539 | daec is not checked here yet, but is declared for future reference. */ | |
540 | if (is_float) | |
541 | NE_base = H_SPR_FNER0; | |
542 | else | |
543 | NE_base = H_SPR_GNER0; | |
544 | ||
545 | GET_NE_FLAGS (NE_flags, NE_base); | |
546 | if (rec) | |
547 | { | |
548 | SET_NE_FLAG (NE_flags, target_index); | |
549 | if (do_elos) | |
550 | SET_NESR_REC (nesr, NESR_REGISTER_NOT_ALIGNED); | |
551 | } | |
552 | ||
553 | if (ec) | |
554 | { | |
555 | SET_NE_FLAG (NE_flags, target_index); | |
556 | if (do_elos) | |
557 | SET_NESR_EC (nesr, NESR_MEM_ADDRESS_NOT_ALIGNED); | |
558 | } | |
559 | ||
560 | if (do_elos) | |
561 | SET_NESR (ne_index, nesr); | |
562 | ||
563 | /* If no interrupt factor was detected then set the NE flag on the | |
564 | target register if the NE flag on one of the input registers | |
565 | is already set. */ | |
566 | if (! rec && ! ec && ! daec) | |
567 | { | |
568 | BI ne_flag = GET_NE_FLAG (NE_flags, base_index); | |
569 | if (disp_index >= 0) | |
570 | ne_flag |= GET_NE_FLAG (NE_flags, disp_index); | |
571 | if (ne_flag) | |
572 | { | |
573 | SET_NE_FLAG (NE_flags, target_index); | |
574 | rc = 0; /* Do not perform the load. */ | |
575 | } | |
576 | else | |
577 | CLEAR_NE_FLAG (NE_flags, target_index); | |
578 | } | |
579 | ||
580 | SET_NE_FLAGS (NE_base, NE_flags); | |
581 | ||
582 | return rc; /* perform the load? */ | |
583 | } | |
584 | ||
585 | /* Record state for media exception: media_cr_not_aligned. */ | |
586 | void | |
587 | frvbf_media_cr_not_aligned (SIM_CPU *current_cpu) | |
588 | { | |
589 | SIM_DESC sd = CPU_STATE (current_cpu); | |
590 | ||
e930b1f5 DB |
591 | /* On some machines this generates an illegal_instruction interrupt. */ |
592 | switch (STATE_ARCHITECTURE (sd)->mach) | |
593 | { | |
676a64f4 RS |
594 | /* Note: there is a discrepancy between V2.2 of the FR400 |
595 | instruction manual and the various FR4xx LSI specs. The former | |
596 | claims that unaligned registers cause an mp_exception while the | |
597 | latter say it's an illegal_instruction. The LSI specs appear | |
598 | to be correct since MTT is fixed at 1. */ | |
e930b1f5 | 599 | case bfd_mach_fr400: |
676a64f4 | 600 | case bfd_mach_fr450: |
e930b1f5 DB |
601 | case bfd_mach_fr550: |
602 | frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION); | |
603 | break; | |
604 | default: | |
605 | frv_set_mp_exception_registers (current_cpu, MTT_CR_NOT_ALIGNED, 0); | |
606 | break; | |
607 | } | |
b34f6357 DB |
608 | } |
609 | ||
610 | /* Record state for media exception: media_acc_not_aligned. */ | |
611 | void | |
612 | frvbf_media_acc_not_aligned (SIM_CPU *current_cpu) | |
613 | { | |
614 | SIM_DESC sd = CPU_STATE (current_cpu); | |
615 | ||
e930b1f5 DB |
616 | /* On some machines this generates an illegal_instruction interrupt. */ |
617 | switch (STATE_ARCHITECTURE (sd)->mach) | |
618 | { | |
676a64f4 | 619 | /* See comment in frvbf_cr_not_aligned(). */ |
e930b1f5 | 620 | case bfd_mach_fr400: |
676a64f4 | 621 | case bfd_mach_fr450: |
e930b1f5 DB |
622 | case bfd_mach_fr550: |
623 | frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION); | |
624 | break; | |
625 | default: | |
626 | frv_set_mp_exception_registers (current_cpu, MTT_ACC_NOT_ALIGNED, 0); | |
627 | break; | |
628 | } | |
b34f6357 DB |
629 | } |
630 | ||
631 | /* Record state for media exception: media_register_not_aligned. */ | |
632 | void | |
633 | frvbf_media_register_not_aligned (SIM_CPU *current_cpu) | |
634 | { | |
635 | SIM_DESC sd = CPU_STATE (current_cpu); | |
636 | ||
e930b1f5 DB |
637 | /* On some machines this generates an illegal_instruction interrupt. */ |
638 | switch (STATE_ARCHITECTURE (sd)->mach) | |
639 | { | |
676a64f4 | 640 | /* See comment in frvbf_cr_not_aligned(). */ |
e930b1f5 | 641 | case bfd_mach_fr400: |
676a64f4 | 642 | case bfd_mach_fr450: |
e930b1f5 DB |
643 | case bfd_mach_fr550: |
644 | frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION); | |
645 | break; | |
646 | default: | |
647 | frv_set_mp_exception_registers (current_cpu, MTT_INVALID_FR, 0); | |
648 | break; | |
649 | } | |
b34f6357 DB |
650 | } |
651 | ||
652 | /* Record state for media exception: media_overflow. */ | |
653 | void | |
654 | frvbf_media_overflow (SIM_CPU *current_cpu, int sie) | |
655 | { | |
656 | frv_set_mp_exception_registers (current_cpu, MTT_OVERFLOW, sie); | |
657 | } | |
658 | ||
659 | /* Queue a division exception. */ | |
660 | enum frv_dtt | |
661 | frvbf_division_exception (SIM_CPU *current_cpu, enum frv_dtt dtt, | |
662 | int target_index, int non_excepting) | |
663 | { | |
664 | /* If there was an overflow and it is masked, then record it in | |
665 | ISR.AEXC. */ | |
666 | USI isr = GET_ISR (); | |
667 | if ((dtt & FRV_DTT_OVERFLOW) && GET_ISR_EDE (isr)) | |
668 | { | |
669 | dtt &= ~FRV_DTT_OVERFLOW; | |
670 | SET_ISR_AEXC (isr); | |
671 | SET_ISR (isr); | |
672 | } | |
673 | if (dtt != FRV_DTT_NO_EXCEPTION) | |
674 | { | |
675 | if (non_excepting) | |
676 | { | |
677 | /* Non excepting instruction, simply set the NE flag for the target | |
678 | register. */ | |
679 | SI NE_flags[2]; | |
680 | GET_NE_FLAGS (NE_flags, H_SPR_GNER0); | |
681 | SET_NE_FLAG (NE_flags, target_index); | |
682 | SET_NE_FLAGS (H_SPR_GNER0, NE_flags); | |
683 | } | |
684 | else | |
685 | frv_queue_division_exception_interrupt (current_cpu, dtt); | |
686 | } | |
687 | return dtt; | |
688 | } | |
689 | ||
690 | void | |
691 | frvbf_check_recovering_store ( | |
692 | SIM_CPU *current_cpu, PCADDR address, SI regno, int size, int is_float | |
693 | ) | |
694 | { | |
695 | FRV_CACHE *cache = CPU_DATA_CACHE (current_cpu); | |
696 | int reg_ix; | |
697 | ||
698 | CPU_RSTR_INVALIDATE(current_cpu) = 0; | |
699 | ||
700 | for (reg_ix = next_valid_nesr (current_cpu, NO_NESR); | |
701 | reg_ix != NO_NESR; | |
702 | reg_ix = next_valid_nesr (current_cpu, reg_ix)) | |
703 | { | |
704 | if (address == GET_H_SPR (H_SPR_NEEAR0 + reg_ix)) | |
705 | { | |
706 | SI nesr = GET_NESR (reg_ix); | |
707 | int nesr_drn = GET_NESR_DRN (nesr); | |
708 | BI nesr_fr = GET_NESR_FR (nesr); | |
709 | SI remain; | |
710 | ||
711 | /* Invalidate cache block containing this address. | |
712 | If we need to count cycles, then the cache operation will be | |
713 | initiated from the model profiling functions. | |
714 | See frvbf_model_.... */ | |
715 | if (model_insn) | |
716 | { | |
717 | CPU_RSTR_INVALIDATE(current_cpu) = 1; | |
718 | CPU_LOAD_ADDRESS (current_cpu) = address; | |
719 | } | |
720 | else | |
721 | frv_cache_invalidate (cache, address, 1/* flush */); | |
722 | ||
723 | /* Copy the stored value to the register indicated by NESR.DRN. */ | |
724 | for (remain = size; remain > 0; remain -= 4) | |
725 | { | |
726 | SI value; | |
727 | ||
728 | if (is_float) | |
729 | value = GET_H_FR (regno); | |
730 | else | |
731 | value = GET_H_GR (regno); | |
732 | ||
733 | switch (size) | |
734 | { | |
735 | case 1: | |
736 | value &= 0xff; | |
737 | break; | |
738 | case 2: | |
739 | value &= 0xffff; | |
740 | break; | |
741 | default: | |
742 | break; | |
743 | } | |
744 | ||
745 | if (nesr_fr) | |
746 | sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, nesr_drn, | |
747 | value); | |
748 | else | |
749 | sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, nesr_drn, | |
750 | value); | |
751 | ||
752 | nesr_drn++; | |
753 | regno++; | |
754 | } | |
755 | break; /* Only consider the first matching register. */ | |
756 | } | |
757 | } /* loop over active neear registers. */ | |
758 | } | |
759 | ||
e930b1f5 DB |
760 | SI |
761 | frvbf_check_acc_range (SIM_CPU *current_cpu, SI regno) | |
762 | { | |
763 | /* Only applicable to fr550 */ | |
764 | SIM_DESC sd = CPU_STATE (current_cpu); | |
765 | if (STATE_ARCHITECTURE (sd)->mach != bfd_mach_fr550) | |
766 | return; | |
767 | ||
768 | /* On the fr550, media insns in slots 0 and 2 can only access | |
769 | accumulators acc0-acc3. Insns in slots 1 and 3 can only access | |
770 | accumulators acc4-acc7 */ | |
771 | switch (frv_current_fm_slot) | |
772 | { | |
773 | case UNIT_FM0: | |
774 | case UNIT_FM2: | |
775 | if (regno <= 3) | |
776 | return 1; /* all is ok */ | |
777 | break; | |
778 | case UNIT_FM1: | |
779 | case UNIT_FM3: | |
780 | if (regno >= 4) | |
781 | return 1; /* all is ok */ | |
782 | break; | |
783 | } | |
784 | ||
785 | /* The specified accumulator is out of range. Queue an illegal_instruction | |
786 | interrupt. */ | |
787 | frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION); | |
788 | return 0; | |
789 | } | |
790 | ||
791 | void | |
792 | frvbf_check_swap_address (SIM_CPU *current_cpu, SI address) | |
793 | { | |
794 | /* Only applicable to fr550 */ | |
795 | SIM_DESC sd = CPU_STATE (current_cpu); | |
796 | if (STATE_ARCHITECTURE (sd)->mach != bfd_mach_fr550) | |
797 | return; | |
798 | ||
799 | /* Adress must be aligned on a word boundary. */ | |
800 | if (address & 0x3) | |
801 | frv_queue_data_access_exception_interrupt (current_cpu); | |
802 | } | |
803 | ||
b34f6357 DB |
804 | static void |
805 | clear_nesr_neear (SIM_CPU *current_cpu, SI target_index, BI is_float) | |
806 | { | |
807 | int reg_ix; | |
808 | ||
809 | /* Only implemented for full frv. */ | |
810 | SIM_DESC sd = CPU_STATE (current_cpu); | |
811 | if (STATE_ARCHITECTURE (sd)->mach != bfd_mach_frv) | |
812 | return; | |
813 | ||
814 | /* Clear the appropriate NESR and NEEAR registers. */ | |
815 | for (reg_ix = next_valid_nesr (current_cpu, NO_NESR); | |
816 | reg_ix != NO_NESR; | |
817 | reg_ix = next_valid_nesr (current_cpu, reg_ix)) | |
818 | { | |
819 | SI nesr; | |
820 | /* The register is available, now check if it is active. */ | |
821 | nesr = GET_NESR (reg_ix); | |
822 | if (GET_NESR_FR (nesr) == is_float) | |
823 | { | |
824 | if (target_index < 0 || GET_NESR_DRN (nesr) == target_index) | |
825 | { | |
826 | SET_NESR (reg_ix, 0); | |
827 | SET_NEEAR (reg_ix, 0); | |
828 | } | |
829 | } | |
830 | } | |
831 | } | |
832 | ||
833 | static void | |
834 | clear_ne_flags ( | |
835 | SIM_CPU *current_cpu, | |
836 | SI target_index, | |
837 | int hi_available, | |
838 | int lo_available, | |
839 | SI NE_base | |
840 | ) | |
841 | { | |
842 | SI NE_flags[2]; | |
843 | int exception; | |
844 | ||
845 | GET_NE_FLAGS (NE_flags, NE_base); | |
846 | if (target_index >= 0) | |
847 | CLEAR_NE_FLAG (NE_flags, target_index); | |
848 | else | |
849 | { | |
850 | if (lo_available) | |
851 | NE_flags[1] = 0; | |
852 | if (hi_available) | |
853 | NE_flags[0] = 0; | |
854 | } | |
855 | SET_NE_FLAGS (NE_base, NE_flags); | |
856 | } | |
857 | ||
858 | /* Return 1 if the given register is available, 0 otherwise. TARGET_INDEX==-1 | |
859 | means to check for any register available. */ | |
860 | static void | |
861 | which_registers_available ( | |
862 | SIM_CPU *current_cpu, int *hi_available, int *lo_available, int is_float | |
863 | ) | |
864 | { | |
865 | if (is_float) | |
866 | frv_fr_registers_available (current_cpu, hi_available, lo_available); | |
867 | else | |
868 | frv_gr_registers_available (current_cpu, hi_available, lo_available); | |
869 | } | |
870 | ||
871 | void | |
872 | frvbf_clear_ne_flags (SIM_CPU *current_cpu, SI target_index, BI is_float) | |
873 | { | |
874 | int hi_available; | |
875 | int lo_available; | |
876 | int exception; | |
877 | SI NE_base; | |
878 | USI necr; | |
879 | FRV_REGISTER_CONTROL *control; | |
880 | ||
881 | /* Check for availability of the target register(s). */ | |
882 | which_registers_available (current_cpu, & hi_available, & lo_available, | |
883 | is_float); | |
884 | ||
885 | /* Check to make sure that the target register is available. */ | |
886 | if (! frv_check_register_access (current_cpu, target_index, | |
887 | hi_available, lo_available)) | |
888 | return; | |
889 | ||
890 | /* Determine whether we're working with GR or FR registers. */ | |
891 | if (is_float) | |
892 | NE_base = H_SPR_FNER0; | |
893 | else | |
894 | NE_base = H_SPR_GNER0; | |
895 | ||
896 | /* Always clear the appropriate NE flags. */ | |
897 | clear_ne_flags (current_cpu, target_index, hi_available, lo_available, | |
898 | NE_base); | |
899 | ||
900 | /* Clear the appropriate NESR and NEEAR registers. */ | |
901 | control = CPU_REGISTER_CONTROL (current_cpu); | |
902 | if (control->spr[H_SPR_NECR].implemented) | |
903 | { | |
904 | necr = GET_NECR (); | |
905 | if (GET_NECR_VALID (necr) && GET_NECR_ELOS (necr)) | |
906 | clear_nesr_neear (current_cpu, target_index, is_float); | |
907 | } | |
908 | } | |
909 | ||
910 | void | |
911 | frvbf_commit (SIM_CPU *current_cpu, SI target_index, BI is_float) | |
912 | { | |
913 | SI NE_base; | |
914 | SI NE_flags[2]; | |
915 | BI NE_flag; | |
916 | int exception; | |
917 | int hi_available; | |
918 | int lo_available; | |
919 | USI necr; | |
920 | FRV_REGISTER_CONTROL *control; | |
921 | ||
922 | /* Check for availability of the target register(s). */ | |
923 | which_registers_available (current_cpu, & hi_available, & lo_available, | |
924 | is_float); | |
925 | ||
926 | /* Check to make sure that the target register is available. */ | |
927 | if (! frv_check_register_access (current_cpu, target_index, | |
928 | hi_available, lo_available)) | |
929 | return; | |
930 | ||
931 | /* Determine whether we're working with GR or FR registers. */ | |
932 | if (is_float) | |
933 | NE_base = H_SPR_FNER0; | |
934 | else | |
935 | NE_base = H_SPR_GNER0; | |
936 | ||
937 | /* Determine whether a ne exception is pending. */ | |
938 | GET_NE_FLAGS (NE_flags, NE_base); | |
939 | if (target_index >= 0) | |
940 | NE_flag = GET_NE_FLAG (NE_flags, target_index); | |
941 | else | |
942 | { | |
943 | NE_flag = | |
944 | hi_available && NE_flags[0] != 0 || lo_available && NE_flags[1] != 0; | |
945 | } | |
946 | ||
947 | /* Always clear the appropriate NE flags. */ | |
948 | clear_ne_flags (current_cpu, target_index, hi_available, lo_available, | |
949 | NE_base); | |
950 | ||
951 | control = CPU_REGISTER_CONTROL (current_cpu); | |
952 | if (control->spr[H_SPR_NECR].implemented) | |
953 | { | |
954 | necr = GET_NECR (); | |
955 | if (GET_NECR_VALID (necr) && GET_NECR_ELOS (necr) && NE_flag) | |
956 | { | |
957 | /* Clear the appropriate NESR and NEEAR registers. */ | |
958 | clear_nesr_neear (current_cpu, target_index, is_float); | |
959 | frv_queue_program_interrupt (current_cpu, FRV_COMMIT_EXCEPTION); | |
960 | } | |
961 | } | |
962 | } | |
963 | ||
964 | /* Generate the appropriate fp_exception(s) based on the given status code. */ | |
965 | void | |
966 | frvbf_fpu_error (CGEN_FPU* fpu, int status) | |
967 | { | |
968 | struct frv_fp_exception_info fp_info = { | |
969 | FSR_NO_EXCEPTION, FTT_IEEE_754_EXCEPTION | |
970 | }; | |
971 | ||
972 | if (status & | |
973 | (sim_fpu_status_invalid_snan | | |
974 | sim_fpu_status_invalid_qnan | | |
975 | sim_fpu_status_invalid_isi | | |
976 | sim_fpu_status_invalid_idi | | |
977 | sim_fpu_status_invalid_zdz | | |
978 | sim_fpu_status_invalid_imz | | |
979 | sim_fpu_status_invalid_cvi | | |
980 | sim_fpu_status_invalid_cmp | | |
981 | sim_fpu_status_invalid_sqrt)) | |
982 | fp_info.fsr_mask |= FSR_INVALID_OPERATION; | |
983 | ||
984 | if (status & sim_fpu_status_invalid_div0) | |
985 | fp_info.fsr_mask |= FSR_DIVISION_BY_ZERO; | |
986 | ||
987 | if (status & sim_fpu_status_inexact) | |
988 | fp_info.fsr_mask |= FSR_INEXACT; | |
989 | ||
990 | if (status & sim_fpu_status_overflow) | |
991 | fp_info.fsr_mask |= FSR_OVERFLOW; | |
992 | ||
993 | if (status & sim_fpu_status_underflow) | |
994 | fp_info.fsr_mask |= FSR_UNDERFLOW; | |
995 | ||
996 | if (status & sim_fpu_status_denorm) | |
997 | { | |
998 | fp_info.fsr_mask |= FSR_DENORMAL_INPUT; | |
999 | fp_info.ftt = FTT_DENORMAL_INPUT; | |
1000 | } | |
1001 | ||
1002 | if (fp_info.fsr_mask != FSR_NO_EXCEPTION) | |
1003 | { | |
1004 | SIM_CPU *current_cpu = (SIM_CPU *)fpu->owner; | |
1005 | frv_queue_fp_exception_interrupt (current_cpu, & fp_info); | |
1006 | } | |
1007 | } |