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ce51bde6 DE |
1 | /* |
2 | * Simulator for the Hitachi H8/300 architecture. | |
3 | * | |
4 | * Written by Steve Chamberlain of Cygnus Support. sac@cygnus.com | |
5 | * | |
6 | * This file is part of H8/300 sim | |
7 | * | |
8 | * | |
9 | * THIS SOFTWARE IS NOT COPYRIGHTED | |
10 | * | |
11 | * Cygnus offers the following for use in the public domain. Cygnus makes no | |
12 | * warranty with regard to the software or its performance and the user | |
13 | * accepts the software "AS IS" with all faults. | |
14 | * | |
15 | * CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO THIS | |
16 | * SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY | |
17 | * AND FITNESS FOR A PARTICULAR PURPOSE. | |
ce51bde6 DE |
18 | */ |
19 | ||
e656ecf9 DE |
20 | #include "config.h" |
21 | ||
ce51bde6 | 22 | #include <signal.h> |
e656ecf9 DE |
23 | #ifdef HAVE_TIME_H |
24 | #include <time.h> | |
25 | #endif | |
26 | #ifdef HAVE_STDLIB_H | |
27 | #include <stdlib.h> | |
7478904c | 28 | #endif |
9e03a68f | 29 | #ifdef HAVE_SYS_PARAM_H |
ce51bde6 | 30 | #include <sys/param.h> |
9e03a68f | 31 | #endif |
4dfb4ffc | 32 | #include "wait.h" |
0693d363 | 33 | #include "ansidecl.h" |
46337270 | 34 | #include "bfd.h" |
e656ecf9 | 35 | #include "callback.h" |
a415cf0a | 36 | #include "remote-sim.h" |
ce51bde6 | 37 | |
9e03a68f AC |
38 | #ifndef SIGTRAP |
39 | # define SIGTRAP 5 | |
40 | #endif | |
41 | ||
ce51bde6 DE |
42 | int debug; |
43 | ||
46337270 DE |
44 | host_callback *sim_callback; |
45 | ||
46 | static SIM_OPEN_KIND sim_kind; | |
47 | static char *myname; | |
48 | ||
49 | /* FIXME: Needs to live in header file. | |
50 | This header should also include the things in remote-sim.h. | |
51 | One could move this to remote-sim.h but this function isn't needed | |
52 | by gdb. */ | |
53 | void sim_set_simcache_size PARAMS ((int)); | |
ce51bde6 DE |
54 | |
55 | #define X(op, size) op*4+size | |
56 | ||
28655f00 | 57 | #define SP (h8300hmode ? SL:SW) |
ce51bde6 DE |
58 | #define SB 0 |
59 | #define SW 1 | |
60 | #define SL 2 | |
61 | #define OP_REG 1 | |
62 | #define OP_DEC 2 | |
63 | #define OP_DISP 3 | |
64 | #define OP_INC 4 | |
65 | #define OP_PCREL 5 | |
66 | #define OP_MEM 6 | |
67 | #define OP_CCR 7 | |
68 | #define OP_IMM 8 | |
69 | #define OP_ABS 10 | |
70 | #define h8_opcodes ops | |
71 | #define DEFINE_TABLE | |
72 | #include "opcode/h8300.h" | |
73 | ||
74 | #include "inst.h" | |
75 | ||
76 | #define LOW_BYTE(x) ((x) & 0xff) | |
77 | #define HIGH_BYTE(x) (((x)>>8) & 0xff) | |
78 | #define P(X,Y) ((X<<8) | Y) | |
79 | ||
80 | #define BUILDSR() cpu.ccr = (N << 3) | (Z << 2) | (V<<1) | C; | |
81 | ||
82 | #define GETSR() \ | |
83 | c = (cpu.ccr >> 0) & 1;\ | |
84 | v = (cpu.ccr >> 1) & 1;\ | |
85 | nz = !((cpu.ccr >> 2) & 1);\ | |
86 | n = (cpu.ccr >> 3) & 1; | |
87 | ||
88 | #ifdef __CHAR_IS_SIGNED__ | |
89 | #define SEXTCHAR(x) ((char)(x)) | |
90 | #endif | |
91 | ||
92 | #ifndef SEXTCHAR | |
171f4664 | 93 | #define SEXTCHAR(x) ((x & 0x80) ? (x | ~0xff): x & 0xff) |
ce51bde6 DE |
94 | #endif |
95 | ||
96 | #define UEXTCHAR(x) ((x) & 0xff) | |
97 | #define UEXTSHORT(x) ((x) & 0xffff) | |
98 | #define SEXTSHORT(x) ((short)(x)) | |
99 | ||
100 | static cpu_state_type cpu; | |
101 | ||
28655f00 | 102 | int h8300hmode = 0; |
171f4664 | 103 | int h8300smode = 0; |
ce51bde6 | 104 | |
e656ecf9 DE |
105 | static int memory_size; |
106 | ||
ce51bde6 DE |
107 | |
108 | static int | |
109 | get_now () | |
110 | { | |
7478904c | 111 | #ifndef WIN32 |
0693d363 | 112 | return time (0); |
28655f00 | 113 | #endif |
7478904c | 114 | return 0; |
ce51bde6 DE |
115 | } |
116 | ||
117 | static int | |
118 | now_persec () | |
119 | { | |
28655f00 | 120 | return 1; |
ce51bde6 DE |
121 | } |
122 | ||
123 | ||
124 | static int | |
125 | bitfrom (x) | |
126 | { | |
ce51bde6 DE |
127 | switch (x & SIZE) |
128 | { | |
129 | case L_8: | |
130 | return SB; | |
131 | case L_16: | |
132 | return SW; | |
133 | case L_32: | |
134 | return SL; | |
135 | case L_P: | |
28655f00 | 136 | return h8300hmode ? SL : SW; |
ce51bde6 | 137 | } |
ce51bde6 DE |
138 | } |
139 | ||
140 | static | |
141 | unsigned int | |
142 | lvalue (x, rn) | |
143 | { | |
144 | switch (x / 4) | |
145 | { | |
146 | case OP_DISP: | |
0693d363 | 147 | if (rn == 8) |
ce51bde6 | 148 | { |
0693d363 | 149 | return X (OP_IMM, SP); |
ce51bde6 | 150 | } |
0693d363 DE |
151 | return X (OP_REG, SP); |
152 | ||
ce51bde6 DE |
153 | case OP_MEM: |
154 | ||
155 | return X (OP_MEM, SP); | |
156 | default: | |
157 | abort (); | |
158 | } | |
159 | } | |
160 | ||
161 | static unsigned int | |
162 | decode (addr, data, dst) | |
163 | int addr; | |
164 | unsigned char *data; | |
165 | decoded_inst *dst; | |
166 | ||
167 | { | |
168 | int rs = 0; | |
169 | int rd = 0; | |
170 | int rdisp = 0; | |
171 | int abs = 0; | |
172 | int plen = 0; | |
e24146ec | 173 | int bit = 0; |
ce51bde6 DE |
174 | |
175 | struct h8_opcode *q = h8_opcodes; | |
176 | int size = 0; | |
177 | dst->dst.type = -1; | |
178 | dst->src.type = -1; | |
179 | /* Find the exact opcode/arg combo */ | |
180 | while (q->name) | |
181 | { | |
182 | op_type *nib; | |
183 | unsigned int len = 0; | |
184 | ||
185 | nib = q->data.nib; | |
186 | ||
187 | while (1) | |
188 | { | |
189 | op_type looking_for = *nib; | |
190 | int thisnib = data[len >> 1]; | |
191 | ||
192 | thisnib = (len & 1) ? (thisnib & 0xf) : ((thisnib >> 4) & 0xf); | |
193 | ||
0693d363 | 194 | if (looking_for < 16 && looking_for >= 0) |
ce51bde6 | 195 | { |
ce51bde6 DE |
196 | if (looking_for != thisnib) |
197 | goto fail; | |
198 | } | |
199 | else | |
200 | { | |
ce51bde6 DE |
201 | if ((int) looking_for & (int) B31) |
202 | { | |
203 | if (!(((int) thisnib & 0x8) != 0)) | |
204 | goto fail; | |
205 | looking_for = (op_type) ((int) looking_for & ~(int) | |
206 | B31); | |
207 | thisnib &= 0x7; | |
ce51bde6 DE |
208 | } |
209 | if ((int) looking_for & (int) B30) | |
210 | { | |
211 | if (!(((int) thisnib & 0x8) == 0)) | |
212 | goto fail; | |
213 | looking_for = (op_type) ((int) looking_for & ~(int) B30); | |
214 | } | |
215 | if (looking_for & DBIT) | |
216 | { | |
0693d363 DE |
217 | if ((looking_for & 5) != (thisnib & 5)) |
218 | goto fail; | |
ce51bde6 DE |
219 | abs = (thisnib & 0x8) ? 2 : 1; |
220 | } | |
221 | else if (looking_for & (REG | IND | INC | DEC)) | |
222 | { | |
223 | if (looking_for & REG) | |
224 | { | |
225 | /* | |
226 | * Can work out size from the | |
227 | * register | |
228 | */ | |
229 | size = bitfrom (looking_for); | |
230 | } | |
231 | if (looking_for & SRC) | |
232 | { | |
233 | rs = thisnib; | |
234 | } | |
235 | else | |
236 | { | |
237 | rd = thisnib; | |
238 | } | |
239 | } | |
240 | else if (looking_for & L_16) | |
241 | { | |
242 | abs = (data[len >> 1]) * 256 + data[(len + 2) >> 1]; | |
243 | plen = 16; | |
0693d363 | 244 | if (looking_for & (PCREL | DISP)) |
ce51bde6 DE |
245 | { |
246 | abs = (short) (abs); | |
247 | } | |
248 | } | |
249 | else if (looking_for & ABSJMP) | |
250 | { | |
251 | abs = | |
252 | (data[1] << 16) | |
253 | | (data[2] << 8) | |
254 | | (data[3]); | |
255 | } | |
0693d363 DE |
256 | else if (looking_for & MEMIND) |
257 | { | |
258 | abs = data[1]; | |
259 | } | |
ce51bde6 DE |
260 | else if (looking_for & L_32) |
261 | { | |
262 | int i = len >> 1; | |
263 | abs = (data[i] << 24) | |
264 | | (data[i + 1] << 16) | |
265 | | (data[i + 2] << 8) | |
266 | | (data[i + 3]); | |
267 | ||
268 | plen = 32; | |
ce51bde6 DE |
269 | } |
270 | else if (looking_for & L_24) | |
271 | { | |
272 | int i = len >> 1; | |
0693d363 | 273 | abs = (data[i] << 16) | (data[i + 1] << 8) | (data[i + 2]); |
ce51bde6 DE |
274 | plen = 24; |
275 | } | |
276 | else if (looking_for & IGNORE) | |
277 | { | |
0693d363 | 278 | /* nothing to do */ |
ce51bde6 DE |
279 | } |
280 | else if (looking_for & DISPREG) | |
281 | { | |
282 | rdisp = thisnib & 0x7; | |
283 | } | |
284 | else if (looking_for & KBIT) | |
285 | { | |
286 | switch (thisnib) | |
287 | { | |
288 | case 9: | |
289 | abs = 4; | |
290 | break; | |
291 | case 8: | |
292 | abs = 2; | |
293 | break; | |
294 | case 0: | |
295 | abs = 1; | |
296 | break; | |
297 | } | |
298 | } | |
299 | else if (looking_for & L_8) | |
300 | { | |
301 | plen = 8; | |
302 | ||
303 | if (looking_for & PCREL) | |
304 | { | |
305 | abs = SEXTCHAR (data[len >> 1]); | |
306 | } | |
e24146ec JL |
307 | else if (looking_for & ABS8MEM) |
308 | { | |
309 | plen = 8; | |
310 | abs = h8300hmode ? ~0xff0000ff : ~0xffff00ff; | |
311 | abs |= data[len >> 1] & 0xff ; | |
312 | } | |
313 | else | |
ce51bde6 DE |
314 | { |
315 | abs = data[len >> 1] & 0xff; | |
316 | } | |
317 | } | |
318 | else if (looking_for & L_3) | |
319 | { | |
320 | plen = 3; | |
321 | ||
e24146ec | 322 | bit = thisnib; |
ce51bde6 DE |
323 | } |
324 | else if (looking_for == E) | |
325 | { | |
326 | dst->op = q; | |
327 | ||
328 | /* Fill in the args */ | |
329 | { | |
330 | op_type *args = q->args.nib; | |
331 | int hadone = 0; | |
332 | ||
ce51bde6 DE |
333 | while (*args != E) |
334 | { | |
335 | int x = *args; | |
336 | int rn = (x & DST) ? rd : rs; | |
337 | ea_type *p; | |
338 | ||
339 | if (x & DST) | |
340 | { | |
341 | p = &(dst->dst); | |
342 | } | |
343 | else | |
344 | { | |
345 | p = &(dst->src); | |
346 | } | |
347 | ||
e24146ec JL |
348 | if (x & (L_3)) |
349 | { | |
350 | p->type = X (OP_IMM, size); | |
351 | p->literal = bit; | |
352 | } | |
353 | else if (x & (IMM | KBIT | DBIT)) | |
ce51bde6 DE |
354 | { |
355 | p->type = X (OP_IMM, size); | |
356 | p->literal = abs; | |
357 | } | |
358 | else if (x & REG) | |
359 | { | |
0693d363 DE |
360 | /* Reset the size, some |
361 | ops (like mul) have two sizes */ | |
362 | ||
ce51bde6 DE |
363 | size = bitfrom (x); |
364 | p->type = X (OP_REG, size); | |
365 | p->reg = rn; | |
366 | } | |
367 | else if (x & INC) | |
368 | { | |
369 | p->type = X (OP_INC, size); | |
370 | p->reg = rn & 0x7; | |
371 | } | |
372 | else if (x & DEC) | |
373 | { | |
374 | p->type = X (OP_DEC, size); | |
375 | p->reg = rn & 0x7; | |
376 | } | |
377 | else if (x & IND) | |
378 | { | |
379 | p->type = X (OP_DISP, size); | |
380 | p->reg = rn & 0x7; | |
381 | p->literal = 0; | |
382 | } | |
e24146ec | 383 | else if (x & (ABS | ABSJMP | ABS8MEM)) |
ce51bde6 DE |
384 | { |
385 | p->type = X (OP_DISP, size); | |
386 | p->literal = abs; | |
387 | p->reg = 8; | |
388 | } | |
389 | else if (x & MEMIND) | |
390 | { | |
391 | p->type = X (OP_MEM, size); | |
392 | p->literal = abs; | |
393 | } | |
394 | else if (x & PCREL) | |
395 | { | |
396 | p->type = X (OP_PCREL, size); | |
397 | p->literal = abs + addr + 2; | |
0693d363 DE |
398 | if (x & L_16) |
399 | p->literal += 2; | |
ce51bde6 DE |
400 | } |
401 | else if (x & ABSJMP) | |
402 | { | |
403 | p->type = X (OP_IMM, SP); | |
404 | p->literal = abs; | |
405 | } | |
406 | else if (x & DISP) | |
407 | { | |
408 | p->type = X (OP_DISP, size); | |
409 | p->literal = abs; | |
410 | p->reg = rdisp & 0x7; | |
411 | } | |
412 | else if (x & CCR) | |
413 | { | |
414 | p->type = OP_CCR; | |
415 | } | |
416 | else | |
417 | printf ("Hmmmm %x", x); | |
418 | ||
ce51bde6 DE |
419 | args++; |
420 | } | |
421 | } | |
422 | ||
423 | /* | |
0693d363 DE |
424 | * But a jmp or a jsr gets |
425 | * automagically lvalued, since we | |
426 | * branch to their address not their | |
427 | * contents | |
428 | */ | |
ce51bde6 DE |
429 | if (q->how == O (O_JSR, SB) |
430 | || q->how == O (O_JMP, SB)) | |
431 | { | |
432 | dst->src.type = lvalue (dst->src.type, dst->src.reg); | |
433 | } | |
434 | ||
ce51bde6 DE |
435 | if (dst->dst.type == -1) |
436 | dst->dst = dst->src; | |
0693d363 | 437 | |
ce51bde6 DE |
438 | dst->opcode = q->how; |
439 | dst->cycles = q->time; | |
440 | ||
441 | /* And a jsr to 0xc4 is turned into a magic trap */ | |
0693d363 DE |
442 | |
443 | if (dst->opcode == O (O_JSR, SB)) | |
ce51bde6 | 444 | { |
0693d363 | 445 | if (dst->src.literal == 0xc4) |
ce51bde6 | 446 | { |
0693d363 | 447 | dst->opcode = O (O_SYSCALL, SB); |
ce51bde6 DE |
448 | } |
449 | } | |
0693d363 | 450 | |
ce51bde6 DE |
451 | dst->next_pc = addr + len / 2; |
452 | return; | |
453 | } | |
454 | else | |
455 | { | |
456 | printf ("Dont understand %x \n", looking_for); | |
457 | } | |
458 | } | |
0693d363 | 459 | |
ce51bde6 DE |
460 | len++; |
461 | nib++; | |
462 | } | |
0693d363 | 463 | |
ce51bde6 DE |
464 | fail: |
465 | q++; | |
466 | } | |
0693d363 | 467 | |
ce51bde6 DE |
468 | dst->opcode = O (O_ILL, SB); |
469 | } | |
470 | ||
471 | ||
472 | static void | |
473 | compile (pc) | |
474 | { | |
475 | int idx; | |
0693d363 | 476 | |
ce51bde6 | 477 | /* find the next cache entry to use */ |
0693d363 | 478 | |
ce51bde6 DE |
479 | idx = cpu.cache_top + 1; |
480 | cpu.compiles++; | |
481 | if (idx >= cpu.csize) | |
482 | { | |
483 | idx = 1; | |
484 | } | |
485 | cpu.cache_top = idx; | |
0693d363 | 486 | |
ce51bde6 DE |
487 | /* Throw away its old meaning */ |
488 | cpu.cache_idx[cpu.cache[idx].oldpc] = 0; | |
0693d363 | 489 | |
ce51bde6 DE |
490 | /* set to new address */ |
491 | cpu.cache[idx].oldpc = pc; | |
0693d363 | 492 | |
ce51bde6 DE |
493 | /* fill in instruction info */ |
494 | decode (pc, cpu.memory + pc, cpu.cache + idx); | |
0693d363 | 495 | |
ce51bde6 DE |
496 | /* point to new cache entry */ |
497 | cpu.cache_idx[pc] = idx; | |
498 | } | |
499 | ||
500 | ||
501 | static unsigned char *breg[18]; | |
502 | static unsigned short *wreg[18]; | |
503 | static unsigned int *lreg[18]; | |
504 | ||
505 | #define GET_B_REG(x) *(breg[x]) | |
506 | #define SET_B_REG(x,y) (*(breg[x])) = (y) | |
507 | #define GET_W_REG(x) *(wreg[x]) | |
508 | #define SET_W_REG(x,y) (*(wreg[x])) = (y) | |
509 | ||
510 | #define GET_L_REG(x) *(lreg[x]) | |
511 | #define SET_L_REG(x,y) (*(lreg[x])) = (y) | |
512 | ||
513 | #define GET_MEMORY_L(x) \ | |
7e1e013f JL |
514 | (x < memory_size \ |
515 | ? ((cpu.memory[x+0] << 24) | (cpu.memory[x+1] << 16) \ | |
516 | | (cpu.memory[x+2] << 8) | cpu.memory[x+3]) \ | |
517 | : ((cpu.eightbit[(x+0) & 0xff] << 24) | (cpu.eightbit[(x+1) & 0xff] << 16) \ | |
518 | | (cpu.eightbit[(x+2) & 0xff] << 8) | cpu.eightbit[(x+3) & 0xff])) | |
ce51bde6 DE |
519 | |
520 | #define GET_MEMORY_W(x) \ | |
7e1e013f JL |
521 | (x < memory_size \ |
522 | ? ((cpu.memory[x+0] << 8) | (cpu.memory[x+1] << 0)) \ | |
523 | : ((cpu.eightbit[(x+0) & 0xff] << 8) | (cpu.eightbit[(x+1) & 0xff] << 0))) | |
ce51bde6 DE |
524 | |
525 | ||
7e1e013f JL |
526 | #define GET_MEMORY_B(x) \ |
527 | (x < memory_size ? (cpu.memory[x]) : (cpu.eightbit[x & 0xff])) | |
ce51bde6 DE |
528 | |
529 | #define SET_MEMORY_L(x,y) \ | |
7e1e013f JL |
530 | { register unsigned char *_p; register int __y = y; \ |
531 | _p = (x < memory_size ? cpu.memory+x : cpu.eightbit + (x & 0xff)); \ | |
532 | _p[0] = (__y)>>24; _p[1] = (__y)>>16; \ | |
533 | _p[2] = (__y)>>8; _p[3] = (__y)>>0;} | |
ce51bde6 | 534 | |
7e1e013f JL |
535 | #define SET_MEMORY_W(x,y) \ |
536 | { register unsigned char *_p; register int __y = y; \ | |
537 | _p = (x < memory_size ? cpu.memory+x : cpu.eightbit + (x & 0xff)); \ | |
538 | _p[0] = (__y)>>8; _p[1] =(__y);} | |
539 | ||
540 | #define SET_MEMORY_B(x,y) \ | |
541 | (x < memory_size ? (cpu.memory[(x)] = y) : (cpu.eightbit[x & 0xff] = y)) | |
ce51bde6 DE |
542 | |
543 | int | |
89a2c4fd | 544 | fetch (arg, n) |
0693d363 | 545 | ea_type *arg; |
ce51bde6 DE |
546 | { |
547 | int rn = arg->reg; | |
548 | int abs = arg->literal; | |
549 | int r; | |
550 | int t; | |
0693d363 | 551 | |
ce51bde6 DE |
552 | switch (arg->type) |
553 | { | |
554 | case X (OP_REG, SB): | |
555 | return GET_B_REG (rn); | |
556 | case X (OP_REG, SW): | |
557 | return GET_W_REG (rn); | |
558 | case X (OP_REG, SL): | |
559 | return GET_L_REG (rn); | |
560 | case X (OP_IMM, SB): | |
561 | case X (OP_IMM, SW): | |
562 | case X (OP_IMM, SL): | |
563 | return abs; | |
564 | case X (OP_DEC, SB): | |
0693d363 | 565 | abort (); |
ce51bde6 | 566 | |
0693d363 DE |
567 | case X (OP_INC, SB): |
568 | t = GET_L_REG (rn); | |
ce51bde6 | 569 | t &= cpu.mask; |
0693d363 DE |
570 | r = GET_MEMORY_B (t); |
571 | t++; | |
ce51bde6 | 572 | t = t & cpu.mask; |
0693d363 | 573 | SET_L_REG (rn, t); |
ce51bde6 DE |
574 | return r; |
575 | break; | |
0693d363 DE |
576 | case X (OP_INC, SW): |
577 | t = GET_L_REG (rn); | |
ce51bde6 | 578 | t &= cpu.mask; |
0693d363 DE |
579 | r = GET_MEMORY_W (t); |
580 | t += 2; | |
ce51bde6 | 581 | t = t & cpu.mask; |
0693d363 | 582 | SET_L_REG (rn, t); |
ce51bde6 | 583 | return r; |
0693d363 DE |
584 | case X (OP_INC, SL): |
585 | t = GET_L_REG (rn); | |
ce51bde6 | 586 | t &= cpu.mask; |
0693d363 DE |
587 | r = GET_MEMORY_L (t); |
588 | ||
589 | t += 4; | |
ce51bde6 | 590 | t = t & cpu.mask; |
0693d363 | 591 | SET_L_REG (rn, t); |
ce51bde6 | 592 | return r; |
0693d363 | 593 | |
ce51bde6 DE |
594 | case X (OP_DISP, SB): |
595 | t = GET_L_REG (rn) + abs; | |
596 | t &= cpu.mask; | |
597 | return GET_MEMORY_B (t); | |
0693d363 | 598 | |
ce51bde6 DE |
599 | case X (OP_DISP, SW): |
600 | t = GET_L_REG (rn) + abs; | |
601 | t &= cpu.mask; | |
602 | return GET_MEMORY_W (t); | |
0693d363 | 603 | |
ce51bde6 DE |
604 | case X (OP_DISP, SL): |
605 | t = GET_L_REG (rn) + abs; | |
606 | t &= cpu.mask; | |
607 | return GET_MEMORY_L (t); | |
0693d363 DE |
608 | |
609 | case X (OP_MEM, SL): | |
610 | t = GET_MEMORY_L (abs); | |
611 | t &= cpu.mask; | |
612 | return t; | |
613 | ||
e24146ec JL |
614 | case X (OP_MEM, SW): |
615 | t = GET_MEMORY_W (abs); | |
616 | t &= cpu.mask; | |
617 | return t; | |
618 | ||
ce51bde6 DE |
619 | default: |
620 | abort (); | |
0693d363 | 621 | |
ce51bde6 DE |
622 | } |
623 | } | |
624 | ||
625 | ||
0693d363 DE |
626 | static |
627 | void | |
628 | store (arg, n) | |
629 | ea_type *arg; | |
630 | int n; | |
ce51bde6 DE |
631 | { |
632 | int rn = arg->reg; | |
633 | int abs = arg->literal; | |
634 | int t; | |
0693d363 | 635 | |
ce51bde6 DE |
636 | switch (arg->type) |
637 | { | |
638 | case X (OP_REG, SB): | |
639 | SET_B_REG (rn, n); | |
640 | break; | |
641 | case X (OP_REG, SW): | |
642 | SET_W_REG (rn, n); | |
643 | break; | |
644 | case X (OP_REG, SL): | |
645 | SET_L_REG (rn, n); | |
646 | break; | |
0693d363 | 647 | |
ce51bde6 | 648 | case X (OP_DEC, SB): |
0693d363 | 649 | t = GET_L_REG (rn) - 1; |
ce51bde6 | 650 | t &= cpu.mask; |
0693d363 | 651 | SET_L_REG (rn, t); |
ce51bde6 DE |
652 | SET_MEMORY_B (t, n); |
653 | ||
654 | break; | |
655 | case X (OP_DEC, SW): | |
0693d363 | 656 | t = (GET_L_REG (rn) - 2) & cpu.mask; |
ce51bde6 DE |
657 | SET_L_REG (rn, t); |
658 | SET_MEMORY_W (t, n); | |
659 | break; | |
660 | ||
661 | case X (OP_DEC, SL): | |
0693d363 | 662 | t = (GET_L_REG (rn) - 4) & cpu.mask; |
89a2c4fd | 663 | SET_L_REG (rn, t); |
0693d363 | 664 | SET_MEMORY_L (t, n); |
ce51bde6 DE |
665 | break; |
666 | ||
ce51bde6 DE |
667 | case X (OP_DISP, SB): |
668 | t = GET_L_REG (rn) + abs; | |
669 | t &= cpu.mask; | |
670 | SET_MEMORY_B (t, n); | |
671 | break; | |
672 | ||
673 | case X (OP_DISP, SW): | |
674 | t = GET_L_REG (rn) + abs; | |
675 | t &= cpu.mask; | |
676 | SET_MEMORY_W (t, n); | |
677 | break; | |
678 | ||
679 | case X (OP_DISP, SL): | |
680 | t = GET_L_REG (rn) + abs; | |
681 | t &= cpu.mask; | |
682 | SET_MEMORY_L (t, n); | |
683 | break; | |
684 | default: | |
685 | abort (); | |
686 | } | |
687 | } | |
688 | ||
689 | ||
690 | static union | |
0693d363 DE |
691 | { |
692 | short int i; | |
693 | struct | |
694 | { | |
695 | char low; | |
696 | char high; | |
697 | } | |
698 | u; | |
699 | } | |
ce51bde6 DE |
700 | |
701 | littleendian; | |
702 | ||
703 | static | |
704 | void | |
705 | init_pointers () | |
706 | { | |
707 | static int init; | |
708 | ||
709 | if (!init) | |
710 | { | |
711 | int i; | |
712 | ||
713 | init = 1; | |
714 | littleendian.i = 1; | |
715 | ||
e656ecf9 DE |
716 | if (h8300hmode) |
717 | memory_size = H8300H_MSIZE; | |
718 | else | |
719 | memory_size = H8300_MSIZE; | |
720 | cpu.memory = (unsigned char *) calloc (sizeof (char), memory_size); | |
721 | cpu.cache_idx = (unsigned short *) calloc (sizeof (short), memory_size); | |
7e1e013f | 722 | cpu.eightbit = (unsigned char *) calloc (sizeof (char), 256); |
e656ecf9 DE |
723 | |
724 | /* `msize' must be a power of two */ | |
725 | if ((memory_size & (memory_size - 1)) != 0) | |
726 | abort (); | |
727 | cpu.mask = memory_size - 1; | |
0693d363 | 728 | |
ce51bde6 DE |
729 | for (i = 0; i < 9; i++) |
730 | { | |
731 | cpu.regs[i] = 0; | |
732 | } | |
733 | ||
734 | for (i = 0; i < 8; i++) | |
735 | { | |
736 | unsigned char *p = (unsigned char *) (cpu.regs + i); | |
737 | unsigned char *e = (unsigned char *) (cpu.regs + i + 1); | |
738 | unsigned short *q = (unsigned short *) (cpu.regs + i); | |
739 | unsigned short *u = (unsigned short *) (cpu.regs + i + 1); | |
740 | cpu.regs[i] = 0x00112233; | |
741 | while (p < e) | |
742 | { | |
743 | if (*p == 0x22) | |
744 | { | |
745 | breg[i] = p; | |
746 | } | |
747 | if (*p == 0x33) | |
748 | { | |
0693d363 | 749 | breg[i + 8] = p; |
ce51bde6 DE |
750 | } |
751 | p++; | |
752 | } | |
753 | while (q < u) | |
754 | { | |
755 | if (*q == 0x2233) | |
756 | { | |
757 | wreg[i] = q; | |
758 | } | |
759 | if (*q == 0x0011) | |
760 | { | |
761 | wreg[i + 8] = q; | |
762 | } | |
763 | q++; | |
764 | } | |
765 | cpu.regs[i] = 0; | |
766 | lreg[i] = &cpu.regs[i]; | |
767 | } | |
768 | ||
ce51bde6 | 769 | lreg[8] = &cpu.regs[8]; |
0693d363 | 770 | |
ce51bde6 DE |
771 | /* initialize the seg registers */ |
772 | if (!cpu.cache) | |
46337270 | 773 | sim_set_simcache_size (CSIZE); |
ce51bde6 DE |
774 | } |
775 | } | |
776 | ||
777 | static void | |
778 | control_c (sig, code, scp, addr) | |
779 | int sig; | |
780 | int code; | |
781 | char *scp; | |
782 | char *addr; | |
783 | { | |
46337270 | 784 | cpu.state = SIM_STATE_STOPPED; |
ce51bde6 DE |
785 | cpu.exception = SIGINT; |
786 | } | |
787 | ||
788 | #define C (c != 0) | |
789 | #define Z (nz == 0) | |
790 | #define V (v != 0) | |
791 | #define N (n != 0) | |
792 | ||
28655f00 | 793 | static int |
0693d363 | 794 | mop (code, bsize, sign) |
28655f00 SC |
795 | decoded_inst *code; |
796 | int bsize; | |
0693d363 DE |
797 | int sign; |
798 | { | |
799 | int multiplier; | |
800 | int multiplicand; | |
801 | int result; | |
802 | int n, nz; | |
803 | ||
804 | if (sign) | |
805 | { | |
806 | multiplicand = | |
807 | bsize ? SEXTCHAR (GET_W_REG (code->dst.reg)) : | |
808 | SEXTSHORT (GET_W_REG (code->dst.reg)); | |
809 | multiplier = | |
810 | bsize ? SEXTCHAR (GET_B_REG (code->src.reg)) : | |
811 | SEXTSHORT (GET_W_REG (code->src.reg)); | |
812 | } | |
813 | else | |
814 | { | |
815 | multiplicand = bsize ? UEXTCHAR (GET_W_REG (code->dst.reg)) : | |
816 | UEXTSHORT (GET_W_REG (code->dst.reg)); | |
817 | multiplier = | |
818 | bsize ? UEXTCHAR (GET_B_REG (code->src.reg)) : | |
819 | UEXTSHORT (GET_W_REG (code->src.reg)); | |
820 | ||
821 | } | |
822 | result = multiplier * multiplicand; | |
823 | ||
824 | if (sign) | |
825 | { | |
826 | n = result & (bsize ? 0x8000 : 0x80000000); | |
827 | nz = result & (bsize ? 0xffff : 0xffffffff); | |
828 | } | |
829 | if (bsize) | |
830 | { | |
831 | SET_W_REG (code->dst.reg, result); | |
832 | } | |
833 | else | |
834 | { | |
835 | SET_L_REG (code->dst.reg, result); | |
836 | } | |
837 | /* return ((n==1) << 1) | (nz==1); */ | |
838 | ||
839 | } | |
840 | ||
7647e0dd | 841 | #define ONOT(name, how) \ |
0693d363 DE |
842 | case O(name, SB): \ |
843 | { \ | |
844 | int t; \ | |
845 | int hm = 0x80; \ | |
846 | rd = GET_B_REG (code->src.reg); \ | |
847 | how; \ | |
848 | goto shift8; \ | |
849 | } \ | |
850 | case O(name, SW): \ | |
851 | { \ | |
852 | int t; \ | |
853 | int hm = 0x8000; \ | |
854 | rd = GET_W_REG (code->src.reg); \ | |
855 | how; \ | |
856 | goto shift16; \ | |
857 | } \ | |
858 | case O(name, SL): \ | |
859 | { \ | |
860 | int t; \ | |
861 | int hm = 0x80000000; \ | |
862 | rd = GET_L_REG (code->src.reg); \ | |
863 | how; \ | |
864 | goto shift32; \ | |
865 | } | |
866 | ||
7647e0dd JL |
867 | #define OSHIFTS(name, how1, how2) \ |
868 | case O(name, SB): \ | |
869 | { \ | |
870 | int t; \ | |
871 | int hm = 0x80; \ | |
872 | rd = GET_B_REG (code->src.reg); \ | |
873 | if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \ | |
874 | { \ | |
875 | how1; \ | |
876 | } \ | |
877 | else \ | |
878 | { \ | |
879 | how2; \ | |
880 | } \ | |
881 | goto shift8; \ | |
882 | } \ | |
883 | case O(name, SW): \ | |
884 | { \ | |
885 | int t; \ | |
886 | int hm = 0x8000; \ | |
887 | rd = GET_W_REG (code->src.reg); \ | |
888 | if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \ | |
889 | { \ | |
890 | how1; \ | |
891 | } \ | |
892 | else \ | |
893 | { \ | |
894 | how2; \ | |
895 | } \ | |
896 | goto shift16; \ | |
897 | } \ | |
898 | case O(name, SL): \ | |
899 | { \ | |
900 | int t; \ | |
901 | int hm = 0x80000000; \ | |
902 | rd = GET_L_REG (code->src.reg); \ | |
903 | if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \ | |
904 | { \ | |
905 | how1; \ | |
906 | } \ | |
907 | else \ | |
908 | { \ | |
909 | how2; \ | |
910 | } \ | |
911 | goto shift32; \ | |
912 | } | |
913 | ||
0693d363 DE |
914 | #define OBITOP(name,f, s, op) \ |
915 | case O(name, SB): \ | |
916 | { \ | |
917 | int m; \ | |
918 | int b; \ | |
919 | if (f) ea = fetch (&code->dst); \ | |
920 | m=1<< fetch(&code->src); \ | |
921 | op; \ | |
922 | if(s) store (&code->dst,ea); goto next; \ | |
923 | } | |
28655f00 | 924 | |
247fccde AC |
925 | int |
926 | sim_stop (sd) | |
927 | SIM_DESC sd; | |
928 | { | |
929 | cpu.state = SIM_STATE_STOPPED; | |
930 | cpu.exception = SIGINT; | |
931 | return 1; | |
932 | } | |
933 | ||
7478904c | 934 | void |
46337270 DE |
935 | sim_resume (sd, step, siggnal) |
936 | SIM_DESC sd; | |
ce51bde6 DE |
937 | { |
938 | static int init1; | |
939 | int cycles = 0; | |
940 | int insts = 0; | |
941 | int tick_start = get_now (); | |
942 | void (*prev) (); | |
0693d363 | 943 | int poll_count = 0; |
ce51bde6 DE |
944 | int res; |
945 | int tmp; | |
946 | int rd; | |
947 | int ea; | |
948 | int bit; | |
949 | int pc; | |
950 | int c, nz, v, n; | |
7478904c | 951 | int oldmask; |
ce51bde6 DE |
952 | init_pointers (); |
953 | ||
954 | prev = signal (SIGINT, control_c); | |
955 | ||
956 | if (step) | |
957 | { | |
46337270 | 958 | cpu.state = SIM_STATE_STOPPED; |
ce51bde6 DE |
959 | cpu.exception = SIGTRAP; |
960 | } | |
961 | else | |
962 | { | |
46337270 | 963 | cpu.state = SIM_STATE_RUNNING; |
ce51bde6 DE |
964 | cpu.exception = 0; |
965 | } | |
966 | ||
967 | pc = cpu.pc; | |
968 | ||
7e1e013f JL |
969 | /* The PC should never be odd. */ |
970 | if (pc & 0x1) | |
971 | abort (); | |
972 | ||
ce51bde6 | 973 | GETSR (); |
7478904c SC |
974 | oldmask = cpu.mask; |
975 | if (!h8300hmode) | |
976 | cpu.mask = 0xffff; | |
ce51bde6 DE |
977 | do |
978 | { | |
979 | int cidx; | |
980 | decoded_inst *code; | |
981 | ||
982 | top: | |
983 | cidx = cpu.cache_idx[pc]; | |
984 | code = cpu.cache + cidx; | |
985 | ||
986 | ||
987 | #define ALUOP(STORE, NAME, HOW) \ | |
988 | case O(NAME,SB): HOW; if(STORE)goto alu8;else goto just_flags_alu8; \ | |
989 | case O(NAME, SW): HOW; if(STORE)goto alu16;else goto just_flags_alu16; \ | |
990 | case O(NAME,SL): HOW; if(STORE)goto alu32;else goto just_flags_alu32; | |
991 | ||
992 | ||
993 | #define LOGOP(NAME, HOW) \ | |
994 | case O(NAME,SB): HOW; goto log8;\ | |
995 | case O(NAME, SW): HOW; goto log16;\ | |
996 | case O(NAME,SL): HOW; goto log32; | |
997 | ||
998 | ||
999 | ||
1000 | #if ADEBUG | |
1001 | if (debug) | |
1002 | { | |
1003 | printf ("%x %d %s\n", pc, code->opcode, | |
1004 | code->op ? code->op->name : "**"); | |
1005 | } | |
1006 | cpu.stats[code->opcode]++; | |
0693d363 | 1007 | |
ce51bde6 DE |
1008 | #endif |
1009 | ||
1010 | cycles += code->cycles; | |
1011 | insts++; | |
1012 | switch (code->opcode) | |
1013 | { | |
1014 | case 0: | |
1015 | /* | |
1016 | * This opcode is a fake for when we get to an | |
1017 | * instruction which hasnt been compiled | |
1018 | */ | |
1019 | compile (pc); | |
1020 | goto top; | |
1021 | break; | |
1022 | ||
1023 | ||
1024 | case O (O_SUBX, SB): | |
1025 | rd = fetch (&code->dst); | |
1026 | ea = fetch (&code->src); | |
0693d363 | 1027 | ea = -(ea + C); |
ce51bde6 DE |
1028 | res = rd + ea; |
1029 | goto alu8; | |
1030 | ||
1031 | case O (O_ADDX, SB): | |
1032 | rd = fetch (&code->dst); | |
1033 | ea = fetch (&code->src); | |
1034 | ea = C + ea; | |
1035 | res = rd + ea; | |
1036 | goto alu8; | |
1037 | ||
cf5b4aa6 DE |
1038 | #define EA ea = fetch(&code->src); |
1039 | #define RD_EA ea = fetch(&code->src); rd = fetch(&code->dst); | |
ce51bde6 | 1040 | |
0693d363 DE |
1041 | ALUOP (1, O_SUB, RD_EA; |
1042 | ea = -ea; | |
1043 | res = rd + ea); | |
1044 | ALUOP (1, O_NEG, EA; | |
1045 | ea = -ea; | |
1046 | rd = 0; | |
1047 | res = rd + ea); | |
ce51bde6 | 1048 | |
0693d363 DE |
1049 | case O (O_ADD, SB): |
1050 | rd = GET_B_REG (code->dst.reg); | |
1051 | ea = fetch (&code->src); | |
ce51bde6 DE |
1052 | res = rd + ea; |
1053 | goto alu8; | |
0693d363 DE |
1054 | case O (O_ADD, SW): |
1055 | rd = GET_W_REG (code->dst.reg); | |
1056 | ea = fetch (&code->src); | |
ce51bde6 DE |
1057 | res = rd + ea; |
1058 | goto alu16; | |
0693d363 DE |
1059 | case O (O_ADD, SL): |
1060 | rd = GET_L_REG (code->dst.reg); | |
1061 | ea = fetch (&code->src); | |
ce51bde6 DE |
1062 | res = rd + ea; |
1063 | goto alu32; | |
ce51bde6 | 1064 | |
ce51bde6 | 1065 | |
0693d363 DE |
1066 | LOGOP (O_AND, RD_EA; |
1067 | res = rd & ea); | |
1068 | ||
1069 | LOGOP (O_OR, RD_EA; | |
1070 | res = rd | ea); | |
ce51bde6 | 1071 | |
0693d363 DE |
1072 | LOGOP (O_XOR, RD_EA; |
1073 | res = rd ^ ea); | |
ce51bde6 DE |
1074 | |
1075 | ||
0693d363 DE |
1076 | case O (O_MOV_TO_MEM, SB): |
1077 | res = GET_B_REG (code->src.reg); | |
ce51bde6 | 1078 | goto log8; |
0693d363 DE |
1079 | case O (O_MOV_TO_MEM, SW): |
1080 | res = GET_W_REG (code->src.reg); | |
ce51bde6 | 1081 | goto log16; |
0693d363 DE |
1082 | case O (O_MOV_TO_MEM, SL): |
1083 | res = GET_L_REG (code->src.reg); | |
ce51bde6 DE |
1084 | goto log32; |
1085 | ||
1086 | ||
0693d363 DE |
1087 | case O (O_MOV_TO_REG, SB): |
1088 | res = fetch (&code->src); | |
1089 | SET_B_REG (code->dst.reg, res); | |
ce51bde6 | 1090 | goto just_flags_log8; |
0693d363 DE |
1091 | case O (O_MOV_TO_REG, SW): |
1092 | res = fetch (&code->src); | |
1093 | SET_W_REG (code->dst.reg, res); | |
ce51bde6 | 1094 | goto just_flags_log16; |
0693d363 DE |
1095 | case O (O_MOV_TO_REG, SL): |
1096 | res = fetch (&code->src); | |
1097 | SET_L_REG (code->dst.reg, res); | |
ce51bde6 DE |
1098 | goto just_flags_log32; |
1099 | ||
1100 | ||
0693d363 DE |
1101 | case O (O_ADDS, SL): |
1102 | SET_L_REG (code->dst.reg, | |
1103 | GET_L_REG (code->dst.reg) | |
1104 | + code->src.literal); | |
1105 | ||
ce51bde6 DE |
1106 | goto next; |
1107 | ||
0693d363 DE |
1108 | case O (O_SUBS, SL): |
1109 | SET_L_REG (code->dst.reg, | |
1110 | GET_L_REG (code->dst.reg) | |
1111 | - code->src.literal); | |
ce51bde6 | 1112 | goto next; |
0693d363 | 1113 | |
ce51bde6 DE |
1114 | case O (O_CMP, SB): |
1115 | rd = fetch (&code->dst); | |
1116 | ea = fetch (&code->src); | |
1117 | ea = -ea; | |
1118 | res = rd + ea; | |
1119 | goto just_flags_alu8; | |
1120 | ||
1121 | case O (O_CMP, SW): | |
1122 | rd = fetch (&code->dst); | |
1123 | ea = fetch (&code->src); | |
1124 | ea = -ea; | |
1125 | res = rd + ea; | |
1126 | goto just_flags_alu16; | |
1127 | ||
1128 | case O (O_CMP, SL): | |
1129 | rd = fetch (&code->dst); | |
1130 | ea = fetch (&code->src); | |
1131 | ea = -ea; | |
1132 | res = rd + ea; | |
1133 | goto just_flags_alu32; | |
1134 | ||
1135 | ||
1136 | case O (O_DEC, SB): | |
1137 | rd = GET_B_REG (code->src.reg); | |
1138 | ea = -1; | |
1139 | res = rd + ea; | |
1140 | SET_B_REG (code->src.reg, res); | |
1141 | goto just_flags_inc8; | |
1142 | ||
1143 | case O (O_DEC, SW): | |
1144 | rd = GET_W_REG (code->dst.reg); | |
0693d363 | 1145 | ea = -code->src.literal; |
ce51bde6 DE |
1146 | res = rd + ea; |
1147 | SET_W_REG (code->dst.reg, res); | |
1148 | goto just_flags_inc16; | |
1149 | ||
1150 | case O (O_DEC, SL): | |
1151 | rd = GET_L_REG (code->dst.reg); | |
1152 | ea = -code->src.literal; | |
1153 | res = rd + ea; | |
1154 | SET_L_REG (code->dst.reg, res); | |
1155 | goto just_flags_inc32; | |
1156 | ||
1157 | ||
1158 | case O (O_INC, SB): | |
1159 | rd = GET_B_REG (code->src.reg); | |
1160 | ea = 1; | |
1161 | res = rd + ea; | |
1162 | SET_B_REG (code->src.reg, res); | |
1163 | goto just_flags_inc8; | |
1164 | ||
1165 | case O (O_INC, SW): | |
1166 | rd = GET_W_REG (code->dst.reg); | |
1167 | ea = code->src.literal; | |
1168 | res = rd + ea; | |
1169 | SET_W_REG (code->dst.reg, res); | |
1170 | goto just_flags_inc16; | |
1171 | ||
1172 | case O (O_INC, SL): | |
1173 | rd = GET_L_REG (code->dst.reg); | |
1174 | ea = code->src.literal; | |
1175 | res = rd + ea; | |
1176 | SET_L_REG (code->dst.reg, res); | |
1177 | goto just_flags_inc32; | |
1178 | ||
1179 | ||
1180 | #define GET_CCR(x) BUILDSR();x = cpu.ccr | |
0693d363 | 1181 | |
ce51bde6 DE |
1182 | case O (O_ANDC, SB): |
1183 | GET_CCR (rd); | |
1184 | ea = code->src.literal; | |
1185 | res = rd & ea; | |
1186 | goto setc; | |
1187 | ||
0693d363 DE |
1188 | case O (O_ORC, SB): |
1189 | GET_CCR (rd); | |
1190 | ea = code->src.literal; | |
1191 | res = rd | ea; | |
1192 | goto setc; | |
1193 | ||
1194 | case O (O_XORC, SB): | |
1195 | GET_CCR (rd); | |
1196 | ea = code->src.literal; | |
1197 | res = rd ^ ea; | |
1198 | goto setc; | |
1199 | ||
ce51bde6 DE |
1200 | |
1201 | case O (O_BRA, SB): | |
1202 | if (1) | |
1203 | goto condtrue; | |
1204 | goto next; | |
1205 | ||
1206 | case O (O_BRN, SB): | |
1207 | if (0) | |
1208 | goto condtrue; | |
1209 | goto next; | |
1210 | ||
1211 | case O (O_BHI, SB): | |
1212 | if ((C || Z) == 0) | |
1213 | goto condtrue; | |
1214 | goto next; | |
1215 | ||
1216 | ||
1217 | case O (O_BLS, SB): | |
1218 | if ((C || Z)) | |
1219 | goto condtrue; | |
1220 | goto next; | |
1221 | ||
1222 | case O (O_BCS, SB): | |
1223 | if ((C == 1)) | |
1224 | goto condtrue; | |
1225 | goto next; | |
1226 | ||
1227 | case O (O_BCC, SB): | |
1228 | if ((C == 0)) | |
1229 | goto condtrue; | |
1230 | goto next; | |
1231 | ||
1232 | case O (O_BEQ, SB): | |
1233 | if (Z) | |
1234 | goto condtrue; | |
1235 | goto next; | |
1236 | case O (O_BGT, SB): | |
1237 | if (((Z || (N ^ V)) == 0)) | |
1238 | goto condtrue; | |
1239 | goto next; | |
1240 | ||
1241 | ||
1242 | case O (O_BLE, SB): | |
1243 | if (((Z || (N ^ V)) == 1)) | |
1244 | goto condtrue; | |
1245 | goto next; | |
1246 | ||
1247 | case O (O_BGE, SB): | |
1248 | if ((N ^ V) == 0) | |
1249 | goto condtrue; | |
1250 | goto next; | |
1251 | case O (O_BLT, SB): | |
1252 | if ((N ^ V)) | |
1253 | goto condtrue; | |
1254 | goto next; | |
1255 | case O (O_BMI, SB): | |
1256 | if ((N)) | |
1257 | goto condtrue; | |
1258 | goto next; | |
1259 | case O (O_BNE, SB): | |
1260 | if ((Z == 0)) | |
1261 | goto condtrue; | |
1262 | goto next; | |
1263 | ||
1264 | case O (O_BPL, SB): | |
1265 | if (N == 0) | |
1266 | goto condtrue; | |
1267 | goto next; | |
1268 | case O (O_BVC, SB): | |
1269 | if ((V == 0)) | |
1270 | goto condtrue; | |
1271 | goto next; | |
1272 | case O (O_BVS, SB): | |
1273 | if ((V == 1)) | |
1274 | goto condtrue; | |
1275 | goto next; | |
1276 | ||
0693d363 | 1277 | case O (O_SYSCALL, SB): |
9e03a68f AC |
1278 | { |
1279 | char c = cpu.regs[2]; | |
1280 | sim_callback->write_stdout (sim_callback, &c, 1); | |
1281 | } | |
ce51bde6 | 1282 | goto next; |
ce51bde6 | 1283 | |
7647e0dd JL |
1284 | ONOT (O_NOT, rd = ~rd; v = 0;); |
1285 | OSHIFTS (O_SHLL, | |
1286 | c = rd & hm; v = 0; rd <<= 1, | |
1287 | c = rd & (hm >> 1); v = 0; rd <<= 2); | |
1288 | OSHIFTS (O_SHLR, | |
1289 | c = rd & 1; v = 0; rd = (unsigned int) rd >> 1, | |
1290 | c = rd & 2; v = 0; rd = (unsigned int) rd >> 2); | |
1291 | OSHIFTS (O_SHAL, | |
1292 | c = rd & hm; v = (rd & hm) != ((rd & (hm >> 1)) << 1); rd <<= 1, | |
1293 | c = rd & (hm >> 1); v = (rd & (hm >> 1)) != ((rd & (hm >> 2)) << 2); rd <<= 2); | |
1294 | OSHIFTS (O_SHAR, | |
1295 | t = rd & hm; c = rd & 1; v = 0; rd >>= 1; rd |= t, | |
1296 | t = rd & hm; c = rd & 2; v = 0; rd >>= 2; rd |= t | t >> 1 ); | |
1297 | OSHIFTS (O_ROTL, | |
1298 | c = rd & hm; v = 0; rd <<= 1; rd |= C, | |
9745c593 | 1299 | c = rd & hm; v = 0; rd <<= 1; rd |= C; c = rd & hm; rd <<= 1; rd |= C); |
7647e0dd JL |
1300 | OSHIFTS (O_ROTR, |
1301 | c = rd & 1; v = 0; rd = (unsigned int) rd >> 1; if (c) rd |= hm, | |
9745c593 | 1302 | c = rd & 1; v = 0; rd = (unsigned int) rd >> 1; if (c) rd |= hm; c = rd & 1; rd = (unsigned int) rd >> 1; if (c) rd |= hm); |
7647e0dd JL |
1303 | OSHIFTS (O_ROTXL, |
1304 | t = rd & hm; rd <<= 1; rd |= C; c = t; v = 0, | |
9745c593 | 1305 | t = rd & hm; rd <<= 1; rd |= C; c = t; v = 0; t = rd & hm; rd <<= 1; rd |= C; c = t); |
7647e0dd JL |
1306 | OSHIFTS (O_ROTXR, |
1307 | t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd |= hm; c = t; v = 0, | |
9745c593 | 1308 | t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd |= hm; c = t; v = 0; t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd |= hm; c = t); |
0693d363 DE |
1309 | |
1310 | case O (O_JMP, SB): | |
ce51bde6 DE |
1311 | { |
1312 | pc = fetch (&code->src); | |
1313 | goto end; | |
0693d363 | 1314 | |
ce51bde6 | 1315 | } |
0693d363 | 1316 | |
ce51bde6 DE |
1317 | case O (O_JSR, SB): |
1318 | { | |
1319 | int tmp; | |
1320 | pc = fetch (&code->src); | |
1321 | call: | |
1322 | tmp = cpu.regs[7]; | |
1323 | ||
28655f00 | 1324 | if (h8300hmode) |
ce51bde6 DE |
1325 | { |
1326 | tmp -= 4; | |
1327 | SET_MEMORY_L (tmp, code->next_pc); | |
1328 | } | |
1329 | else | |
1330 | { | |
1331 | tmp -= 2; | |
1332 | SET_MEMORY_W (tmp, code->next_pc); | |
1333 | } | |
1334 | cpu.regs[7] = tmp; | |
1335 | ||
1336 | goto end; | |
1337 | } | |
0693d363 | 1338 | case O (O_BSR, SB): |
ce51bde6 DE |
1339 | pc = code->src.literal; |
1340 | goto call; | |
0693d363 | 1341 | |
46337270 | 1342 | case O (O_RTS, SN): |
ce51bde6 DE |
1343 | { |
1344 | int tmp; | |
1345 | ||
ce51bde6 DE |
1346 | tmp = cpu.regs[7]; |
1347 | ||
28655f00 | 1348 | if (h8300hmode) |
ce51bde6 DE |
1349 | { |
1350 | pc = GET_MEMORY_L (tmp); | |
1351 | tmp += 4; | |
ce51bde6 DE |
1352 | } |
1353 | else | |
1354 | { | |
1355 | pc = GET_MEMORY_W (tmp); | |
1356 | tmp += 2; | |
1357 | } | |
1358 | ||
1359 | cpu.regs[7] = tmp; | |
1360 | goto end; | |
1361 | } | |
1362 | ||
1363 | case O (O_ILL, SB): | |
46337270 | 1364 | cpu.state = SIM_STATE_STOPPED; |
ce51bde6 DE |
1365 | cpu.exception = SIGILL; |
1366 | goto end; | |
46337270 DE |
1367 | case O (O_SLEEP, SN): |
1368 | /* The format of r0 is defined by devo/include/wait.h. */ | |
1369 | #if 0 /* FIXME: Ugh. A breakpoint is the sleep insn. */ | |
1370 | if (WIFEXITED (cpu.regs[0])) | |
1371 | { | |
1372 | cpu.state = SIM_STATE_EXITED; | |
1373 | cpu.exception = WEXITSTATUS (cpu.regs[0]); | |
1374 | } | |
1375 | else if (WIFSTOPPED (cpu.regs[0])) | |
1376 | { | |
1377 | cpu.state = SIM_STATE_STOPPED; | |
1378 | cpu.exception = WSTOPSIG (cpu.regs[0]); | |
1379 | } | |
1380 | else | |
1381 | { | |
1382 | cpu.state = SIM_STATE_SIGNALLED; | |
1383 | cpu.exception = WTERMSIG (cpu.regs[0]); | |
1384 | } | |
1385 | #else | |
1386 | /* FIXME: Doesn't this break for breakpoints when r0 | |
1387 | contains just the right (er, wrong) value? */ | |
1388 | cpu.state = SIM_STATE_STOPPED; | |
4dfb4ffc | 1389 | if (! WIFEXITED (cpu.regs[0]) && WIFSIGNALED (cpu.regs[0])) |
e656ecf9 DE |
1390 | cpu.exception = SIGILL; |
1391 | else | |
1392 | cpu.exception = SIGTRAP; | |
46337270 | 1393 | #endif |
e656ecf9 | 1394 | goto end; |
46337270 DE |
1395 | case O (O_BPT, SN): |
1396 | cpu.state = SIM_STATE_STOPPED; | |
ce51bde6 DE |
1397 | cpu.exception = SIGTRAP; |
1398 | goto end; | |
1399 | ||
0693d363 DE |
1400 | OBITOP (O_BNOT, 1, 1, ea ^= m); |
1401 | OBITOP (O_BTST, 1, 0, nz = ea & m); | |
1402 | OBITOP (O_BCLR, 1, 1, ea &= ~m); | |
1403 | OBITOP (O_BSET, 1, 1, ea |= m); | |
1404 | OBITOP (O_BLD, 1, 0, c = ea & m); | |
1405 | OBITOP (O_BILD, 1, 0, c = !(ea & m)); | |
1406 | OBITOP (O_BST, 1, 1, ea &= ~m; | |
1407 | if (C) ea |= m); | |
1408 | OBITOP (O_BIST, 1, 1, ea &= ~m; | |
1409 | if (!C) ea |= m); | |
1410 | OBITOP (O_BAND, 1, 0, c = (ea & m) && C); | |
1411 | OBITOP (O_BIAND, 1, 0, c = !(ea & m) && C); | |
1412 | OBITOP (O_BOR, 1, 0, c = (ea & m) || C); | |
1413 | OBITOP (O_BIOR, 1, 0, c = !(ea & m) || C); | |
1414 | OBITOP (O_BXOR, 1, 0, c = (ea & m) != C); | |
1415 | OBITOP (O_BIXOR, 1, 0, c = !(ea & m) != C); | |
ce51bde6 DE |
1416 | |
1417 | ||
28655f00 | 1418 | #define MOP(bsize, signed) mop(code, bsize,signed); goto next; |
ce51bde6 | 1419 | |
0693d363 DE |
1420 | case O (O_MULS, SB): |
1421 | MOP (1, 1); | |
1422 | break; | |
1423 | case O (O_MULS, SW): | |
1424 | MOP (0, 1); | |
1425 | break; | |
1426 | case O (O_MULU, SB): | |
1427 | MOP (1, 0); | |
1428 | break; | |
1429 | case O (O_MULU, SW): | |
1430 | MOP (0, 0); | |
1431 | break; | |
ce51bde6 | 1432 | |
ce51bde6 | 1433 | |
0693d363 DE |
1434 | case O (O_DIVU, SB): |
1435 | { | |
1436 | rd = GET_W_REG (code->dst.reg); | |
1437 | ea = GET_B_REG (code->src.reg); | |
1438 | if (ea) | |
1439 | { | |
7e1e013f JL |
1440 | tmp = (unsigned)rd % ea; |
1441 | rd = (unsigned)rd / ea; | |
0693d363 DE |
1442 | } |
1443 | SET_W_REG (code->dst.reg, (rd & 0xff) | (tmp << 8)); | |
1444 | n = ea & 0x80; | |
1445 | nz = ea & 0xff; | |
ce51bde6 | 1446 | |
0693d363 DE |
1447 | goto next; |
1448 | } | |
1449 | case O (O_DIVU, SW): | |
1450 | { | |
1451 | rd = GET_L_REG (code->dst.reg); | |
1452 | ea = GET_W_REG (code->src.reg); | |
1453 | n = ea & 0x8000; | |
1454 | nz = ea & 0xffff; | |
1455 | if (ea) | |
1456 | { | |
7e1e013f JL |
1457 | tmp = (unsigned)rd % ea; |
1458 | rd = (unsigned)rd / ea; | |
0693d363 DE |
1459 | } |
1460 | SET_L_REG (code->dst.reg, (rd & 0xffff) | (tmp << 16)); | |
1461 | goto next; | |
1462 | } | |
ce51bde6 | 1463 | |
0693d363 DE |
1464 | case O (O_DIVS, SB): |
1465 | { | |
ce51bde6 | 1466 | |
0693d363 DE |
1467 | rd = SEXTSHORT (GET_W_REG (code->dst.reg)); |
1468 | ea = SEXTCHAR (GET_B_REG (code->src.reg)); | |
1469 | if (ea) | |
1470 | { | |
1471 | tmp = (int) rd % (int) ea; | |
1472 | rd = (int) rd / (int) ea; | |
1473 | n = rd & 0x8000; | |
1474 | nz = 1; | |
1475 | } | |
1476 | else | |
1477 | nz = 0; | |
1478 | SET_W_REG (code->dst.reg, (rd & 0xff) | (tmp << 8)); | |
1479 | goto next; | |
1480 | } | |
1481 | case O (O_DIVS, SW): | |
1482 | { | |
1483 | rd = GET_L_REG (code->dst.reg); | |
1484 | ea = SEXTSHORT (GET_W_REG (code->src.reg)); | |
1485 | if (ea) | |
1486 | { | |
1487 | tmp = (int) rd % (int) ea; | |
1488 | rd = (int) rd / (int) ea; | |
1489 | n = rd & 0x80000000; | |
1490 | nz = 1; | |
1491 | } | |
1492 | else | |
1493 | nz = 0; | |
1494 | SET_L_REG (code->dst.reg, (rd & 0xffff) | (tmp << 16)); | |
1495 | goto next; | |
1496 | } | |
1497 | case O (O_EXTS, SW): | |
7478904c | 1498 | rd = GET_B_REG (code->src.reg + 8) & 0xff; /* Yes, src, not dst. */ |
0693d363 DE |
1499 | ea = rd & 0x80 ? -256 : 0; |
1500 | res = rd + ea; | |
1501 | goto log16; | |
1502 | case O (O_EXTS, SL): | |
1503 | rd = GET_W_REG (code->src.reg) & 0xffff; | |
1504 | ea = rd & 0x8000 ? -65536 : 0; | |
1505 | res = rd + ea; | |
1506 | goto log32; | |
1507 | case O (O_EXTU, SW): | |
1508 | rd = GET_B_REG (code->src.reg + 8) & 0xff; | |
1509 | ea = 0; | |
1510 | res = rd + ea; | |
1511 | goto log16; | |
1512 | case O (O_EXTU, SL): | |
1513 | rd = GET_W_REG (code->src.reg) & 0xffff; | |
1514 | ea = 0; | |
1515 | res = rd + ea; | |
1516 | goto log32; | |
ce51bde6 | 1517 | |
46337270 | 1518 | case O (O_NOP, SN): |
0693d363 | 1519 | goto next; |
ce51bde6 | 1520 | |
171f4664 JL |
1521 | case O (O_STM, SL): |
1522 | { | |
1523 | int nregs, firstreg, i; | |
1524 | ||
1525 | nregs = GET_MEMORY_B (pc + 1); | |
1526 | nregs >>= 4; | |
1527 | nregs &= 0xf; | |
1528 | firstreg = GET_MEMORY_B (pc + 3); | |
1529 | firstreg &= 0xf; | |
1530 | for (i = firstreg; i <= firstreg + nregs; i++) | |
1531 | { | |
1532 | cpu.regs[7] -= 4; | |
1533 | SET_MEMORY_L (cpu.regs[7], cpu.regs[i]); | |
1534 | } | |
1535 | } | |
1536 | goto next; | |
1537 | ||
1538 | case O (O_LDM, SL): | |
1539 | { | |
1540 | int nregs, firstreg, i; | |
1541 | ||
1542 | nregs = GET_MEMORY_B (pc + 1); | |
1543 | nregs >>= 4; | |
1544 | nregs &= 0xf; | |
1545 | firstreg = GET_MEMORY_B (pc + 3); | |
1546 | firstreg &= 0xf; | |
1547 | for (i = firstreg; i >= firstreg - nregs; i--) | |
1548 | { | |
1549 | cpu.regs[i] = GET_MEMORY_L (cpu.regs[7]); | |
1550 | cpu.regs[7] += 4; | |
1551 | } | |
1552 | } | |
1553 | goto next; | |
1554 | ||
0693d363 | 1555 | default: |
46337270 | 1556 | cpu.state = SIM_STATE_STOPPED; |
7478904c | 1557 | cpu.exception = SIGILL; |
0693d363 | 1558 | goto end; |
ce51bde6 DE |
1559 | |
1560 | } | |
0693d363 DE |
1561 | abort (); |
1562 | ||
1563 | setc: | |
1564 | cpu.ccr = res; | |
1565 | GETSR (); | |
28655f00 SC |
1566 | goto next; |
1567 | ||
0693d363 DE |
1568 | condtrue: |
1569 | /* When a branch works */ | |
1570 | pc = code->src.literal; | |
ce51bde6 DE |
1571 | goto end; |
1572 | ||
0693d363 DE |
1573 | /* Set the cond codes from res */ |
1574 | bitop: | |
ce51bde6 | 1575 | |
0693d363 DE |
1576 | /* Set the flags after an 8 bit inc/dec operation */ |
1577 | just_flags_inc8: | |
1578 | n = res & 0x80; | |
1579 | nz = res & 0xff; | |
1580 | v = (rd & 0x7f) == 0x7f; | |
1581 | goto next; | |
ce51bde6 | 1582 | |
ce51bde6 | 1583 | |
0693d363 DE |
1584 | /* Set the flags after an 16 bit inc/dec operation */ |
1585 | just_flags_inc16: | |
1586 | n = res & 0x8000; | |
1587 | nz = res & 0xffff; | |
1588 | v = (rd & 0x7fff) == 0x7fff; | |
1589 | goto next; | |
1590 | ||
1591 | ||
1592 | /* Set the flags after an 32 bit inc/dec operation */ | |
1593 | just_flags_inc32: | |
1594 | n = res & 0x80000000; | |
1595 | nz = res & 0xffffffff; | |
1596 | v = (rd & 0x7fffffff) == 0x7fffffff; | |
1597 | goto next; | |
1598 | ||
1599 | ||
1600 | shift8: | |
5d06fa80 | 1601 | /* Set flags after an 8 bit shift op, carry,overflow set in insn */ |
0693d363 | 1602 | n = (rd & 0x80); |
0693d363 DE |
1603 | nz = rd & 0xff; |
1604 | SET_B_REG (code->src.reg, rd); | |
1605 | goto next; | |
1606 | ||
0693d363 | 1607 | shift16: |
5d06fa80 | 1608 | /* Set flags after an 16 bit shift op, carry,overflow set in insn */ |
0693d363 | 1609 | n = (rd & 0x8000); |
0693d363 | 1610 | nz = rd & 0xffff; |
0693d363 DE |
1611 | SET_W_REG (code->src.reg, rd); |
1612 | goto next; | |
1613 | ||
1614 | shift32: | |
5d06fa80 | 1615 | /* Set flags after an 32 bit shift op, carry,overflow set in insn */ |
0693d363 | 1616 | n = (rd & 0x80000000); |
0693d363 DE |
1617 | nz = rd & 0xffffffff; |
1618 | SET_L_REG (code->src.reg, rd); | |
1619 | goto next; | |
1620 | ||
1621 | log32: | |
1622 | store (&code->dst, res); | |
1623 | just_flags_log32: | |
1624 | /* flags after a 32bit logical operation */ | |
1625 | n = res & 0x80000000; | |
1626 | nz = res & 0xffffffff; | |
1627 | v = 0; | |
1628 | goto next; | |
1629 | ||
1630 | log16: | |
1631 | store (&code->dst, res); | |
1632 | just_flags_log16: | |
1633 | /* flags after a 16bit logical operation */ | |
1634 | n = res & 0x8000; | |
1635 | nz = res & 0xffff; | |
1636 | v = 0; | |
1637 | goto next; | |
1638 | ||
1639 | ||
1640 | log8: | |
1641 | store (&code->dst, res); | |
1642 | just_flags_log8: | |
1643 | n = res & 0x80; | |
1644 | nz = res & 0xff; | |
1645 | v = 0; | |
1646 | goto next; | |
1647 | ||
1648 | alu8: | |
1649 | SET_B_REG (code->dst.reg, res); | |
1650 | just_flags_alu8: | |
1651 | n = res & 0x80; | |
1652 | nz = res & 0xff; | |
0693d363 | 1653 | c = (res & 0x100); |
50d45d1b JL |
1654 | switch (code->opcode / 4) |
1655 | { | |
1656 | case O_ADD: | |
1657 | v = ((rd & 0x80) == (ea & 0x80) | |
1658 | && (rd & 0x80) != (res & 0x80)); | |
1659 | break; | |
1660 | case O_SUB: | |
1661 | case O_CMP: | |
1662 | v = ((rd & 0x80) != (-ea & 0x80) | |
1663 | && (rd & 0x80) != (res & 0x80)); | |
1664 | break; | |
1665 | case O_NEG: | |
1666 | v = (rd == 0x80); | |
1667 | break; | |
1668 | } | |
0693d363 DE |
1669 | goto next; |
1670 | ||
1671 | alu16: | |
1672 | SET_W_REG (code->dst.reg, res); | |
1673 | just_flags_alu16: | |
1674 | n = res & 0x8000; | |
1675 | nz = res & 0xffff; | |
0693d363 | 1676 | c = (res & 0x10000); |
50d45d1b JL |
1677 | switch (code->opcode / 4) |
1678 | { | |
1679 | case O_ADD: | |
1680 | v = ((rd & 0x8000) == (ea & 0x8000) | |
1681 | && (rd & 0x8000) != (res & 0x8000)); | |
1682 | break; | |
1683 | case O_SUB: | |
1684 | case O_CMP: | |
1685 | v = ((rd & 0x8000) != (-ea & 0x8000) | |
1686 | && (rd & 0x8000) != (res & 0x8000)); | |
1687 | break; | |
1688 | case O_NEG: | |
1689 | v = (rd == 0x8000); | |
1690 | break; | |
1691 | } | |
0693d363 DE |
1692 | goto next; |
1693 | ||
1694 | alu32: | |
1695 | SET_L_REG (code->dst.reg, res); | |
1696 | just_flags_alu32: | |
1697 | n = res & 0x80000000; | |
1698 | nz = res & 0xffffffff; | |
50d45d1b JL |
1699 | switch (code->opcode / 4) |
1700 | { | |
1701 | case O_ADD: | |
1702 | v = ((rd & 0x80000000) == (ea & 0x80000000) | |
1703 | && (rd & 0x80000000) != (res & 0x80000000)); | |
9b127161 | 1704 | c = ((unsigned) res < (unsigned) rd) || ((unsigned) res < (unsigned) ea); |
50d45d1b JL |
1705 | break; |
1706 | case O_SUB: | |
1707 | case O_CMP: | |
1708 | v = ((rd & 0x80000000) != (-ea & 0x80000000) | |
1709 | && (rd & 0x80000000) != (res & 0x80000000)); | |
0693d363 DE |
1710 | c = (unsigned) rd < (unsigned) -ea; |
1711 | break; | |
1712 | case O_NEG: | |
9b127161 | 1713 | v = (rd == 0x80000000); |
0693d363 DE |
1714 | c = res != 0; |
1715 | break; | |
1716 | } | |
1717 | goto next; | |
1718 | ||
1719 | next:; | |
1720 | pc = code->next_pc; | |
1721 | ||
1722 | end: | |
1723 | ; | |
1724 | /* if (cpu.regs[8] ) abort(); */ | |
1725 | ||
9e03a68f | 1726 | if (--poll_count < 0) |
7478904c | 1727 | { |
9e03a68f | 1728 | poll_count = 100; |
247fccde AC |
1729 | if ((*sim_callback->poll_quit) != NULL |
1730 | && (*sim_callback->poll_quit) (sim_callback)) | |
1731 | sim_stop (sd); | |
7478904c | 1732 | } |
0693d363 DE |
1733 | |
1734 | } | |
46337270 | 1735 | while (cpu.state == SIM_STATE_RUNNING); |
ce51bde6 DE |
1736 | cpu.ticks += get_now () - tick_start; |
1737 | cpu.cycles += cycles; | |
1738 | cpu.insts += insts; | |
7478904c | 1739 | |
ce51bde6 DE |
1740 | cpu.pc = pc; |
1741 | BUILDSR (); | |
7478904c | 1742 | cpu.mask = oldmask; |
ce51bde6 DE |
1743 | signal (SIGINT, prev); |
1744 | } | |
1745 | ||
46337270 DE |
1746 | int |
1747 | sim_trace (sd) | |
1748 | SIM_DESC sd; | |
1749 | { | |
1750 | /* FIXME: unfinished */ | |
1751 | abort (); | |
1752 | } | |
ce51bde6 | 1753 | |
28655f00 | 1754 | int |
46337270 DE |
1755 | sim_write (sd, addr, buffer, size) |
1756 | SIM_DESC sd; | |
a415cf0a | 1757 | SIM_ADDR addr; |
ce51bde6 DE |
1758 | unsigned char *buffer; |
1759 | int size; | |
1760 | { | |
1761 | int i; | |
1762 | ||
1763 | init_pointers (); | |
7e1e013f | 1764 | if (addr < 0) |
a415cf0a | 1765 | return 0; |
ce51bde6 DE |
1766 | for (i = 0; i < size; i++) |
1767 | { | |
7e1e013f JL |
1768 | if (addr < memory_size) |
1769 | { | |
1770 | cpu.memory[addr + i] = buffer[i]; | |
1771 | cpu.cache_idx[addr + i] = 0; | |
1772 | } | |
1773 | else | |
1774 | cpu.eightbit[(addr + i) & 0xff] = buffer[i]; | |
ce51bde6 | 1775 | } |
a415cf0a | 1776 | return size; |
ce51bde6 DE |
1777 | } |
1778 | ||
28655f00 | 1779 | int |
46337270 DE |
1780 | sim_read (sd, addr, buffer, size) |
1781 | SIM_DESC sd; | |
a415cf0a DE |
1782 | SIM_ADDR addr; |
1783 | unsigned char *buffer; | |
ce51bde6 DE |
1784 | int size; |
1785 | { | |
1786 | init_pointers (); | |
7e1e013f | 1787 | if (addr < 0) |
a415cf0a | 1788 | return 0; |
7e1e013f JL |
1789 | if (addr < memory_size) |
1790 | memcpy (buffer, cpu.memory + addr, size); | |
1791 | else | |
1792 | memcpy (buffer, cpu.eightbit + (addr & 0xff), size); | |
28655f00 | 1793 | return size; |
ce51bde6 DE |
1794 | } |
1795 | ||
1796 | ||
ce51bde6 DE |
1797 | #define R0_REGNUM 0 |
1798 | #define R1_REGNUM 1 | |
1799 | #define R2_REGNUM 2 | |
1800 | #define R3_REGNUM 3 | |
1801 | #define R4_REGNUM 4 | |
1802 | #define R5_REGNUM 5 | |
1803 | #define R6_REGNUM 6 | |
1804 | #define R7_REGNUM 7 | |
1805 | ||
1806 | #define SP_REGNUM R7_REGNUM /* Contains address of top of stack */ | |
1807 | #define FP_REGNUM R6_REGNUM /* Contains address of executing | |
0693d363 | 1808 | * stack frame */ |
ce51bde6 DE |
1809 | |
1810 | #define CCR_REGNUM 8 /* Contains processor status */ | |
1811 | #define PC_REGNUM 9 /* Contains program counter */ | |
1812 | ||
1813 | #define CYCLE_REGNUM 10 | |
1814 | #define INST_REGNUM 11 | |
1815 | #define TICK_REGNUM 12 | |
1816 | ||
1817 | ||
7478904c | 1818 | void |
46337270 DE |
1819 | sim_store_register (sd, rn, value) |
1820 | SIM_DESC sd; | |
ce51bde6 | 1821 | int rn; |
28655f00 | 1822 | unsigned char *value; |
ce51bde6 | 1823 | { |
28655f00 SC |
1824 | int longval; |
1825 | int shortval; | |
1826 | int intval; | |
0693d363 DE |
1827 | longval = (value[0] << 24) | (value[1] << 16) | (value[2] << 8) | value[3]; |
1828 | shortval = (value[0] << 8) | (value[1]); | |
28655f00 | 1829 | intval = h8300hmode ? longval : shortval; |
ce51bde6 DE |
1830 | |
1831 | init_pointers (); | |
1832 | switch (rn) | |
1833 | { | |
1834 | case PC_REGNUM: | |
28655f00 | 1835 | cpu.pc = intval; |
ce51bde6 DE |
1836 | break; |
1837 | default: | |
1838 | abort (); | |
1839 | case R0_REGNUM: | |
1840 | case R1_REGNUM: | |
1841 | case R2_REGNUM: | |
1842 | case R3_REGNUM: | |
1843 | case R4_REGNUM: | |
1844 | case R5_REGNUM: | |
1845 | case R6_REGNUM: | |
1846 | case R7_REGNUM: | |
28655f00 | 1847 | cpu.regs[rn] = intval; |
ce51bde6 DE |
1848 | break; |
1849 | case CCR_REGNUM: | |
28655f00 | 1850 | cpu.ccr = intval; |
ce51bde6 DE |
1851 | break; |
1852 | case CYCLE_REGNUM: | |
28655f00 | 1853 | cpu.cycles = longval; |
ce51bde6 DE |
1854 | break; |
1855 | ||
1856 | case INST_REGNUM: | |
28655f00 | 1857 | cpu.insts = longval; |
ce51bde6 DE |
1858 | break; |
1859 | ||
1860 | case TICK_REGNUM: | |
28655f00 | 1861 | cpu.ticks = longval; |
ce51bde6 DE |
1862 | break; |
1863 | } | |
1864 | } | |
1865 | ||
7478904c | 1866 | void |
46337270 DE |
1867 | sim_fetch_register (sd, rn, buf) |
1868 | SIM_DESC sd; | |
ce51bde6 | 1869 | int rn; |
a415cf0a | 1870 | unsigned char *buf; |
ce51bde6 DE |
1871 | { |
1872 | int v; | |
1873 | int longreg = 0; | |
1874 | ||
1875 | init_pointers (); | |
1876 | ||
1877 | switch (rn) | |
1878 | { | |
1879 | default: | |
1880 | abort (); | |
1881 | case 8: | |
1882 | v = cpu.ccr; | |
1883 | break; | |
1884 | case 9: | |
1885 | v = cpu.pc; | |
1886 | break; | |
1887 | case R0_REGNUM: | |
1888 | case R1_REGNUM: | |
1889 | case R2_REGNUM: | |
1890 | case R3_REGNUM: | |
1891 | case R4_REGNUM: | |
1892 | case R5_REGNUM: | |
1893 | case R6_REGNUM: | |
1894 | case R7_REGNUM: | |
1895 | v = cpu.regs[rn]; | |
1896 | break; | |
1897 | case 10: | |
1898 | v = cpu.cycles; | |
1899 | longreg = 1; | |
ce51bde6 DE |
1900 | break; |
1901 | case 11: | |
1902 | v = cpu.ticks; | |
1903 | longreg = 1; | |
1904 | break; | |
1905 | case 12: | |
1906 | v = cpu.insts; | |
1907 | longreg = 1; | |
1908 | break; | |
ce51bde6 | 1909 | } |
28655f00 | 1910 | if (h8300hmode || longreg) |
ce51bde6 DE |
1911 | { |
1912 | buf[0] = v >> 24; | |
1913 | buf[1] = v >> 16; | |
1914 | buf[2] = v >> 8; | |
1915 | buf[3] = v >> 0; | |
1916 | } | |
1917 | else | |
1918 | { | |
1919 | buf[0] = v >> 8; | |
1920 | buf[1] = v; | |
1921 | } | |
1922 | } | |
1923 | ||
7478904c | 1924 | void |
46337270 DE |
1925 | sim_stop_reason (sd, reason, sigrc) |
1926 | SIM_DESC sd; | |
a415cf0a DE |
1927 | enum sim_stop *reason; |
1928 | int *sigrc; | |
ce51bde6 | 1929 | { |
46337270 DE |
1930 | #if 0 /* FIXME: This should work but we can't use it. |
1931 | grep for SLEEP above. */ | |
1932 | switch (cpu.state) | |
1933 | { | |
1934 | case SIM_STATE_EXITED : *reason = sim_exited; break; | |
1935 | case SIM_STATE_SIGNALLED : *reason = sim_signalled; break; | |
1936 | case SIM_STATE_STOPPED : *reason = sim_stopped; break; | |
1937 | default : abort (); | |
1938 | } | |
1939 | #else | |
a415cf0a | 1940 | *reason = sim_stopped; |
46337270 | 1941 | #endif |
7db9345b | 1942 | *sigrc = cpu.exception; |
ce51bde6 DE |
1943 | } |
1944 | ||
46337270 DE |
1945 | /* FIXME: Rename to sim_set_mem_size. */ |
1946 | ||
1947 | void | |
1948 | sim_size (n) | |
1949 | int n; | |
1950 | { | |
1951 | /* Memory size is fixed. */ | |
1952 | } | |
1953 | ||
1954 | void | |
1955 | sim_set_simcache_size (n) | |
ce51bde6 DE |
1956 | { |
1957 | if (cpu.cache) | |
1958 | free (cpu.cache); | |
1959 | if (n < 2) | |
1960 | n = 2; | |
1961 | cpu.cache = (decoded_inst *) malloc (sizeof (decoded_inst) * n); | |
1962 | memset (cpu.cache, 0, sizeof (decoded_inst) * n); | |
1963 | cpu.csize = n; | |
1964 | } | |
1965 | ||
1966 | ||
7478904c | 1967 | void |
46337270 DE |
1968 | sim_info (sd, verbose) |
1969 | SIM_DESC sd; | |
ce51bde6 | 1970 | int verbose; |
ce51bde6 DE |
1971 | { |
1972 | double timetaken = (double) cpu.ticks / (double) now_persec (); | |
1973 | double virttime = cpu.cycles / 10.0e6; | |
1974 | ||
46337270 DE |
1975 | (*sim_callback->printf_filtered) (sim_callback, |
1976 | "\n\n#instructions executed %10d\n", | |
1977 | cpu.insts); | |
1978 | (*sim_callback->printf_filtered) (sim_callback, | |
1979 | "#cycles (v approximate) %10d\n", | |
1980 | cpu.cycles); | |
1981 | (*sim_callback->printf_filtered) (sim_callback, | |
1982 | "#real time taken %10.4f\n", | |
1983 | timetaken); | |
1984 | (*sim_callback->printf_filtered) (sim_callback, | |
1985 | "#virtual time taked %10.4f\n", | |
1986 | virttime); | |
0693d363 | 1987 | if (timetaken != 0.0) |
46337270 DE |
1988 | (*sim_callback->printf_filtered) (sim_callback, |
1989 | "#simulation ratio %10.4f\n", | |
1990 | virttime / timetaken); | |
1991 | (*sim_callback->printf_filtered) (sim_callback, | |
1992 | "#compiles %10d\n", | |
1993 | cpu.compiles); | |
1994 | (*sim_callback->printf_filtered) (sim_callback, | |
1995 | "#cache size %10d\n", | |
1996 | cpu.csize); | |
ce51bde6 DE |
1997 | |
1998 | #ifdef ADEBUG | |
46337270 DE |
1999 | /* This to be conditional on `what' (aka `verbose'), |
2000 | however it was never passed as non-zero. */ | |
2001 | if (1) | |
ce51bde6 DE |
2002 | { |
2003 | int i; | |
0693d363 | 2004 | for (i = 0; i < O_LAST; i++) |
ce51bde6 DE |
2005 | { |
2006 | if (cpu.stats[i]) | |
46337270 DE |
2007 | (*sim_callback->printf_filtered) (sim_callback, |
2008 | "%d: %d\n", i, cpu.stats[i]); | |
ce51bde6 DE |
2009 | } |
2010 | } | |
2011 | #endif | |
2012 | } | |
2013 | ||
7478904c SC |
2014 | /* Indicate whether the cpu is an h8/300 or h8/300h. |
2015 | FLAG is non-zero for the h8/300h. */ | |
2016 | ||
89a2c4fd | 2017 | void |
7478904c SC |
2018 | set_h8300h (flag) |
2019 | int flag; | |
89a2c4fd | 2020 | { |
fafce69a AC |
2021 | /* FIXME: Much of the code in sim_load can be moved to sim_open. |
2022 | This function being replaced by a sim_open:ARGV configuration | |
2023 | option */ | |
7478904c | 2024 | h8300hmode = flag; |
89a2c4fd | 2025 | } |
28655f00 | 2026 | |
46337270 | 2027 | SIM_DESC |
247fccde | 2028 | sim_open (kind, ptr, abfd, argv) |
46337270 | 2029 | SIM_OPEN_KIND kind; |
247fccde AC |
2030 | struct host_callback_struct *ptr; |
2031 | struct _bfd *abfd; | |
46337270 | 2032 | char **argv; |
7db9345b | 2033 | { |
fafce69a AC |
2034 | /* FIXME: Much of the code in sim_load can be moved here */ |
2035 | ||
46337270 DE |
2036 | sim_kind = kind; |
2037 | myname = argv[0]; | |
247fccde | 2038 | sim_callback = ptr; |
46337270 DE |
2039 | /* fudge our descriptor */ |
2040 | return (SIM_DESC) 1; | |
7db9345b DE |
2041 | } |
2042 | ||
7478904c | 2043 | void |
46337270 DE |
2044 | sim_close (sd, quitting) |
2045 | SIM_DESC sd; | |
7478904c SC |
2046 | int quitting; |
2047 | { | |
2048 | /* nothing to do */ | |
2049 | } | |
2050 | ||
2051 | /* Called by gdb to load a program into memory. */ | |
2052 | ||
46337270 DE |
2053 | SIM_RC |
2054 | sim_load (sd, prog, abfd, from_tty) | |
2055 | SIM_DESC sd; | |
7478904c | 2056 | char *prog; |
46337270 | 2057 | bfd *abfd; |
7478904c SC |
2058 | int from_tty; |
2059 | { | |
46337270 | 2060 | bfd *prog_bfd; |
7478904c | 2061 | |
fafce69a AC |
2062 | /* FIXME: The code below that sets a specific variant of the h8/300 |
2063 | being simulated should be moved to sim_open(). */ | |
2064 | ||
7478904c SC |
2065 | /* See if the file is for the h8/300 or h8/300h. */ |
2066 | /* ??? This may not be the most efficient way. The z8k simulator | |
2067 | does this via a different mechanism (INIT_EXTRA_SYMTAB_INFO). */ | |
46337270 DE |
2068 | if (abfd != NULL) |
2069 | prog_bfd = abfd; | |
2070 | else | |
2071 | prog_bfd = bfd_openr (prog, "coff-h8300"); | |
2072 | if (prog_bfd != NULL) | |
7478904c | 2073 | { |
247fccde AC |
2074 | /* Set the cpu type. We ignore failure from bfd_check_format |
2075 | and bfd_openr as sim_load_file checks too. */ | |
46337270 | 2076 | if (bfd_check_format (prog_bfd, bfd_object)) |
171f4664 | 2077 | { |
247fccde AC |
2078 | unsigned long mach = bfd_get_mach (prog_bfd); |
2079 | set_h8300h (mach == bfd_mach_h8300h | |
2080 | || mach == bfd_mach_h8300s); | |
171f4664 | 2081 | } |
7478904c SC |
2082 | } |
2083 | ||
132fdcb9 JL |
2084 | /* If we're using gdb attached to the simulator, then we have to |
2085 | reallocate memory for the simulator. | |
2086 | ||
2087 | When gdb first starts, it calls fetch_registers (among other | |
2088 | functions), which in turn calls init_pointers, which allocates | |
2089 | simulator memory. | |
2090 | ||
2091 | The problem is when we do that, we don't know whether we're | |
2092 | debugging an h8/300 or h8/300h program. | |
2093 | ||
2094 | This is the first point at which we can make that determination, | |
2095 | so we just reallocate memory now; this will also allow us to handle | |
2096 | switching between h8/300 and h8/300h programs without exiting | |
2097 | gdb. */ | |
2098 | if (h8300hmode) | |
2099 | memory_size = H8300H_MSIZE; | |
2100 | else | |
2101 | memory_size = H8300_MSIZE; | |
2102 | ||
2103 | if (cpu.memory) | |
2104 | free (cpu.memory); | |
2105 | if (cpu.cache_idx) | |
2106 | free (cpu.cache_idx); | |
7e1e013f JL |
2107 | if (cpu.eightbit) |
2108 | free (cpu.eightbit); | |
132fdcb9 JL |
2109 | |
2110 | cpu.memory = (unsigned char *) calloc (sizeof (char), memory_size); | |
2111 | cpu.cache_idx = (unsigned short *) calloc (sizeof (short), memory_size); | |
2112 | cpu.eightbit = (unsigned char *) calloc (sizeof (char), 256); | |
2113 | ||
2114 | /* `msize' must be a power of two */ | |
2115 | if ((memory_size & (memory_size - 1)) != 0) | |
2116 | abort (); | |
2117 | cpu.mask = memory_size - 1; | |
2118 | ||
46337270 | 2119 | if (sim_load_file (sd, myname, sim_callback, prog, prog_bfd, |
9e03a68f AC |
2120 | sim_kind == SIM_OPEN_DEBUG, |
2121 | 0, sim_write) | |
46337270 DE |
2122 | == NULL) |
2123 | { | |
2124 | /* Close the bfd if we opened it. */ | |
2125 | if (abfd == NULL && prog_bfd != NULL) | |
2126 | bfd_close (prog_bfd); | |
2127 | return SIM_RC_FAIL; | |
2128 | } | |
2129 | ||
46337270 DE |
2130 | /* Close the bfd if we opened it. */ |
2131 | if (abfd == NULL && prog_bfd != NULL) | |
2132 | bfd_close (prog_bfd); | |
2133 | return SIM_RC_OK; | |
7478904c SC |
2134 | } |
2135 | ||
46337270 | 2136 | SIM_RC |
fafce69a | 2137 | sim_create_inferior (sd, abfd, argv, env) |
46337270 | 2138 | SIM_DESC sd; |
fafce69a | 2139 | struct _bfd *abfd; |
a415cf0a DE |
2140 | char **argv; |
2141 | char **env; | |
7db9345b | 2142 | { |
fafce69a AC |
2143 | if (abfd != NULL) |
2144 | cpu.pc = bfd_get_start_address (abfd); | |
2145 | else | |
2146 | cpu.pc = 0; | |
46337270 | 2147 | return SIM_RC_OK; |
7db9345b | 2148 | } |
e656ecf9 DE |
2149 | |
2150 | void | |
46337270 DE |
2151 | sim_do_command (sd, cmd) |
2152 | SIM_DESC sd; | |
e656ecf9 DE |
2153 | char *cmd; |
2154 | { | |
46337270 DE |
2155 | (*sim_callback->printf_filtered) (sim_callback, |
2156 | "This simulator does not accept any commands.\n"); | |
e656ecf9 DE |
2157 | } |
2158 | ||
e656ecf9 | 2159 | void |
247fccde | 2160 | sim_set_callbacks (ptr) |
46337270 | 2161 | struct host_callback_struct *ptr; |
e656ecf9 | 2162 | { |
46337270 | 2163 | sim_callback = ptr; |
e656ecf9 | 2164 | } |