Commit | Line | Data |
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ce51bde6 DE |
1 | /* |
2 | * Simulator for the Hitachi H8/300 architecture. | |
3 | * | |
4 | * Written by Steve Chamberlain of Cygnus Support. sac@cygnus.com | |
5 | * | |
6 | * This file is part of H8/300 sim | |
7 | * | |
8 | * | |
9 | * THIS SOFTWARE IS NOT COPYRIGHTED | |
10 | * | |
11 | * Cygnus offers the following for use in the public domain. Cygnus makes no | |
12 | * warranty with regard to the software or its performance and the user | |
13 | * accepts the software "AS IS" with all faults. | |
14 | * | |
15 | * CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO THIS | |
16 | * SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY | |
17 | * AND FITNESS FOR A PARTICULAR PURPOSE. | |
ce51bde6 DE |
18 | */ |
19 | ||
e656ecf9 DE |
20 | #include "config.h" |
21 | ||
ce51bde6 | 22 | #include <signal.h> |
e656ecf9 DE |
23 | #ifdef HAVE_TIME_H |
24 | #include <time.h> | |
25 | #endif | |
26 | #ifdef HAVE_STDLIB_H | |
27 | #include <stdlib.h> | |
7478904c | 28 | #endif |
ce51bde6 | 29 | #include <sys/param.h> |
4dfb4ffc | 30 | #include "wait.h" |
0693d363 | 31 | #include "ansidecl.h" |
e656ecf9 | 32 | #include "callback.h" |
a415cf0a | 33 | #include "remote-sim.h" |
7478904c | 34 | #include "bfd.h" |
ce51bde6 DE |
35 | |
36 | int debug; | |
37 | ||
38 | ||
39 | #define X(op, size) op*4+size | |
40 | ||
28655f00 | 41 | #define SP (h8300hmode ? SL:SW) |
ce51bde6 DE |
42 | #define SB 0 |
43 | #define SW 1 | |
44 | #define SL 2 | |
45 | #define OP_REG 1 | |
46 | #define OP_DEC 2 | |
47 | #define OP_DISP 3 | |
48 | #define OP_INC 4 | |
49 | #define OP_PCREL 5 | |
50 | #define OP_MEM 6 | |
51 | #define OP_CCR 7 | |
52 | #define OP_IMM 8 | |
53 | #define OP_ABS 10 | |
54 | #define h8_opcodes ops | |
55 | #define DEFINE_TABLE | |
56 | #include "opcode/h8300.h" | |
57 | ||
58 | #include "inst.h" | |
59 | ||
60 | #define LOW_BYTE(x) ((x) & 0xff) | |
61 | #define HIGH_BYTE(x) (((x)>>8) & 0xff) | |
62 | #define P(X,Y) ((X<<8) | Y) | |
63 | ||
64 | #define BUILDSR() cpu.ccr = (N << 3) | (Z << 2) | (V<<1) | C; | |
65 | ||
66 | #define GETSR() \ | |
67 | c = (cpu.ccr >> 0) & 1;\ | |
68 | v = (cpu.ccr >> 1) & 1;\ | |
69 | nz = !((cpu.ccr >> 2) & 1);\ | |
70 | n = (cpu.ccr >> 3) & 1; | |
71 | ||
72 | #ifdef __CHAR_IS_SIGNED__ | |
73 | #define SEXTCHAR(x) ((char)(x)) | |
74 | #endif | |
75 | ||
76 | #ifndef SEXTCHAR | |
171f4664 | 77 | #define SEXTCHAR(x) ((x & 0x80) ? (x | ~0xff): x & 0xff) |
ce51bde6 DE |
78 | #endif |
79 | ||
80 | #define UEXTCHAR(x) ((x) & 0xff) | |
81 | #define UEXTSHORT(x) ((x) & 0xffff) | |
82 | #define SEXTSHORT(x) ((short)(x)) | |
83 | ||
84 | static cpu_state_type cpu; | |
85 | ||
28655f00 | 86 | int h8300hmode = 0; |
171f4664 | 87 | int h8300smode = 0; |
ce51bde6 | 88 | |
e656ecf9 DE |
89 | static int memory_size; |
90 | ||
ce51bde6 DE |
91 | |
92 | static int | |
93 | get_now () | |
94 | { | |
7478904c | 95 | #ifndef WIN32 |
0693d363 | 96 | return time (0); |
28655f00 | 97 | #endif |
7478904c | 98 | return 0; |
ce51bde6 DE |
99 | } |
100 | ||
101 | static int | |
102 | now_persec () | |
103 | { | |
28655f00 | 104 | return 1; |
ce51bde6 DE |
105 | } |
106 | ||
107 | ||
108 | static int | |
109 | bitfrom (x) | |
110 | { | |
ce51bde6 DE |
111 | switch (x & SIZE) |
112 | { | |
113 | case L_8: | |
114 | return SB; | |
115 | case L_16: | |
116 | return SW; | |
117 | case L_32: | |
118 | return SL; | |
119 | case L_P: | |
28655f00 | 120 | return h8300hmode ? SL : SW; |
ce51bde6 | 121 | } |
ce51bde6 DE |
122 | } |
123 | ||
124 | static | |
125 | unsigned int | |
126 | lvalue (x, rn) | |
127 | { | |
128 | switch (x / 4) | |
129 | { | |
130 | case OP_DISP: | |
0693d363 | 131 | if (rn == 8) |
ce51bde6 | 132 | { |
0693d363 | 133 | return X (OP_IMM, SP); |
ce51bde6 | 134 | } |
0693d363 DE |
135 | return X (OP_REG, SP); |
136 | ||
ce51bde6 DE |
137 | case OP_MEM: |
138 | ||
139 | return X (OP_MEM, SP); | |
140 | default: | |
141 | abort (); | |
142 | } | |
143 | } | |
144 | ||
145 | static unsigned int | |
146 | decode (addr, data, dst) | |
147 | int addr; | |
148 | unsigned char *data; | |
149 | decoded_inst *dst; | |
150 | ||
151 | { | |
152 | int rs = 0; | |
153 | int rd = 0; | |
154 | int rdisp = 0; | |
155 | int abs = 0; | |
156 | int plen = 0; | |
e24146ec | 157 | int bit = 0; |
ce51bde6 DE |
158 | |
159 | struct h8_opcode *q = h8_opcodes; | |
160 | int size = 0; | |
161 | dst->dst.type = -1; | |
162 | dst->src.type = -1; | |
163 | /* Find the exact opcode/arg combo */ | |
164 | while (q->name) | |
165 | { | |
166 | op_type *nib; | |
167 | unsigned int len = 0; | |
168 | ||
169 | nib = q->data.nib; | |
170 | ||
171 | while (1) | |
172 | { | |
173 | op_type looking_for = *nib; | |
174 | int thisnib = data[len >> 1]; | |
175 | ||
176 | thisnib = (len & 1) ? (thisnib & 0xf) : ((thisnib >> 4) & 0xf); | |
177 | ||
0693d363 | 178 | if (looking_for < 16 && looking_for >= 0) |
ce51bde6 | 179 | { |
ce51bde6 DE |
180 | if (looking_for != thisnib) |
181 | goto fail; | |
182 | } | |
183 | else | |
184 | { | |
ce51bde6 DE |
185 | if ((int) looking_for & (int) B31) |
186 | { | |
187 | if (!(((int) thisnib & 0x8) != 0)) | |
188 | goto fail; | |
189 | looking_for = (op_type) ((int) looking_for & ~(int) | |
190 | B31); | |
191 | thisnib &= 0x7; | |
ce51bde6 DE |
192 | } |
193 | if ((int) looking_for & (int) B30) | |
194 | { | |
195 | if (!(((int) thisnib & 0x8) == 0)) | |
196 | goto fail; | |
197 | looking_for = (op_type) ((int) looking_for & ~(int) B30); | |
198 | } | |
199 | if (looking_for & DBIT) | |
200 | { | |
0693d363 DE |
201 | if ((looking_for & 5) != (thisnib & 5)) |
202 | goto fail; | |
ce51bde6 DE |
203 | abs = (thisnib & 0x8) ? 2 : 1; |
204 | } | |
205 | else if (looking_for & (REG | IND | INC | DEC)) | |
206 | { | |
207 | if (looking_for & REG) | |
208 | { | |
209 | /* | |
210 | * Can work out size from the | |
211 | * register | |
212 | */ | |
213 | size = bitfrom (looking_for); | |
214 | } | |
215 | if (looking_for & SRC) | |
216 | { | |
217 | rs = thisnib; | |
218 | } | |
219 | else | |
220 | { | |
221 | rd = thisnib; | |
222 | } | |
223 | } | |
224 | else if (looking_for & L_16) | |
225 | { | |
226 | abs = (data[len >> 1]) * 256 + data[(len + 2) >> 1]; | |
227 | plen = 16; | |
0693d363 | 228 | if (looking_for & (PCREL | DISP)) |
ce51bde6 DE |
229 | { |
230 | abs = (short) (abs); | |
231 | } | |
232 | } | |
233 | else if (looking_for & ABSJMP) | |
234 | { | |
235 | abs = | |
236 | (data[1] << 16) | |
237 | | (data[2] << 8) | |
238 | | (data[3]); | |
239 | } | |
0693d363 DE |
240 | else if (looking_for & MEMIND) |
241 | { | |
242 | abs = data[1]; | |
243 | } | |
ce51bde6 DE |
244 | else if (looking_for & L_32) |
245 | { | |
246 | int i = len >> 1; | |
247 | abs = (data[i] << 24) | |
248 | | (data[i + 1] << 16) | |
249 | | (data[i + 2] << 8) | |
250 | | (data[i + 3]); | |
251 | ||
252 | plen = 32; | |
ce51bde6 DE |
253 | } |
254 | else if (looking_for & L_24) | |
255 | { | |
256 | int i = len >> 1; | |
0693d363 | 257 | abs = (data[i] << 16) | (data[i + 1] << 8) | (data[i + 2]); |
ce51bde6 DE |
258 | plen = 24; |
259 | } | |
260 | else if (looking_for & IGNORE) | |
261 | { | |
0693d363 | 262 | /* nothing to do */ |
ce51bde6 DE |
263 | } |
264 | else if (looking_for & DISPREG) | |
265 | { | |
266 | rdisp = thisnib & 0x7; | |
267 | } | |
268 | else if (looking_for & KBIT) | |
269 | { | |
270 | switch (thisnib) | |
271 | { | |
272 | case 9: | |
273 | abs = 4; | |
274 | break; | |
275 | case 8: | |
276 | abs = 2; | |
277 | break; | |
278 | case 0: | |
279 | abs = 1; | |
280 | break; | |
281 | } | |
282 | } | |
283 | else if (looking_for & L_8) | |
284 | { | |
285 | plen = 8; | |
286 | ||
287 | if (looking_for & PCREL) | |
288 | { | |
289 | abs = SEXTCHAR (data[len >> 1]); | |
290 | } | |
e24146ec JL |
291 | else if (looking_for & ABS8MEM) |
292 | { | |
293 | plen = 8; | |
294 | abs = h8300hmode ? ~0xff0000ff : ~0xffff00ff; | |
295 | abs |= data[len >> 1] & 0xff ; | |
296 | } | |
297 | else | |
ce51bde6 DE |
298 | { |
299 | abs = data[len >> 1] & 0xff; | |
300 | } | |
301 | } | |
302 | else if (looking_for & L_3) | |
303 | { | |
304 | plen = 3; | |
305 | ||
e24146ec | 306 | bit = thisnib; |
ce51bde6 DE |
307 | } |
308 | else if (looking_for == E) | |
309 | { | |
310 | dst->op = q; | |
311 | ||
312 | /* Fill in the args */ | |
313 | { | |
314 | op_type *args = q->args.nib; | |
315 | int hadone = 0; | |
316 | ||
ce51bde6 DE |
317 | while (*args != E) |
318 | { | |
319 | int x = *args; | |
320 | int rn = (x & DST) ? rd : rs; | |
321 | ea_type *p; | |
322 | ||
323 | if (x & DST) | |
324 | { | |
325 | p = &(dst->dst); | |
326 | } | |
327 | else | |
328 | { | |
329 | p = &(dst->src); | |
330 | } | |
331 | ||
e24146ec JL |
332 | if (x & (L_3)) |
333 | { | |
334 | p->type = X (OP_IMM, size); | |
335 | p->literal = bit; | |
336 | } | |
337 | else if (x & (IMM | KBIT | DBIT)) | |
ce51bde6 DE |
338 | { |
339 | p->type = X (OP_IMM, size); | |
340 | p->literal = abs; | |
341 | } | |
342 | else if (x & REG) | |
343 | { | |
0693d363 DE |
344 | /* Reset the size, some |
345 | ops (like mul) have two sizes */ | |
346 | ||
ce51bde6 DE |
347 | size = bitfrom (x); |
348 | p->type = X (OP_REG, size); | |
349 | p->reg = rn; | |
350 | } | |
351 | else if (x & INC) | |
352 | { | |
353 | p->type = X (OP_INC, size); | |
354 | p->reg = rn & 0x7; | |
355 | } | |
356 | else if (x & DEC) | |
357 | { | |
358 | p->type = X (OP_DEC, size); | |
359 | p->reg = rn & 0x7; | |
360 | } | |
361 | else if (x & IND) | |
362 | { | |
363 | p->type = X (OP_DISP, size); | |
364 | p->reg = rn & 0x7; | |
365 | p->literal = 0; | |
366 | } | |
e24146ec | 367 | else if (x & (ABS | ABSJMP | ABS8MEM)) |
ce51bde6 DE |
368 | { |
369 | p->type = X (OP_DISP, size); | |
370 | p->literal = abs; | |
371 | p->reg = 8; | |
372 | } | |
373 | else if (x & MEMIND) | |
374 | { | |
375 | p->type = X (OP_MEM, size); | |
376 | p->literal = abs; | |
377 | } | |
378 | else if (x & PCREL) | |
379 | { | |
380 | p->type = X (OP_PCREL, size); | |
381 | p->literal = abs + addr + 2; | |
0693d363 DE |
382 | if (x & L_16) |
383 | p->literal += 2; | |
ce51bde6 DE |
384 | } |
385 | else if (x & ABSJMP) | |
386 | { | |
387 | p->type = X (OP_IMM, SP); | |
388 | p->literal = abs; | |
389 | } | |
390 | else if (x & DISP) | |
391 | { | |
392 | p->type = X (OP_DISP, size); | |
393 | p->literal = abs; | |
394 | p->reg = rdisp & 0x7; | |
395 | } | |
396 | else if (x & CCR) | |
397 | { | |
398 | p->type = OP_CCR; | |
399 | } | |
400 | else | |
401 | printf ("Hmmmm %x", x); | |
402 | ||
ce51bde6 DE |
403 | args++; |
404 | } | |
405 | } | |
406 | ||
407 | /* | |
0693d363 DE |
408 | * But a jmp or a jsr gets |
409 | * automagically lvalued, since we | |
410 | * branch to their address not their | |
411 | * contents | |
412 | */ | |
ce51bde6 DE |
413 | if (q->how == O (O_JSR, SB) |
414 | || q->how == O (O_JMP, SB)) | |
415 | { | |
416 | dst->src.type = lvalue (dst->src.type, dst->src.reg); | |
417 | } | |
418 | ||
ce51bde6 DE |
419 | if (dst->dst.type == -1) |
420 | dst->dst = dst->src; | |
0693d363 | 421 | |
ce51bde6 DE |
422 | dst->opcode = q->how; |
423 | dst->cycles = q->time; | |
424 | ||
425 | /* And a jsr to 0xc4 is turned into a magic trap */ | |
0693d363 DE |
426 | |
427 | if (dst->opcode == O (O_JSR, SB)) | |
ce51bde6 | 428 | { |
0693d363 | 429 | if (dst->src.literal == 0xc4) |
ce51bde6 | 430 | { |
0693d363 | 431 | dst->opcode = O (O_SYSCALL, SB); |
ce51bde6 DE |
432 | } |
433 | } | |
0693d363 | 434 | |
ce51bde6 DE |
435 | dst->next_pc = addr + len / 2; |
436 | return; | |
437 | } | |
438 | else | |
439 | { | |
440 | printf ("Dont understand %x \n", looking_for); | |
441 | } | |
442 | } | |
0693d363 | 443 | |
ce51bde6 DE |
444 | len++; |
445 | nib++; | |
446 | } | |
0693d363 | 447 | |
ce51bde6 DE |
448 | fail: |
449 | q++; | |
450 | } | |
0693d363 | 451 | |
ce51bde6 DE |
452 | dst->opcode = O (O_ILL, SB); |
453 | } | |
454 | ||
455 | ||
456 | static void | |
457 | compile (pc) | |
458 | { | |
459 | int idx; | |
0693d363 | 460 | |
ce51bde6 | 461 | /* find the next cache entry to use */ |
0693d363 | 462 | |
ce51bde6 DE |
463 | idx = cpu.cache_top + 1; |
464 | cpu.compiles++; | |
465 | if (idx >= cpu.csize) | |
466 | { | |
467 | idx = 1; | |
468 | } | |
469 | cpu.cache_top = idx; | |
0693d363 | 470 | |
ce51bde6 DE |
471 | /* Throw away its old meaning */ |
472 | cpu.cache_idx[cpu.cache[idx].oldpc] = 0; | |
0693d363 | 473 | |
ce51bde6 DE |
474 | /* set to new address */ |
475 | cpu.cache[idx].oldpc = pc; | |
0693d363 | 476 | |
ce51bde6 DE |
477 | /* fill in instruction info */ |
478 | decode (pc, cpu.memory + pc, cpu.cache + idx); | |
0693d363 | 479 | |
ce51bde6 DE |
480 | /* point to new cache entry */ |
481 | cpu.cache_idx[pc] = idx; | |
482 | } | |
483 | ||
484 | ||
485 | static unsigned char *breg[18]; | |
486 | static unsigned short *wreg[18]; | |
487 | static unsigned int *lreg[18]; | |
488 | ||
489 | #define GET_B_REG(x) *(breg[x]) | |
490 | #define SET_B_REG(x,y) (*(breg[x])) = (y) | |
491 | #define GET_W_REG(x) *(wreg[x]) | |
492 | #define SET_W_REG(x,y) (*(wreg[x])) = (y) | |
493 | ||
494 | #define GET_L_REG(x) *(lreg[x]) | |
495 | #define SET_L_REG(x,y) (*(lreg[x])) = (y) | |
496 | ||
497 | #define GET_MEMORY_L(x) \ | |
7e1e013f JL |
498 | (x < memory_size \ |
499 | ? ((cpu.memory[x+0] << 24) | (cpu.memory[x+1] << 16) \ | |
500 | | (cpu.memory[x+2] << 8) | cpu.memory[x+3]) \ | |
501 | : ((cpu.eightbit[(x+0) & 0xff] << 24) | (cpu.eightbit[(x+1) & 0xff] << 16) \ | |
502 | | (cpu.eightbit[(x+2) & 0xff] << 8) | cpu.eightbit[(x+3) & 0xff])) | |
ce51bde6 DE |
503 | |
504 | #define GET_MEMORY_W(x) \ | |
7e1e013f JL |
505 | (x < memory_size \ |
506 | ? ((cpu.memory[x+0] << 8) | (cpu.memory[x+1] << 0)) \ | |
507 | : ((cpu.eightbit[(x+0) & 0xff] << 8) | (cpu.eightbit[(x+1) & 0xff] << 0))) | |
ce51bde6 DE |
508 | |
509 | ||
7e1e013f JL |
510 | #define GET_MEMORY_B(x) \ |
511 | (x < memory_size ? (cpu.memory[x]) : (cpu.eightbit[x & 0xff])) | |
ce51bde6 DE |
512 | |
513 | #define SET_MEMORY_L(x,y) \ | |
7e1e013f JL |
514 | { register unsigned char *_p; register int __y = y; \ |
515 | _p = (x < memory_size ? cpu.memory+x : cpu.eightbit + (x & 0xff)); \ | |
516 | _p[0] = (__y)>>24; _p[1] = (__y)>>16; \ | |
517 | _p[2] = (__y)>>8; _p[3] = (__y)>>0;} | |
ce51bde6 | 518 | |
7e1e013f JL |
519 | #define SET_MEMORY_W(x,y) \ |
520 | { register unsigned char *_p; register int __y = y; \ | |
521 | _p = (x < memory_size ? cpu.memory+x : cpu.eightbit + (x & 0xff)); \ | |
522 | _p[0] = (__y)>>8; _p[1] =(__y);} | |
523 | ||
524 | #define SET_MEMORY_B(x,y) \ | |
525 | (x < memory_size ? (cpu.memory[(x)] = y) : (cpu.eightbit[x & 0xff] = y)) | |
ce51bde6 DE |
526 | |
527 | int | |
89a2c4fd | 528 | fetch (arg, n) |
0693d363 | 529 | ea_type *arg; |
ce51bde6 DE |
530 | { |
531 | int rn = arg->reg; | |
532 | int abs = arg->literal; | |
533 | int r; | |
534 | int t; | |
0693d363 | 535 | |
ce51bde6 DE |
536 | switch (arg->type) |
537 | { | |
538 | case X (OP_REG, SB): | |
539 | return GET_B_REG (rn); | |
540 | case X (OP_REG, SW): | |
541 | return GET_W_REG (rn); | |
542 | case X (OP_REG, SL): | |
543 | return GET_L_REG (rn); | |
544 | case X (OP_IMM, SB): | |
545 | case X (OP_IMM, SW): | |
546 | case X (OP_IMM, SL): | |
547 | return abs; | |
548 | case X (OP_DEC, SB): | |
0693d363 | 549 | abort (); |
ce51bde6 | 550 | |
0693d363 DE |
551 | case X (OP_INC, SB): |
552 | t = GET_L_REG (rn); | |
ce51bde6 | 553 | t &= cpu.mask; |
0693d363 DE |
554 | r = GET_MEMORY_B (t); |
555 | t++; | |
ce51bde6 | 556 | t = t & cpu.mask; |
0693d363 | 557 | SET_L_REG (rn, t); |
ce51bde6 DE |
558 | return r; |
559 | break; | |
0693d363 DE |
560 | case X (OP_INC, SW): |
561 | t = GET_L_REG (rn); | |
ce51bde6 | 562 | t &= cpu.mask; |
0693d363 DE |
563 | r = GET_MEMORY_W (t); |
564 | t += 2; | |
ce51bde6 | 565 | t = t & cpu.mask; |
0693d363 | 566 | SET_L_REG (rn, t); |
ce51bde6 | 567 | return r; |
0693d363 DE |
568 | case X (OP_INC, SL): |
569 | t = GET_L_REG (rn); | |
ce51bde6 | 570 | t &= cpu.mask; |
0693d363 DE |
571 | r = GET_MEMORY_L (t); |
572 | ||
573 | t += 4; | |
ce51bde6 | 574 | t = t & cpu.mask; |
0693d363 | 575 | SET_L_REG (rn, t); |
ce51bde6 | 576 | return r; |
0693d363 | 577 | |
ce51bde6 DE |
578 | case X (OP_DISP, SB): |
579 | t = GET_L_REG (rn) + abs; | |
580 | t &= cpu.mask; | |
581 | return GET_MEMORY_B (t); | |
0693d363 | 582 | |
ce51bde6 DE |
583 | case X (OP_DISP, SW): |
584 | t = GET_L_REG (rn) + abs; | |
585 | t &= cpu.mask; | |
586 | return GET_MEMORY_W (t); | |
0693d363 | 587 | |
ce51bde6 DE |
588 | case X (OP_DISP, SL): |
589 | t = GET_L_REG (rn) + abs; | |
590 | t &= cpu.mask; | |
591 | return GET_MEMORY_L (t); | |
0693d363 DE |
592 | |
593 | case X (OP_MEM, SL): | |
594 | t = GET_MEMORY_L (abs); | |
595 | t &= cpu.mask; | |
596 | return t; | |
597 | ||
e24146ec JL |
598 | case X (OP_MEM, SW): |
599 | t = GET_MEMORY_W (abs); | |
600 | t &= cpu.mask; | |
601 | return t; | |
602 | ||
ce51bde6 DE |
603 | default: |
604 | abort (); | |
0693d363 | 605 | |
ce51bde6 DE |
606 | } |
607 | } | |
608 | ||
609 | ||
0693d363 DE |
610 | static |
611 | void | |
612 | store (arg, n) | |
613 | ea_type *arg; | |
614 | int n; | |
ce51bde6 DE |
615 | { |
616 | int rn = arg->reg; | |
617 | int abs = arg->literal; | |
618 | int t; | |
0693d363 | 619 | |
ce51bde6 DE |
620 | switch (arg->type) |
621 | { | |
622 | case X (OP_REG, SB): | |
623 | SET_B_REG (rn, n); | |
624 | break; | |
625 | case X (OP_REG, SW): | |
626 | SET_W_REG (rn, n); | |
627 | break; | |
628 | case X (OP_REG, SL): | |
629 | SET_L_REG (rn, n); | |
630 | break; | |
0693d363 | 631 | |
ce51bde6 | 632 | case X (OP_DEC, SB): |
0693d363 | 633 | t = GET_L_REG (rn) - 1; |
ce51bde6 | 634 | t &= cpu.mask; |
0693d363 | 635 | SET_L_REG (rn, t); |
ce51bde6 DE |
636 | SET_MEMORY_B (t, n); |
637 | ||
638 | break; | |
639 | case X (OP_DEC, SW): | |
0693d363 | 640 | t = (GET_L_REG (rn) - 2) & cpu.mask; |
ce51bde6 DE |
641 | SET_L_REG (rn, t); |
642 | SET_MEMORY_W (t, n); | |
643 | break; | |
644 | ||
645 | case X (OP_DEC, SL): | |
0693d363 | 646 | t = (GET_L_REG (rn) - 4) & cpu.mask; |
89a2c4fd | 647 | SET_L_REG (rn, t); |
0693d363 | 648 | SET_MEMORY_L (t, n); |
ce51bde6 DE |
649 | break; |
650 | ||
ce51bde6 DE |
651 | case X (OP_DISP, SB): |
652 | t = GET_L_REG (rn) + abs; | |
653 | t &= cpu.mask; | |
654 | SET_MEMORY_B (t, n); | |
655 | break; | |
656 | ||
657 | case X (OP_DISP, SW): | |
658 | t = GET_L_REG (rn) + abs; | |
659 | t &= cpu.mask; | |
660 | SET_MEMORY_W (t, n); | |
661 | break; | |
662 | ||
663 | case X (OP_DISP, SL): | |
664 | t = GET_L_REG (rn) + abs; | |
665 | t &= cpu.mask; | |
666 | SET_MEMORY_L (t, n); | |
667 | break; | |
668 | default: | |
669 | abort (); | |
670 | } | |
671 | } | |
672 | ||
673 | ||
674 | static union | |
0693d363 DE |
675 | { |
676 | short int i; | |
677 | struct | |
678 | { | |
679 | char low; | |
680 | char high; | |
681 | } | |
682 | u; | |
683 | } | |
ce51bde6 DE |
684 | |
685 | littleendian; | |
686 | ||
687 | static | |
688 | void | |
689 | init_pointers () | |
690 | { | |
691 | static int init; | |
692 | ||
693 | if (!init) | |
694 | { | |
695 | int i; | |
696 | ||
697 | init = 1; | |
698 | littleendian.i = 1; | |
699 | ||
e656ecf9 DE |
700 | if (h8300hmode) |
701 | memory_size = H8300H_MSIZE; | |
702 | else | |
703 | memory_size = H8300_MSIZE; | |
704 | cpu.memory = (unsigned char *) calloc (sizeof (char), memory_size); | |
705 | cpu.cache_idx = (unsigned short *) calloc (sizeof (short), memory_size); | |
7e1e013f | 706 | cpu.eightbit = (unsigned char *) calloc (sizeof (char), 256); |
e656ecf9 DE |
707 | |
708 | /* `msize' must be a power of two */ | |
709 | if ((memory_size & (memory_size - 1)) != 0) | |
710 | abort (); | |
711 | cpu.mask = memory_size - 1; | |
0693d363 | 712 | |
ce51bde6 DE |
713 | for (i = 0; i < 9; i++) |
714 | { | |
715 | cpu.regs[i] = 0; | |
716 | } | |
717 | ||
718 | for (i = 0; i < 8; i++) | |
719 | { | |
720 | unsigned char *p = (unsigned char *) (cpu.regs + i); | |
721 | unsigned char *e = (unsigned char *) (cpu.regs + i + 1); | |
722 | unsigned short *q = (unsigned short *) (cpu.regs + i); | |
723 | unsigned short *u = (unsigned short *) (cpu.regs + i + 1); | |
724 | cpu.regs[i] = 0x00112233; | |
725 | while (p < e) | |
726 | { | |
727 | if (*p == 0x22) | |
728 | { | |
729 | breg[i] = p; | |
730 | } | |
731 | if (*p == 0x33) | |
732 | { | |
0693d363 | 733 | breg[i + 8] = p; |
ce51bde6 DE |
734 | } |
735 | p++; | |
736 | } | |
737 | while (q < u) | |
738 | { | |
739 | if (*q == 0x2233) | |
740 | { | |
741 | wreg[i] = q; | |
742 | } | |
743 | if (*q == 0x0011) | |
744 | { | |
745 | wreg[i + 8] = q; | |
746 | } | |
747 | q++; | |
748 | } | |
749 | cpu.regs[i] = 0; | |
750 | lreg[i] = &cpu.regs[i]; | |
751 | } | |
752 | ||
ce51bde6 | 753 | lreg[8] = &cpu.regs[8]; |
0693d363 | 754 | |
ce51bde6 DE |
755 | /* initialize the seg registers */ |
756 | if (!cpu.cache) | |
757 | sim_csize (CSIZE); | |
ce51bde6 DE |
758 | } |
759 | } | |
760 | ||
761 | static void | |
762 | control_c (sig, code, scp, addr) | |
763 | int sig; | |
764 | int code; | |
765 | char *scp; | |
766 | char *addr; | |
767 | { | |
768 | cpu.exception = SIGINT; | |
769 | } | |
770 | ||
771 | #define C (c != 0) | |
772 | #define Z (nz == 0) | |
773 | #define V (v != 0) | |
774 | #define N (n != 0) | |
775 | ||
28655f00 | 776 | static int |
0693d363 | 777 | mop (code, bsize, sign) |
28655f00 SC |
778 | decoded_inst *code; |
779 | int bsize; | |
0693d363 DE |
780 | int sign; |
781 | { | |
782 | int multiplier; | |
783 | int multiplicand; | |
784 | int result; | |
785 | int n, nz; | |
786 | ||
787 | if (sign) | |
788 | { | |
789 | multiplicand = | |
790 | bsize ? SEXTCHAR (GET_W_REG (code->dst.reg)) : | |
791 | SEXTSHORT (GET_W_REG (code->dst.reg)); | |
792 | multiplier = | |
793 | bsize ? SEXTCHAR (GET_B_REG (code->src.reg)) : | |
794 | SEXTSHORT (GET_W_REG (code->src.reg)); | |
795 | } | |
796 | else | |
797 | { | |
798 | multiplicand = bsize ? UEXTCHAR (GET_W_REG (code->dst.reg)) : | |
799 | UEXTSHORT (GET_W_REG (code->dst.reg)); | |
800 | multiplier = | |
801 | bsize ? UEXTCHAR (GET_B_REG (code->src.reg)) : | |
802 | UEXTSHORT (GET_W_REG (code->src.reg)); | |
803 | ||
804 | } | |
805 | result = multiplier * multiplicand; | |
806 | ||
807 | if (sign) | |
808 | { | |
809 | n = result & (bsize ? 0x8000 : 0x80000000); | |
810 | nz = result & (bsize ? 0xffff : 0xffffffff); | |
811 | } | |
812 | if (bsize) | |
813 | { | |
814 | SET_W_REG (code->dst.reg, result); | |
815 | } | |
816 | else | |
817 | { | |
818 | SET_L_REG (code->dst.reg, result); | |
819 | } | |
820 | /* return ((n==1) << 1) | (nz==1); */ | |
821 | ||
822 | } | |
823 | ||
7647e0dd | 824 | #define ONOT(name, how) \ |
0693d363 DE |
825 | case O(name, SB): \ |
826 | { \ | |
827 | int t; \ | |
828 | int hm = 0x80; \ | |
829 | rd = GET_B_REG (code->src.reg); \ | |
830 | how; \ | |
831 | goto shift8; \ | |
832 | } \ | |
833 | case O(name, SW): \ | |
834 | { \ | |
835 | int t; \ | |
836 | int hm = 0x8000; \ | |
837 | rd = GET_W_REG (code->src.reg); \ | |
838 | how; \ | |
839 | goto shift16; \ | |
840 | } \ | |
841 | case O(name, SL): \ | |
842 | { \ | |
843 | int t; \ | |
844 | int hm = 0x80000000; \ | |
845 | rd = GET_L_REG (code->src.reg); \ | |
846 | how; \ | |
847 | goto shift32; \ | |
848 | } | |
849 | ||
7647e0dd JL |
850 | #define OSHIFTS(name, how1, how2) \ |
851 | case O(name, SB): \ | |
852 | { \ | |
853 | int t; \ | |
854 | int hm = 0x80; \ | |
855 | rd = GET_B_REG (code->src.reg); \ | |
856 | if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \ | |
857 | { \ | |
858 | how1; \ | |
859 | } \ | |
860 | else \ | |
861 | { \ | |
862 | how2; \ | |
863 | } \ | |
864 | goto shift8; \ | |
865 | } \ | |
866 | case O(name, SW): \ | |
867 | { \ | |
868 | int t; \ | |
869 | int hm = 0x8000; \ | |
870 | rd = GET_W_REG (code->src.reg); \ | |
871 | if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \ | |
872 | { \ | |
873 | how1; \ | |
874 | } \ | |
875 | else \ | |
876 | { \ | |
877 | how2; \ | |
878 | } \ | |
879 | goto shift16; \ | |
880 | } \ | |
881 | case O(name, SL): \ | |
882 | { \ | |
883 | int t; \ | |
884 | int hm = 0x80000000; \ | |
885 | rd = GET_L_REG (code->src.reg); \ | |
886 | if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \ | |
887 | { \ | |
888 | how1; \ | |
889 | } \ | |
890 | else \ | |
891 | { \ | |
892 | how2; \ | |
893 | } \ | |
894 | goto shift32; \ | |
895 | } | |
896 | ||
0693d363 DE |
897 | #define OBITOP(name,f, s, op) \ |
898 | case O(name, SB): \ | |
899 | { \ | |
900 | int m; \ | |
901 | int b; \ | |
902 | if (f) ea = fetch (&code->dst); \ | |
903 | m=1<< fetch(&code->src); \ | |
904 | op; \ | |
905 | if(s) store (&code->dst,ea); goto next; \ | |
906 | } | |
28655f00 | 907 | |
7478904c | 908 | void |
a415cf0a | 909 | sim_resume (step, siggnal) |
ce51bde6 DE |
910 | { |
911 | static int init1; | |
912 | int cycles = 0; | |
913 | int insts = 0; | |
914 | int tick_start = get_now (); | |
915 | void (*prev) (); | |
0693d363 | 916 | int poll_count = 0; |
ce51bde6 DE |
917 | int res; |
918 | int tmp; | |
919 | int rd; | |
920 | int ea; | |
921 | int bit; | |
922 | int pc; | |
923 | int c, nz, v, n; | |
7478904c | 924 | int oldmask; |
ce51bde6 DE |
925 | init_pointers (); |
926 | ||
927 | prev = signal (SIGINT, control_c); | |
928 | ||
929 | if (step) | |
930 | { | |
931 | cpu.exception = SIGTRAP; | |
932 | } | |
933 | else | |
934 | { | |
935 | cpu.exception = 0; | |
936 | } | |
937 | ||
938 | pc = cpu.pc; | |
939 | ||
7e1e013f JL |
940 | /* The PC should never be odd. */ |
941 | if (pc & 0x1) | |
942 | abort (); | |
943 | ||
ce51bde6 | 944 | GETSR (); |
7478904c SC |
945 | oldmask = cpu.mask; |
946 | if (!h8300hmode) | |
947 | cpu.mask = 0xffff; | |
ce51bde6 DE |
948 | do |
949 | { | |
950 | int cidx; | |
951 | decoded_inst *code; | |
952 | ||
953 | top: | |
954 | cidx = cpu.cache_idx[pc]; | |
955 | code = cpu.cache + cidx; | |
956 | ||
957 | ||
958 | #define ALUOP(STORE, NAME, HOW) \ | |
959 | case O(NAME,SB): HOW; if(STORE)goto alu8;else goto just_flags_alu8; \ | |
960 | case O(NAME, SW): HOW; if(STORE)goto alu16;else goto just_flags_alu16; \ | |
961 | case O(NAME,SL): HOW; if(STORE)goto alu32;else goto just_flags_alu32; | |
962 | ||
963 | ||
964 | #define LOGOP(NAME, HOW) \ | |
965 | case O(NAME,SB): HOW; goto log8;\ | |
966 | case O(NAME, SW): HOW; goto log16;\ | |
967 | case O(NAME,SL): HOW; goto log32; | |
968 | ||
969 | ||
970 | ||
971 | #if ADEBUG | |
972 | if (debug) | |
973 | { | |
974 | printf ("%x %d %s\n", pc, code->opcode, | |
975 | code->op ? code->op->name : "**"); | |
976 | } | |
977 | cpu.stats[code->opcode]++; | |
0693d363 | 978 | |
ce51bde6 DE |
979 | #endif |
980 | ||
981 | cycles += code->cycles; | |
982 | insts++; | |
983 | switch (code->opcode) | |
984 | { | |
985 | case 0: | |
986 | /* | |
987 | * This opcode is a fake for when we get to an | |
988 | * instruction which hasnt been compiled | |
989 | */ | |
990 | compile (pc); | |
991 | goto top; | |
992 | break; | |
993 | ||
994 | ||
995 | case O (O_SUBX, SB): | |
996 | rd = fetch (&code->dst); | |
997 | ea = fetch (&code->src); | |
0693d363 | 998 | ea = -(ea + C); |
ce51bde6 DE |
999 | res = rd + ea; |
1000 | goto alu8; | |
1001 | ||
1002 | case O (O_ADDX, SB): | |
1003 | rd = fetch (&code->dst); | |
1004 | ea = fetch (&code->src); | |
1005 | ea = C + ea; | |
1006 | res = rd + ea; | |
1007 | goto alu8; | |
1008 | ||
cf5b4aa6 DE |
1009 | #define EA ea = fetch(&code->src); |
1010 | #define RD_EA ea = fetch(&code->src); rd = fetch(&code->dst); | |
ce51bde6 | 1011 | |
0693d363 DE |
1012 | ALUOP (1, O_SUB, RD_EA; |
1013 | ea = -ea; | |
1014 | res = rd + ea); | |
1015 | ALUOP (1, O_NEG, EA; | |
1016 | ea = -ea; | |
1017 | rd = 0; | |
1018 | res = rd + ea); | |
ce51bde6 | 1019 | |
0693d363 DE |
1020 | case O (O_ADD, SB): |
1021 | rd = GET_B_REG (code->dst.reg); | |
1022 | ea = fetch (&code->src); | |
ce51bde6 DE |
1023 | res = rd + ea; |
1024 | goto alu8; | |
0693d363 DE |
1025 | case O (O_ADD, SW): |
1026 | rd = GET_W_REG (code->dst.reg); | |
1027 | ea = fetch (&code->src); | |
ce51bde6 DE |
1028 | res = rd + ea; |
1029 | goto alu16; | |
0693d363 DE |
1030 | case O (O_ADD, SL): |
1031 | rd = GET_L_REG (code->dst.reg); | |
1032 | ea = fetch (&code->src); | |
ce51bde6 DE |
1033 | res = rd + ea; |
1034 | goto alu32; | |
ce51bde6 | 1035 | |
ce51bde6 | 1036 | |
0693d363 DE |
1037 | LOGOP (O_AND, RD_EA; |
1038 | res = rd & ea); | |
1039 | ||
1040 | LOGOP (O_OR, RD_EA; | |
1041 | res = rd | ea); | |
ce51bde6 | 1042 | |
0693d363 DE |
1043 | LOGOP (O_XOR, RD_EA; |
1044 | res = rd ^ ea); | |
ce51bde6 DE |
1045 | |
1046 | ||
0693d363 DE |
1047 | case O (O_MOV_TO_MEM, SB): |
1048 | res = GET_B_REG (code->src.reg); | |
ce51bde6 | 1049 | goto log8; |
0693d363 DE |
1050 | case O (O_MOV_TO_MEM, SW): |
1051 | res = GET_W_REG (code->src.reg); | |
ce51bde6 | 1052 | goto log16; |
0693d363 DE |
1053 | case O (O_MOV_TO_MEM, SL): |
1054 | res = GET_L_REG (code->src.reg); | |
ce51bde6 DE |
1055 | goto log32; |
1056 | ||
1057 | ||
0693d363 DE |
1058 | case O (O_MOV_TO_REG, SB): |
1059 | res = fetch (&code->src); | |
1060 | SET_B_REG (code->dst.reg, res); | |
ce51bde6 | 1061 | goto just_flags_log8; |
0693d363 DE |
1062 | case O (O_MOV_TO_REG, SW): |
1063 | res = fetch (&code->src); | |
1064 | SET_W_REG (code->dst.reg, res); | |
ce51bde6 | 1065 | goto just_flags_log16; |
0693d363 DE |
1066 | case O (O_MOV_TO_REG, SL): |
1067 | res = fetch (&code->src); | |
1068 | SET_L_REG (code->dst.reg, res); | |
ce51bde6 DE |
1069 | goto just_flags_log32; |
1070 | ||
1071 | ||
0693d363 DE |
1072 | case O (O_ADDS, SL): |
1073 | SET_L_REG (code->dst.reg, | |
1074 | GET_L_REG (code->dst.reg) | |
1075 | + code->src.literal); | |
1076 | ||
ce51bde6 DE |
1077 | goto next; |
1078 | ||
0693d363 DE |
1079 | case O (O_SUBS, SL): |
1080 | SET_L_REG (code->dst.reg, | |
1081 | GET_L_REG (code->dst.reg) | |
1082 | - code->src.literal); | |
ce51bde6 | 1083 | goto next; |
0693d363 | 1084 | |
ce51bde6 DE |
1085 | case O (O_CMP, SB): |
1086 | rd = fetch (&code->dst); | |
1087 | ea = fetch (&code->src); | |
1088 | ea = -ea; | |
1089 | res = rd + ea; | |
1090 | goto just_flags_alu8; | |
1091 | ||
1092 | case O (O_CMP, SW): | |
1093 | rd = fetch (&code->dst); | |
1094 | ea = fetch (&code->src); | |
1095 | ea = -ea; | |
1096 | res = rd + ea; | |
1097 | goto just_flags_alu16; | |
1098 | ||
1099 | case O (O_CMP, SL): | |
1100 | rd = fetch (&code->dst); | |
1101 | ea = fetch (&code->src); | |
1102 | ea = -ea; | |
1103 | res = rd + ea; | |
1104 | goto just_flags_alu32; | |
1105 | ||
1106 | ||
1107 | case O (O_DEC, SB): | |
1108 | rd = GET_B_REG (code->src.reg); | |
1109 | ea = -1; | |
1110 | res = rd + ea; | |
1111 | SET_B_REG (code->src.reg, res); | |
1112 | goto just_flags_inc8; | |
1113 | ||
1114 | case O (O_DEC, SW): | |
1115 | rd = GET_W_REG (code->dst.reg); | |
0693d363 | 1116 | ea = -code->src.literal; |
ce51bde6 DE |
1117 | res = rd + ea; |
1118 | SET_W_REG (code->dst.reg, res); | |
1119 | goto just_flags_inc16; | |
1120 | ||
1121 | case O (O_DEC, SL): | |
1122 | rd = GET_L_REG (code->dst.reg); | |
1123 | ea = -code->src.literal; | |
1124 | res = rd + ea; | |
1125 | SET_L_REG (code->dst.reg, res); | |
1126 | goto just_flags_inc32; | |
1127 | ||
1128 | ||
1129 | case O (O_INC, SB): | |
1130 | rd = GET_B_REG (code->src.reg); | |
1131 | ea = 1; | |
1132 | res = rd + ea; | |
1133 | SET_B_REG (code->src.reg, res); | |
1134 | goto just_flags_inc8; | |
1135 | ||
1136 | case O (O_INC, SW): | |
1137 | rd = GET_W_REG (code->dst.reg); | |
1138 | ea = code->src.literal; | |
1139 | res = rd + ea; | |
1140 | SET_W_REG (code->dst.reg, res); | |
1141 | goto just_flags_inc16; | |
1142 | ||
1143 | case O (O_INC, SL): | |
1144 | rd = GET_L_REG (code->dst.reg); | |
1145 | ea = code->src.literal; | |
1146 | res = rd + ea; | |
1147 | SET_L_REG (code->dst.reg, res); | |
1148 | goto just_flags_inc32; | |
1149 | ||
1150 | ||
1151 | #define GET_CCR(x) BUILDSR();x = cpu.ccr | |
0693d363 | 1152 | |
ce51bde6 DE |
1153 | case O (O_ANDC, SB): |
1154 | GET_CCR (rd); | |
1155 | ea = code->src.literal; | |
1156 | res = rd & ea; | |
1157 | goto setc; | |
1158 | ||
0693d363 DE |
1159 | case O (O_ORC, SB): |
1160 | GET_CCR (rd); | |
1161 | ea = code->src.literal; | |
1162 | res = rd | ea; | |
1163 | goto setc; | |
1164 | ||
1165 | case O (O_XORC, SB): | |
1166 | GET_CCR (rd); | |
1167 | ea = code->src.literal; | |
1168 | res = rd ^ ea; | |
1169 | goto setc; | |
1170 | ||
ce51bde6 DE |
1171 | |
1172 | case O (O_BRA, SB): | |
1173 | if (1) | |
1174 | goto condtrue; | |
1175 | goto next; | |
1176 | ||
1177 | case O (O_BRN, SB): | |
1178 | if (0) | |
1179 | goto condtrue; | |
1180 | goto next; | |
1181 | ||
1182 | case O (O_BHI, SB): | |
1183 | if ((C || Z) == 0) | |
1184 | goto condtrue; | |
1185 | goto next; | |
1186 | ||
1187 | ||
1188 | case O (O_BLS, SB): | |
1189 | if ((C || Z)) | |
1190 | goto condtrue; | |
1191 | goto next; | |
1192 | ||
1193 | case O (O_BCS, SB): | |
1194 | if ((C == 1)) | |
1195 | goto condtrue; | |
1196 | goto next; | |
1197 | ||
1198 | case O (O_BCC, SB): | |
1199 | if ((C == 0)) | |
1200 | goto condtrue; | |
1201 | goto next; | |
1202 | ||
1203 | case O (O_BEQ, SB): | |
1204 | if (Z) | |
1205 | goto condtrue; | |
1206 | goto next; | |
1207 | case O (O_BGT, SB): | |
1208 | if (((Z || (N ^ V)) == 0)) | |
1209 | goto condtrue; | |
1210 | goto next; | |
1211 | ||
1212 | ||
1213 | case O (O_BLE, SB): | |
1214 | if (((Z || (N ^ V)) == 1)) | |
1215 | goto condtrue; | |
1216 | goto next; | |
1217 | ||
1218 | case O (O_BGE, SB): | |
1219 | if ((N ^ V) == 0) | |
1220 | goto condtrue; | |
1221 | goto next; | |
1222 | case O (O_BLT, SB): | |
1223 | if ((N ^ V)) | |
1224 | goto condtrue; | |
1225 | goto next; | |
1226 | case O (O_BMI, SB): | |
1227 | if ((N)) | |
1228 | goto condtrue; | |
1229 | goto next; | |
1230 | case O (O_BNE, SB): | |
1231 | if ((Z == 0)) | |
1232 | goto condtrue; | |
1233 | goto next; | |
1234 | ||
1235 | case O (O_BPL, SB): | |
1236 | if (N == 0) | |
1237 | goto condtrue; | |
1238 | goto next; | |
1239 | case O (O_BVC, SB): | |
1240 | if ((V == 0)) | |
1241 | goto condtrue; | |
1242 | goto next; | |
1243 | case O (O_BVS, SB): | |
1244 | if ((V == 1)) | |
1245 | goto condtrue; | |
1246 | goto next; | |
1247 | ||
0693d363 DE |
1248 | case O (O_SYSCALL, SB): |
1249 | printf ("%c", cpu.regs[2]); | |
ce51bde6 | 1250 | goto next; |
ce51bde6 | 1251 | |
7647e0dd JL |
1252 | ONOT (O_NOT, rd = ~rd; v = 0;); |
1253 | OSHIFTS (O_SHLL, | |
1254 | c = rd & hm; v = 0; rd <<= 1, | |
1255 | c = rd & (hm >> 1); v = 0; rd <<= 2); | |
1256 | OSHIFTS (O_SHLR, | |
1257 | c = rd & 1; v = 0; rd = (unsigned int) rd >> 1, | |
1258 | c = rd & 2; v = 0; rd = (unsigned int) rd >> 2); | |
1259 | OSHIFTS (O_SHAL, | |
1260 | c = rd & hm; v = (rd & hm) != ((rd & (hm >> 1)) << 1); rd <<= 1, | |
1261 | c = rd & (hm >> 1); v = (rd & (hm >> 1)) != ((rd & (hm >> 2)) << 2); rd <<= 2); | |
1262 | OSHIFTS (O_SHAR, | |
1263 | t = rd & hm; c = rd & 1; v = 0; rd >>= 1; rd |= t, | |
1264 | t = rd & hm; c = rd & 2; v = 0; rd >>= 2; rd |= t | t >> 1 ); | |
1265 | OSHIFTS (O_ROTL, | |
1266 | c = rd & hm; v = 0; rd <<= 1; rd |= C, | |
9745c593 | 1267 | c = rd & hm; v = 0; rd <<= 1; rd |= C; c = rd & hm; rd <<= 1; rd |= C); |
7647e0dd JL |
1268 | OSHIFTS (O_ROTR, |
1269 | c = rd & 1; v = 0; rd = (unsigned int) rd >> 1; if (c) rd |= hm, | |
9745c593 | 1270 | c = rd & 1; v = 0; rd = (unsigned int) rd >> 1; if (c) rd |= hm; c = rd & 1; rd = (unsigned int) rd >> 1; if (c) rd |= hm); |
7647e0dd JL |
1271 | OSHIFTS (O_ROTXL, |
1272 | t = rd & hm; rd <<= 1; rd |= C; c = t; v = 0, | |
9745c593 | 1273 | t = rd & hm; rd <<= 1; rd |= C; c = t; v = 0; t = rd & hm; rd <<= 1; rd |= C; c = t); |
7647e0dd JL |
1274 | OSHIFTS (O_ROTXR, |
1275 | t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd |= hm; c = t; v = 0, | |
9745c593 | 1276 | t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd |= hm; c = t; v = 0; t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd |= hm; c = t); |
0693d363 DE |
1277 | |
1278 | case O (O_JMP, SB): | |
ce51bde6 DE |
1279 | { |
1280 | pc = fetch (&code->src); | |
1281 | goto end; | |
0693d363 | 1282 | |
ce51bde6 | 1283 | } |
0693d363 | 1284 | |
ce51bde6 DE |
1285 | case O (O_JSR, SB): |
1286 | { | |
1287 | int tmp; | |
1288 | pc = fetch (&code->src); | |
1289 | call: | |
1290 | tmp = cpu.regs[7]; | |
1291 | ||
28655f00 | 1292 | if (h8300hmode) |
ce51bde6 DE |
1293 | { |
1294 | tmp -= 4; | |
1295 | SET_MEMORY_L (tmp, code->next_pc); | |
1296 | } | |
1297 | else | |
1298 | { | |
1299 | tmp -= 2; | |
1300 | SET_MEMORY_W (tmp, code->next_pc); | |
1301 | } | |
1302 | cpu.regs[7] = tmp; | |
1303 | ||
1304 | goto end; | |
1305 | } | |
0693d363 | 1306 | case O (O_BSR, SB): |
ce51bde6 DE |
1307 | pc = code->src.literal; |
1308 | goto call; | |
0693d363 | 1309 | |
ce51bde6 DE |
1310 | case O (O_RTS, SB): |
1311 | { | |
1312 | int tmp; | |
1313 | ||
ce51bde6 DE |
1314 | tmp = cpu.regs[7]; |
1315 | ||
28655f00 | 1316 | if (h8300hmode) |
ce51bde6 DE |
1317 | { |
1318 | pc = GET_MEMORY_L (tmp); | |
1319 | tmp += 4; | |
ce51bde6 DE |
1320 | } |
1321 | else | |
1322 | { | |
1323 | pc = GET_MEMORY_W (tmp); | |
1324 | tmp += 2; | |
1325 | } | |
1326 | ||
1327 | cpu.regs[7] = tmp; | |
1328 | goto end; | |
1329 | } | |
1330 | ||
1331 | case O (O_ILL, SB): | |
1332 | cpu.exception = SIGILL; | |
1333 | goto end; | |
0693d363 | 1334 | case O (O_SLEEP, SB): |
4dfb4ffc DE |
1335 | /* The format of r0 is defined by devo/include/wait.h. |
1336 | cpu.exception handling needs some cleanup: we need to make the | |
1337 | the handling of normal exits vs signals, etc. more sensible. */ | |
1338 | if (! WIFEXITED (cpu.regs[0]) && WIFSIGNALED (cpu.regs[0])) | |
e656ecf9 DE |
1339 | cpu.exception = SIGILL; |
1340 | else | |
1341 | cpu.exception = SIGTRAP; | |
1342 | goto end; | |
0693d363 | 1343 | case O (O_BPT, SB): |
ce51bde6 DE |
1344 | cpu.exception = SIGTRAP; |
1345 | goto end; | |
1346 | ||
0693d363 DE |
1347 | OBITOP (O_BNOT, 1, 1, ea ^= m); |
1348 | OBITOP (O_BTST, 1, 0, nz = ea & m); | |
1349 | OBITOP (O_BCLR, 1, 1, ea &= ~m); | |
1350 | OBITOP (O_BSET, 1, 1, ea |= m); | |
1351 | OBITOP (O_BLD, 1, 0, c = ea & m); | |
1352 | OBITOP (O_BILD, 1, 0, c = !(ea & m)); | |
1353 | OBITOP (O_BST, 1, 1, ea &= ~m; | |
1354 | if (C) ea |= m); | |
1355 | OBITOP (O_BIST, 1, 1, ea &= ~m; | |
1356 | if (!C) ea |= m); | |
1357 | OBITOP (O_BAND, 1, 0, c = (ea & m) && C); | |
1358 | OBITOP (O_BIAND, 1, 0, c = !(ea & m) && C); | |
1359 | OBITOP (O_BOR, 1, 0, c = (ea & m) || C); | |
1360 | OBITOP (O_BIOR, 1, 0, c = !(ea & m) || C); | |
1361 | OBITOP (O_BXOR, 1, 0, c = (ea & m) != C); | |
1362 | OBITOP (O_BIXOR, 1, 0, c = !(ea & m) != C); | |
ce51bde6 DE |
1363 | |
1364 | ||
28655f00 | 1365 | #define MOP(bsize, signed) mop(code, bsize,signed); goto next; |
ce51bde6 | 1366 | |
0693d363 DE |
1367 | case O (O_MULS, SB): |
1368 | MOP (1, 1); | |
1369 | break; | |
1370 | case O (O_MULS, SW): | |
1371 | MOP (0, 1); | |
1372 | break; | |
1373 | case O (O_MULU, SB): | |
1374 | MOP (1, 0); | |
1375 | break; | |
1376 | case O (O_MULU, SW): | |
1377 | MOP (0, 0); | |
1378 | break; | |
ce51bde6 | 1379 | |
ce51bde6 | 1380 | |
0693d363 DE |
1381 | case O (O_DIVU, SB): |
1382 | { | |
1383 | rd = GET_W_REG (code->dst.reg); | |
1384 | ea = GET_B_REG (code->src.reg); | |
1385 | if (ea) | |
1386 | { | |
7e1e013f JL |
1387 | tmp = (unsigned)rd % ea; |
1388 | rd = (unsigned)rd / ea; | |
0693d363 DE |
1389 | } |
1390 | SET_W_REG (code->dst.reg, (rd & 0xff) | (tmp << 8)); | |
1391 | n = ea & 0x80; | |
1392 | nz = ea & 0xff; | |
ce51bde6 | 1393 | |
0693d363 DE |
1394 | goto next; |
1395 | } | |
1396 | case O (O_DIVU, SW): | |
1397 | { | |
1398 | rd = GET_L_REG (code->dst.reg); | |
1399 | ea = GET_W_REG (code->src.reg); | |
1400 | n = ea & 0x8000; | |
1401 | nz = ea & 0xffff; | |
1402 | if (ea) | |
1403 | { | |
7e1e013f JL |
1404 | tmp = (unsigned)rd % ea; |
1405 | rd = (unsigned)rd / ea; | |
0693d363 DE |
1406 | } |
1407 | SET_L_REG (code->dst.reg, (rd & 0xffff) | (tmp << 16)); | |
1408 | goto next; | |
1409 | } | |
ce51bde6 | 1410 | |
0693d363 DE |
1411 | case O (O_DIVS, SB): |
1412 | { | |
ce51bde6 | 1413 | |
0693d363 DE |
1414 | rd = SEXTSHORT (GET_W_REG (code->dst.reg)); |
1415 | ea = SEXTCHAR (GET_B_REG (code->src.reg)); | |
1416 | if (ea) | |
1417 | { | |
1418 | tmp = (int) rd % (int) ea; | |
1419 | rd = (int) rd / (int) ea; | |
1420 | n = rd & 0x8000; | |
1421 | nz = 1; | |
1422 | } | |
1423 | else | |
1424 | nz = 0; | |
1425 | SET_W_REG (code->dst.reg, (rd & 0xff) | (tmp << 8)); | |
1426 | goto next; | |
1427 | } | |
1428 | case O (O_DIVS, SW): | |
1429 | { | |
1430 | rd = GET_L_REG (code->dst.reg); | |
1431 | ea = SEXTSHORT (GET_W_REG (code->src.reg)); | |
1432 | if (ea) | |
1433 | { | |
1434 | tmp = (int) rd % (int) ea; | |
1435 | rd = (int) rd / (int) ea; | |
1436 | n = rd & 0x80000000; | |
1437 | nz = 1; | |
1438 | } | |
1439 | else | |
1440 | nz = 0; | |
1441 | SET_L_REG (code->dst.reg, (rd & 0xffff) | (tmp << 16)); | |
1442 | goto next; | |
1443 | } | |
1444 | case O (O_EXTS, SW): | |
7478904c | 1445 | rd = GET_B_REG (code->src.reg + 8) & 0xff; /* Yes, src, not dst. */ |
0693d363 DE |
1446 | ea = rd & 0x80 ? -256 : 0; |
1447 | res = rd + ea; | |
1448 | goto log16; | |
1449 | case O (O_EXTS, SL): | |
1450 | rd = GET_W_REG (code->src.reg) & 0xffff; | |
1451 | ea = rd & 0x8000 ? -65536 : 0; | |
1452 | res = rd + ea; | |
1453 | goto log32; | |
1454 | case O (O_EXTU, SW): | |
1455 | rd = GET_B_REG (code->src.reg + 8) & 0xff; | |
1456 | ea = 0; | |
1457 | res = rd + ea; | |
1458 | goto log16; | |
1459 | case O (O_EXTU, SL): | |
1460 | rd = GET_W_REG (code->src.reg) & 0xffff; | |
1461 | ea = 0; | |
1462 | res = rd + ea; | |
1463 | goto log32; | |
ce51bde6 | 1464 | |
0693d363 DE |
1465 | case O (O_NOP, SB): |
1466 | goto next; | |
ce51bde6 | 1467 | |
171f4664 JL |
1468 | case O (O_STM, SL): |
1469 | { | |
1470 | int nregs, firstreg, i; | |
1471 | ||
1472 | nregs = GET_MEMORY_B (pc + 1); | |
1473 | nregs >>= 4; | |
1474 | nregs &= 0xf; | |
1475 | firstreg = GET_MEMORY_B (pc + 3); | |
1476 | firstreg &= 0xf; | |
1477 | for (i = firstreg; i <= firstreg + nregs; i++) | |
1478 | { | |
1479 | cpu.regs[7] -= 4; | |
1480 | SET_MEMORY_L (cpu.regs[7], cpu.regs[i]); | |
1481 | } | |
1482 | } | |
1483 | goto next; | |
1484 | ||
1485 | case O (O_LDM, SL): | |
1486 | { | |
1487 | int nregs, firstreg, i; | |
1488 | ||
1489 | nregs = GET_MEMORY_B (pc + 1); | |
1490 | nregs >>= 4; | |
1491 | nregs &= 0xf; | |
1492 | firstreg = GET_MEMORY_B (pc + 3); | |
1493 | firstreg &= 0xf; | |
1494 | for (i = firstreg; i >= firstreg - nregs; i--) | |
1495 | { | |
1496 | cpu.regs[i] = GET_MEMORY_L (cpu.regs[7]); | |
1497 | cpu.regs[7] += 4; | |
1498 | } | |
1499 | } | |
1500 | goto next; | |
1501 | ||
0693d363 | 1502 | default: |
7478904c | 1503 | cpu.exception = SIGILL; |
0693d363 | 1504 | goto end; |
ce51bde6 DE |
1505 | |
1506 | } | |
0693d363 DE |
1507 | abort (); |
1508 | ||
1509 | setc: | |
1510 | cpu.ccr = res; | |
1511 | GETSR (); | |
28655f00 SC |
1512 | goto next; |
1513 | ||
0693d363 DE |
1514 | condtrue: |
1515 | /* When a branch works */ | |
1516 | pc = code->src.literal; | |
ce51bde6 DE |
1517 | goto end; |
1518 | ||
0693d363 DE |
1519 | /* Set the cond codes from res */ |
1520 | bitop: | |
ce51bde6 | 1521 | |
0693d363 DE |
1522 | /* Set the flags after an 8 bit inc/dec operation */ |
1523 | just_flags_inc8: | |
1524 | n = res & 0x80; | |
1525 | nz = res & 0xff; | |
1526 | v = (rd & 0x7f) == 0x7f; | |
1527 | goto next; | |
ce51bde6 | 1528 | |
ce51bde6 | 1529 | |
0693d363 DE |
1530 | /* Set the flags after an 16 bit inc/dec operation */ |
1531 | just_flags_inc16: | |
1532 | n = res & 0x8000; | |
1533 | nz = res & 0xffff; | |
1534 | v = (rd & 0x7fff) == 0x7fff; | |
1535 | goto next; | |
1536 | ||
1537 | ||
1538 | /* Set the flags after an 32 bit inc/dec operation */ | |
1539 | just_flags_inc32: | |
1540 | n = res & 0x80000000; | |
1541 | nz = res & 0xffffffff; | |
1542 | v = (rd & 0x7fffffff) == 0x7fffffff; | |
1543 | goto next; | |
1544 | ||
1545 | ||
1546 | shift8: | |
5d06fa80 | 1547 | /* Set flags after an 8 bit shift op, carry,overflow set in insn */ |
0693d363 | 1548 | n = (rd & 0x80); |
0693d363 DE |
1549 | nz = rd & 0xff; |
1550 | SET_B_REG (code->src.reg, rd); | |
1551 | goto next; | |
1552 | ||
0693d363 | 1553 | shift16: |
5d06fa80 | 1554 | /* Set flags after an 16 bit shift op, carry,overflow set in insn */ |
0693d363 | 1555 | n = (rd & 0x8000); |
0693d363 | 1556 | nz = rd & 0xffff; |
0693d363 DE |
1557 | SET_W_REG (code->src.reg, rd); |
1558 | goto next; | |
1559 | ||
1560 | shift32: | |
5d06fa80 | 1561 | /* Set flags after an 32 bit shift op, carry,overflow set in insn */ |
0693d363 | 1562 | n = (rd & 0x80000000); |
0693d363 DE |
1563 | nz = rd & 0xffffffff; |
1564 | SET_L_REG (code->src.reg, rd); | |
1565 | goto next; | |
1566 | ||
1567 | log32: | |
1568 | store (&code->dst, res); | |
1569 | just_flags_log32: | |
1570 | /* flags after a 32bit logical operation */ | |
1571 | n = res & 0x80000000; | |
1572 | nz = res & 0xffffffff; | |
1573 | v = 0; | |
1574 | goto next; | |
1575 | ||
1576 | log16: | |
1577 | store (&code->dst, res); | |
1578 | just_flags_log16: | |
1579 | /* flags after a 16bit logical operation */ | |
1580 | n = res & 0x8000; | |
1581 | nz = res & 0xffff; | |
1582 | v = 0; | |
1583 | goto next; | |
1584 | ||
1585 | ||
1586 | log8: | |
1587 | store (&code->dst, res); | |
1588 | just_flags_log8: | |
1589 | n = res & 0x80; | |
1590 | nz = res & 0xff; | |
1591 | v = 0; | |
1592 | goto next; | |
1593 | ||
1594 | alu8: | |
1595 | SET_B_REG (code->dst.reg, res); | |
1596 | just_flags_alu8: | |
1597 | n = res & 0x80; | |
1598 | nz = res & 0xff; | |
0693d363 | 1599 | c = (res & 0x100); |
50d45d1b JL |
1600 | switch (code->opcode / 4) |
1601 | { | |
1602 | case O_ADD: | |
1603 | v = ((rd & 0x80) == (ea & 0x80) | |
1604 | && (rd & 0x80) != (res & 0x80)); | |
1605 | break; | |
1606 | case O_SUB: | |
1607 | case O_CMP: | |
1608 | v = ((rd & 0x80) != (-ea & 0x80) | |
1609 | && (rd & 0x80) != (res & 0x80)); | |
1610 | break; | |
1611 | case O_NEG: | |
1612 | v = (rd == 0x80); | |
1613 | break; | |
1614 | } | |
0693d363 DE |
1615 | goto next; |
1616 | ||
1617 | alu16: | |
1618 | SET_W_REG (code->dst.reg, res); | |
1619 | just_flags_alu16: | |
1620 | n = res & 0x8000; | |
1621 | nz = res & 0xffff; | |
0693d363 | 1622 | c = (res & 0x10000); |
50d45d1b JL |
1623 | switch (code->opcode / 4) |
1624 | { | |
1625 | case O_ADD: | |
1626 | v = ((rd & 0x8000) == (ea & 0x8000) | |
1627 | && (rd & 0x8000) != (res & 0x8000)); | |
1628 | break; | |
1629 | case O_SUB: | |
1630 | case O_CMP: | |
1631 | v = ((rd & 0x8000) != (-ea & 0x8000) | |
1632 | && (rd & 0x8000) != (res & 0x8000)); | |
1633 | break; | |
1634 | case O_NEG: | |
1635 | v = (rd == 0x8000); | |
1636 | break; | |
1637 | } | |
0693d363 DE |
1638 | goto next; |
1639 | ||
1640 | alu32: | |
1641 | SET_L_REG (code->dst.reg, res); | |
1642 | just_flags_alu32: | |
1643 | n = res & 0x80000000; | |
1644 | nz = res & 0xffffffff; | |
50d45d1b JL |
1645 | switch (code->opcode / 4) |
1646 | { | |
1647 | case O_ADD: | |
1648 | v = ((rd & 0x80000000) == (ea & 0x80000000) | |
1649 | && (rd & 0x80000000) != (res & 0x80000000)); | |
9b127161 | 1650 | c = ((unsigned) res < (unsigned) rd) || ((unsigned) res < (unsigned) ea); |
50d45d1b JL |
1651 | break; |
1652 | case O_SUB: | |
1653 | case O_CMP: | |
1654 | v = ((rd & 0x80000000) != (-ea & 0x80000000) | |
1655 | && (rd & 0x80000000) != (res & 0x80000000)); | |
0693d363 DE |
1656 | c = (unsigned) rd < (unsigned) -ea; |
1657 | break; | |
1658 | case O_NEG: | |
9b127161 | 1659 | v = (rd == 0x80000000); |
0693d363 DE |
1660 | c = res != 0; |
1661 | break; | |
1662 | } | |
1663 | goto next; | |
1664 | ||
1665 | next:; | |
1666 | pc = code->next_pc; | |
1667 | ||
1668 | end: | |
1669 | ; | |
1670 | /* if (cpu.regs[8] ) abort(); */ | |
1671 | ||
7478904c SC |
1672 | #if defined (WIN32) |
1673 | /* Poll after every 100th insn, */ | |
1674 | if (poll_count++ > 100) | |
1675 | { | |
1676 | poll_count = 0; | |
1677 | if (win32pollquit()) | |
1678 | { | |
1679 | control_c(); | |
1680 | } | |
1681 | } | |
1682 | #endif | |
1683 | #if defined(__GO32__) | |
0693d363 DE |
1684 | /* Poll after every 100th insn, */ |
1685 | if (poll_count++ > 100) | |
1686 | { | |
1687 | poll_count = 0; | |
1688 | if (kbhit ()) | |
1689 | { | |
1690 | int c = getkey (); | |
1691 | control_c (); | |
1692 | } | |
1693 | } | |
1694 | #endif | |
1695 | ||
1696 | } | |
ce51bde6 DE |
1697 | while (!cpu.exception); |
1698 | cpu.ticks += get_now () - tick_start; | |
1699 | cpu.cycles += cycles; | |
1700 | cpu.insts += insts; | |
7478904c | 1701 | |
ce51bde6 DE |
1702 | cpu.pc = pc; |
1703 | BUILDSR (); | |
7478904c | 1704 | cpu.mask = oldmask; |
ce51bde6 DE |
1705 | signal (SIGINT, prev); |
1706 | } | |
1707 | ||
1708 | ||
28655f00 | 1709 | int |
ce51bde6 | 1710 | sim_write (addr, buffer, size) |
a415cf0a | 1711 | SIM_ADDR addr; |
ce51bde6 DE |
1712 | unsigned char *buffer; |
1713 | int size; | |
1714 | { | |
1715 | int i; | |
1716 | ||
1717 | init_pointers (); | |
7e1e013f | 1718 | if (addr < 0) |
a415cf0a | 1719 | return 0; |
ce51bde6 DE |
1720 | for (i = 0; i < size; i++) |
1721 | { | |
7e1e013f JL |
1722 | if (addr < memory_size) |
1723 | { | |
1724 | cpu.memory[addr + i] = buffer[i]; | |
1725 | cpu.cache_idx[addr + i] = 0; | |
1726 | } | |
1727 | else | |
1728 | cpu.eightbit[(addr + i) & 0xff] = buffer[i]; | |
ce51bde6 | 1729 | } |
a415cf0a | 1730 | return size; |
ce51bde6 DE |
1731 | } |
1732 | ||
28655f00 | 1733 | int |
ce51bde6 | 1734 | sim_read (addr, buffer, size) |
a415cf0a DE |
1735 | SIM_ADDR addr; |
1736 | unsigned char *buffer; | |
ce51bde6 DE |
1737 | int size; |
1738 | { | |
1739 | init_pointers (); | |
7e1e013f | 1740 | if (addr < 0) |
a415cf0a | 1741 | return 0; |
7e1e013f JL |
1742 | if (addr < memory_size) |
1743 | memcpy (buffer, cpu.memory + addr, size); | |
1744 | else | |
1745 | memcpy (buffer, cpu.eightbit + (addr & 0xff), size); | |
28655f00 | 1746 | return size; |
ce51bde6 DE |
1747 | } |
1748 | ||
1749 | ||
ce51bde6 DE |
1750 | #define R0_REGNUM 0 |
1751 | #define R1_REGNUM 1 | |
1752 | #define R2_REGNUM 2 | |
1753 | #define R3_REGNUM 3 | |
1754 | #define R4_REGNUM 4 | |
1755 | #define R5_REGNUM 5 | |
1756 | #define R6_REGNUM 6 | |
1757 | #define R7_REGNUM 7 | |
1758 | ||
1759 | #define SP_REGNUM R7_REGNUM /* Contains address of top of stack */ | |
1760 | #define FP_REGNUM R6_REGNUM /* Contains address of executing | |
0693d363 | 1761 | * stack frame */ |
ce51bde6 DE |
1762 | |
1763 | #define CCR_REGNUM 8 /* Contains processor status */ | |
1764 | #define PC_REGNUM 9 /* Contains program counter */ | |
1765 | ||
1766 | #define CYCLE_REGNUM 10 | |
1767 | #define INST_REGNUM 11 | |
1768 | #define TICK_REGNUM 12 | |
1769 | ||
1770 | ||
7478904c | 1771 | void |
ce51bde6 DE |
1772 | sim_store_register (rn, value) |
1773 | int rn; | |
28655f00 | 1774 | unsigned char *value; |
ce51bde6 | 1775 | { |
28655f00 SC |
1776 | int longval; |
1777 | int shortval; | |
1778 | int intval; | |
0693d363 DE |
1779 | longval = (value[0] << 24) | (value[1] << 16) | (value[2] << 8) | value[3]; |
1780 | shortval = (value[0] << 8) | (value[1]); | |
28655f00 | 1781 | intval = h8300hmode ? longval : shortval; |
ce51bde6 DE |
1782 | |
1783 | init_pointers (); | |
1784 | switch (rn) | |
1785 | { | |
1786 | case PC_REGNUM: | |
28655f00 | 1787 | cpu.pc = intval; |
ce51bde6 DE |
1788 | break; |
1789 | default: | |
1790 | abort (); | |
1791 | case R0_REGNUM: | |
1792 | case R1_REGNUM: | |
1793 | case R2_REGNUM: | |
1794 | case R3_REGNUM: | |
1795 | case R4_REGNUM: | |
1796 | case R5_REGNUM: | |
1797 | case R6_REGNUM: | |
1798 | case R7_REGNUM: | |
28655f00 | 1799 | cpu.regs[rn] = intval; |
ce51bde6 DE |
1800 | break; |
1801 | case CCR_REGNUM: | |
28655f00 | 1802 | cpu.ccr = intval; |
ce51bde6 DE |
1803 | break; |
1804 | case CYCLE_REGNUM: | |
28655f00 | 1805 | cpu.cycles = longval; |
ce51bde6 DE |
1806 | break; |
1807 | ||
1808 | case INST_REGNUM: | |
28655f00 | 1809 | cpu.insts = longval; |
ce51bde6 DE |
1810 | break; |
1811 | ||
1812 | case TICK_REGNUM: | |
28655f00 | 1813 | cpu.ticks = longval; |
ce51bde6 DE |
1814 | break; |
1815 | } | |
1816 | } | |
1817 | ||
7478904c | 1818 | void |
ce51bde6 DE |
1819 | sim_fetch_register (rn, buf) |
1820 | int rn; | |
a415cf0a | 1821 | unsigned char *buf; |
ce51bde6 DE |
1822 | { |
1823 | int v; | |
1824 | int longreg = 0; | |
1825 | ||
1826 | init_pointers (); | |
1827 | ||
1828 | switch (rn) | |
1829 | { | |
1830 | default: | |
1831 | abort (); | |
1832 | case 8: | |
1833 | v = cpu.ccr; | |
1834 | break; | |
1835 | case 9: | |
1836 | v = cpu.pc; | |
1837 | break; | |
1838 | case R0_REGNUM: | |
1839 | case R1_REGNUM: | |
1840 | case R2_REGNUM: | |
1841 | case R3_REGNUM: | |
1842 | case R4_REGNUM: | |
1843 | case R5_REGNUM: | |
1844 | case R6_REGNUM: | |
1845 | case R7_REGNUM: | |
1846 | v = cpu.regs[rn]; | |
1847 | break; | |
1848 | case 10: | |
1849 | v = cpu.cycles; | |
1850 | longreg = 1; | |
ce51bde6 DE |
1851 | break; |
1852 | case 11: | |
1853 | v = cpu.ticks; | |
1854 | longreg = 1; | |
1855 | break; | |
1856 | case 12: | |
1857 | v = cpu.insts; | |
1858 | longreg = 1; | |
1859 | break; | |
ce51bde6 | 1860 | } |
28655f00 | 1861 | if (h8300hmode || longreg) |
ce51bde6 DE |
1862 | { |
1863 | buf[0] = v >> 24; | |
1864 | buf[1] = v >> 16; | |
1865 | buf[2] = v >> 8; | |
1866 | buf[3] = v >> 0; | |
1867 | } | |
1868 | else | |
1869 | { | |
1870 | buf[0] = v >> 8; | |
1871 | buf[1] = v; | |
1872 | } | |
1873 | } | |
1874 | ||
7478904c | 1875 | void |
a415cf0a DE |
1876 | sim_stop_reason (reason, sigrc) |
1877 | enum sim_stop *reason; | |
1878 | int *sigrc; | |
ce51bde6 | 1879 | { |
a415cf0a | 1880 | *reason = sim_stopped; |
7db9345b | 1881 | *sigrc = cpu.exception; |
ce51bde6 DE |
1882 | } |
1883 | ||
ce51bde6 DE |
1884 | sim_csize (n) |
1885 | { | |
1886 | if (cpu.cache) | |
1887 | free (cpu.cache); | |
1888 | if (n < 2) | |
1889 | n = 2; | |
1890 | cpu.cache = (decoded_inst *) malloc (sizeof (decoded_inst) * n); | |
1891 | memset (cpu.cache, 0, sizeof (decoded_inst) * n); | |
1892 | cpu.csize = n; | |
1893 | } | |
1894 | ||
1895 | ||
7478904c SC |
1896 | void |
1897 | sim_info (verbose) | |
ce51bde6 | 1898 | int verbose; |
ce51bde6 DE |
1899 | { |
1900 | double timetaken = (double) cpu.ticks / (double) now_persec (); | |
1901 | double virttime = cpu.cycles / 10.0e6; | |
1902 | ||
7478904c SC |
1903 | printf_filtered ("\n\n#instructions executed %10d\n", cpu.insts); |
1904 | printf_filtered ("#cycles (v approximate) %10d\n", cpu.cycles); | |
1905 | printf_filtered ("#real time taken %10.4f\n", timetaken); | |
1906 | printf_filtered ("#virtual time taked %10.4f\n", virttime); | |
0693d363 | 1907 | if (timetaken != 0.0) |
7478904c SC |
1908 | printf_filtered ("#simulation ratio %10.4f\n", virttime / timetaken); |
1909 | printf_filtered ("#compiles %10d\n", cpu.compiles); | |
1910 | printf_filtered ("#cache size %10d\n", cpu.csize); | |
ce51bde6 DE |
1911 | |
1912 | #ifdef ADEBUG | |
0693d363 | 1913 | if (verbose) |
ce51bde6 DE |
1914 | { |
1915 | int i; | |
0693d363 | 1916 | for (i = 0; i < O_LAST; i++) |
ce51bde6 DE |
1917 | { |
1918 | if (cpu.stats[i]) | |
7478904c | 1919 | printf_filtered ("%d: %d\n", i, cpu.stats[i]); |
ce51bde6 DE |
1920 | } |
1921 | } | |
1922 | #endif | |
1923 | } | |
1924 | ||
7478904c SC |
1925 | /* Indicate whether the cpu is an h8/300 or h8/300h. |
1926 | FLAG is non-zero for the h8/300h. */ | |
1927 | ||
89a2c4fd | 1928 | void |
7478904c SC |
1929 | set_h8300h (flag) |
1930 | int flag; | |
89a2c4fd | 1931 | { |
7478904c | 1932 | h8300hmode = flag; |
89a2c4fd | 1933 | } |
28655f00 | 1934 | |
7478904c | 1935 | void |
0693d363 | 1936 | sim_kill () |
7db9345b | 1937 | { |
7478904c | 1938 | /* nothing to do */ |
7db9345b DE |
1939 | } |
1940 | ||
7478904c SC |
1941 | void |
1942 | sim_open (args) | |
1943 | char *args; | |
7db9345b | 1944 | { |
7478904c | 1945 | /* nothing to do */ |
7db9345b DE |
1946 | } |
1947 | ||
7478904c SC |
1948 | void |
1949 | sim_close (quitting) | |
1950 | int quitting; | |
1951 | { | |
1952 | /* nothing to do */ | |
1953 | } | |
1954 | ||
1955 | /* Called by gdb to load a program into memory. */ | |
1956 | ||
1957 | int | |
1958 | sim_load (prog, from_tty) | |
1959 | char *prog; | |
1960 | int from_tty; | |
1961 | { | |
1962 | bfd *abfd; | |
1963 | ||
1964 | /* See if the file is for the h8/300 or h8/300h. */ | |
1965 | /* ??? This may not be the most efficient way. The z8k simulator | |
1966 | does this via a different mechanism (INIT_EXTRA_SYMTAB_INFO). */ | |
1967 | if ((abfd = bfd_openr (prog, "coff-h8300")) != 0) | |
1968 | { | |
1969 | if (bfd_check_format (abfd, bfd_object)) | |
171f4664 JL |
1970 | { |
1971 | set_h8300h (abfd->arch_info->mach == bfd_mach_h8300h | |
25b344a4 | 1972 | || abfd->arch_info->mach == bfd_mach_h8300s); |
171f4664 | 1973 | } |
7478904c SC |
1974 | bfd_close (abfd); |
1975 | } | |
1976 | ||
132fdcb9 JL |
1977 | /* If we're using gdb attached to the simulator, then we have to |
1978 | reallocate memory for the simulator. | |
1979 | ||
1980 | When gdb first starts, it calls fetch_registers (among other | |
1981 | functions), which in turn calls init_pointers, which allocates | |
1982 | simulator memory. | |
1983 | ||
1984 | The problem is when we do that, we don't know whether we're | |
1985 | debugging an h8/300 or h8/300h program. | |
1986 | ||
1987 | This is the first point at which we can make that determination, | |
1988 | so we just reallocate memory now; this will also allow us to handle | |
1989 | switching between h8/300 and h8/300h programs without exiting | |
1990 | gdb. */ | |
1991 | if (h8300hmode) | |
1992 | memory_size = H8300H_MSIZE; | |
1993 | else | |
1994 | memory_size = H8300_MSIZE; | |
1995 | ||
1996 | if (cpu.memory) | |
1997 | free (cpu.memory); | |
1998 | if (cpu.cache_idx) | |
1999 | free (cpu.cache_idx); | |
7e1e013f JL |
2000 | if (cpu.eightbit) |
2001 | free (cpu.eightbit); | |
132fdcb9 JL |
2002 | |
2003 | cpu.memory = (unsigned char *) calloc (sizeof (char), memory_size); | |
2004 | cpu.cache_idx = (unsigned short *) calloc (sizeof (short), memory_size); | |
2005 | cpu.eightbit = (unsigned char *) calloc (sizeof (char), 256); | |
2006 | ||
2007 | /* `msize' must be a power of two */ | |
2008 | if ((memory_size & (memory_size - 1)) != 0) | |
2009 | abort (); | |
2010 | cpu.mask = memory_size - 1; | |
2011 | ||
7478904c SC |
2012 | /* Return non-zero so gdb will handle it. */ |
2013 | return 1; | |
2014 | } | |
2015 | ||
2016 | void | |
2017 | sim_create_inferior (start_address, argv, env) | |
2018 | SIM_ADDR start_address; | |
a415cf0a DE |
2019 | char **argv; |
2020 | char **env; | |
7db9345b | 2021 | { |
7478904c | 2022 | cpu.pc = start_address; |
7db9345b | 2023 | } |
e656ecf9 DE |
2024 | |
2025 | void | |
2026 | sim_do_command (cmd) | |
2027 | char *cmd; | |
2028 | { | |
2029 | printf_filtered ("This simulator does not accept any commands.\n"); | |
2030 | } | |
2031 | ||
2032 | ||
2033 | ||
2034 | void | |
2035 | sim_set_callbacks (ptr) | |
2036 | struct host_callback_struct *ptr; | |
2037 | { | |
2038 | ||
2039 | } | |
2040 |