Commit | Line | Data |
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ce51bde6 DE |
1 | /* |
2 | * Simulator for the Hitachi H8/300 architecture. | |
3 | * | |
4 | * Written by Steve Chamberlain of Cygnus Support. sac@cygnus.com | |
5 | * | |
6 | * This file is part of H8/300 sim | |
7 | * | |
8 | * | |
9 | * THIS SOFTWARE IS NOT COPYRIGHTED | |
10 | * | |
11 | * Cygnus offers the following for use in the public domain. Cygnus makes no | |
12 | * warranty with regard to the software or its performance and the user | |
13 | * accepts the software "AS IS" with all faults. | |
14 | * | |
15 | * CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO THIS | |
16 | * SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY | |
17 | * AND FITNESS FOR A PARTICULAR PURPOSE. | |
ce51bde6 DE |
18 | */ |
19 | ||
e656ecf9 DE |
20 | #include "config.h" |
21 | ||
ce51bde6 | 22 | #include <signal.h> |
e656ecf9 DE |
23 | #ifdef HAVE_TIME_H |
24 | #include <time.h> | |
25 | #endif | |
26 | #ifdef HAVE_STDLIB_H | |
27 | #include <stdlib.h> | |
7478904c | 28 | #endif |
ce51bde6 | 29 | #include <sys/param.h> |
4dfb4ffc | 30 | #include "wait.h" |
0693d363 | 31 | #include "ansidecl.h" |
e656ecf9 | 32 | #include "callback.h" |
a415cf0a | 33 | #include "remote-sim.h" |
7478904c | 34 | #include "bfd.h" |
ce51bde6 DE |
35 | |
36 | int debug; | |
37 | ||
38 | ||
39 | #define X(op, size) op*4+size | |
40 | ||
28655f00 | 41 | #define SP (h8300hmode ? SL:SW) |
ce51bde6 DE |
42 | #define SB 0 |
43 | #define SW 1 | |
44 | #define SL 2 | |
45 | #define OP_REG 1 | |
46 | #define OP_DEC 2 | |
47 | #define OP_DISP 3 | |
48 | #define OP_INC 4 | |
49 | #define OP_PCREL 5 | |
50 | #define OP_MEM 6 | |
51 | #define OP_CCR 7 | |
52 | #define OP_IMM 8 | |
53 | #define OP_ABS 10 | |
54 | #define h8_opcodes ops | |
55 | #define DEFINE_TABLE | |
56 | #include "opcode/h8300.h" | |
57 | ||
58 | #include "inst.h" | |
59 | ||
60 | #define LOW_BYTE(x) ((x) & 0xff) | |
61 | #define HIGH_BYTE(x) (((x)>>8) & 0xff) | |
62 | #define P(X,Y) ((X<<8) | Y) | |
63 | ||
64 | #define BUILDSR() cpu.ccr = (N << 3) | (Z << 2) | (V<<1) | C; | |
65 | ||
66 | #define GETSR() \ | |
67 | c = (cpu.ccr >> 0) & 1;\ | |
68 | v = (cpu.ccr >> 1) & 1;\ | |
69 | nz = !((cpu.ccr >> 2) & 1);\ | |
70 | n = (cpu.ccr >> 3) & 1; | |
71 | ||
72 | #ifdef __CHAR_IS_SIGNED__ | |
73 | #define SEXTCHAR(x) ((char)(x)) | |
74 | #endif | |
75 | ||
76 | #ifndef SEXTCHAR | |
77 | #define SEXTCHAR(x) ((x & 0x80) ? (x | ~0xff):x) | |
78 | #endif | |
79 | ||
80 | #define UEXTCHAR(x) ((x) & 0xff) | |
81 | #define UEXTSHORT(x) ((x) & 0xffff) | |
82 | #define SEXTSHORT(x) ((short)(x)) | |
83 | ||
84 | static cpu_state_type cpu; | |
85 | ||
28655f00 | 86 | int h8300hmode = 0; |
ce51bde6 | 87 | |
e656ecf9 DE |
88 | static int memory_size; |
89 | ||
ce51bde6 DE |
90 | |
91 | static int | |
92 | get_now () | |
93 | { | |
7478904c | 94 | #ifndef WIN32 |
0693d363 | 95 | return time (0); |
28655f00 | 96 | #endif |
7478904c | 97 | return 0; |
ce51bde6 DE |
98 | } |
99 | ||
100 | static int | |
101 | now_persec () | |
102 | { | |
28655f00 | 103 | return 1; |
ce51bde6 DE |
104 | } |
105 | ||
106 | ||
107 | static int | |
108 | bitfrom (x) | |
109 | { | |
ce51bde6 DE |
110 | switch (x & SIZE) |
111 | { | |
112 | case L_8: | |
113 | return SB; | |
114 | case L_16: | |
115 | return SW; | |
116 | case L_32: | |
117 | return SL; | |
118 | case L_P: | |
28655f00 | 119 | return h8300hmode ? SL : SW; |
ce51bde6 | 120 | } |
ce51bde6 DE |
121 | } |
122 | ||
123 | static | |
124 | unsigned int | |
125 | lvalue (x, rn) | |
126 | { | |
127 | switch (x / 4) | |
128 | { | |
129 | case OP_DISP: | |
0693d363 | 130 | if (rn == 8) |
ce51bde6 | 131 | { |
0693d363 | 132 | return X (OP_IMM, SP); |
ce51bde6 | 133 | } |
0693d363 DE |
134 | return X (OP_REG, SP); |
135 | ||
ce51bde6 DE |
136 | case OP_MEM: |
137 | ||
138 | return X (OP_MEM, SP); | |
139 | default: | |
140 | abort (); | |
141 | } | |
142 | } | |
143 | ||
144 | static unsigned int | |
145 | decode (addr, data, dst) | |
146 | int addr; | |
147 | unsigned char *data; | |
148 | decoded_inst *dst; | |
149 | ||
150 | { | |
151 | int rs = 0; | |
152 | int rd = 0; | |
153 | int rdisp = 0; | |
154 | int abs = 0; | |
155 | int plen = 0; | |
156 | ||
157 | struct h8_opcode *q = h8_opcodes; | |
158 | int size = 0; | |
159 | dst->dst.type = -1; | |
160 | dst->src.type = -1; | |
161 | /* Find the exact opcode/arg combo */ | |
162 | while (q->name) | |
163 | { | |
164 | op_type *nib; | |
165 | unsigned int len = 0; | |
166 | ||
167 | nib = q->data.nib; | |
168 | ||
169 | while (1) | |
170 | { | |
171 | op_type looking_for = *nib; | |
172 | int thisnib = data[len >> 1]; | |
173 | ||
174 | thisnib = (len & 1) ? (thisnib & 0xf) : ((thisnib >> 4) & 0xf); | |
175 | ||
0693d363 | 176 | if (looking_for < 16 && looking_for >= 0) |
ce51bde6 | 177 | { |
ce51bde6 DE |
178 | if (looking_for != thisnib) |
179 | goto fail; | |
180 | } | |
181 | else | |
182 | { | |
ce51bde6 DE |
183 | if ((int) looking_for & (int) B31) |
184 | { | |
185 | if (!(((int) thisnib & 0x8) != 0)) | |
186 | goto fail; | |
187 | looking_for = (op_type) ((int) looking_for & ~(int) | |
188 | B31); | |
189 | thisnib &= 0x7; | |
ce51bde6 DE |
190 | } |
191 | if ((int) looking_for & (int) B30) | |
192 | { | |
193 | if (!(((int) thisnib & 0x8) == 0)) | |
194 | goto fail; | |
195 | looking_for = (op_type) ((int) looking_for & ~(int) B30); | |
196 | } | |
197 | if (looking_for & DBIT) | |
198 | { | |
0693d363 DE |
199 | if ((looking_for & 5) != (thisnib & 5)) |
200 | goto fail; | |
ce51bde6 DE |
201 | abs = (thisnib & 0x8) ? 2 : 1; |
202 | } | |
203 | else if (looking_for & (REG | IND | INC | DEC)) | |
204 | { | |
205 | if (looking_for & REG) | |
206 | { | |
207 | /* | |
208 | * Can work out size from the | |
209 | * register | |
210 | */ | |
211 | size = bitfrom (looking_for); | |
212 | } | |
213 | if (looking_for & SRC) | |
214 | { | |
215 | rs = thisnib; | |
216 | } | |
217 | else | |
218 | { | |
219 | rd = thisnib; | |
220 | } | |
221 | } | |
222 | else if (looking_for & L_16) | |
223 | { | |
224 | abs = (data[len >> 1]) * 256 + data[(len + 2) >> 1]; | |
225 | plen = 16; | |
0693d363 | 226 | if (looking_for & (PCREL | DISP)) |
ce51bde6 DE |
227 | { |
228 | abs = (short) (abs); | |
229 | } | |
230 | } | |
231 | else if (looking_for & ABSJMP) | |
232 | { | |
233 | abs = | |
234 | (data[1] << 16) | |
235 | | (data[2] << 8) | |
236 | | (data[3]); | |
237 | } | |
0693d363 DE |
238 | else if (looking_for & MEMIND) |
239 | { | |
240 | abs = data[1]; | |
241 | } | |
ce51bde6 DE |
242 | else if (looking_for & L_32) |
243 | { | |
244 | int i = len >> 1; | |
245 | abs = (data[i] << 24) | |
246 | | (data[i + 1] << 16) | |
247 | | (data[i + 2] << 8) | |
248 | | (data[i + 3]); | |
249 | ||
250 | plen = 32; | |
ce51bde6 DE |
251 | } |
252 | else if (looking_for & L_24) | |
253 | { | |
254 | int i = len >> 1; | |
0693d363 | 255 | abs = (data[i] << 16) | (data[i + 1] << 8) | (data[i + 2]); |
ce51bde6 DE |
256 | plen = 24; |
257 | } | |
258 | else if (looking_for & IGNORE) | |
259 | { | |
0693d363 | 260 | /* nothing to do */ |
ce51bde6 DE |
261 | } |
262 | else if (looking_for & DISPREG) | |
263 | { | |
264 | rdisp = thisnib & 0x7; | |
265 | } | |
266 | else if (looking_for & KBIT) | |
267 | { | |
268 | switch (thisnib) | |
269 | { | |
270 | case 9: | |
271 | abs = 4; | |
272 | break; | |
273 | case 8: | |
274 | abs = 2; | |
275 | break; | |
276 | case 0: | |
277 | abs = 1; | |
278 | break; | |
279 | } | |
280 | } | |
281 | else if (looking_for & L_8) | |
282 | { | |
283 | plen = 8; | |
284 | ||
285 | if (looking_for & PCREL) | |
286 | { | |
287 | abs = SEXTCHAR (data[len >> 1]); | |
288 | } | |
289 | else | |
290 | { | |
291 | abs = data[len >> 1] & 0xff; | |
292 | } | |
293 | } | |
294 | else if (looking_for & L_3) | |
295 | { | |
296 | plen = 3; | |
297 | ||
298 | abs = thisnib; | |
299 | } | |
300 | else if (looking_for == E) | |
301 | { | |
302 | dst->op = q; | |
303 | ||
304 | /* Fill in the args */ | |
305 | { | |
306 | op_type *args = q->args.nib; | |
307 | int hadone = 0; | |
308 | ||
ce51bde6 DE |
309 | while (*args != E) |
310 | { | |
311 | int x = *args; | |
312 | int rn = (x & DST) ? rd : rs; | |
313 | ea_type *p; | |
314 | ||
315 | if (x & DST) | |
316 | { | |
317 | p = &(dst->dst); | |
318 | } | |
319 | else | |
320 | { | |
321 | p = &(dst->src); | |
322 | } | |
323 | ||
ce51bde6 DE |
324 | if (x & (IMM | KBIT | DBIT)) |
325 | { | |
326 | p->type = X (OP_IMM, size); | |
327 | p->literal = abs; | |
328 | } | |
329 | else if (x & REG) | |
330 | { | |
0693d363 DE |
331 | /* Reset the size, some |
332 | ops (like mul) have two sizes */ | |
333 | ||
ce51bde6 DE |
334 | size = bitfrom (x); |
335 | p->type = X (OP_REG, size); | |
336 | p->reg = rn; | |
337 | } | |
338 | else if (x & INC) | |
339 | { | |
340 | p->type = X (OP_INC, size); | |
341 | p->reg = rn & 0x7; | |
342 | } | |
343 | else if (x & DEC) | |
344 | { | |
345 | p->type = X (OP_DEC, size); | |
346 | p->reg = rn & 0x7; | |
347 | } | |
348 | else if (x & IND) | |
349 | { | |
350 | p->type = X (OP_DISP, size); | |
351 | p->reg = rn & 0x7; | |
352 | p->literal = 0; | |
353 | } | |
354 | else if (x & (ABS | ABSJMP | ABSMOV)) | |
355 | { | |
356 | p->type = X (OP_DISP, size); | |
357 | p->literal = abs; | |
358 | p->reg = 8; | |
359 | } | |
360 | else if (x & MEMIND) | |
361 | { | |
362 | p->type = X (OP_MEM, size); | |
363 | p->literal = abs; | |
364 | } | |
365 | else if (x & PCREL) | |
366 | { | |
367 | p->type = X (OP_PCREL, size); | |
368 | p->literal = abs + addr + 2; | |
0693d363 DE |
369 | if (x & L_16) |
370 | p->literal += 2; | |
ce51bde6 DE |
371 | } |
372 | else if (x & ABSJMP) | |
373 | { | |
374 | p->type = X (OP_IMM, SP); | |
375 | p->literal = abs; | |
376 | } | |
377 | else if (x & DISP) | |
378 | { | |
379 | p->type = X (OP_DISP, size); | |
380 | p->literal = abs; | |
381 | p->reg = rdisp & 0x7; | |
382 | } | |
383 | else if (x & CCR) | |
384 | { | |
385 | p->type = OP_CCR; | |
386 | } | |
387 | else | |
388 | printf ("Hmmmm %x", x); | |
389 | ||
ce51bde6 DE |
390 | args++; |
391 | } | |
392 | } | |
393 | ||
394 | /* | |
0693d363 DE |
395 | * But a jmp or a jsr gets |
396 | * automagically lvalued, since we | |
397 | * branch to their address not their | |
398 | * contents | |
399 | */ | |
ce51bde6 DE |
400 | if (q->how == O (O_JSR, SB) |
401 | || q->how == O (O_JMP, SB)) | |
402 | { | |
403 | dst->src.type = lvalue (dst->src.type, dst->src.reg); | |
404 | } | |
405 | ||
ce51bde6 DE |
406 | if (dst->dst.type == -1) |
407 | dst->dst = dst->src; | |
0693d363 | 408 | |
ce51bde6 DE |
409 | dst->opcode = q->how; |
410 | dst->cycles = q->time; | |
411 | ||
412 | /* And a jsr to 0xc4 is turned into a magic trap */ | |
0693d363 DE |
413 | |
414 | if (dst->opcode == O (O_JSR, SB)) | |
ce51bde6 | 415 | { |
0693d363 | 416 | if (dst->src.literal == 0xc4) |
ce51bde6 | 417 | { |
0693d363 | 418 | dst->opcode = O (O_SYSCALL, SB); |
ce51bde6 DE |
419 | } |
420 | } | |
0693d363 | 421 | |
ce51bde6 DE |
422 | dst->next_pc = addr + len / 2; |
423 | return; | |
424 | } | |
425 | else | |
426 | { | |
427 | printf ("Dont understand %x \n", looking_for); | |
428 | } | |
429 | } | |
0693d363 | 430 | |
ce51bde6 DE |
431 | len++; |
432 | nib++; | |
433 | } | |
0693d363 | 434 | |
ce51bde6 DE |
435 | fail: |
436 | q++; | |
437 | } | |
0693d363 | 438 | |
ce51bde6 DE |
439 | dst->opcode = O (O_ILL, SB); |
440 | } | |
441 | ||
442 | ||
443 | static void | |
444 | compile (pc) | |
445 | { | |
446 | int idx; | |
0693d363 | 447 | |
ce51bde6 | 448 | /* find the next cache entry to use */ |
0693d363 | 449 | |
ce51bde6 DE |
450 | idx = cpu.cache_top + 1; |
451 | cpu.compiles++; | |
452 | if (idx >= cpu.csize) | |
453 | { | |
454 | idx = 1; | |
455 | } | |
456 | cpu.cache_top = idx; | |
0693d363 | 457 | |
ce51bde6 DE |
458 | /* Throw away its old meaning */ |
459 | cpu.cache_idx[cpu.cache[idx].oldpc] = 0; | |
0693d363 | 460 | |
ce51bde6 DE |
461 | /* set to new address */ |
462 | cpu.cache[idx].oldpc = pc; | |
0693d363 | 463 | |
ce51bde6 DE |
464 | /* fill in instruction info */ |
465 | decode (pc, cpu.memory + pc, cpu.cache + idx); | |
0693d363 | 466 | |
ce51bde6 DE |
467 | /* point to new cache entry */ |
468 | cpu.cache_idx[pc] = idx; | |
469 | } | |
470 | ||
471 | ||
472 | static unsigned char *breg[18]; | |
473 | static unsigned short *wreg[18]; | |
474 | static unsigned int *lreg[18]; | |
475 | ||
476 | #define GET_B_REG(x) *(breg[x]) | |
477 | #define SET_B_REG(x,y) (*(breg[x])) = (y) | |
478 | #define GET_W_REG(x) *(wreg[x]) | |
479 | #define SET_W_REG(x,y) (*(wreg[x])) = (y) | |
480 | ||
481 | #define GET_L_REG(x) *(lreg[x]) | |
482 | #define SET_L_REG(x,y) (*(lreg[x])) = (y) | |
483 | ||
484 | #define GET_MEMORY_L(x) \ | |
485 | ((cpu.memory[x+0] << 24) | (cpu.memory[x+1] << 16) | (cpu.memory[x+2] << 8) | cpu.memory[x+3]) | |
486 | ||
487 | #define GET_MEMORY_W(x) \ | |
488 | ((cpu.memory[x+0] << 8) | (cpu.memory[x+1] << 0)) | |
489 | ||
490 | ||
491 | #define SET_MEMORY_B(x,y) \ | |
492 | (cpu.memory[(x)] = y) | |
493 | ||
494 | #define SET_MEMORY_W(x,y) \ | |
495 | {register unsigned char *_p = cpu.memory+x;\ | |
496 | register int __y = y;\ | |
497 | _p[0] = (__y)>>8;\ | |
498 | _p[1] =(__y); } | |
499 | ||
500 | #define SET_MEMORY_L(x,y) \ | |
501 | {register unsigned char *_p = cpu.memory+x;register int __y = y;\ | |
502 | _p[0] = (__y)>>24; _p[1] = (__y)>>16; _p[2] = (__y)>>8; _p[3] = (__y)>>0;} | |
503 | ||
504 | #define GET_MEMORY_B(x) (cpu.memory[x]) | |
505 | ||
506 | int | |
89a2c4fd | 507 | fetch (arg, n) |
0693d363 | 508 | ea_type *arg; |
ce51bde6 DE |
509 | { |
510 | int rn = arg->reg; | |
511 | int abs = arg->literal; | |
512 | int r; | |
513 | int t; | |
0693d363 | 514 | |
ce51bde6 DE |
515 | switch (arg->type) |
516 | { | |
517 | case X (OP_REG, SB): | |
518 | return GET_B_REG (rn); | |
519 | case X (OP_REG, SW): | |
520 | return GET_W_REG (rn); | |
521 | case X (OP_REG, SL): | |
522 | return GET_L_REG (rn); | |
523 | case X (OP_IMM, SB): | |
524 | case X (OP_IMM, SW): | |
525 | case X (OP_IMM, SL): | |
526 | return abs; | |
527 | case X (OP_DEC, SB): | |
0693d363 | 528 | abort (); |
ce51bde6 | 529 | |
0693d363 DE |
530 | case X (OP_INC, SB): |
531 | t = GET_L_REG (rn); | |
ce51bde6 | 532 | t &= cpu.mask; |
0693d363 DE |
533 | r = GET_MEMORY_B (t); |
534 | t++; | |
ce51bde6 | 535 | t = t & cpu.mask; |
0693d363 | 536 | SET_L_REG (rn, t); |
ce51bde6 DE |
537 | return r; |
538 | break; | |
0693d363 DE |
539 | case X (OP_INC, SW): |
540 | t = GET_L_REG (rn); | |
ce51bde6 | 541 | t &= cpu.mask; |
0693d363 DE |
542 | r = GET_MEMORY_W (t); |
543 | t += 2; | |
ce51bde6 | 544 | t = t & cpu.mask; |
0693d363 | 545 | SET_L_REG (rn, t); |
ce51bde6 | 546 | return r; |
0693d363 DE |
547 | case X (OP_INC, SL): |
548 | t = GET_L_REG (rn); | |
ce51bde6 | 549 | t &= cpu.mask; |
0693d363 DE |
550 | r = GET_MEMORY_L (t); |
551 | ||
552 | t += 4; | |
ce51bde6 | 553 | t = t & cpu.mask; |
0693d363 | 554 | SET_L_REG (rn, t); |
ce51bde6 | 555 | return r; |
0693d363 | 556 | |
ce51bde6 DE |
557 | case X (OP_DISP, SB): |
558 | t = GET_L_REG (rn) + abs; | |
559 | t &= cpu.mask; | |
560 | return GET_MEMORY_B (t); | |
0693d363 | 561 | |
ce51bde6 DE |
562 | case X (OP_DISP, SW): |
563 | t = GET_L_REG (rn) + abs; | |
564 | t &= cpu.mask; | |
565 | return GET_MEMORY_W (t); | |
0693d363 | 566 | |
ce51bde6 DE |
567 | case X (OP_DISP, SL): |
568 | t = GET_L_REG (rn) + abs; | |
569 | t &= cpu.mask; | |
570 | return GET_MEMORY_L (t); | |
0693d363 DE |
571 | |
572 | case X (OP_MEM, SL): | |
573 | t = GET_MEMORY_L (abs); | |
574 | t &= cpu.mask; | |
575 | return t; | |
576 | ||
ce51bde6 DE |
577 | default: |
578 | abort (); | |
0693d363 | 579 | |
ce51bde6 DE |
580 | } |
581 | } | |
582 | ||
583 | ||
0693d363 DE |
584 | static |
585 | void | |
586 | store (arg, n) | |
587 | ea_type *arg; | |
588 | int n; | |
ce51bde6 DE |
589 | { |
590 | int rn = arg->reg; | |
591 | int abs = arg->literal; | |
592 | int t; | |
0693d363 | 593 | |
ce51bde6 DE |
594 | switch (arg->type) |
595 | { | |
596 | case X (OP_REG, SB): | |
597 | SET_B_REG (rn, n); | |
598 | break; | |
599 | case X (OP_REG, SW): | |
600 | SET_W_REG (rn, n); | |
601 | break; | |
602 | case X (OP_REG, SL): | |
603 | SET_L_REG (rn, n); | |
604 | break; | |
0693d363 | 605 | |
ce51bde6 | 606 | case X (OP_DEC, SB): |
0693d363 | 607 | t = GET_L_REG (rn) - 1; |
ce51bde6 | 608 | t &= cpu.mask; |
0693d363 | 609 | SET_L_REG (rn, t); |
ce51bde6 DE |
610 | SET_MEMORY_B (t, n); |
611 | ||
612 | break; | |
613 | case X (OP_DEC, SW): | |
0693d363 | 614 | t = (GET_L_REG (rn) - 2) & cpu.mask; |
ce51bde6 DE |
615 | SET_L_REG (rn, t); |
616 | SET_MEMORY_W (t, n); | |
617 | break; | |
618 | ||
619 | case X (OP_DEC, SL): | |
0693d363 | 620 | t = (GET_L_REG (rn) - 4) & cpu.mask; |
89a2c4fd | 621 | SET_L_REG (rn, t); |
0693d363 | 622 | SET_MEMORY_L (t, n); |
ce51bde6 DE |
623 | break; |
624 | ||
ce51bde6 DE |
625 | case X (OP_DISP, SB): |
626 | t = GET_L_REG (rn) + abs; | |
627 | t &= cpu.mask; | |
628 | SET_MEMORY_B (t, n); | |
629 | break; | |
630 | ||
631 | case X (OP_DISP, SW): | |
632 | t = GET_L_REG (rn) + abs; | |
633 | t &= cpu.mask; | |
634 | SET_MEMORY_W (t, n); | |
635 | break; | |
636 | ||
637 | case X (OP_DISP, SL): | |
638 | t = GET_L_REG (rn) + abs; | |
639 | t &= cpu.mask; | |
640 | SET_MEMORY_L (t, n); | |
641 | break; | |
642 | default: | |
643 | abort (); | |
644 | } | |
645 | } | |
646 | ||
647 | ||
648 | static union | |
0693d363 DE |
649 | { |
650 | short int i; | |
651 | struct | |
652 | { | |
653 | char low; | |
654 | char high; | |
655 | } | |
656 | u; | |
657 | } | |
ce51bde6 DE |
658 | |
659 | littleendian; | |
660 | ||
661 | static | |
662 | void | |
663 | init_pointers () | |
664 | { | |
665 | static int init; | |
666 | ||
667 | if (!init) | |
668 | { | |
669 | int i; | |
670 | ||
671 | init = 1; | |
672 | littleendian.i = 1; | |
673 | ||
e656ecf9 DE |
674 | if (h8300hmode) |
675 | memory_size = H8300H_MSIZE; | |
676 | else | |
677 | memory_size = H8300_MSIZE; | |
678 | cpu.memory = (unsigned char *) calloc (sizeof (char), memory_size); | |
679 | cpu.cache_idx = (unsigned short *) calloc (sizeof (short), memory_size); | |
680 | ||
681 | /* `msize' must be a power of two */ | |
682 | if ((memory_size & (memory_size - 1)) != 0) | |
683 | abort (); | |
684 | cpu.mask = memory_size - 1; | |
0693d363 | 685 | |
ce51bde6 DE |
686 | for (i = 0; i < 9; i++) |
687 | { | |
688 | cpu.regs[i] = 0; | |
689 | } | |
690 | ||
691 | for (i = 0; i < 8; i++) | |
692 | { | |
693 | unsigned char *p = (unsigned char *) (cpu.regs + i); | |
694 | unsigned char *e = (unsigned char *) (cpu.regs + i + 1); | |
695 | unsigned short *q = (unsigned short *) (cpu.regs + i); | |
696 | unsigned short *u = (unsigned short *) (cpu.regs + i + 1); | |
697 | cpu.regs[i] = 0x00112233; | |
698 | while (p < e) | |
699 | { | |
700 | if (*p == 0x22) | |
701 | { | |
702 | breg[i] = p; | |
703 | } | |
704 | if (*p == 0x33) | |
705 | { | |
0693d363 | 706 | breg[i + 8] = p; |
ce51bde6 DE |
707 | } |
708 | p++; | |
709 | } | |
710 | while (q < u) | |
711 | { | |
712 | if (*q == 0x2233) | |
713 | { | |
714 | wreg[i] = q; | |
715 | } | |
716 | if (*q == 0x0011) | |
717 | { | |
718 | wreg[i + 8] = q; | |
719 | } | |
720 | q++; | |
721 | } | |
722 | cpu.regs[i] = 0; | |
723 | lreg[i] = &cpu.regs[i]; | |
724 | } | |
725 | ||
ce51bde6 | 726 | lreg[8] = &cpu.regs[8]; |
0693d363 | 727 | |
ce51bde6 DE |
728 | /* initialize the seg registers */ |
729 | if (!cpu.cache) | |
730 | sim_csize (CSIZE); | |
ce51bde6 DE |
731 | } |
732 | } | |
733 | ||
734 | static void | |
735 | control_c (sig, code, scp, addr) | |
736 | int sig; | |
737 | int code; | |
738 | char *scp; | |
739 | char *addr; | |
740 | { | |
741 | cpu.exception = SIGINT; | |
742 | } | |
743 | ||
744 | #define C (c != 0) | |
745 | #define Z (nz == 0) | |
746 | #define V (v != 0) | |
747 | #define N (n != 0) | |
748 | ||
28655f00 | 749 | static int |
0693d363 | 750 | mop (code, bsize, sign) |
28655f00 SC |
751 | decoded_inst *code; |
752 | int bsize; | |
0693d363 DE |
753 | int sign; |
754 | { | |
755 | int multiplier; | |
756 | int multiplicand; | |
757 | int result; | |
758 | int n, nz; | |
759 | ||
760 | if (sign) | |
761 | { | |
762 | multiplicand = | |
763 | bsize ? SEXTCHAR (GET_W_REG (code->dst.reg)) : | |
764 | SEXTSHORT (GET_W_REG (code->dst.reg)); | |
765 | multiplier = | |
766 | bsize ? SEXTCHAR (GET_B_REG (code->src.reg)) : | |
767 | SEXTSHORT (GET_W_REG (code->src.reg)); | |
768 | } | |
769 | else | |
770 | { | |
771 | multiplicand = bsize ? UEXTCHAR (GET_W_REG (code->dst.reg)) : | |
772 | UEXTSHORT (GET_W_REG (code->dst.reg)); | |
773 | multiplier = | |
774 | bsize ? UEXTCHAR (GET_B_REG (code->src.reg)) : | |
775 | UEXTSHORT (GET_W_REG (code->src.reg)); | |
776 | ||
777 | } | |
778 | result = multiplier * multiplicand; | |
779 | ||
780 | if (sign) | |
781 | { | |
782 | n = result & (bsize ? 0x8000 : 0x80000000); | |
783 | nz = result & (bsize ? 0xffff : 0xffffffff); | |
784 | } | |
785 | if (bsize) | |
786 | { | |
787 | SET_W_REG (code->dst.reg, result); | |
788 | } | |
789 | else | |
790 | { | |
791 | SET_L_REG (code->dst.reg, result); | |
792 | } | |
793 | /* return ((n==1) << 1) | (nz==1); */ | |
794 | ||
795 | } | |
796 | ||
797 | #define OSHIFTS(name, how) \ | |
798 | case O(name, SB): \ | |
799 | { \ | |
800 | int t; \ | |
801 | int hm = 0x80; \ | |
802 | rd = GET_B_REG (code->src.reg); \ | |
803 | how; \ | |
804 | goto shift8; \ | |
805 | } \ | |
806 | case O(name, SW): \ | |
807 | { \ | |
808 | int t; \ | |
809 | int hm = 0x8000; \ | |
810 | rd = GET_W_REG (code->src.reg); \ | |
811 | how; \ | |
812 | goto shift16; \ | |
813 | } \ | |
814 | case O(name, SL): \ | |
815 | { \ | |
816 | int t; \ | |
817 | int hm = 0x80000000; \ | |
818 | rd = GET_L_REG (code->src.reg); \ | |
819 | how; \ | |
820 | goto shift32; \ | |
821 | } | |
822 | ||
823 | #define OBITOP(name,f, s, op) \ | |
824 | case O(name, SB): \ | |
825 | { \ | |
826 | int m; \ | |
827 | int b; \ | |
828 | if (f) ea = fetch (&code->dst); \ | |
829 | m=1<< fetch(&code->src); \ | |
830 | op; \ | |
831 | if(s) store (&code->dst,ea); goto next; \ | |
832 | } | |
28655f00 | 833 | |
7478904c | 834 | void |
a415cf0a | 835 | sim_resume (step, siggnal) |
ce51bde6 DE |
836 | { |
837 | static int init1; | |
838 | int cycles = 0; | |
839 | int insts = 0; | |
840 | int tick_start = get_now (); | |
841 | void (*prev) (); | |
0693d363 | 842 | int poll_count = 0; |
ce51bde6 DE |
843 | int res; |
844 | int tmp; | |
845 | int rd; | |
846 | int ea; | |
847 | int bit; | |
848 | int pc; | |
849 | int c, nz, v, n; | |
7478904c | 850 | int oldmask; |
ce51bde6 DE |
851 | init_pointers (); |
852 | ||
853 | prev = signal (SIGINT, control_c); | |
854 | ||
855 | if (step) | |
856 | { | |
857 | cpu.exception = SIGTRAP; | |
858 | } | |
859 | else | |
860 | { | |
861 | cpu.exception = 0; | |
862 | } | |
863 | ||
864 | pc = cpu.pc; | |
865 | ||
866 | GETSR (); | |
7478904c SC |
867 | oldmask = cpu.mask; |
868 | if (!h8300hmode) | |
869 | cpu.mask = 0xffff; | |
ce51bde6 DE |
870 | do |
871 | { | |
872 | int cidx; | |
873 | decoded_inst *code; | |
874 | ||
875 | top: | |
876 | cidx = cpu.cache_idx[pc]; | |
877 | code = cpu.cache + cidx; | |
878 | ||
879 | ||
880 | #define ALUOP(STORE, NAME, HOW) \ | |
881 | case O(NAME,SB): HOW; if(STORE)goto alu8;else goto just_flags_alu8; \ | |
882 | case O(NAME, SW): HOW; if(STORE)goto alu16;else goto just_flags_alu16; \ | |
883 | case O(NAME,SL): HOW; if(STORE)goto alu32;else goto just_flags_alu32; | |
884 | ||
885 | ||
886 | #define LOGOP(NAME, HOW) \ | |
887 | case O(NAME,SB): HOW; goto log8;\ | |
888 | case O(NAME, SW): HOW; goto log16;\ | |
889 | case O(NAME,SL): HOW; goto log32; | |
890 | ||
891 | ||
892 | ||
893 | #if ADEBUG | |
894 | if (debug) | |
895 | { | |
896 | printf ("%x %d %s\n", pc, code->opcode, | |
897 | code->op ? code->op->name : "**"); | |
898 | } | |
899 | cpu.stats[code->opcode]++; | |
0693d363 | 900 | |
ce51bde6 DE |
901 | #endif |
902 | ||
903 | cycles += code->cycles; | |
904 | insts++; | |
905 | switch (code->opcode) | |
906 | { | |
907 | case 0: | |
908 | /* | |
909 | * This opcode is a fake for when we get to an | |
910 | * instruction which hasnt been compiled | |
911 | */ | |
912 | compile (pc); | |
913 | goto top; | |
914 | break; | |
915 | ||
916 | ||
917 | case O (O_SUBX, SB): | |
918 | rd = fetch (&code->dst); | |
919 | ea = fetch (&code->src); | |
0693d363 | 920 | ea = -(ea + C); |
ce51bde6 DE |
921 | res = rd + ea; |
922 | goto alu8; | |
923 | ||
924 | case O (O_ADDX, SB): | |
925 | rd = fetch (&code->dst); | |
926 | ea = fetch (&code->src); | |
927 | ea = C + ea; | |
928 | res = rd + ea; | |
929 | goto alu8; | |
930 | ||
cf5b4aa6 DE |
931 | #define EA ea = fetch(&code->src); |
932 | #define RD_EA ea = fetch(&code->src); rd = fetch(&code->dst); | |
ce51bde6 | 933 | |
0693d363 DE |
934 | ALUOP (1, O_SUB, RD_EA; |
935 | ea = -ea; | |
936 | res = rd + ea); | |
937 | ALUOP (1, O_NEG, EA; | |
938 | ea = -ea; | |
939 | rd = 0; | |
940 | res = rd + ea); | |
ce51bde6 | 941 | |
0693d363 DE |
942 | case O (O_ADD, SB): |
943 | rd = GET_B_REG (code->dst.reg); | |
944 | ea = fetch (&code->src); | |
ce51bde6 DE |
945 | res = rd + ea; |
946 | goto alu8; | |
0693d363 DE |
947 | case O (O_ADD, SW): |
948 | rd = GET_W_REG (code->dst.reg); | |
949 | ea = fetch (&code->src); | |
ce51bde6 DE |
950 | res = rd + ea; |
951 | goto alu16; | |
0693d363 DE |
952 | case O (O_ADD, SL): |
953 | rd = GET_L_REG (code->dst.reg); | |
954 | ea = fetch (&code->src); | |
ce51bde6 DE |
955 | res = rd + ea; |
956 | goto alu32; | |
ce51bde6 | 957 | |
ce51bde6 | 958 | |
0693d363 DE |
959 | LOGOP (O_AND, RD_EA; |
960 | res = rd & ea); | |
961 | ||
962 | LOGOP (O_OR, RD_EA; | |
963 | res = rd | ea); | |
ce51bde6 | 964 | |
0693d363 DE |
965 | LOGOP (O_XOR, RD_EA; |
966 | res = rd ^ ea); | |
ce51bde6 DE |
967 | |
968 | ||
0693d363 DE |
969 | case O (O_MOV_TO_MEM, SB): |
970 | res = GET_B_REG (code->src.reg); | |
ce51bde6 | 971 | goto log8; |
0693d363 DE |
972 | case O (O_MOV_TO_MEM, SW): |
973 | res = GET_W_REG (code->src.reg); | |
ce51bde6 | 974 | goto log16; |
0693d363 DE |
975 | case O (O_MOV_TO_MEM, SL): |
976 | res = GET_L_REG (code->src.reg); | |
ce51bde6 DE |
977 | goto log32; |
978 | ||
979 | ||
0693d363 DE |
980 | case O (O_MOV_TO_REG, SB): |
981 | res = fetch (&code->src); | |
982 | SET_B_REG (code->dst.reg, res); | |
ce51bde6 | 983 | goto just_flags_log8; |
0693d363 DE |
984 | case O (O_MOV_TO_REG, SW): |
985 | res = fetch (&code->src); | |
986 | SET_W_REG (code->dst.reg, res); | |
ce51bde6 | 987 | goto just_flags_log16; |
0693d363 DE |
988 | case O (O_MOV_TO_REG, SL): |
989 | res = fetch (&code->src); | |
990 | SET_L_REG (code->dst.reg, res); | |
ce51bde6 DE |
991 | goto just_flags_log32; |
992 | ||
993 | ||
0693d363 DE |
994 | case O (O_ADDS, SL): |
995 | SET_L_REG (code->dst.reg, | |
996 | GET_L_REG (code->dst.reg) | |
997 | + code->src.literal); | |
998 | ||
ce51bde6 DE |
999 | goto next; |
1000 | ||
0693d363 DE |
1001 | case O (O_SUBS, SL): |
1002 | SET_L_REG (code->dst.reg, | |
1003 | GET_L_REG (code->dst.reg) | |
1004 | - code->src.literal); | |
ce51bde6 | 1005 | goto next; |
0693d363 | 1006 | |
ce51bde6 DE |
1007 | case O (O_CMP, SB): |
1008 | rd = fetch (&code->dst); | |
1009 | ea = fetch (&code->src); | |
1010 | ea = -ea; | |
1011 | res = rd + ea; | |
1012 | goto just_flags_alu8; | |
1013 | ||
1014 | case O (O_CMP, SW): | |
1015 | rd = fetch (&code->dst); | |
1016 | ea = fetch (&code->src); | |
1017 | ea = -ea; | |
1018 | res = rd + ea; | |
1019 | goto just_flags_alu16; | |
1020 | ||
1021 | case O (O_CMP, SL): | |
1022 | rd = fetch (&code->dst); | |
1023 | ea = fetch (&code->src); | |
1024 | ea = -ea; | |
1025 | res = rd + ea; | |
1026 | goto just_flags_alu32; | |
1027 | ||
1028 | ||
1029 | case O (O_DEC, SB): | |
1030 | rd = GET_B_REG (code->src.reg); | |
1031 | ea = -1; | |
1032 | res = rd + ea; | |
1033 | SET_B_REG (code->src.reg, res); | |
1034 | goto just_flags_inc8; | |
1035 | ||
1036 | case O (O_DEC, SW): | |
1037 | rd = GET_W_REG (code->dst.reg); | |
0693d363 | 1038 | ea = -code->src.literal; |
ce51bde6 DE |
1039 | res = rd + ea; |
1040 | SET_W_REG (code->dst.reg, res); | |
1041 | goto just_flags_inc16; | |
1042 | ||
1043 | case O (O_DEC, SL): | |
1044 | rd = GET_L_REG (code->dst.reg); | |
1045 | ea = -code->src.literal; | |
1046 | res = rd + ea; | |
1047 | SET_L_REG (code->dst.reg, res); | |
1048 | goto just_flags_inc32; | |
1049 | ||
1050 | ||
1051 | case O (O_INC, SB): | |
1052 | rd = GET_B_REG (code->src.reg); | |
1053 | ea = 1; | |
1054 | res = rd + ea; | |
1055 | SET_B_REG (code->src.reg, res); | |
1056 | goto just_flags_inc8; | |
1057 | ||
1058 | case O (O_INC, SW): | |
1059 | rd = GET_W_REG (code->dst.reg); | |
1060 | ea = code->src.literal; | |
1061 | res = rd + ea; | |
1062 | SET_W_REG (code->dst.reg, res); | |
1063 | goto just_flags_inc16; | |
1064 | ||
1065 | case O (O_INC, SL): | |
1066 | rd = GET_L_REG (code->dst.reg); | |
1067 | ea = code->src.literal; | |
1068 | res = rd + ea; | |
1069 | SET_L_REG (code->dst.reg, res); | |
1070 | goto just_flags_inc32; | |
1071 | ||
1072 | ||
1073 | #define GET_CCR(x) BUILDSR();x = cpu.ccr | |
0693d363 | 1074 | |
ce51bde6 DE |
1075 | case O (O_ANDC, SB): |
1076 | GET_CCR (rd); | |
1077 | ea = code->src.literal; | |
1078 | res = rd & ea; | |
1079 | goto setc; | |
1080 | ||
0693d363 DE |
1081 | case O (O_ORC, SB): |
1082 | GET_CCR (rd); | |
1083 | ea = code->src.literal; | |
1084 | res = rd | ea; | |
1085 | goto setc; | |
1086 | ||
1087 | case O (O_XORC, SB): | |
1088 | GET_CCR (rd); | |
1089 | ea = code->src.literal; | |
1090 | res = rd ^ ea; | |
1091 | goto setc; | |
1092 | ||
ce51bde6 DE |
1093 | |
1094 | case O (O_BRA, SB): | |
1095 | if (1) | |
1096 | goto condtrue; | |
1097 | goto next; | |
1098 | ||
1099 | case O (O_BRN, SB): | |
1100 | if (0) | |
1101 | goto condtrue; | |
1102 | goto next; | |
1103 | ||
1104 | case O (O_BHI, SB): | |
1105 | if ((C || Z) == 0) | |
1106 | goto condtrue; | |
1107 | goto next; | |
1108 | ||
1109 | ||
1110 | case O (O_BLS, SB): | |
1111 | if ((C || Z)) | |
1112 | goto condtrue; | |
1113 | goto next; | |
1114 | ||
1115 | case O (O_BCS, SB): | |
1116 | if ((C == 1)) | |
1117 | goto condtrue; | |
1118 | goto next; | |
1119 | ||
1120 | case O (O_BCC, SB): | |
1121 | if ((C == 0)) | |
1122 | goto condtrue; | |
1123 | goto next; | |
1124 | ||
1125 | case O (O_BEQ, SB): | |
1126 | if (Z) | |
1127 | goto condtrue; | |
1128 | goto next; | |
1129 | case O (O_BGT, SB): | |
1130 | if (((Z || (N ^ V)) == 0)) | |
1131 | goto condtrue; | |
1132 | goto next; | |
1133 | ||
1134 | ||
1135 | case O (O_BLE, SB): | |
1136 | if (((Z || (N ^ V)) == 1)) | |
1137 | goto condtrue; | |
1138 | goto next; | |
1139 | ||
1140 | case O (O_BGE, SB): | |
1141 | if ((N ^ V) == 0) | |
1142 | goto condtrue; | |
1143 | goto next; | |
1144 | case O (O_BLT, SB): | |
1145 | if ((N ^ V)) | |
1146 | goto condtrue; | |
1147 | goto next; | |
1148 | case O (O_BMI, SB): | |
1149 | if ((N)) | |
1150 | goto condtrue; | |
1151 | goto next; | |
1152 | case O (O_BNE, SB): | |
1153 | if ((Z == 0)) | |
1154 | goto condtrue; | |
1155 | goto next; | |
1156 | ||
1157 | case O (O_BPL, SB): | |
1158 | if (N == 0) | |
1159 | goto condtrue; | |
1160 | goto next; | |
1161 | case O (O_BVC, SB): | |
1162 | if ((V == 0)) | |
1163 | goto condtrue; | |
1164 | goto next; | |
1165 | case O (O_BVS, SB): | |
1166 | if ((V == 1)) | |
1167 | goto condtrue; | |
1168 | goto next; | |
1169 | ||
0693d363 DE |
1170 | case O (O_SYSCALL, SB): |
1171 | printf ("%c", cpu.regs[2]); | |
ce51bde6 | 1172 | goto next; |
ce51bde6 | 1173 | |
5d06fa80 DE |
1174 | OSHIFTS (O_NOT, rd = ~rd; v = 0;); |
1175 | OSHIFTS (O_SHLL, c = rd & hm; v = 0; | |
0693d363 | 1176 | rd <<= 1); |
5d06fa80 | 1177 | OSHIFTS (O_SHLR, c = rd & 1; v = 0; |
0693d363 DE |
1178 | rd = (unsigned int) rd >> 1); |
1179 | OSHIFTS (O_SHAL, c = rd & hm; | |
5d06fa80 | 1180 | v = (rd & hm) != ((rd & (hm >> 1)) << 1); |
0693d363 DE |
1181 | rd <<= 1); |
1182 | OSHIFTS (O_SHAR, t = rd & hm; | |
1183 | c = rd & 1; | |
5d06fa80 | 1184 | v = 0; |
0693d363 DE |
1185 | rd >>= 1; |
1186 | rd |= t; | |
7478904c | 1187 | ); |
0693d363 | 1188 | OSHIFTS (O_ROTL, c = rd & hm; |
5d06fa80 | 1189 | v = 0; |
0693d363 DE |
1190 | rd <<= 1; |
1191 | rd |= C); | |
1192 | OSHIFTS (O_ROTR, c = rd & 1; | |
5d06fa80 | 1193 | v = 0; |
0693d363 DE |
1194 | rd = (unsigned int) rd >> 1; |
1195 | if (c) rd |= hm;); | |
1196 | OSHIFTS (O_ROTXL, t = rd & hm; | |
1197 | rd <<= 1; | |
1198 | rd |= C; | |
1199 | c = t; | |
5d06fa80 | 1200 | v = 0; |
7478904c | 1201 | ); |
0693d363 DE |
1202 | OSHIFTS (O_ROTXR, t = rd & 1; |
1203 | rd = (unsigned int) rd >> 1; | |
5d06fa80 DE |
1204 | if (C) rd |= hm; c = t; |
1205 | v = 0;); | |
0693d363 DE |
1206 | |
1207 | case O (O_JMP, SB): | |
ce51bde6 DE |
1208 | { |
1209 | pc = fetch (&code->src); | |
1210 | goto end; | |
0693d363 | 1211 | |
ce51bde6 | 1212 | } |
0693d363 | 1213 | |
ce51bde6 DE |
1214 | case O (O_JSR, SB): |
1215 | { | |
1216 | int tmp; | |
1217 | pc = fetch (&code->src); | |
1218 | call: | |
1219 | tmp = cpu.regs[7]; | |
1220 | ||
28655f00 | 1221 | if (h8300hmode) |
ce51bde6 DE |
1222 | { |
1223 | tmp -= 4; | |
1224 | SET_MEMORY_L (tmp, code->next_pc); | |
1225 | } | |
1226 | else | |
1227 | { | |
1228 | tmp -= 2; | |
1229 | SET_MEMORY_W (tmp, code->next_pc); | |
1230 | } | |
1231 | cpu.regs[7] = tmp; | |
1232 | ||
1233 | goto end; | |
1234 | } | |
0693d363 | 1235 | case O (O_BSR, SB): |
ce51bde6 DE |
1236 | pc = code->src.literal; |
1237 | goto call; | |
0693d363 | 1238 | |
ce51bde6 DE |
1239 | case O (O_RTS, SB): |
1240 | { | |
1241 | int tmp; | |
1242 | ||
ce51bde6 DE |
1243 | tmp = cpu.regs[7]; |
1244 | ||
28655f00 | 1245 | if (h8300hmode) |
ce51bde6 DE |
1246 | { |
1247 | pc = GET_MEMORY_L (tmp); | |
1248 | tmp += 4; | |
ce51bde6 DE |
1249 | } |
1250 | else | |
1251 | { | |
1252 | pc = GET_MEMORY_W (tmp); | |
1253 | tmp += 2; | |
1254 | } | |
1255 | ||
1256 | cpu.regs[7] = tmp; | |
1257 | goto end; | |
1258 | } | |
1259 | ||
1260 | case O (O_ILL, SB): | |
1261 | cpu.exception = SIGILL; | |
1262 | goto end; | |
0693d363 | 1263 | case O (O_SLEEP, SB): |
4dfb4ffc DE |
1264 | /* The format of r0 is defined by devo/include/wait.h. |
1265 | cpu.exception handling needs some cleanup: we need to make the | |
1266 | the handling of normal exits vs signals, etc. more sensible. */ | |
1267 | if (! WIFEXITED (cpu.regs[0]) && WIFSIGNALED (cpu.regs[0])) | |
e656ecf9 DE |
1268 | cpu.exception = SIGILL; |
1269 | else | |
1270 | cpu.exception = SIGTRAP; | |
1271 | goto end; | |
0693d363 | 1272 | case O (O_BPT, SB): |
ce51bde6 DE |
1273 | cpu.exception = SIGTRAP; |
1274 | goto end; | |
1275 | ||
0693d363 DE |
1276 | OBITOP (O_BNOT, 1, 1, ea ^= m); |
1277 | OBITOP (O_BTST, 1, 0, nz = ea & m); | |
1278 | OBITOP (O_BCLR, 1, 1, ea &= ~m); | |
1279 | OBITOP (O_BSET, 1, 1, ea |= m); | |
1280 | OBITOP (O_BLD, 1, 0, c = ea & m); | |
1281 | OBITOP (O_BILD, 1, 0, c = !(ea & m)); | |
1282 | OBITOP (O_BST, 1, 1, ea &= ~m; | |
1283 | if (C) ea |= m); | |
1284 | OBITOP (O_BIST, 1, 1, ea &= ~m; | |
1285 | if (!C) ea |= m); | |
1286 | OBITOP (O_BAND, 1, 0, c = (ea & m) && C); | |
1287 | OBITOP (O_BIAND, 1, 0, c = !(ea & m) && C); | |
1288 | OBITOP (O_BOR, 1, 0, c = (ea & m) || C); | |
1289 | OBITOP (O_BIOR, 1, 0, c = !(ea & m) || C); | |
1290 | OBITOP (O_BXOR, 1, 0, c = (ea & m) != C); | |
1291 | OBITOP (O_BIXOR, 1, 0, c = !(ea & m) != C); | |
ce51bde6 DE |
1292 | |
1293 | ||
28655f00 | 1294 | #define MOP(bsize, signed) mop(code, bsize,signed); goto next; |
ce51bde6 | 1295 | |
0693d363 DE |
1296 | case O (O_MULS, SB): |
1297 | MOP (1, 1); | |
1298 | break; | |
1299 | case O (O_MULS, SW): | |
1300 | MOP (0, 1); | |
1301 | break; | |
1302 | case O (O_MULU, SB): | |
1303 | MOP (1, 0); | |
1304 | break; | |
1305 | case O (O_MULU, SW): | |
1306 | MOP (0, 0); | |
1307 | break; | |
ce51bde6 | 1308 | |
ce51bde6 | 1309 | |
0693d363 DE |
1310 | case O (O_DIVU, SB): |
1311 | { | |
1312 | rd = GET_W_REG (code->dst.reg); | |
1313 | ea = GET_B_REG (code->src.reg); | |
1314 | if (ea) | |
1315 | { | |
1316 | tmp = rd % ea; | |
1317 | rd = rd / ea; | |
1318 | } | |
1319 | SET_W_REG (code->dst.reg, (rd & 0xff) | (tmp << 8)); | |
1320 | n = ea & 0x80; | |
1321 | nz = ea & 0xff; | |
ce51bde6 | 1322 | |
0693d363 DE |
1323 | goto next; |
1324 | } | |
1325 | case O (O_DIVU, SW): | |
1326 | { | |
1327 | rd = GET_L_REG (code->dst.reg); | |
1328 | ea = GET_W_REG (code->src.reg); | |
1329 | n = ea & 0x8000; | |
1330 | nz = ea & 0xffff; | |
1331 | if (ea) | |
1332 | { | |
1333 | tmp = rd % ea; | |
1334 | rd = rd / ea; | |
1335 | } | |
1336 | SET_L_REG (code->dst.reg, (rd & 0xffff) | (tmp << 16)); | |
1337 | goto next; | |
1338 | } | |
ce51bde6 | 1339 | |
0693d363 DE |
1340 | case O (O_DIVS, SB): |
1341 | { | |
ce51bde6 | 1342 | |
0693d363 DE |
1343 | rd = SEXTSHORT (GET_W_REG (code->dst.reg)); |
1344 | ea = SEXTCHAR (GET_B_REG (code->src.reg)); | |
1345 | if (ea) | |
1346 | { | |
1347 | tmp = (int) rd % (int) ea; | |
1348 | rd = (int) rd / (int) ea; | |
1349 | n = rd & 0x8000; | |
1350 | nz = 1; | |
1351 | } | |
1352 | else | |
1353 | nz = 0; | |
1354 | SET_W_REG (code->dst.reg, (rd & 0xff) | (tmp << 8)); | |
1355 | goto next; | |
1356 | } | |
1357 | case O (O_DIVS, SW): | |
1358 | { | |
1359 | rd = GET_L_REG (code->dst.reg); | |
1360 | ea = SEXTSHORT (GET_W_REG (code->src.reg)); | |
1361 | if (ea) | |
1362 | { | |
1363 | tmp = (int) rd % (int) ea; | |
1364 | rd = (int) rd / (int) ea; | |
1365 | n = rd & 0x80000000; | |
1366 | nz = 1; | |
1367 | } | |
1368 | else | |
1369 | nz = 0; | |
1370 | SET_L_REG (code->dst.reg, (rd & 0xffff) | (tmp << 16)); | |
1371 | goto next; | |
1372 | } | |
1373 | case O (O_EXTS, SW): | |
7478904c | 1374 | rd = GET_B_REG (code->src.reg + 8) & 0xff; /* Yes, src, not dst. */ |
0693d363 DE |
1375 | ea = rd & 0x80 ? -256 : 0; |
1376 | res = rd + ea; | |
1377 | goto log16; | |
1378 | case O (O_EXTS, SL): | |
1379 | rd = GET_W_REG (code->src.reg) & 0xffff; | |
1380 | ea = rd & 0x8000 ? -65536 : 0; | |
1381 | res = rd + ea; | |
1382 | goto log32; | |
1383 | case O (O_EXTU, SW): | |
1384 | rd = GET_B_REG (code->src.reg + 8) & 0xff; | |
1385 | ea = 0; | |
1386 | res = rd + ea; | |
1387 | goto log16; | |
1388 | case O (O_EXTU, SL): | |
1389 | rd = GET_W_REG (code->src.reg) & 0xffff; | |
1390 | ea = 0; | |
1391 | res = rd + ea; | |
1392 | goto log32; | |
ce51bde6 | 1393 | |
0693d363 DE |
1394 | case O (O_NOP, SB): |
1395 | goto next; | |
ce51bde6 | 1396 | |
0693d363 | 1397 | default: |
7478904c | 1398 | cpu.exception = SIGILL; |
0693d363 | 1399 | goto end; |
ce51bde6 DE |
1400 | |
1401 | } | |
0693d363 DE |
1402 | abort (); |
1403 | ||
1404 | setc: | |
1405 | cpu.ccr = res; | |
1406 | GETSR (); | |
28655f00 SC |
1407 | goto next; |
1408 | ||
0693d363 DE |
1409 | condtrue: |
1410 | /* When a branch works */ | |
1411 | pc = code->src.literal; | |
ce51bde6 DE |
1412 | goto end; |
1413 | ||
0693d363 DE |
1414 | /* Set the cond codes from res */ |
1415 | bitop: | |
ce51bde6 | 1416 | |
0693d363 DE |
1417 | /* Set the flags after an 8 bit inc/dec operation */ |
1418 | just_flags_inc8: | |
1419 | n = res & 0x80; | |
1420 | nz = res & 0xff; | |
1421 | v = (rd & 0x7f) == 0x7f; | |
1422 | goto next; | |
ce51bde6 | 1423 | |
ce51bde6 | 1424 | |
0693d363 DE |
1425 | /* Set the flags after an 16 bit inc/dec operation */ |
1426 | just_flags_inc16: | |
1427 | n = res & 0x8000; | |
1428 | nz = res & 0xffff; | |
1429 | v = (rd & 0x7fff) == 0x7fff; | |
1430 | goto next; | |
1431 | ||
1432 | ||
1433 | /* Set the flags after an 32 bit inc/dec operation */ | |
1434 | just_flags_inc32: | |
1435 | n = res & 0x80000000; | |
1436 | nz = res & 0xffffffff; | |
1437 | v = (rd & 0x7fffffff) == 0x7fffffff; | |
1438 | goto next; | |
1439 | ||
1440 | ||
1441 | shift8: | |
5d06fa80 | 1442 | /* Set flags after an 8 bit shift op, carry,overflow set in insn */ |
0693d363 | 1443 | n = (rd & 0x80); |
0693d363 DE |
1444 | nz = rd & 0xff; |
1445 | SET_B_REG (code->src.reg, rd); | |
1446 | goto next; | |
1447 | ||
0693d363 | 1448 | shift16: |
5d06fa80 | 1449 | /* Set flags after an 16 bit shift op, carry,overflow set in insn */ |
0693d363 | 1450 | n = (rd & 0x8000); |
0693d363 | 1451 | nz = rd & 0xffff; |
0693d363 DE |
1452 | SET_W_REG (code->src.reg, rd); |
1453 | goto next; | |
1454 | ||
1455 | shift32: | |
5d06fa80 | 1456 | /* Set flags after an 32 bit shift op, carry,overflow set in insn */ |
0693d363 | 1457 | n = (rd & 0x80000000); |
0693d363 DE |
1458 | nz = rd & 0xffffffff; |
1459 | SET_L_REG (code->src.reg, rd); | |
1460 | goto next; | |
1461 | ||
1462 | log32: | |
1463 | store (&code->dst, res); | |
1464 | just_flags_log32: | |
1465 | /* flags after a 32bit logical operation */ | |
1466 | n = res & 0x80000000; | |
1467 | nz = res & 0xffffffff; | |
1468 | v = 0; | |
1469 | goto next; | |
1470 | ||
1471 | log16: | |
1472 | store (&code->dst, res); | |
1473 | just_flags_log16: | |
1474 | /* flags after a 16bit logical operation */ | |
1475 | n = res & 0x8000; | |
1476 | nz = res & 0xffff; | |
1477 | v = 0; | |
1478 | goto next; | |
1479 | ||
1480 | ||
1481 | log8: | |
1482 | store (&code->dst, res); | |
1483 | just_flags_log8: | |
1484 | n = res & 0x80; | |
1485 | nz = res & 0xff; | |
1486 | v = 0; | |
1487 | goto next; | |
1488 | ||
1489 | alu8: | |
1490 | SET_B_REG (code->dst.reg, res); | |
1491 | just_flags_alu8: | |
1492 | n = res & 0x80; | |
1493 | nz = res & 0xff; | |
1494 | v = ((ea & 0x80) == (rd & 0x80)) && ((ea & 0x80) != (res & 0x80)); | |
1495 | c = (res & 0x100); | |
1496 | goto next; | |
1497 | ||
1498 | alu16: | |
1499 | SET_W_REG (code->dst.reg, res); | |
1500 | just_flags_alu16: | |
1501 | n = res & 0x8000; | |
1502 | nz = res & 0xffff; | |
1503 | v = ((ea & 0x8000) == (rd & 0x8000)) && ((ea & 0x8000) != (res & 0x8000)); | |
1504 | c = (res & 0x10000); | |
1505 | goto next; | |
1506 | ||
1507 | alu32: | |
1508 | SET_L_REG (code->dst.reg, res); | |
1509 | just_flags_alu32: | |
1510 | n = res & 0x80000000; | |
1511 | nz = res & 0xffffffff; | |
1512 | v = ((ea & 0x80000000) == (rd & 0x80000000)) | |
1513 | && ((ea & 0x80000000) != (res & 0x80000000)); | |
1514 | switch (code->opcode / 4) | |
1515 | { | |
1516 | case O_ADD: | |
1517 | c = ((unsigned) res < (unsigned) rd) || ((unsigned) res < (unsigned) ea); | |
1518 | break; | |
1519 | case O_SUB: | |
1520 | case O_CMP: | |
1521 | c = (unsigned) rd < (unsigned) -ea; | |
1522 | break; | |
1523 | case O_NEG: | |
1524 | c = res != 0; | |
1525 | break; | |
1526 | } | |
1527 | goto next; | |
1528 | ||
1529 | next:; | |
1530 | pc = code->next_pc; | |
1531 | ||
1532 | end: | |
1533 | ; | |
1534 | /* if (cpu.regs[8] ) abort(); */ | |
1535 | ||
7478904c SC |
1536 | #if defined (WIN32) |
1537 | /* Poll after every 100th insn, */ | |
1538 | if (poll_count++ > 100) | |
1539 | { | |
1540 | poll_count = 0; | |
1541 | if (win32pollquit()) | |
1542 | { | |
1543 | control_c(); | |
1544 | } | |
1545 | } | |
1546 | #endif | |
1547 | #if defined(__GO32__) | |
0693d363 DE |
1548 | /* Poll after every 100th insn, */ |
1549 | if (poll_count++ > 100) | |
1550 | { | |
1551 | poll_count = 0; | |
1552 | if (kbhit ()) | |
1553 | { | |
1554 | int c = getkey (); | |
1555 | control_c (); | |
1556 | } | |
1557 | } | |
1558 | #endif | |
1559 | ||
1560 | } | |
ce51bde6 DE |
1561 | while (!cpu.exception); |
1562 | cpu.ticks += get_now () - tick_start; | |
1563 | cpu.cycles += cycles; | |
1564 | cpu.insts += insts; | |
7478904c | 1565 | |
ce51bde6 DE |
1566 | cpu.pc = pc; |
1567 | BUILDSR (); | |
7478904c | 1568 | cpu.mask = oldmask; |
ce51bde6 DE |
1569 | signal (SIGINT, prev); |
1570 | } | |
1571 | ||
1572 | ||
28655f00 | 1573 | int |
ce51bde6 | 1574 | sim_write (addr, buffer, size) |
a415cf0a | 1575 | SIM_ADDR addr; |
ce51bde6 DE |
1576 | unsigned char *buffer; |
1577 | int size; | |
1578 | { | |
1579 | int i; | |
1580 | ||
1581 | init_pointers (); | |
e656ecf9 | 1582 | if (addr < 0 || addr + size > memory_size) |
a415cf0a | 1583 | return 0; |
ce51bde6 DE |
1584 | for (i = 0; i < size; i++) |
1585 | { | |
1586 | cpu.memory[addr + i] = buffer[i]; | |
1587 | cpu.cache_idx[addr + i] = 0; | |
1588 | } | |
a415cf0a | 1589 | return size; |
ce51bde6 DE |
1590 | } |
1591 | ||
28655f00 | 1592 | int |
ce51bde6 | 1593 | sim_read (addr, buffer, size) |
a415cf0a DE |
1594 | SIM_ADDR addr; |
1595 | unsigned char *buffer; | |
ce51bde6 DE |
1596 | int size; |
1597 | { | |
1598 | init_pointers (); | |
e656ecf9 | 1599 | if (addr < 0 || addr + size > memory_size) |
a415cf0a | 1600 | return 0; |
ce51bde6 | 1601 | memcpy (buffer, cpu.memory + addr, size); |
28655f00 | 1602 | return size; |
ce51bde6 DE |
1603 | } |
1604 | ||
1605 | ||
ce51bde6 DE |
1606 | #define R0_REGNUM 0 |
1607 | #define R1_REGNUM 1 | |
1608 | #define R2_REGNUM 2 | |
1609 | #define R3_REGNUM 3 | |
1610 | #define R4_REGNUM 4 | |
1611 | #define R5_REGNUM 5 | |
1612 | #define R6_REGNUM 6 | |
1613 | #define R7_REGNUM 7 | |
1614 | ||
1615 | #define SP_REGNUM R7_REGNUM /* Contains address of top of stack */ | |
1616 | #define FP_REGNUM R6_REGNUM /* Contains address of executing | |
0693d363 | 1617 | * stack frame */ |
ce51bde6 DE |
1618 | |
1619 | #define CCR_REGNUM 8 /* Contains processor status */ | |
1620 | #define PC_REGNUM 9 /* Contains program counter */ | |
1621 | ||
1622 | #define CYCLE_REGNUM 10 | |
1623 | #define INST_REGNUM 11 | |
1624 | #define TICK_REGNUM 12 | |
1625 | ||
1626 | ||
7478904c | 1627 | void |
ce51bde6 DE |
1628 | sim_store_register (rn, value) |
1629 | int rn; | |
28655f00 | 1630 | unsigned char *value; |
ce51bde6 | 1631 | { |
28655f00 SC |
1632 | int longval; |
1633 | int shortval; | |
1634 | int intval; | |
0693d363 DE |
1635 | longval = (value[0] << 24) | (value[1] << 16) | (value[2] << 8) | value[3]; |
1636 | shortval = (value[0] << 8) | (value[1]); | |
28655f00 | 1637 | intval = h8300hmode ? longval : shortval; |
ce51bde6 DE |
1638 | |
1639 | init_pointers (); | |
1640 | switch (rn) | |
1641 | { | |
1642 | case PC_REGNUM: | |
28655f00 | 1643 | cpu.pc = intval; |
ce51bde6 DE |
1644 | break; |
1645 | default: | |
1646 | abort (); | |
1647 | case R0_REGNUM: | |
1648 | case R1_REGNUM: | |
1649 | case R2_REGNUM: | |
1650 | case R3_REGNUM: | |
1651 | case R4_REGNUM: | |
1652 | case R5_REGNUM: | |
1653 | case R6_REGNUM: | |
1654 | case R7_REGNUM: | |
28655f00 | 1655 | cpu.regs[rn] = intval; |
ce51bde6 DE |
1656 | break; |
1657 | case CCR_REGNUM: | |
28655f00 | 1658 | cpu.ccr = intval; |
ce51bde6 DE |
1659 | break; |
1660 | case CYCLE_REGNUM: | |
28655f00 | 1661 | cpu.cycles = longval; |
ce51bde6 DE |
1662 | break; |
1663 | ||
1664 | case INST_REGNUM: | |
28655f00 | 1665 | cpu.insts = longval; |
ce51bde6 DE |
1666 | break; |
1667 | ||
1668 | case TICK_REGNUM: | |
28655f00 | 1669 | cpu.ticks = longval; |
ce51bde6 DE |
1670 | break; |
1671 | } | |
1672 | } | |
1673 | ||
7478904c | 1674 | void |
ce51bde6 DE |
1675 | sim_fetch_register (rn, buf) |
1676 | int rn; | |
a415cf0a | 1677 | unsigned char *buf; |
ce51bde6 DE |
1678 | { |
1679 | int v; | |
1680 | int longreg = 0; | |
1681 | ||
1682 | init_pointers (); | |
1683 | ||
1684 | switch (rn) | |
1685 | { | |
1686 | default: | |
1687 | abort (); | |
1688 | case 8: | |
1689 | v = cpu.ccr; | |
1690 | break; | |
1691 | case 9: | |
1692 | v = cpu.pc; | |
1693 | break; | |
1694 | case R0_REGNUM: | |
1695 | case R1_REGNUM: | |
1696 | case R2_REGNUM: | |
1697 | case R3_REGNUM: | |
1698 | case R4_REGNUM: | |
1699 | case R5_REGNUM: | |
1700 | case R6_REGNUM: | |
1701 | case R7_REGNUM: | |
1702 | v = cpu.regs[rn]; | |
1703 | break; | |
1704 | case 10: | |
1705 | v = cpu.cycles; | |
1706 | longreg = 1; | |
ce51bde6 DE |
1707 | break; |
1708 | case 11: | |
1709 | v = cpu.ticks; | |
1710 | longreg = 1; | |
1711 | break; | |
1712 | case 12: | |
1713 | v = cpu.insts; | |
1714 | longreg = 1; | |
1715 | break; | |
ce51bde6 | 1716 | } |
28655f00 | 1717 | if (h8300hmode || longreg) |
ce51bde6 DE |
1718 | { |
1719 | buf[0] = v >> 24; | |
1720 | buf[1] = v >> 16; | |
1721 | buf[2] = v >> 8; | |
1722 | buf[3] = v >> 0; | |
1723 | } | |
1724 | else | |
1725 | { | |
1726 | buf[0] = v >> 8; | |
1727 | buf[1] = v; | |
1728 | } | |
1729 | } | |
1730 | ||
7478904c | 1731 | void |
a415cf0a DE |
1732 | sim_stop_reason (reason, sigrc) |
1733 | enum sim_stop *reason; | |
1734 | int *sigrc; | |
ce51bde6 | 1735 | { |
a415cf0a | 1736 | *reason = sim_stopped; |
7db9345b | 1737 | *sigrc = cpu.exception; |
ce51bde6 DE |
1738 | } |
1739 | ||
ce51bde6 DE |
1740 | sim_csize (n) |
1741 | { | |
1742 | if (cpu.cache) | |
1743 | free (cpu.cache); | |
1744 | if (n < 2) | |
1745 | n = 2; | |
1746 | cpu.cache = (decoded_inst *) malloc (sizeof (decoded_inst) * n); | |
1747 | memset (cpu.cache, 0, sizeof (decoded_inst) * n); | |
1748 | cpu.csize = n; | |
1749 | } | |
1750 | ||
1751 | ||
7478904c SC |
1752 | void |
1753 | sim_info (verbose) | |
ce51bde6 | 1754 | int verbose; |
ce51bde6 DE |
1755 | { |
1756 | double timetaken = (double) cpu.ticks / (double) now_persec (); | |
1757 | double virttime = cpu.cycles / 10.0e6; | |
1758 | ||
7478904c SC |
1759 | printf_filtered ("\n\n#instructions executed %10d\n", cpu.insts); |
1760 | printf_filtered ("#cycles (v approximate) %10d\n", cpu.cycles); | |
1761 | printf_filtered ("#real time taken %10.4f\n", timetaken); | |
1762 | printf_filtered ("#virtual time taked %10.4f\n", virttime); | |
0693d363 | 1763 | if (timetaken != 0.0) |
7478904c SC |
1764 | printf_filtered ("#simulation ratio %10.4f\n", virttime / timetaken); |
1765 | printf_filtered ("#compiles %10d\n", cpu.compiles); | |
1766 | printf_filtered ("#cache size %10d\n", cpu.csize); | |
ce51bde6 DE |
1767 | |
1768 | #ifdef ADEBUG | |
0693d363 | 1769 | if (verbose) |
ce51bde6 DE |
1770 | { |
1771 | int i; | |
0693d363 | 1772 | for (i = 0; i < O_LAST; i++) |
ce51bde6 DE |
1773 | { |
1774 | if (cpu.stats[i]) | |
7478904c | 1775 | printf_filtered ("%d: %d\n", i, cpu.stats[i]); |
ce51bde6 DE |
1776 | } |
1777 | } | |
1778 | #endif | |
1779 | } | |
1780 | ||
7478904c SC |
1781 | /* Indicate whether the cpu is an h8/300 or h8/300h. |
1782 | FLAG is non-zero for the h8/300h. */ | |
1783 | ||
89a2c4fd | 1784 | void |
7478904c SC |
1785 | set_h8300h (flag) |
1786 | int flag; | |
89a2c4fd | 1787 | { |
7478904c | 1788 | h8300hmode = flag; |
89a2c4fd | 1789 | } |
28655f00 | 1790 | |
7478904c | 1791 | void |
0693d363 | 1792 | sim_kill () |
7db9345b | 1793 | { |
7478904c | 1794 | /* nothing to do */ |
7db9345b DE |
1795 | } |
1796 | ||
7478904c SC |
1797 | void |
1798 | sim_open (args) | |
1799 | char *args; | |
7db9345b | 1800 | { |
7478904c | 1801 | /* nothing to do */ |
7db9345b DE |
1802 | } |
1803 | ||
7478904c SC |
1804 | void |
1805 | sim_close (quitting) | |
1806 | int quitting; | |
1807 | { | |
1808 | /* nothing to do */ | |
1809 | } | |
1810 | ||
1811 | /* Called by gdb to load a program into memory. */ | |
1812 | ||
1813 | int | |
1814 | sim_load (prog, from_tty) | |
1815 | char *prog; | |
1816 | int from_tty; | |
1817 | { | |
1818 | bfd *abfd; | |
1819 | ||
1820 | /* See if the file is for the h8/300 or h8/300h. */ | |
1821 | /* ??? This may not be the most efficient way. The z8k simulator | |
1822 | does this via a different mechanism (INIT_EXTRA_SYMTAB_INFO). */ | |
1823 | if ((abfd = bfd_openr (prog, "coff-h8300")) != 0) | |
1824 | { | |
1825 | if (bfd_check_format (abfd, bfd_object)) | |
1826 | set_h8300h (abfd->arch_info->mach == bfd_mach_h8300h); | |
1827 | bfd_close (abfd); | |
1828 | } | |
1829 | ||
1830 | /* Return non-zero so gdb will handle it. */ | |
1831 | return 1; | |
1832 | } | |
1833 | ||
1834 | void | |
1835 | sim_create_inferior (start_address, argv, env) | |
1836 | SIM_ADDR start_address; | |
a415cf0a DE |
1837 | char **argv; |
1838 | char **env; | |
7db9345b | 1839 | { |
7478904c | 1840 | cpu.pc = start_address; |
7db9345b | 1841 | } |
e656ecf9 DE |
1842 | |
1843 | void | |
1844 | sim_do_command (cmd) | |
1845 | char *cmd; | |
1846 | { | |
1847 | printf_filtered ("This simulator does not accept any commands.\n"); | |
1848 | } | |
1849 | ||
1850 | ||
1851 | ||
1852 | void | |
1853 | sim_set_callbacks (ptr) | |
1854 | struct host_callback_struct *ptr; | |
1855 | { | |
1856 | ||
1857 | } | |
1858 |