Commit | Line | Data |
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c906108c SS |
1 | /* |
2 | * Simulator for the Hitachi H8/300 architecture. | |
3 | * | |
4 | * Written by Steve Chamberlain of Cygnus Support. sac@cygnus.com | |
5 | * | |
6 | * This file is part of H8/300 sim | |
7 | * | |
8 | * | |
9 | * THIS SOFTWARE IS NOT COPYRIGHTED | |
10 | * | |
11 | * Cygnus offers the following for use in the public domain. Cygnus makes no | |
12 | * warranty with regard to the software or its performance and the user | |
13 | * accepts the software "AS IS" with all faults. | |
14 | * | |
15 | * CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO THIS | |
16 | * SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY | |
17 | * AND FITNESS FOR A PARTICULAR PURPOSE. | |
18 | */ | |
19 | ||
20 | #include "config.h" | |
21 | ||
22 | #include <stdio.h> | |
23 | #include <signal.h> | |
24 | #ifdef HAVE_TIME_H | |
25 | #include <time.h> | |
26 | #endif | |
27 | #ifdef HAVE_STDLIB_H | |
28 | #include <stdlib.h> | |
29 | #endif | |
30 | #ifdef HAVE_SYS_PARAM_H | |
31 | #include <sys/param.h> | |
32 | #endif | |
c906108c SS |
33 | #include "ansidecl.h" |
34 | #include "bfd.h" | |
3c25f8c7 AC |
35 | #include "gdb/callback.h" |
36 | #include "gdb/remote-sim.h" | |
a64bfde3 | 37 | #include "gdb/sim-h8300.h" |
c906108c SS |
38 | |
39 | #ifndef SIGTRAP | |
40 | # define SIGTRAP 5 | |
41 | #endif | |
42 | ||
43 | int debug; | |
44 | ||
45 | host_callback *sim_callback; | |
46 | ||
47 | static SIM_OPEN_KIND sim_kind; | |
48 | static char *myname; | |
49 | ||
50 | /* FIXME: Needs to live in header file. | |
51 | This header should also include the things in remote-sim.h. | |
52 | One could move this to remote-sim.h but this function isn't needed | |
53 | by gdb. */ | |
54 | void sim_set_simcache_size PARAMS ((int)); | |
55 | ||
de9b1892 | 56 | #define X(op, size) op * 4 + size |
c906108c | 57 | |
de9b1892 | 58 | #define SP (h8300hmode ? SL : SW) |
c906108c SS |
59 | #define SB 0 |
60 | #define SW 1 | |
61 | #define SL 2 | |
62 | #define OP_REG 1 | |
63 | #define OP_DEC 2 | |
64 | #define OP_DISP 3 | |
65 | #define OP_INC 4 | |
66 | #define OP_PCREL 5 | |
67 | #define OP_MEM 6 | |
68 | #define OP_CCR 7 | |
69 | #define OP_IMM 8 | |
70 | #define OP_ABS 10 | |
fc974602 | 71 | #define OP_EXR 11 |
c906108c SS |
72 | #define h8_opcodes ops |
73 | #define DEFINE_TABLE | |
74 | #include "opcode/h8300.h" | |
75 | ||
76 | #include "inst.h" | |
77 | ||
0ef9643e | 78 | /* The rate at which to call the host's poll_quit callback. */ |
7a292a7a SS |
79 | |
80 | #define POLL_QUIT_INTERVAL 0x80000 | |
81 | ||
c906108c | 82 | #define LOW_BYTE(x) ((x) & 0xff) |
de9b1892 KH |
83 | #define HIGH_BYTE(x) (((x) >> 8) & 0xff) |
84 | #define P(X,Y) ((X << 8) | Y) | |
c906108c | 85 | |
d0fe2f7e KH |
86 | #define BUILDSR() \ |
87 | cpu.ccr = ((I << 7) | (UI << 6) | (H << 5) | (U << 4) \ | |
88 | | (N << 3) | (Z << 2) | (V << 1) | C); | |
c906108c | 89 | |
fc974602 | 90 | #define BUILDEXR() \ |
d1335144 | 91 | if (h8300smode) cpu.exr = (trace<<7) | intMask; |
fc974602 | 92 | |
c906108c SS |
93 | #define GETSR() \ |
94 | c = (cpu.ccr >> 0) & 1;\ | |
95 | v = (cpu.ccr >> 1) & 1;\ | |
96 | nz = !((cpu.ccr >> 2) & 1);\ | |
f6225c96 AV |
97 | n = (cpu.ccr >> 3) & 1;\ |
98 | u = (cpu.ccr >> 4) & 1;\ | |
99 | h = (cpu.ccr >> 5) & 1;\ | |
100 | ui = ((cpu.ccr >> 6) & 1);\ | |
101 | intMaskBit = (cpu.ccr >> 7) & 1; | |
c906108c | 102 | |
d0fe2f7e KH |
103 | #define GETEXR() \ |
104 | if (h8300smode) \ | |
105 | { \ | |
106 | trace = (cpu.exr >> 7) & 1; \ | |
107 | intMask = cpu.exr & 7; \ | |
108 | } | |
fc974602 | 109 | |
c906108c | 110 | #ifdef __CHAR_IS_SIGNED__ |
de9b1892 | 111 | #define SEXTCHAR(x) ((char) (x)) |
c906108c SS |
112 | #endif |
113 | ||
114 | #ifndef SEXTCHAR | |
d0fe2f7e | 115 | #define SEXTCHAR(x) ((x & 0x80) ? (x | ~0xff) : x & 0xff) |
c906108c SS |
116 | #endif |
117 | ||
118 | #define UEXTCHAR(x) ((x) & 0xff) | |
119 | #define UEXTSHORT(x) ((x) & 0xffff) | |
de9b1892 | 120 | #define SEXTSHORT(x) ((short) (x)) |
c906108c SS |
121 | |
122 | static cpu_state_type cpu; | |
123 | ||
124 | int h8300hmode = 0; | |
125 | int h8300smode = 0; | |
126 | ||
127 | static int memory_size; | |
128 | ||
c906108c | 129 | static int |
a4f27e3e | 130 | get_now (void) |
c906108c | 131 | { |
3b02cf92 | 132 | return time (0); /* WinXX HAS UNIX like 'time', so why not using it? */ |
c906108c SS |
133 | } |
134 | ||
135 | static int | |
a4f27e3e | 136 | now_persec (void) |
c906108c SS |
137 | { |
138 | return 1; | |
139 | } | |
140 | ||
c906108c | 141 | static int |
a4f27e3e | 142 | bitfrom (int x) |
c906108c SS |
143 | { |
144 | switch (x & SIZE) | |
145 | { | |
146 | case L_8: | |
147 | return SB; | |
148 | case L_16: | |
149 | return SW; | |
150 | case L_32: | |
151 | return SL; | |
152 | case L_P: | |
153 | return h8300hmode ? SL : SW; | |
154 | } | |
155 | } | |
156 | ||
0ef9643e | 157 | static unsigned int |
a4f27e3e | 158 | lvalue (int x, int rn) |
c906108c SS |
159 | { |
160 | switch (x / 4) | |
161 | { | |
162 | case OP_DISP: | |
163 | if (rn == 8) | |
164 | { | |
165 | return X (OP_IMM, SP); | |
166 | } | |
167 | return X (OP_REG, SP); | |
168 | ||
169 | case OP_MEM: | |
c906108c | 170 | return X (OP_MEM, SP); |
0ef9643e | 171 | |
c906108c | 172 | default: |
3b02cf92 | 173 | abort (); /* ?? May be something more usefull? */ |
c906108c SS |
174 | } |
175 | } | |
176 | ||
177 | static unsigned int | |
a4f27e3e | 178 | decode (int addr, unsigned char *data, decoded_inst *dst) |
c906108c SS |
179 | { |
180 | int rs = 0; | |
181 | int rd = 0; | |
182 | int rdisp = 0; | |
183 | int abs = 0; | |
c906108c | 184 | int bit = 0; |
0ef9643e | 185 | int plen = 0; |
6d028502 | 186 | struct h8_opcode *q; |
c906108c | 187 | int size = 0; |
0ef9643e | 188 | |
c906108c SS |
189 | dst->dst.type = -1; |
190 | dst->src.type = -1; | |
0ef9643e JL |
191 | |
192 | /* Find the exact opcode/arg combo. */ | |
6d028502 | 193 | for (q = h8_opcodes; q->name; q++) |
c906108c | 194 | { |
6d028502 | 195 | op_type *nib = q->data.nib; |
c906108c SS |
196 | unsigned int len = 0; |
197 | ||
c906108c SS |
198 | while (1) |
199 | { | |
200 | op_type looking_for = *nib; | |
201 | int thisnib = data[len >> 1]; | |
202 | ||
203 | thisnib = (len & 1) ? (thisnib & 0xf) : ((thisnib >> 4) & 0xf); | |
204 | ||
205 | if (looking_for < 16 && looking_for >= 0) | |
206 | { | |
207 | if (looking_for != thisnib) | |
208 | goto fail; | |
209 | } | |
210 | else | |
211 | { | |
212 | if ((int) looking_for & (int) B31) | |
213 | { | |
214 | if (!(((int) thisnib & 0x8) != 0)) | |
215 | goto fail; | |
0ef9643e JL |
216 | |
217 | looking_for = (op_type) ((int) looking_for & ~(int) B31); | |
c906108c SS |
218 | thisnib &= 0x7; |
219 | } | |
0ef9643e | 220 | |
c906108c SS |
221 | if ((int) looking_for & (int) B30) |
222 | { | |
223 | if (!(((int) thisnib & 0x8) == 0)) | |
224 | goto fail; | |
0ef9643e | 225 | |
c906108c SS |
226 | looking_for = (op_type) ((int) looking_for & ~(int) B30); |
227 | } | |
0ef9643e | 228 | |
c906108c SS |
229 | if (looking_for & DBIT) |
230 | { | |
0a17cd59 AC |
231 | /* Exclude adds/subs by looking at bit 0 and 2, and |
232 | make sure the operand size, either w or l, | |
233 | matches by looking at bit 1. */ | |
234 | if ((looking_for & 7) != (thisnib & 7)) | |
c906108c | 235 | goto fail; |
0ef9643e | 236 | |
c906108c SS |
237 | abs = (thisnib & 0x8) ? 2 : 1; |
238 | } | |
239 | else if (looking_for & (REG | IND | INC | DEC)) | |
240 | { | |
241 | if (looking_for & REG) | |
242 | { | |
0ef9643e | 243 | /* Can work out size from the register. */ |
c906108c SS |
244 | size = bitfrom (looking_for); |
245 | } | |
246 | if (looking_for & SRC) | |
0ef9643e | 247 | rs = thisnib; |
c906108c | 248 | else |
0ef9643e | 249 | rd = thisnib; |
c906108c SS |
250 | } |
251 | else if (looking_for & L_16) | |
252 | { | |
253 | abs = (data[len >> 1]) * 256 + data[(len + 2) >> 1]; | |
254 | plen = 16; | |
255 | if (looking_for & (PCREL | DISP)) | |
256 | { | |
257 | abs = (short) (abs); | |
258 | } | |
259 | } | |
260 | else if (looking_for & ABSJMP) | |
261 | { | |
0ef9643e | 262 | abs = (data[1] << 16) | (data[2] << 8) | (data[3]); |
c906108c SS |
263 | } |
264 | else if (looking_for & MEMIND) | |
265 | { | |
266 | abs = data[1]; | |
267 | } | |
268 | else if (looking_for & L_32) | |
269 | { | |
270 | int i = len >> 1; | |
0ef9643e | 271 | |
c906108c SS |
272 | abs = (data[i] << 24) |
273 | | (data[i + 1] << 16) | |
274 | | (data[i + 2] << 8) | |
275 | | (data[i + 3]); | |
276 | ||
277 | plen = 32; | |
278 | } | |
279 | else if (looking_for & L_24) | |
280 | { | |
281 | int i = len >> 1; | |
0ef9643e | 282 | |
c906108c SS |
283 | abs = (data[i] << 16) | (data[i + 1] << 8) | (data[i + 2]); |
284 | plen = 24; | |
285 | } | |
286 | else if (looking_for & IGNORE) | |
287 | { | |
0ef9643e | 288 | ; |
c906108c SS |
289 | } |
290 | else if (looking_for & DISPREG) | |
291 | { | |
292 | rdisp = thisnib & 0x7; | |
293 | } | |
294 | else if (looking_for & KBIT) | |
295 | { | |
296 | switch (thisnib) | |
297 | { | |
298 | case 9: | |
299 | abs = 4; | |
300 | break; | |
301 | case 8: | |
302 | abs = 2; | |
303 | break; | |
304 | case 0: | |
305 | abs = 1; | |
306 | break; | |
0a17cd59 AC |
307 | default: |
308 | goto fail; | |
c906108c SS |
309 | } |
310 | } | |
311 | else if (looking_for & L_8) | |
312 | { | |
313 | plen = 8; | |
314 | ||
315 | if (looking_for & PCREL) | |
316 | { | |
317 | abs = SEXTCHAR (data[len >> 1]); | |
318 | } | |
319 | else if (looking_for & ABS8MEM) | |
320 | { | |
321 | plen = 8; | |
322 | abs = h8300hmode ? ~0xff0000ff : ~0xffff00ff; | |
0ef9643e | 323 | abs |= data[len >> 1] & 0xff; |
c906108c | 324 | } |
0ef9643e | 325 | else |
c906108c SS |
326 | { |
327 | abs = data[len >> 1] & 0xff; | |
328 | } | |
329 | } | |
330 | else if (looking_for & L_3) | |
331 | { | |
332 | plen = 3; | |
333 | ||
334 | bit = thisnib; | |
335 | } | |
336 | else if (looking_for == E) | |
337 | { | |
338 | dst->op = q; | |
339 | ||
0ef9643e | 340 | /* Fill in the args. */ |
c906108c SS |
341 | { |
342 | op_type *args = q->args.nib; | |
343 | int hadone = 0; | |
344 | ||
345 | while (*args != E) | |
346 | { | |
347 | int x = *args; | |
348 | int rn = (x & DST) ? rd : rs; | |
349 | ea_type *p; | |
350 | ||
351 | if (x & DST) | |
0ef9643e | 352 | p = &(dst->dst); |
c906108c | 353 | else |
0ef9643e | 354 | p = &(dst->src); |
c906108c | 355 | |
0ef9643e | 356 | if (x & L_3) |
c906108c SS |
357 | { |
358 | p->type = X (OP_IMM, size); | |
359 | p->literal = bit; | |
360 | } | |
361 | else if (x & (IMM | KBIT | DBIT)) | |
362 | { | |
363 | p->type = X (OP_IMM, size); | |
364 | p->literal = abs; | |
365 | } | |
366 | else if (x & REG) | |
367 | { | |
6d028502 KH |
368 | /* Reset the size. |
369 | Some ops (like mul) have two sizes. */ | |
c906108c SS |
370 | |
371 | size = bitfrom (x); | |
372 | p->type = X (OP_REG, size); | |
373 | p->reg = rn; | |
374 | } | |
375 | else if (x & INC) | |
376 | { | |
377 | p->type = X (OP_INC, size); | |
378 | p->reg = rn & 0x7; | |
379 | } | |
380 | else if (x & DEC) | |
381 | { | |
382 | p->type = X (OP_DEC, size); | |
383 | p->reg = rn & 0x7; | |
384 | } | |
385 | else if (x & IND) | |
386 | { | |
387 | p->type = X (OP_DISP, size); | |
388 | p->reg = rn & 0x7; | |
389 | p->literal = 0; | |
390 | } | |
391 | else if (x & (ABS | ABSJMP | ABS8MEM)) | |
392 | { | |
393 | p->type = X (OP_DISP, size); | |
394 | p->literal = abs; | |
395 | p->reg = 8; | |
396 | } | |
397 | else if (x & MEMIND) | |
398 | { | |
399 | p->type = X (OP_MEM, size); | |
400 | p->literal = abs; | |
401 | } | |
402 | else if (x & PCREL) | |
403 | { | |
404 | p->type = X (OP_PCREL, size); | |
405 | p->literal = abs + addr + 2; | |
406 | if (x & L_16) | |
407 | p->literal += 2; | |
408 | } | |
409 | else if (x & ABSJMP) | |
410 | { | |
411 | p->type = X (OP_IMM, SP); | |
412 | p->literal = abs; | |
413 | } | |
414 | else if (x & DISP) | |
415 | { | |
416 | p->type = X (OP_DISP, size); | |
417 | p->literal = abs; | |
418 | p->reg = rdisp & 0x7; | |
419 | } | |
420 | else if (x & CCR) | |
421 | { | |
422 | p->type = OP_CCR; | |
423 | } | |
fc974602 AV |
424 | else if (x & EXR) |
425 | { | |
426 | p->type = OP_EXR; | |
427 | } | |
c906108c SS |
428 | else |
429 | printf ("Hmmmm %x", x); | |
430 | ||
431 | args++; | |
432 | } | |
433 | } | |
434 | ||
0ef9643e JL |
435 | /* But a jmp or a jsr gets automagically lvalued, |
436 | since we branch to their address not their | |
437 | contents. */ | |
c906108c SS |
438 | if (q->how == O (O_JSR, SB) |
439 | || q->how == O (O_JMP, SB)) | |
440 | { | |
441 | dst->src.type = lvalue (dst->src.type, dst->src.reg); | |
442 | } | |
443 | ||
444 | if (dst->dst.type == -1) | |
445 | dst->dst = dst->src; | |
446 | ||
447 | dst->opcode = q->how; | |
448 | dst->cycles = q->time; | |
449 | ||
0ef9643e | 450 | /* And a jsr to 0xc4 is turned into a magic trap. */ |
c906108c SS |
451 | |
452 | if (dst->opcode == O (O_JSR, SB)) | |
453 | { | |
454 | if (dst->src.literal == 0xc4) | |
455 | { | |
456 | dst->opcode = O (O_SYSCALL, SB); | |
457 | } | |
458 | } | |
459 | ||
460 | dst->next_pc = addr + len / 2; | |
461 | return; | |
462 | } | |
463 | else | |
98ecb0a7 | 464 | printf ("Don't understand %x \n", looking_for); |
c906108c SS |
465 | } |
466 | ||
467 | len++; | |
468 | nib++; | |
469 | } | |
470 | ||
471 | fail: | |
6d028502 | 472 | ; |
c906108c SS |
473 | } |
474 | ||
0ef9643e | 475 | /* Fell off the end. */ |
c906108c SS |
476 | dst->opcode = O (O_ILL, SB); |
477 | } | |
478 | ||
c906108c | 479 | static void |
a4f27e3e | 480 | compile (int pc) |
c906108c SS |
481 | { |
482 | int idx; | |
483 | ||
2ea716f6 | 484 | /* Find the next cache entry to use. */ |
c906108c SS |
485 | idx = cpu.cache_top + 1; |
486 | cpu.compiles++; | |
487 | if (idx >= cpu.csize) | |
488 | { | |
489 | idx = 1; | |
490 | } | |
491 | cpu.cache_top = idx; | |
492 | ||
2ea716f6 | 493 | /* Throw away its old meaning. */ |
c906108c SS |
494 | cpu.cache_idx[cpu.cache[idx].oldpc] = 0; |
495 | ||
2ea716f6 | 496 | /* Set to new address. */ |
c906108c SS |
497 | cpu.cache[idx].oldpc = pc; |
498 | ||
2ea716f6 | 499 | /* Fill in instruction info. */ |
c906108c SS |
500 | decode (pc, cpu.memory + pc, cpu.cache + idx); |
501 | ||
2ea716f6 | 502 | /* Point to new cache entry. */ |
c906108c SS |
503 | cpu.cache_idx[pc] = idx; |
504 | } | |
505 | ||
506 | ||
507 | static unsigned char *breg[18]; | |
508 | static unsigned short *wreg[18]; | |
509 | static unsigned int *lreg[18]; | |
510 | ||
511 | #define GET_B_REG(x) *(breg[x]) | |
512 | #define SET_B_REG(x,y) (*(breg[x])) = (y) | |
513 | #define GET_W_REG(x) *(wreg[x]) | |
514 | #define SET_W_REG(x,y) (*(wreg[x])) = (y) | |
515 | ||
516 | #define GET_L_REG(x) *(lreg[x]) | |
517 | #define SET_L_REG(x,y) (*(lreg[x])) = (y) | |
518 | ||
519 | #define GET_MEMORY_L(x) \ | |
520 | (x < memory_size \ | |
521 | ? ((cpu.memory[x+0] << 24) | (cpu.memory[x+1] << 16) \ | |
522 | | (cpu.memory[x+2] << 8) | cpu.memory[x+3]) \ | |
523 | : ((cpu.eightbit[(x+0) & 0xff] << 24) | (cpu.eightbit[(x+1) & 0xff] << 16) \ | |
524 | | (cpu.eightbit[(x+2) & 0xff] << 8) | cpu.eightbit[(x+3) & 0xff])) | |
525 | ||
526 | #define GET_MEMORY_W(x) \ | |
527 | (x < memory_size \ | |
528 | ? ((cpu.memory[x+0] << 8) | (cpu.memory[x+1] << 0)) \ | |
529 | : ((cpu.eightbit[(x+0) & 0xff] << 8) | (cpu.eightbit[(x+1) & 0xff] << 0))) | |
530 | ||
531 | ||
532 | #define GET_MEMORY_B(x) \ | |
533 | (x < memory_size ? (cpu.memory[x]) : (cpu.eightbit[x & 0xff])) | |
534 | ||
535 | #define SET_MEMORY_L(x,y) \ | |
536 | { register unsigned char *_p; register int __y = y; \ | |
537 | _p = (x < memory_size ? cpu.memory+x : cpu.eightbit + (x & 0xff)); \ | |
538 | _p[0] = (__y)>>24; _p[1] = (__y)>>16; \ | |
539 | _p[2] = (__y)>>8; _p[3] = (__y)>>0;} | |
540 | ||
541 | #define SET_MEMORY_W(x,y) \ | |
542 | { register unsigned char *_p; register int __y = y; \ | |
543 | _p = (x < memory_size ? cpu.memory+x : cpu.eightbit + (x & 0xff)); \ | |
544 | _p[0] = (__y)>>8; _p[1] =(__y);} | |
545 | ||
546 | #define SET_MEMORY_B(x,y) \ | |
547 | (x < memory_size ? (cpu.memory[(x)] = y) : (cpu.eightbit[x & 0xff] = y)) | |
548 | ||
a4f27e3e MS |
549 | static int |
550 | fetch (ea_type *arg) | |
c906108c SS |
551 | { |
552 | int rn = arg->reg; | |
553 | int abs = arg->literal; | |
554 | int r; | |
555 | int t; | |
556 | ||
557 | switch (arg->type) | |
558 | { | |
559 | case X (OP_REG, SB): | |
560 | return GET_B_REG (rn); | |
561 | case X (OP_REG, SW): | |
562 | return GET_W_REG (rn); | |
563 | case X (OP_REG, SL): | |
564 | return GET_L_REG (rn); | |
565 | case X (OP_IMM, SB): | |
566 | case X (OP_IMM, SW): | |
567 | case X (OP_IMM, SL): | |
568 | return abs; | |
569 | case X (OP_DEC, SB): | |
570 | abort (); | |
571 | ||
572 | case X (OP_INC, SB): | |
573 | t = GET_L_REG (rn); | |
574 | t &= cpu.mask; | |
575 | r = GET_MEMORY_B (t); | |
576 | t++; | |
577 | t = t & cpu.mask; | |
578 | SET_L_REG (rn, t); | |
579 | return r; | |
580 | break; | |
581 | case X (OP_INC, SW): | |
582 | t = GET_L_REG (rn); | |
583 | t &= cpu.mask; | |
584 | r = GET_MEMORY_W (t); | |
585 | t += 2; | |
586 | t = t & cpu.mask; | |
587 | SET_L_REG (rn, t); | |
588 | return r; | |
589 | case X (OP_INC, SL): | |
590 | t = GET_L_REG (rn); | |
591 | t &= cpu.mask; | |
592 | r = GET_MEMORY_L (t); | |
593 | ||
594 | t += 4; | |
595 | t = t & cpu.mask; | |
596 | SET_L_REG (rn, t); | |
597 | return r; | |
598 | ||
599 | case X (OP_DISP, SB): | |
600 | t = GET_L_REG (rn) + abs; | |
601 | t &= cpu.mask; | |
602 | return GET_MEMORY_B (t); | |
603 | ||
604 | case X (OP_DISP, SW): | |
605 | t = GET_L_REG (rn) + abs; | |
606 | t &= cpu.mask; | |
607 | return GET_MEMORY_W (t); | |
608 | ||
609 | case X (OP_DISP, SL): | |
610 | t = GET_L_REG (rn) + abs; | |
611 | t &= cpu.mask; | |
612 | return GET_MEMORY_L (t); | |
613 | ||
614 | case X (OP_MEM, SL): | |
615 | t = GET_MEMORY_L (abs); | |
616 | t &= cpu.mask; | |
617 | return t; | |
618 | ||
619 | case X (OP_MEM, SW): | |
620 | t = GET_MEMORY_W (abs); | |
621 | t &= cpu.mask; | |
622 | return t; | |
623 | ||
624 | default: | |
3b02cf92 | 625 | abort (); /* ?? May be something more usefull? */ |
c906108c SS |
626 | |
627 | } | |
628 | } | |
629 | ||
630 | ||
de9b1892 | 631 | static void |
a4f27e3e | 632 | store (ea_type *arg, int n) |
c906108c SS |
633 | { |
634 | int rn = arg->reg; | |
635 | int abs = arg->literal; | |
636 | int t; | |
637 | ||
638 | switch (arg->type) | |
639 | { | |
640 | case X (OP_REG, SB): | |
641 | SET_B_REG (rn, n); | |
642 | break; | |
643 | case X (OP_REG, SW): | |
644 | SET_W_REG (rn, n); | |
645 | break; | |
646 | case X (OP_REG, SL): | |
647 | SET_L_REG (rn, n); | |
648 | break; | |
649 | ||
650 | case X (OP_DEC, SB): | |
651 | t = GET_L_REG (rn) - 1; | |
652 | t &= cpu.mask; | |
653 | SET_L_REG (rn, t); | |
654 | SET_MEMORY_B (t, n); | |
655 | ||
656 | break; | |
657 | case X (OP_DEC, SW): | |
658 | t = (GET_L_REG (rn) - 2) & cpu.mask; | |
659 | SET_L_REG (rn, t); | |
660 | SET_MEMORY_W (t, n); | |
661 | break; | |
662 | ||
663 | case X (OP_DEC, SL): | |
664 | t = (GET_L_REG (rn) - 4) & cpu.mask; | |
665 | SET_L_REG (rn, t); | |
666 | SET_MEMORY_L (t, n); | |
667 | break; | |
668 | ||
669 | case X (OP_DISP, SB): | |
670 | t = GET_L_REG (rn) + abs; | |
671 | t &= cpu.mask; | |
672 | SET_MEMORY_B (t, n); | |
673 | break; | |
674 | ||
675 | case X (OP_DISP, SW): | |
676 | t = GET_L_REG (rn) + abs; | |
677 | t &= cpu.mask; | |
678 | SET_MEMORY_W (t, n); | |
679 | break; | |
680 | ||
681 | case X (OP_DISP, SL): | |
682 | t = GET_L_REG (rn) + abs; | |
683 | t &= cpu.mask; | |
684 | SET_MEMORY_L (t, n); | |
685 | break; | |
686 | default: | |
687 | abort (); | |
688 | } | |
689 | } | |
690 | ||
691 | ||
692 | static union | |
693 | { | |
694 | short int i; | |
695 | struct | |
696 | { | |
697 | char low; | |
698 | char high; | |
699 | } | |
700 | u; | |
701 | } | |
702 | ||
703 | littleendian; | |
704 | ||
de9b1892 | 705 | static void |
a4f27e3e | 706 | init_pointers (void) |
c906108c SS |
707 | { |
708 | static int init; | |
709 | ||
710 | if (!init) | |
711 | { | |
712 | int i; | |
713 | ||
714 | init = 1; | |
715 | littleendian.i = 1; | |
716 | ||
a8cdafbd AV |
717 | if (h8300smode) |
718 | memory_size = H8300S_MSIZE; | |
719 | else if (h8300hmode) | |
c906108c SS |
720 | memory_size = H8300H_MSIZE; |
721 | else | |
722 | memory_size = H8300_MSIZE; | |
723 | cpu.memory = (unsigned char *) calloc (sizeof (char), memory_size); | |
724 | cpu.cache_idx = (unsigned short *) calloc (sizeof (short), memory_size); | |
725 | cpu.eightbit = (unsigned char *) calloc (sizeof (char), 256); | |
726 | ||
2ea716f6 | 727 | /* `msize' must be a power of two. */ |
c906108c SS |
728 | if ((memory_size & (memory_size - 1)) != 0) |
729 | abort (); | |
730 | cpu.mask = memory_size - 1; | |
731 | ||
732 | for (i = 0; i < 9; i++) | |
733 | { | |
734 | cpu.regs[i] = 0; | |
735 | } | |
736 | ||
737 | for (i = 0; i < 8; i++) | |
738 | { | |
739 | unsigned char *p = (unsigned char *) (cpu.regs + i); | |
740 | unsigned char *e = (unsigned char *) (cpu.regs + i + 1); | |
741 | unsigned short *q = (unsigned short *) (cpu.regs + i); | |
742 | unsigned short *u = (unsigned short *) (cpu.regs + i + 1); | |
743 | cpu.regs[i] = 0x00112233; | |
744 | while (p < e) | |
745 | { | |
746 | if (*p == 0x22) | |
747 | { | |
748 | breg[i] = p; | |
749 | } | |
750 | if (*p == 0x33) | |
751 | { | |
752 | breg[i + 8] = p; | |
753 | } | |
754 | p++; | |
755 | } | |
ec38ce99 | 756 | wreg[i] = wreg[i + 8] = 0; |
c906108c SS |
757 | while (q < u) |
758 | { | |
759 | if (*q == 0x2233) | |
760 | { | |
761 | wreg[i] = q; | |
762 | } | |
763 | if (*q == 0x0011) | |
764 | { | |
765 | wreg[i + 8] = q; | |
766 | } | |
767 | q++; | |
768 | } | |
ec38ce99 KH |
769 | if (wreg[i] == 0 || wreg[i + 8] == 0) |
770 | abort (); | |
c906108c SS |
771 | cpu.regs[i] = 0; |
772 | lreg[i] = &cpu.regs[i]; | |
773 | } | |
774 | ||
775 | lreg[8] = &cpu.regs[8]; | |
776 | ||
2ea716f6 | 777 | /* Initialize the seg registers. */ |
c906108c SS |
778 | if (!cpu.cache) |
779 | sim_set_simcache_size (CSIZE); | |
780 | } | |
781 | } | |
782 | ||
783 | static void | |
a4f27e3e | 784 | control_c (int sig) |
c906108c SS |
785 | { |
786 | cpu.state = SIM_STATE_STOPPED; | |
787 | cpu.exception = SIGINT; | |
788 | } | |
789 | ||
790 | #define C (c != 0) | |
791 | #define Z (nz == 0) | |
792 | #define V (v != 0) | |
793 | #define N (n != 0) | |
f6225c96 AV |
794 | #define U (u != 0) |
795 | #define H (h != 0) | |
796 | #define UI (ui != 0) | |
797 | #define I (intMaskBit != 0) | |
c906108c SS |
798 | |
799 | static int | |
a4f27e3e | 800 | mop (decoded_inst *code, int bsize, int sign) |
c906108c SS |
801 | { |
802 | int multiplier; | |
803 | int multiplicand; | |
804 | int result; | |
805 | int n, nz; | |
806 | ||
807 | if (sign) | |
808 | { | |
809 | multiplicand = | |
810 | bsize ? SEXTCHAR (GET_W_REG (code->dst.reg)) : | |
811 | SEXTSHORT (GET_W_REG (code->dst.reg)); | |
812 | multiplier = | |
813 | bsize ? SEXTCHAR (GET_B_REG (code->src.reg)) : | |
814 | SEXTSHORT (GET_W_REG (code->src.reg)); | |
815 | } | |
816 | else | |
817 | { | |
818 | multiplicand = bsize ? UEXTCHAR (GET_W_REG (code->dst.reg)) : | |
819 | UEXTSHORT (GET_W_REG (code->dst.reg)); | |
820 | multiplier = | |
821 | bsize ? UEXTCHAR (GET_B_REG (code->src.reg)) : | |
822 | UEXTSHORT (GET_W_REG (code->src.reg)); | |
823 | ||
824 | } | |
825 | result = multiplier * multiplicand; | |
826 | ||
827 | if (sign) | |
828 | { | |
829 | n = result & (bsize ? 0x8000 : 0x80000000); | |
830 | nz = result & (bsize ? 0xffff : 0xffffffff); | |
831 | } | |
832 | if (bsize) | |
833 | { | |
834 | SET_W_REG (code->dst.reg, result); | |
835 | } | |
836 | else | |
837 | { | |
838 | SET_L_REG (code->dst.reg, result); | |
839 | } | |
de9b1892 KH |
840 | #if 0 |
841 | return ((n == 1) << 1) | (nz == 1); | |
842 | #endif | |
c906108c SS |
843 | } |
844 | ||
845 | #define ONOT(name, how) \ | |
d1335144 | 846 | case O (name, SB): \ |
c906108c SS |
847 | { \ |
848 | int t; \ | |
849 | int hm = 0x80; \ | |
850 | rd = GET_B_REG (code->src.reg); \ | |
851 | how; \ | |
852 | goto shift8; \ | |
853 | } \ | |
d1335144 | 854 | case O (name, SW): \ |
c906108c SS |
855 | { \ |
856 | int t; \ | |
857 | int hm = 0x8000; \ | |
858 | rd = GET_W_REG (code->src.reg); \ | |
859 | how; \ | |
860 | goto shift16; \ | |
861 | } \ | |
d1335144 | 862 | case O (name, SL): \ |
c906108c SS |
863 | { \ |
864 | int t; \ | |
865 | int hm = 0x80000000; \ | |
866 | rd = GET_L_REG (code->src.reg); \ | |
867 | how; \ | |
868 | goto shift32; \ | |
869 | } | |
870 | ||
871 | #define OSHIFTS(name, how1, how2) \ | |
d1335144 | 872 | case O (name, SB): \ |
c906108c SS |
873 | { \ |
874 | int t; \ | |
875 | int hm = 0x80; \ | |
876 | rd = GET_B_REG (code->src.reg); \ | |
877 | if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \ | |
878 | { \ | |
879 | how1; \ | |
880 | } \ | |
881 | else \ | |
882 | { \ | |
883 | how2; \ | |
884 | } \ | |
885 | goto shift8; \ | |
886 | } \ | |
d1335144 | 887 | case O (name, SW): \ |
c906108c SS |
888 | { \ |
889 | int t; \ | |
890 | int hm = 0x8000; \ | |
891 | rd = GET_W_REG (code->src.reg); \ | |
892 | if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \ | |
893 | { \ | |
894 | how1; \ | |
895 | } \ | |
896 | else \ | |
897 | { \ | |
898 | how2; \ | |
899 | } \ | |
900 | goto shift16; \ | |
901 | } \ | |
d1335144 | 902 | case O (name, SL): \ |
c906108c SS |
903 | { \ |
904 | int t; \ | |
905 | int hm = 0x80000000; \ | |
906 | rd = GET_L_REG (code->src.reg); \ | |
907 | if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \ | |
908 | { \ | |
909 | how1; \ | |
910 | } \ | |
911 | else \ | |
912 | { \ | |
913 | how2; \ | |
914 | } \ | |
915 | goto shift32; \ | |
916 | } | |
917 | ||
918 | #define OBITOP(name,f, s, op) \ | |
d1335144 | 919 | case O (name, SB): \ |
c906108c SS |
920 | { \ |
921 | int m; \ | |
922 | int b; \ | |
923 | if (f) ea = fetch (&code->dst); \ | |
d1335144 | 924 | m=1<< fetch (&code->src); \ |
c906108c | 925 | op; \ |
d1335144 | 926 | if (s) store (&code->dst,ea); goto next; \ |
c906108c SS |
927 | } |
928 | ||
929 | int | |
837fd61c | 930 | sim_stop (SIM_DESC sd) |
c906108c SS |
931 | { |
932 | cpu.state = SIM_STATE_STOPPED; | |
933 | cpu.exception = SIGINT; | |
934 | return 1; | |
935 | } | |
936 | ||
6147b1f6 AV |
937 | #define R0_REGNUM 0 |
938 | #define R1_REGNUM 1 | |
939 | #define R2_REGNUM 2 | |
940 | #define R3_REGNUM 3 | |
941 | #define R4_REGNUM 4 | |
942 | #define R5_REGNUM 5 | |
943 | #define R6_REGNUM 6 | |
944 | #define R7_REGNUM 7 | |
945 | ||
946 | #define SP_REGNUM R7_REGNUM /* Contains address of top of stack */ | |
947 | #define FP_REGNUM R6_REGNUM /* Contains address of executing | |
948 | * stack frame */ | |
949 | ||
950 | #define CCR_REGNUM 8 /* Contains processor status */ | |
951 | #define PC_REGNUM 9 /* Contains program counter */ | |
952 | ||
953 | #define CYCLE_REGNUM 10 | |
954 | ||
955 | #define EXR_REGNUM 11 | |
956 | #define INST_REGNUM 12 | |
957 | #define TICK_REGNUM 13 | |
958 | ||
c906108c | 959 | void |
a4f27e3e | 960 | sim_resume (SIM_DESC sd, int step, int siggnal) |
c906108c SS |
961 | { |
962 | static int init1; | |
963 | int cycles = 0; | |
964 | int insts = 0; | |
965 | int tick_start = get_now (); | |
966 | void (*prev) (); | |
967 | int poll_count = 0; | |
968 | int res; | |
969 | int tmp; | |
970 | int rd; | |
971 | int ea; | |
972 | int bit; | |
973 | int pc; | |
f6225c96 | 974 | int c, nz, v, n, u, h, ui, intMaskBit; |
fc974602 | 975 | int trace, intMask; |
c906108c SS |
976 | int oldmask; |
977 | init_pointers (); | |
978 | ||
979 | prev = signal (SIGINT, control_c); | |
980 | ||
981 | if (step) | |
982 | { | |
983 | cpu.state = SIM_STATE_STOPPED; | |
984 | cpu.exception = SIGTRAP; | |
985 | } | |
986 | else | |
987 | { | |
988 | cpu.state = SIM_STATE_RUNNING; | |
989 | cpu.exception = 0; | |
990 | } | |
991 | ||
992 | pc = cpu.pc; | |
993 | ||
994 | /* The PC should never be odd. */ | |
995 | if (pc & 0x1) | |
996 | abort (); | |
997 | ||
998 | GETSR (); | |
fc974602 AV |
999 | GETEXR (); |
1000 | ||
c906108c SS |
1001 | oldmask = cpu.mask; |
1002 | if (!h8300hmode) | |
1003 | cpu.mask = 0xffff; | |
1004 | do | |
1005 | { | |
1006 | int cidx; | |
1007 | decoded_inst *code; | |
1008 | ||
1009 | top: | |
1010 | cidx = cpu.cache_idx[pc]; | |
1011 | code = cpu.cache + cidx; | |
1012 | ||
1013 | ||
1014 | #define ALUOP(STORE, NAME, HOW) \ | |
d0fe2f7e KH |
1015 | case O (NAME, SB): HOW; if (STORE) goto alu8; else goto just_flags_alu8; \ |
1016 | case O (NAME, SW): HOW; if (STORE) goto alu16; else goto just_flags_alu16; \ | |
1017 | case O (NAME, SL): HOW; if (STORE) goto alu32; else goto just_flags_alu32; | |
c906108c SS |
1018 | |
1019 | ||
d0fe2f7e KH |
1020 | #define LOGOP(NAME, HOW) \ |
1021 | case O (NAME, SB): HOW; goto log8; \ | |
1022 | case O (NAME, SW): HOW; goto log16; \ | |
1023 | case O (NAME, SL): HOW; goto log32; | |
c906108c SS |
1024 | |
1025 | ||
1026 | ||
1027 | #if ADEBUG | |
1028 | if (debug) | |
1029 | { | |
1030 | printf ("%x %d %s\n", pc, code->opcode, | |
1031 | code->op ? code->op->name : "**"); | |
1032 | } | |
1033 | cpu.stats[code->opcode]++; | |
1034 | ||
1035 | #endif | |
1036 | ||
3b02cf92 | 1037 | if (code->opcode) |
c3f4437e KH |
1038 | { |
1039 | cycles += code->cycles; | |
1040 | insts++; | |
1041 | } | |
3b02cf92 | 1042 | |
c906108c SS |
1043 | switch (code->opcode) |
1044 | { | |
1045 | case 0: | |
1046 | /* | |
1047 | * This opcode is a fake for when we get to an | |
1048 | * instruction which hasnt been compiled | |
1049 | */ | |
1050 | compile (pc); | |
1051 | goto top; | |
1052 | break; | |
1053 | ||
1054 | ||
1055 | case O (O_SUBX, SB): | |
1056 | rd = fetch (&code->dst); | |
1057 | ea = fetch (&code->src); | |
1058 | ea = -(ea + C); | |
1059 | res = rd + ea; | |
1060 | goto alu8; | |
1061 | ||
1062 | case O (O_ADDX, SB): | |
1063 | rd = fetch (&code->dst); | |
1064 | ea = fetch (&code->src); | |
1065 | ea = C + ea; | |
1066 | res = rd + ea; | |
1067 | goto alu8; | |
1068 | ||
d1335144 KH |
1069 | #define EA ea = fetch (&code->src); |
1070 | #define RD_EA ea = fetch (&code->src); rd = fetch (&code->dst); | |
c906108c SS |
1071 | |
1072 | ALUOP (1, O_SUB, RD_EA; | |
1073 | ea = -ea; | |
1074 | res = rd + ea); | |
1075 | ALUOP (1, O_NEG, EA; | |
1076 | ea = -ea; | |
1077 | rd = 0; | |
1078 | res = rd + ea); | |
1079 | ||
1080 | case O (O_ADD, SB): | |
1081 | rd = GET_B_REG (code->dst.reg); | |
1082 | ea = fetch (&code->src); | |
1083 | res = rd + ea; | |
1084 | goto alu8; | |
1085 | case O (O_ADD, SW): | |
1086 | rd = GET_W_REG (code->dst.reg); | |
1087 | ea = fetch (&code->src); | |
1088 | res = rd + ea; | |
1089 | goto alu16; | |
1090 | case O (O_ADD, SL): | |
1091 | rd = GET_L_REG (code->dst.reg); | |
1092 | ea = fetch (&code->src); | |
1093 | res = rd + ea; | |
1094 | goto alu32; | |
1095 | ||
1096 | ||
1097 | LOGOP (O_AND, RD_EA; | |
1098 | res = rd & ea); | |
1099 | ||
1100 | LOGOP (O_OR, RD_EA; | |
1101 | res = rd | ea); | |
1102 | ||
1103 | LOGOP (O_XOR, RD_EA; | |
1104 | res = rd ^ ea); | |
1105 | ||
1106 | ||
1107 | case O (O_MOV_TO_MEM, SB): | |
1108 | res = GET_B_REG (code->src.reg); | |
1109 | goto log8; | |
1110 | case O (O_MOV_TO_MEM, SW): | |
1111 | res = GET_W_REG (code->src.reg); | |
1112 | goto log16; | |
1113 | case O (O_MOV_TO_MEM, SL): | |
1114 | res = GET_L_REG (code->src.reg); | |
1115 | goto log32; | |
1116 | ||
1117 | ||
1118 | case O (O_MOV_TO_REG, SB): | |
1119 | res = fetch (&code->src); | |
1120 | SET_B_REG (code->dst.reg, res); | |
1121 | goto just_flags_log8; | |
1122 | case O (O_MOV_TO_REG, SW): | |
1123 | res = fetch (&code->src); | |
1124 | SET_W_REG (code->dst.reg, res); | |
1125 | goto just_flags_log16; | |
1126 | case O (O_MOV_TO_REG, SL): | |
1127 | res = fetch (&code->src); | |
1128 | SET_L_REG (code->dst.reg, res); | |
1129 | goto just_flags_log32; | |
1130 | ||
6147b1f6 AV |
1131 | case O (O_EEPMOV, SB): |
1132 | case O (O_EEPMOV, SW): | |
d0fe2f7e | 1133 | if (h8300hmode || h8300smode) |
c3f4437e | 1134 | { |
d0fe2f7e KH |
1135 | register unsigned char *_src, *_dst; |
1136 | unsigned int count = ((code->opcode == O (O_EEPMOV, SW)) | |
1137 | ? cpu.regs[R4_REGNUM] & 0xffff | |
1138 | : cpu.regs[R4_REGNUM] & 0xff); | |
1139 | ||
1140 | _src = (cpu.regs[R5_REGNUM] < memory_size | |
1141 | ? cpu.memory + cpu.regs[R5_REGNUM] | |
1142 | : cpu.eightbit + (cpu.regs[R5_REGNUM] & 0xff)); | |
1143 | if ((_src + count) >= (cpu.memory + memory_size)) | |
c3f4437e | 1144 | { |
d0fe2f7e | 1145 | if ((_src + count) >= (cpu.eightbit + 0x100)) |
c3f4437e KH |
1146 | goto illegal; |
1147 | } | |
d0fe2f7e KH |
1148 | _dst = (cpu.regs[R6_REGNUM] < memory_size |
1149 | ? cpu.memory + cpu.regs[R6_REGNUM] | |
1150 | : cpu.eightbit + (cpu.regs[R6_REGNUM] & 0xff)); | |
1151 | if ((_dst + count) >= (cpu.memory + memory_size)) | |
c3f4437e | 1152 | { |
d0fe2f7e | 1153 | if ((_dst + count) >= (cpu.eightbit + 0x100)) |
c3f4437e KH |
1154 | goto illegal; |
1155 | } | |
d0fe2f7e | 1156 | memcpy (_dst, _src, count); |
c3f4437e | 1157 | |
d0fe2f7e KH |
1158 | cpu.regs[R5_REGNUM] += count; |
1159 | cpu.regs[R6_REGNUM] += count; | |
1160 | cpu.regs[R4_REGNUM] &= ((code->opcode == O (O_EEPMOV, SW)) | |
1161 | ? (~0xffff) : (~0xff)); | |
1162 | cycles += 2 * count; | |
c3f4437e KH |
1163 | goto next; |
1164 | } | |
1165 | goto illegal; | |
c906108c SS |
1166 | |
1167 | case O (O_ADDS, SL): | |
1168 | SET_L_REG (code->dst.reg, | |
1169 | GET_L_REG (code->dst.reg) | |
1170 | + code->src.literal); | |
1171 | ||
1172 | goto next; | |
1173 | ||
1174 | case O (O_SUBS, SL): | |
1175 | SET_L_REG (code->dst.reg, | |
1176 | GET_L_REG (code->dst.reg) | |
1177 | - code->src.literal); | |
1178 | goto next; | |
1179 | ||
1180 | case O (O_CMP, SB): | |
1181 | rd = fetch (&code->dst); | |
1182 | ea = fetch (&code->src); | |
1183 | ea = -ea; | |
1184 | res = rd + ea; | |
1185 | goto just_flags_alu8; | |
1186 | ||
1187 | case O (O_CMP, SW): | |
1188 | rd = fetch (&code->dst); | |
1189 | ea = fetch (&code->src); | |
1190 | ea = -ea; | |
1191 | res = rd + ea; | |
1192 | goto just_flags_alu16; | |
1193 | ||
1194 | case O (O_CMP, SL): | |
1195 | rd = fetch (&code->dst); | |
1196 | ea = fetch (&code->src); | |
1197 | ea = -ea; | |
1198 | res = rd + ea; | |
1199 | goto just_flags_alu32; | |
1200 | ||
1201 | ||
1202 | case O (O_DEC, SB): | |
1203 | rd = GET_B_REG (code->src.reg); | |
1204 | ea = -1; | |
1205 | res = rd + ea; | |
1206 | SET_B_REG (code->src.reg, res); | |
1207 | goto just_flags_inc8; | |
1208 | ||
1209 | case O (O_DEC, SW): | |
1210 | rd = GET_W_REG (code->dst.reg); | |
1211 | ea = -code->src.literal; | |
1212 | res = rd + ea; | |
1213 | SET_W_REG (code->dst.reg, res); | |
1214 | goto just_flags_inc16; | |
1215 | ||
1216 | case O (O_DEC, SL): | |
1217 | rd = GET_L_REG (code->dst.reg); | |
1218 | ea = -code->src.literal; | |
1219 | res = rd + ea; | |
1220 | SET_L_REG (code->dst.reg, res); | |
1221 | goto just_flags_inc32; | |
1222 | ||
1223 | ||
1224 | case O (O_INC, SB): | |
1225 | rd = GET_B_REG (code->src.reg); | |
1226 | ea = 1; | |
1227 | res = rd + ea; | |
1228 | SET_B_REG (code->src.reg, res); | |
1229 | goto just_flags_inc8; | |
1230 | ||
1231 | case O (O_INC, SW): | |
1232 | rd = GET_W_REG (code->dst.reg); | |
1233 | ea = code->src.literal; | |
1234 | res = rd + ea; | |
1235 | SET_W_REG (code->dst.reg, res); | |
1236 | goto just_flags_inc16; | |
1237 | ||
1238 | case O (O_INC, SL): | |
1239 | rd = GET_L_REG (code->dst.reg); | |
1240 | ea = code->src.literal; | |
1241 | res = rd + ea; | |
1242 | SET_L_REG (code->dst.reg, res); | |
1243 | goto just_flags_inc32; | |
1244 | ||
c906108c | 1245 | #define GET_CCR(x) BUILDSR();x = cpu.ccr |
d1335144 | 1246 | #define GET_EXR(x) BUILDEXR ();x = cpu.exr |
c906108c | 1247 | |
6147b1f6 AV |
1248 | case O (O_LDC, SB): |
1249 | case O (O_LDC, SW): | |
d1335144 | 1250 | res = fetch (&code->src); |
6147b1f6 AV |
1251 | goto setc; |
1252 | case O (O_STC, SB): | |
1253 | case O (O_STC, SW): | |
d1335144 | 1254 | if (code->src.type == OP_CCR) |
c3f4437e | 1255 | { |
d1335144 | 1256 | GET_CCR (res); |
c3f4437e | 1257 | } |
d1335144 | 1258 | else if (code->src.type == OP_EXR && h8300smode) |
c3f4437e | 1259 | { |
d1335144 | 1260 | GET_EXR (res); |
c3f4437e KH |
1261 | } |
1262 | else | |
6147b1f6 AV |
1263 | goto illegal; |
1264 | store (&code->dst, res); | |
1265 | goto next; | |
1266 | ||
c906108c | 1267 | case O (O_ANDC, SB): |
d1335144 | 1268 | if (code->dst.type == OP_CCR) |
c3f4437e KH |
1269 | { |
1270 | GET_CCR (rd); | |
1271 | } | |
d1335144 | 1272 | else if (code->dst.type == OP_EXR && h8300smode) |
c3f4437e KH |
1273 | { |
1274 | GET_EXR (rd); | |
1275 | } | |
1276 | else | |
fc974602 | 1277 | goto illegal; |
c906108c SS |
1278 | ea = code->src.literal; |
1279 | res = rd & ea; | |
1280 | goto setc; | |
1281 | ||
1282 | case O (O_ORC, SB): | |
d1335144 | 1283 | if (code->dst.type == OP_CCR) |
c3f4437e KH |
1284 | { |
1285 | GET_CCR (rd); | |
1286 | } | |
d1335144 | 1287 | else if (code->dst.type == OP_EXR && h8300smode) |
c3f4437e KH |
1288 | { |
1289 | GET_EXR (rd); | |
1290 | } | |
1291 | else | |
fc974602 | 1292 | goto illegal; |
c906108c SS |
1293 | ea = code->src.literal; |
1294 | res = rd | ea; | |
1295 | goto setc; | |
1296 | ||
1297 | case O (O_XORC, SB): | |
d1335144 | 1298 | if (code->dst.type == OP_CCR) |
c3f4437e KH |
1299 | { |
1300 | GET_CCR (rd); | |
1301 | } | |
d1335144 | 1302 | else if (code->dst.type == OP_EXR && h8300smode) |
c3f4437e KH |
1303 | { |
1304 | GET_EXR (rd); | |
1305 | } | |
1306 | else | |
fc974602 | 1307 | goto illegal; |
c906108c SS |
1308 | ea = code->src.literal; |
1309 | res = rd ^ ea; | |
1310 | goto setc; | |
1311 | ||
1312 | ||
1313 | case O (O_BRA, SB): | |
1314 | if (1) | |
1315 | goto condtrue; | |
1316 | goto next; | |
1317 | ||
1318 | case O (O_BRN, SB): | |
1319 | if (0) | |
1320 | goto condtrue; | |
1321 | goto next; | |
1322 | ||
1323 | case O (O_BHI, SB): | |
1324 | if ((C || Z) == 0) | |
1325 | goto condtrue; | |
1326 | goto next; | |
1327 | ||
1328 | ||
1329 | case O (O_BLS, SB): | |
1330 | if ((C || Z)) | |
1331 | goto condtrue; | |
1332 | goto next; | |
1333 | ||
1334 | case O (O_BCS, SB): | |
1335 | if ((C == 1)) | |
1336 | goto condtrue; | |
1337 | goto next; | |
1338 | ||
1339 | case O (O_BCC, SB): | |
1340 | if ((C == 0)) | |
1341 | goto condtrue; | |
1342 | goto next; | |
1343 | ||
1344 | case O (O_BEQ, SB): | |
1345 | if (Z) | |
1346 | goto condtrue; | |
1347 | goto next; | |
1348 | case O (O_BGT, SB): | |
1349 | if (((Z || (N ^ V)) == 0)) | |
1350 | goto condtrue; | |
1351 | goto next; | |
1352 | ||
1353 | ||
1354 | case O (O_BLE, SB): | |
1355 | if (((Z || (N ^ V)) == 1)) | |
1356 | goto condtrue; | |
1357 | goto next; | |
1358 | ||
1359 | case O (O_BGE, SB): | |
1360 | if ((N ^ V) == 0) | |
1361 | goto condtrue; | |
1362 | goto next; | |
1363 | case O (O_BLT, SB): | |
1364 | if ((N ^ V)) | |
1365 | goto condtrue; | |
1366 | goto next; | |
1367 | case O (O_BMI, SB): | |
1368 | if ((N)) | |
1369 | goto condtrue; | |
1370 | goto next; | |
1371 | case O (O_BNE, SB): | |
1372 | if ((Z == 0)) | |
1373 | goto condtrue; | |
1374 | goto next; | |
1375 | ||
1376 | case O (O_BPL, SB): | |
1377 | if (N == 0) | |
1378 | goto condtrue; | |
1379 | goto next; | |
1380 | case O (O_BVC, SB): | |
1381 | if ((V == 0)) | |
1382 | goto condtrue; | |
1383 | goto next; | |
1384 | case O (O_BVS, SB): | |
1385 | if ((V == 1)) | |
1386 | goto condtrue; | |
1387 | goto next; | |
1388 | ||
1389 | case O (O_SYSCALL, SB): | |
1390 | { | |
1391 | char c = cpu.regs[2]; | |
1392 | sim_callback->write_stdout (sim_callback, &c, 1); | |
1393 | } | |
1394 | goto next; | |
1395 | ||
1396 | ONOT (O_NOT, rd = ~rd; v = 0;); | |
1397 | OSHIFTS (O_SHLL, | |
1398 | c = rd & hm; v = 0; rd <<= 1, | |
1399 | c = rd & (hm >> 1); v = 0; rd <<= 2); | |
1400 | OSHIFTS (O_SHLR, | |
1401 | c = rd & 1; v = 0; rd = (unsigned int) rd >> 1, | |
1402 | c = rd & 2; v = 0; rd = (unsigned int) rd >> 2); | |
1403 | OSHIFTS (O_SHAL, | |
1404 | c = rd & hm; v = (rd & hm) != ((rd & (hm >> 1)) << 1); rd <<= 1, | |
1405 | c = rd & (hm >> 1); v = (rd & (hm >> 1)) != ((rd & (hm >> 2)) << 2); rd <<= 2); | |
1406 | OSHIFTS (O_SHAR, | |
1407 | t = rd & hm; c = rd & 1; v = 0; rd >>= 1; rd |= t, | |
d1335144 | 1408 | t = rd & hm; c = rd & 2; v = 0; rd >>= 2; rd |= t | t >> 1); |
c906108c SS |
1409 | OSHIFTS (O_ROTL, |
1410 | c = rd & hm; v = 0; rd <<= 1; rd |= C, | |
1411 | c = rd & hm; v = 0; rd <<= 1; rd |= C; c = rd & hm; rd <<= 1; rd |= C); | |
1412 | OSHIFTS (O_ROTR, | |
1413 | c = rd & 1; v = 0; rd = (unsigned int) rd >> 1; if (c) rd |= hm, | |
1414 | c = rd & 1; v = 0; rd = (unsigned int) rd >> 1; if (c) rd |= hm; c = rd & 1; rd = (unsigned int) rd >> 1; if (c) rd |= hm); | |
1415 | OSHIFTS (O_ROTXL, | |
1416 | t = rd & hm; rd <<= 1; rd |= C; c = t; v = 0, | |
1417 | t = rd & hm; rd <<= 1; rd |= C; c = t; v = 0; t = rd & hm; rd <<= 1; rd |= C; c = t); | |
1418 | OSHIFTS (O_ROTXR, | |
1419 | t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd |= hm; c = t; v = 0, | |
1420 | t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd |= hm; c = t; v = 0; t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd |= hm; c = t); | |
1421 | ||
1422 | case O (O_JMP, SB): | |
1423 | { | |
1424 | pc = fetch (&code->src); | |
1425 | goto end; | |
1426 | ||
1427 | } | |
1428 | ||
1429 | case O (O_JSR, SB): | |
1430 | { | |
1431 | int tmp; | |
1432 | pc = fetch (&code->src); | |
1433 | call: | |
1434 | tmp = cpu.regs[7]; | |
1435 | ||
1436 | if (h8300hmode) | |
1437 | { | |
1438 | tmp -= 4; | |
1439 | SET_MEMORY_L (tmp, code->next_pc); | |
1440 | } | |
1441 | else | |
1442 | { | |
1443 | tmp -= 2; | |
1444 | SET_MEMORY_W (tmp, code->next_pc); | |
1445 | } | |
1446 | cpu.regs[7] = tmp; | |
1447 | ||
1448 | goto end; | |
1449 | } | |
1450 | case O (O_BSR, SB): | |
1451 | pc = code->src.literal; | |
1452 | goto call; | |
1453 | ||
1454 | case O (O_RTS, SN): | |
1455 | { | |
1456 | int tmp; | |
1457 | ||
1458 | tmp = cpu.regs[7]; | |
1459 | ||
1460 | if (h8300hmode) | |
1461 | { | |
1462 | pc = GET_MEMORY_L (tmp); | |
1463 | tmp += 4; | |
1464 | } | |
1465 | else | |
1466 | { | |
1467 | pc = GET_MEMORY_W (tmp); | |
1468 | tmp += 2; | |
1469 | } | |
1470 | ||
1471 | cpu.regs[7] = tmp; | |
1472 | goto end; | |
1473 | } | |
1474 | ||
1475 | case O (O_ILL, SB): | |
1476 | cpu.state = SIM_STATE_STOPPED; | |
1477 | cpu.exception = SIGILL; | |
1478 | goto end; | |
1479 | case O (O_SLEEP, SN): | |
c906108c SS |
1480 | /* FIXME: Doesn't this break for breakpoints when r0 |
1481 | contains just the right (er, wrong) value? */ | |
1482 | cpu.state = SIM_STATE_STOPPED; | |
97ee9e5a FCE |
1483 | /* The format of r0 is defined by target newlib. Expand |
1484 | the macros here instead of looking for .../sys/wait.h. */ | |
1485 | #define SIM_WIFEXITED(v) (((v) & 0xff) == 0) | |
1486 | #define SIM_WIFSIGNALED(v) (((v) & 0x7f) > 0 && (((v) & 0x7f) < 0x7f)) | |
c3f4437e | 1487 | if (! SIM_WIFEXITED (cpu.regs[0]) && SIM_WIFSIGNALED (cpu.regs[0])) |
c906108c SS |
1488 | cpu.exception = SIGILL; |
1489 | else | |
1490 | cpu.exception = SIGTRAP; | |
c906108c SS |
1491 | goto end; |
1492 | case O (O_BPT, SN): | |
1493 | cpu.state = SIM_STATE_STOPPED; | |
1494 | cpu.exception = SIGTRAP; | |
1495 | goto end; | |
1496 | ||
1497 | OBITOP (O_BNOT, 1, 1, ea ^= m); | |
1498 | OBITOP (O_BTST, 1, 0, nz = ea & m); | |
1499 | OBITOP (O_BCLR, 1, 1, ea &= ~m); | |
c3f4437e | 1500 | OBITOP (O_BSET, 1, 1, ea |= m); |
c906108c SS |
1501 | OBITOP (O_BLD, 1, 0, c = ea & m); |
1502 | OBITOP (O_BILD, 1, 0, c = !(ea & m)); | |
1503 | OBITOP (O_BST, 1, 1, ea &= ~m; | |
1504 | if (C) ea |= m); | |
1505 | OBITOP (O_BIST, 1, 1, ea &= ~m; | |
1506 | if (!C) ea |= m); | |
1507 | OBITOP (O_BAND, 1, 0, c = (ea & m) && C); | |
1508 | OBITOP (O_BIAND, 1, 0, c = !(ea & m) && C); | |
1509 | OBITOP (O_BOR, 1, 0, c = (ea & m) || C); | |
1510 | OBITOP (O_BIOR, 1, 0, c = !(ea & m) || C); | |
ad4cda16 | 1511 | OBITOP (O_BXOR, 1, 0, c = ((ea & m) != 0) != C); |
c906108c SS |
1512 | OBITOP (O_BIXOR, 1, 0, c = !(ea & m) != C); |
1513 | ||
de9b1892 KH |
1514 | #define MOP(bsize, signed) \ |
1515 | mop (code, bsize, signed); \ | |
1516 | goto next; | |
c906108c SS |
1517 | |
1518 | case O (O_MULS, SB): | |
1519 | MOP (1, 1); | |
1520 | break; | |
1521 | case O (O_MULS, SW): | |
1522 | MOP (0, 1); | |
1523 | break; | |
1524 | case O (O_MULU, SB): | |
1525 | MOP (1, 0); | |
1526 | break; | |
1527 | case O (O_MULU, SW): | |
1528 | MOP (0, 0); | |
1529 | break; | |
1530 | ||
6147b1f6 | 1531 | case O (O_TAS, SB): |
d1335144 | 1532 | if (!h8300smode || code->src.type != X (OP_REG, SL)) |
c3f4437e | 1533 | goto illegal; |
d1335144 | 1534 | switch (code->src.reg) |
c3f4437e KH |
1535 | { |
1536 | case R0_REGNUM: | |
1537 | case R1_REGNUM: | |
1538 | case R4_REGNUM: | |
1539 | case R5_REGNUM: | |
1540 | break; | |
1541 | default: | |
1542 | goto illegal; | |
1543 | } | |
1544 | res = fetch (&code->src); | |
d0fe2f7e | 1545 | store (&code->src, res | 0x80); |
6147b1f6 | 1546 | goto just_flags_log8; |
c906108c SS |
1547 | |
1548 | case O (O_DIVU, SB): | |
1549 | { | |
1550 | rd = GET_W_REG (code->dst.reg); | |
1551 | ea = GET_B_REG (code->src.reg); | |
1552 | if (ea) | |
1553 | { | |
de9b1892 KH |
1554 | tmp = (unsigned) rd % ea; |
1555 | rd = (unsigned) rd / ea; | |
c906108c SS |
1556 | } |
1557 | SET_W_REG (code->dst.reg, (rd & 0xff) | (tmp << 8)); | |
1558 | n = ea & 0x80; | |
1559 | nz = ea & 0xff; | |
1560 | ||
1561 | goto next; | |
1562 | } | |
1563 | case O (O_DIVU, SW): | |
1564 | { | |
1565 | rd = GET_L_REG (code->dst.reg); | |
1566 | ea = GET_W_REG (code->src.reg); | |
1567 | n = ea & 0x8000; | |
1568 | nz = ea & 0xffff; | |
1569 | if (ea) | |
1570 | { | |
de9b1892 KH |
1571 | tmp = (unsigned) rd % ea; |
1572 | rd = (unsigned) rd / ea; | |
c906108c SS |
1573 | } |
1574 | SET_L_REG (code->dst.reg, (rd & 0xffff) | (tmp << 16)); | |
1575 | goto next; | |
1576 | } | |
1577 | ||
1578 | case O (O_DIVS, SB): | |
1579 | { | |
1580 | ||
1581 | rd = SEXTSHORT (GET_W_REG (code->dst.reg)); | |
1582 | ea = SEXTCHAR (GET_B_REG (code->src.reg)); | |
1583 | if (ea) | |
1584 | { | |
1585 | tmp = (int) rd % (int) ea; | |
1586 | rd = (int) rd / (int) ea; | |
1587 | n = rd & 0x8000; | |
1588 | nz = 1; | |
1589 | } | |
1590 | else | |
1591 | nz = 0; | |
1592 | SET_W_REG (code->dst.reg, (rd & 0xff) | (tmp << 8)); | |
1593 | goto next; | |
1594 | } | |
1595 | case O (O_DIVS, SW): | |
1596 | { | |
1597 | rd = GET_L_REG (code->dst.reg); | |
1598 | ea = SEXTSHORT (GET_W_REG (code->src.reg)); | |
1599 | if (ea) | |
1600 | { | |
1601 | tmp = (int) rd % (int) ea; | |
1602 | rd = (int) rd / (int) ea; | |
1603 | n = rd & 0x80000000; | |
1604 | nz = 1; | |
1605 | } | |
1606 | else | |
1607 | nz = 0; | |
1608 | SET_L_REG (code->dst.reg, (rd & 0xffff) | (tmp << 16)); | |
1609 | goto next; | |
1610 | } | |
1611 | case O (O_EXTS, SW): | |
ec38ce99 | 1612 | rd = GET_W_REG (code->src.reg) & 0xff; /* Yes, src, not dst. */ |
c906108c SS |
1613 | ea = rd & 0x80 ? -256 : 0; |
1614 | res = rd + ea; | |
1615 | goto log16; | |
1616 | case O (O_EXTS, SL): | |
1617 | rd = GET_W_REG (code->src.reg) & 0xffff; | |
1618 | ea = rd & 0x8000 ? -65536 : 0; | |
1619 | res = rd + ea; | |
1620 | goto log32; | |
1621 | case O (O_EXTU, SW): | |
ec38ce99 | 1622 | rd = GET_W_REG (code->src.reg) & 0xff; |
c906108c SS |
1623 | ea = 0; |
1624 | res = rd + ea; | |
1625 | goto log16; | |
1626 | case O (O_EXTU, SL): | |
1627 | rd = GET_W_REG (code->src.reg) & 0xffff; | |
1628 | ea = 0; | |
1629 | res = rd + ea; | |
1630 | goto log32; | |
1631 | ||
1632 | case O (O_NOP, SN): | |
1633 | goto next; | |
1634 | ||
1635 | case O (O_STM, SL): | |
1636 | { | |
1637 | int nregs, firstreg, i; | |
1638 | ||
1639 | nregs = GET_MEMORY_B (pc + 1); | |
1640 | nregs >>= 4; | |
1641 | nregs &= 0xf; | |
1642 | firstreg = GET_MEMORY_B (pc + 3); | |
1643 | firstreg &= 0xf; | |
1644 | for (i = firstreg; i <= firstreg + nregs; i++) | |
1645 | { | |
1646 | cpu.regs[7] -= 4; | |
1647 | SET_MEMORY_L (cpu.regs[7], cpu.regs[i]); | |
1648 | } | |
1649 | } | |
1650 | goto next; | |
1651 | ||
1652 | case O (O_LDM, SL): | |
1653 | { | |
1654 | int nregs, firstreg, i; | |
1655 | ||
1656 | nregs = GET_MEMORY_B (pc + 1); | |
1657 | nregs >>= 4; | |
1658 | nregs &= 0xf; | |
1659 | firstreg = GET_MEMORY_B (pc + 3); | |
1660 | firstreg &= 0xf; | |
1661 | for (i = firstreg; i >= firstreg - nregs; i--) | |
1662 | { | |
1663 | cpu.regs[i] = GET_MEMORY_L (cpu.regs[7]); | |
1664 | cpu.regs[7] += 4; | |
1665 | } | |
1666 | } | |
1667 | goto next; | |
1668 | ||
1669 | default: | |
d0fe2f7e | 1670 | illegal: |
c906108c SS |
1671 | cpu.state = SIM_STATE_STOPPED; |
1672 | cpu.exception = SIGILL; | |
1673 | goto end; | |
1674 | ||
1675 | } | |
1676 | abort (); | |
1677 | ||
1678 | setc: | |
d1335144 | 1679 | if (code->dst.type == OP_CCR) |
c3f4437e KH |
1680 | { |
1681 | cpu.ccr = res; | |
1682 | GETSR (); | |
1683 | } | |
d1335144 | 1684 | else if (code->dst.type == OP_EXR && h8300smode) |
c3f4437e KH |
1685 | { |
1686 | cpu.exr = res; | |
1687 | GETEXR (); | |
1688 | } | |
fc974602 | 1689 | else |
c3f4437e | 1690 | goto illegal; |
fc974602 | 1691 | |
c906108c SS |
1692 | goto next; |
1693 | ||
1694 | condtrue: | |
1695 | /* When a branch works */ | |
1696 | pc = code->src.literal; | |
1697 | goto end; | |
1698 | ||
1699 | /* Set the cond codes from res */ | |
1700 | bitop: | |
1701 | ||
1702 | /* Set the flags after an 8 bit inc/dec operation */ | |
1703 | just_flags_inc8: | |
1704 | n = res & 0x80; | |
1705 | nz = res & 0xff; | |
1706 | v = (rd & 0x7f) == 0x7f; | |
1707 | goto next; | |
1708 | ||
1709 | ||
1710 | /* Set the flags after an 16 bit inc/dec operation */ | |
1711 | just_flags_inc16: | |
1712 | n = res & 0x8000; | |
1713 | nz = res & 0xffff; | |
1714 | v = (rd & 0x7fff) == 0x7fff; | |
1715 | goto next; | |
1716 | ||
1717 | ||
1718 | /* Set the flags after an 32 bit inc/dec operation */ | |
1719 | just_flags_inc32: | |
1720 | n = res & 0x80000000; | |
1721 | nz = res & 0xffffffff; | |
1722 | v = (rd & 0x7fffffff) == 0x7fffffff; | |
1723 | goto next; | |
1724 | ||
1725 | ||
1726 | shift8: | |
1727 | /* Set flags after an 8 bit shift op, carry,overflow set in insn */ | |
1728 | n = (rd & 0x80); | |
1729 | nz = rd & 0xff; | |
1730 | SET_B_REG (code->src.reg, rd); | |
1731 | goto next; | |
1732 | ||
1733 | shift16: | |
1734 | /* Set flags after an 16 bit shift op, carry,overflow set in insn */ | |
1735 | n = (rd & 0x8000); | |
1736 | nz = rd & 0xffff; | |
1737 | SET_W_REG (code->src.reg, rd); | |
1738 | goto next; | |
1739 | ||
1740 | shift32: | |
1741 | /* Set flags after an 32 bit shift op, carry,overflow set in insn */ | |
1742 | n = (rd & 0x80000000); | |
1743 | nz = rd & 0xffffffff; | |
1744 | SET_L_REG (code->src.reg, rd); | |
1745 | goto next; | |
1746 | ||
1747 | log32: | |
1748 | store (&code->dst, res); | |
1749 | just_flags_log32: | |
1750 | /* flags after a 32bit logical operation */ | |
1751 | n = res & 0x80000000; | |
1752 | nz = res & 0xffffffff; | |
1753 | v = 0; | |
1754 | goto next; | |
1755 | ||
1756 | log16: | |
1757 | store (&code->dst, res); | |
1758 | just_flags_log16: | |
1759 | /* flags after a 16bit logical operation */ | |
1760 | n = res & 0x8000; | |
1761 | nz = res & 0xffff; | |
1762 | v = 0; | |
1763 | goto next; | |
1764 | ||
1765 | ||
1766 | log8: | |
1767 | store (&code->dst, res); | |
1768 | just_flags_log8: | |
1769 | n = res & 0x80; | |
1770 | nz = res & 0xff; | |
1771 | v = 0; | |
1772 | goto next; | |
1773 | ||
1774 | alu8: | |
1775 | SET_B_REG (code->dst.reg, res); | |
1776 | just_flags_alu8: | |
1777 | n = res & 0x80; | |
1778 | nz = res & 0xff; | |
1779 | c = (res & 0x100); | |
1780 | switch (code->opcode / 4) | |
1781 | { | |
1782 | case O_ADD: | |
1783 | v = ((rd & 0x80) == (ea & 0x80) | |
1784 | && (rd & 0x80) != (res & 0x80)); | |
1785 | break; | |
1786 | case O_SUB: | |
1787 | case O_CMP: | |
1788 | v = ((rd & 0x80) != (-ea & 0x80) | |
1789 | && (rd & 0x80) != (res & 0x80)); | |
1790 | break; | |
1791 | case O_NEG: | |
1792 | v = (rd == 0x80); | |
1793 | break; | |
1794 | } | |
1795 | goto next; | |
1796 | ||
1797 | alu16: | |
1798 | SET_W_REG (code->dst.reg, res); | |
1799 | just_flags_alu16: | |
1800 | n = res & 0x8000; | |
1801 | nz = res & 0xffff; | |
1802 | c = (res & 0x10000); | |
1803 | switch (code->opcode / 4) | |
1804 | { | |
1805 | case O_ADD: | |
1806 | v = ((rd & 0x8000) == (ea & 0x8000) | |
1807 | && (rd & 0x8000) != (res & 0x8000)); | |
1808 | break; | |
1809 | case O_SUB: | |
1810 | case O_CMP: | |
1811 | v = ((rd & 0x8000) != (-ea & 0x8000) | |
1812 | && (rd & 0x8000) != (res & 0x8000)); | |
1813 | break; | |
1814 | case O_NEG: | |
1815 | v = (rd == 0x8000); | |
1816 | break; | |
1817 | } | |
1818 | goto next; | |
1819 | ||
1820 | alu32: | |
1821 | SET_L_REG (code->dst.reg, res); | |
1822 | just_flags_alu32: | |
1823 | n = res & 0x80000000; | |
1824 | nz = res & 0xffffffff; | |
1825 | switch (code->opcode / 4) | |
1826 | { | |
1827 | case O_ADD: | |
1828 | v = ((rd & 0x80000000) == (ea & 0x80000000) | |
1829 | && (rd & 0x80000000) != (res & 0x80000000)); | |
1830 | c = ((unsigned) res < (unsigned) rd) || ((unsigned) res < (unsigned) ea); | |
1831 | break; | |
1832 | case O_SUB: | |
1833 | case O_CMP: | |
1834 | v = ((rd & 0x80000000) != (-ea & 0x80000000) | |
1835 | && (rd & 0x80000000) != (res & 0x80000000)); | |
1836 | c = (unsigned) rd < (unsigned) -ea; | |
1837 | break; | |
1838 | case O_NEG: | |
1839 | v = (rd == 0x80000000); | |
1840 | c = res != 0; | |
1841 | break; | |
1842 | } | |
1843 | goto next; | |
1844 | ||
1845 | next:; | |
1846 | pc = code->next_pc; | |
1847 | ||
1848 | end: | |
1849 | ; | |
de9b1892 KH |
1850 | #if 0 |
1851 | if (cpu.regs[8]) | |
1852 | abort (); | |
1853 | #endif | |
c906108c SS |
1854 | |
1855 | if (--poll_count < 0) | |
1856 | { | |
7a292a7a | 1857 | poll_count = POLL_QUIT_INTERVAL; |
c906108c SS |
1858 | if ((*sim_callback->poll_quit) != NULL |
1859 | && (*sim_callback->poll_quit) (sim_callback)) | |
1860 | sim_stop (sd); | |
1861 | } | |
1862 | ||
1863 | } | |
1864 | while (cpu.state == SIM_STATE_RUNNING); | |
1865 | cpu.ticks += get_now () - tick_start; | |
1866 | cpu.cycles += cycles; | |
1867 | cpu.insts += insts; | |
de9b1892 | 1868 | |
c906108c SS |
1869 | cpu.pc = pc; |
1870 | BUILDSR (); | |
d1335144 | 1871 | BUILDEXR (); |
c906108c SS |
1872 | cpu.mask = oldmask; |
1873 | signal (SIGINT, prev); | |
1874 | } | |
1875 | ||
1876 | int | |
a4f27e3e | 1877 | sim_trace (SIM_DESC sd) |
c906108c | 1878 | { |
2ea716f6 | 1879 | /* FIXME: Unfinished. */ |
c906108c SS |
1880 | abort (); |
1881 | } | |
1882 | ||
1883 | int | |
a4f27e3e | 1884 | sim_write (SIM_DESC sd, SIM_ADDR addr, unsigned char *buffer, int size) |
c906108c SS |
1885 | { |
1886 | int i; | |
1887 | ||
1888 | init_pointers (); | |
1889 | if (addr < 0) | |
1890 | return 0; | |
1891 | for (i = 0; i < size; i++) | |
1892 | { | |
1893 | if (addr < memory_size) | |
1894 | { | |
1895 | cpu.memory[addr + i] = buffer[i]; | |
1896 | cpu.cache_idx[addr + i] = 0; | |
1897 | } | |
1898 | else | |
1899 | cpu.eightbit[(addr + i) & 0xff] = buffer[i]; | |
1900 | } | |
1901 | return size; | |
1902 | } | |
1903 | ||
1904 | int | |
a4f27e3e | 1905 | sim_read (SIM_DESC sd, SIM_ADDR addr, unsigned char *buffer, int size) |
c906108c SS |
1906 | { |
1907 | init_pointers (); | |
1908 | if (addr < 0) | |
1909 | return 0; | |
1910 | if (addr < memory_size) | |
1911 | memcpy (buffer, cpu.memory + addr, size); | |
1912 | else | |
1913 | memcpy (buffer, cpu.eightbit + (addr & 0xff), size); | |
1914 | return size; | |
1915 | } | |
1916 | ||
1917 | ||
c906108c | 1918 | int |
a4f27e3e | 1919 | sim_store_register (SIM_DESC sd, int rn, unsigned char *value, int length) |
c906108c SS |
1920 | { |
1921 | int longval; | |
1922 | int shortval; | |
1923 | int intval; | |
1924 | longval = (value[0] << 24) | (value[1] << 16) | (value[2] << 8) | value[3]; | |
1925 | shortval = (value[0] << 8) | (value[1]); | |
1926 | intval = h8300hmode ? longval : shortval; | |
1927 | ||
1928 | init_pointers (); | |
1929 | switch (rn) | |
1930 | { | |
1931 | case PC_REGNUM: | |
1932 | cpu.pc = intval; | |
1933 | break; | |
1934 | default: | |
1935 | abort (); | |
1936 | case R0_REGNUM: | |
1937 | case R1_REGNUM: | |
1938 | case R2_REGNUM: | |
1939 | case R3_REGNUM: | |
1940 | case R4_REGNUM: | |
1941 | case R5_REGNUM: | |
1942 | case R6_REGNUM: | |
1943 | case R7_REGNUM: | |
1944 | cpu.regs[rn] = intval; | |
1945 | break; | |
1946 | case CCR_REGNUM: | |
1947 | cpu.ccr = intval; | |
1948 | break; | |
fc974602 AV |
1949 | case EXR_REGNUM: |
1950 | cpu.exr = intval; | |
1951 | break; | |
c906108c SS |
1952 | case CYCLE_REGNUM: |
1953 | cpu.cycles = longval; | |
1954 | break; | |
1955 | ||
1956 | case INST_REGNUM: | |
1957 | cpu.insts = longval; | |
1958 | break; | |
1959 | ||
1960 | case TICK_REGNUM: | |
1961 | cpu.ticks = longval; | |
1962 | break; | |
1963 | } | |
1964 | return -1; | |
1965 | } | |
1966 | ||
1967 | int | |
a4f27e3e | 1968 | sim_fetch_register (SIM_DESC sd, int rn, unsigned char *buf, int length) |
c906108c SS |
1969 | { |
1970 | int v; | |
1971 | int longreg = 0; | |
1972 | ||
1973 | init_pointers (); | |
1974 | ||
d0fe2f7e | 1975 | if (!h8300smode && rn >= EXR_REGNUM) |
c3f4437e | 1976 | rn++; |
c906108c SS |
1977 | switch (rn) |
1978 | { | |
1979 | default: | |
1980 | abort (); | |
3b02cf92 | 1981 | case CCR_REGNUM: |
c906108c SS |
1982 | v = cpu.ccr; |
1983 | break; | |
fc974602 AV |
1984 | case EXR_REGNUM: |
1985 | v = cpu.exr; | |
1986 | break; | |
3b02cf92 | 1987 | case PC_REGNUM: |
c906108c SS |
1988 | v = cpu.pc; |
1989 | break; | |
1990 | case R0_REGNUM: | |
1991 | case R1_REGNUM: | |
1992 | case R2_REGNUM: | |
1993 | case R3_REGNUM: | |
1994 | case R4_REGNUM: | |
1995 | case R5_REGNUM: | |
1996 | case R6_REGNUM: | |
1997 | case R7_REGNUM: | |
1998 | v = cpu.regs[rn]; | |
1999 | break; | |
3b02cf92 | 2000 | case CYCLE_REGNUM: |
c906108c SS |
2001 | v = cpu.cycles; |
2002 | longreg = 1; | |
2003 | break; | |
3b02cf92 | 2004 | case TICK_REGNUM: |
c906108c SS |
2005 | v = cpu.ticks; |
2006 | longreg = 1; | |
2007 | break; | |
3b02cf92 | 2008 | case INST_REGNUM: |
c906108c SS |
2009 | v = cpu.insts; |
2010 | longreg = 1; | |
2011 | break; | |
2012 | } | |
2013 | if (h8300hmode || longreg) | |
2014 | { | |
2015 | buf[0] = v >> 24; | |
2016 | buf[1] = v >> 16; | |
2017 | buf[2] = v >> 8; | |
2018 | buf[3] = v >> 0; | |
2019 | } | |
2020 | else | |
2021 | { | |
2022 | buf[0] = v >> 8; | |
2023 | buf[1] = v; | |
2024 | } | |
2025 | return -1; | |
2026 | } | |
2027 | ||
2028 | void | |
a4f27e3e | 2029 | sim_stop_reason (SIM_DESC sd, enum sim_stop *reason, int *sigrc) |
c906108c SS |
2030 | { |
2031 | #if 0 /* FIXME: This should work but we can't use it. | |
2032 | grep for SLEEP above. */ | |
2033 | switch (cpu.state) | |
2034 | { | |
2035 | case SIM_STATE_EXITED : *reason = sim_exited; break; | |
2036 | case SIM_STATE_SIGNALLED : *reason = sim_signalled; break; | |
2037 | case SIM_STATE_STOPPED : *reason = sim_stopped; break; | |
2038 | default : abort (); | |
2039 | } | |
2040 | #else | |
2041 | *reason = sim_stopped; | |
2042 | #endif | |
2043 | *sigrc = cpu.exception; | |
2044 | } | |
2045 | ||
2046 | /* FIXME: Rename to sim_set_mem_size. */ | |
2047 | ||
2048 | void | |
a4f27e3e | 2049 | sim_size (int n) |
c906108c SS |
2050 | { |
2051 | /* Memory size is fixed. */ | |
2052 | } | |
2053 | ||
2054 | void | |
a4f27e3e | 2055 | sim_set_simcache_size (int n) |
c906108c SS |
2056 | { |
2057 | if (cpu.cache) | |
2058 | free (cpu.cache); | |
2059 | if (n < 2) | |
2060 | n = 2; | |
2061 | cpu.cache = (decoded_inst *) malloc (sizeof (decoded_inst) * n); | |
2062 | memset (cpu.cache, 0, sizeof (decoded_inst) * n); | |
2063 | cpu.csize = n; | |
2064 | } | |
2065 | ||
2066 | ||
2067 | void | |
a4f27e3e | 2068 | sim_info (SIM_DESC sd, int verbose) |
c906108c SS |
2069 | { |
2070 | double timetaken = (double) cpu.ticks / (double) now_persec (); | |
2071 | double virttime = cpu.cycles / 10.0e6; | |
2072 | ||
2073 | (*sim_callback->printf_filtered) (sim_callback, | |
2074 | "\n\n#instructions executed %10d\n", | |
2075 | cpu.insts); | |
2076 | (*sim_callback->printf_filtered) (sim_callback, | |
2077 | "#cycles (v approximate) %10d\n", | |
2078 | cpu.cycles); | |
2079 | (*sim_callback->printf_filtered) (sim_callback, | |
2080 | "#real time taken %10.4f\n", | |
2081 | timetaken); | |
2082 | (*sim_callback->printf_filtered) (sim_callback, | |
2083 | "#virtual time taked %10.4f\n", | |
2084 | virttime); | |
2085 | if (timetaken != 0.0) | |
2086 | (*sim_callback->printf_filtered) (sim_callback, | |
2087 | "#simulation ratio %10.4f\n", | |
2088 | virttime / timetaken); | |
2089 | (*sim_callback->printf_filtered) (sim_callback, | |
2090 | "#compiles %10d\n", | |
2091 | cpu.compiles); | |
2092 | (*sim_callback->printf_filtered) (sim_callback, | |
2093 | "#cache size %10d\n", | |
2094 | cpu.csize); | |
2095 | ||
2096 | #ifdef ADEBUG | |
2097 | /* This to be conditional on `what' (aka `verbose'), | |
2098 | however it was never passed as non-zero. */ | |
2099 | if (1) | |
2100 | { | |
2101 | int i; | |
2102 | for (i = 0; i < O_LAST; i++) | |
2103 | { | |
2104 | if (cpu.stats[i]) | |
2105 | (*sim_callback->printf_filtered) (sim_callback, | |
2106 | "%d: %d\n", i, cpu.stats[i]); | |
2107 | } | |
2108 | } | |
2109 | #endif | |
2110 | } | |
2111 | ||
2ea716f6 KH |
2112 | /* Indicate whether the cpu is an H8/300 or H8/300H. |
2113 | FLAG is non-zero for the H8/300H. */ | |
c906108c SS |
2114 | |
2115 | void | |
a4f27e3e | 2116 | set_h8300h (int h_flag, int s_flag) |
c906108c SS |
2117 | { |
2118 | /* FIXME: Much of the code in sim_load can be moved to sim_open. | |
2119 | This function being replaced by a sim_open:ARGV configuration | |
2ea716f6 | 2120 | option. */ |
a8cdafbd AV |
2121 | h8300hmode = h_flag; |
2122 | h8300smode = s_flag; | |
c906108c SS |
2123 | } |
2124 | ||
2125 | SIM_DESC | |
a4f27e3e MS |
2126 | sim_open (SIM_OPEN_KIND kind, |
2127 | struct host_callback_struct *ptr, | |
6b4a8935 | 2128 | struct bfd *abfd, |
a4f27e3e | 2129 | char **argv) |
c906108c | 2130 | { |
2ea716f6 | 2131 | /* FIXME: Much of the code in sim_load can be moved here. */ |
c906108c SS |
2132 | |
2133 | sim_kind = kind; | |
2134 | myname = argv[0]; | |
2135 | sim_callback = ptr; | |
2ea716f6 | 2136 | /* Fudge our descriptor. */ |
c906108c SS |
2137 | return (SIM_DESC) 1; |
2138 | } | |
2139 | ||
2140 | void | |
a4f27e3e | 2141 | sim_close (SIM_DESC sd, int quitting) |
c906108c | 2142 | { |
2ea716f6 | 2143 | /* Nothing to do. */ |
c906108c SS |
2144 | } |
2145 | ||
2146 | /* Called by gdb to load a program into memory. */ | |
2147 | ||
2148 | SIM_RC | |
a4f27e3e | 2149 | sim_load (SIM_DESC sd, char *prog, bfd *abfd, int from_tty) |
c906108c SS |
2150 | { |
2151 | bfd *prog_bfd; | |
2152 | ||
2ea716f6 KH |
2153 | /* FIXME: The code below that sets a specific variant of the H8/300 |
2154 | being simulated should be moved to sim_open(). */ | |
c906108c | 2155 | |
2ea716f6 | 2156 | /* See if the file is for the H8/300 or H8/300H. */ |
c906108c SS |
2157 | /* ??? This may not be the most efficient way. The z8k simulator |
2158 | does this via a different mechanism (INIT_EXTRA_SYMTAB_INFO). */ | |
2159 | if (abfd != NULL) | |
2160 | prog_bfd = abfd; | |
2161 | else | |
2162 | prog_bfd = bfd_openr (prog, "coff-h8300"); | |
2163 | if (prog_bfd != NULL) | |
2164 | { | |
2165 | /* Set the cpu type. We ignore failure from bfd_check_format | |
2166 | and bfd_openr as sim_load_file checks too. */ | |
de9b1892 | 2167 | if (bfd_check_format (prog_bfd, bfd_object)) |
c906108c SS |
2168 | { |
2169 | unsigned long mach = bfd_get_mach (prog_bfd); | |
a8cdafbd AV |
2170 | set_h8300h (mach == bfd_mach_h8300h || mach == bfd_mach_h8300s, |
2171 | mach == bfd_mach_h8300s); | |
c906108c SS |
2172 | } |
2173 | } | |
2174 | ||
2175 | /* If we're using gdb attached to the simulator, then we have to | |
2176 | reallocate memory for the simulator. | |
2177 | ||
2178 | When gdb first starts, it calls fetch_registers (among other | |
2179 | functions), which in turn calls init_pointers, which allocates | |
2180 | simulator memory. | |
2181 | ||
2182 | The problem is when we do that, we don't know whether we're | |
2ea716f6 | 2183 | debugging an H8/300 or H8/300H program. |
c906108c SS |
2184 | |
2185 | This is the first point at which we can make that determination, | |
2186 | so we just reallocate memory now; this will also allow us to handle | |
2ea716f6 | 2187 | switching between H8/300 and H8/300H programs without exiting |
c906108c | 2188 | gdb. */ |
a8cdafbd AV |
2189 | |
2190 | if (h8300smode) | |
2191 | memory_size = H8300S_MSIZE; | |
2192 | else if (h8300hmode) | |
c906108c SS |
2193 | memory_size = H8300H_MSIZE; |
2194 | else | |
2195 | memory_size = H8300_MSIZE; | |
2196 | ||
2197 | if (cpu.memory) | |
2198 | free (cpu.memory); | |
2199 | if (cpu.cache_idx) | |
2200 | free (cpu.cache_idx); | |
2201 | if (cpu.eightbit) | |
2202 | free (cpu.eightbit); | |
2203 | ||
2204 | cpu.memory = (unsigned char *) calloc (sizeof (char), memory_size); | |
2205 | cpu.cache_idx = (unsigned short *) calloc (sizeof (short), memory_size); | |
2206 | cpu.eightbit = (unsigned char *) calloc (sizeof (char), 256); | |
2207 | ||
2ea716f6 | 2208 | /* `msize' must be a power of two. */ |
c906108c SS |
2209 | if ((memory_size & (memory_size - 1)) != 0) |
2210 | abort (); | |
2211 | cpu.mask = memory_size - 1; | |
2212 | ||
2213 | if (sim_load_file (sd, myname, sim_callback, prog, prog_bfd, | |
2214 | sim_kind == SIM_OPEN_DEBUG, | |
2215 | 0, sim_write) | |
2216 | == NULL) | |
2217 | { | |
2218 | /* Close the bfd if we opened it. */ | |
2219 | if (abfd == NULL && prog_bfd != NULL) | |
2220 | bfd_close (prog_bfd); | |
2221 | return SIM_RC_FAIL; | |
2222 | } | |
2223 | ||
2224 | /* Close the bfd if we opened it. */ | |
2225 | if (abfd == NULL && prog_bfd != NULL) | |
2226 | bfd_close (prog_bfd); | |
2227 | return SIM_RC_OK; | |
2228 | } | |
2229 | ||
2230 | SIM_RC | |
6b4a8935 | 2231 | sim_create_inferior (SIM_DESC sd, struct bfd *abfd, char **argv, char **env) |
c906108c SS |
2232 | { |
2233 | if (abfd != NULL) | |
2234 | cpu.pc = bfd_get_start_address (abfd); | |
2235 | else | |
2236 | cpu.pc = 0; | |
2237 | return SIM_RC_OK; | |
2238 | } | |
2239 | ||
2240 | void | |
a4f27e3e | 2241 | sim_do_command (SIM_DESC sd, char *cmd) |
c906108c SS |
2242 | { |
2243 | (*sim_callback->printf_filtered) (sim_callback, | |
2244 | "This simulator does not accept any commands.\n"); | |
2245 | } | |
2246 | ||
2247 | void | |
a4f27e3e | 2248 | sim_set_callbacks (struct host_callback_struct *ptr) |
c906108c SS |
2249 | { |
2250 | sim_callback = ptr; | |
2251 | } |