Commit | Line | Data |
---|---|---|
ce51bde6 DE |
1 | /* |
2 | * Simulator for the Hitachi H8/300 architecture. | |
3 | * | |
4 | * Written by Steve Chamberlain of Cygnus Support. sac@cygnus.com | |
5 | * | |
6 | * This file is part of H8/300 sim | |
7 | * | |
8 | * | |
9 | * THIS SOFTWARE IS NOT COPYRIGHTED | |
10 | * | |
11 | * Cygnus offers the following for use in the public domain. Cygnus makes no | |
12 | * warranty with regard to the software or its performance and the user | |
13 | * accepts the software "AS IS" with all faults. | |
14 | * | |
15 | * CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO THIS | |
16 | * SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY | |
17 | * AND FITNESS FOR A PARTICULAR PURPOSE. | |
ce51bde6 DE |
18 | */ |
19 | ||
20 | #include <signal.h> | |
7478904c | 21 | #ifndef WIN32 |
ce51bde6 | 22 | #include <sys/times.h> |
7478904c | 23 | #endif |
ce51bde6 | 24 | #include <sys/param.h> |
0693d363 DE |
25 | #include "ansidecl.h" |
26 | #include "sysdep.h" | |
a415cf0a | 27 | #include "remote-sim.h" |
7478904c | 28 | #include "bfd.h" |
ce51bde6 DE |
29 | |
30 | int debug; | |
31 | ||
32 | ||
33 | #define X(op, size) op*4+size | |
34 | ||
28655f00 | 35 | #define SP (h8300hmode ? SL:SW) |
ce51bde6 DE |
36 | #define SB 0 |
37 | #define SW 1 | |
38 | #define SL 2 | |
39 | #define OP_REG 1 | |
40 | #define OP_DEC 2 | |
41 | #define OP_DISP 3 | |
42 | #define OP_INC 4 | |
43 | #define OP_PCREL 5 | |
44 | #define OP_MEM 6 | |
45 | #define OP_CCR 7 | |
46 | #define OP_IMM 8 | |
47 | #define OP_ABS 10 | |
48 | #define h8_opcodes ops | |
49 | #define DEFINE_TABLE | |
50 | #include "opcode/h8300.h" | |
51 | ||
52 | #include "inst.h" | |
53 | ||
54 | #define LOW_BYTE(x) ((x) & 0xff) | |
55 | #define HIGH_BYTE(x) (((x)>>8) & 0xff) | |
56 | #define P(X,Y) ((X<<8) | Y) | |
57 | ||
58 | #define BUILDSR() cpu.ccr = (N << 3) | (Z << 2) | (V<<1) | C; | |
59 | ||
60 | #define GETSR() \ | |
61 | c = (cpu.ccr >> 0) & 1;\ | |
62 | v = (cpu.ccr >> 1) & 1;\ | |
63 | nz = !((cpu.ccr >> 2) & 1);\ | |
64 | n = (cpu.ccr >> 3) & 1; | |
65 | ||
66 | #ifdef __CHAR_IS_SIGNED__ | |
67 | #define SEXTCHAR(x) ((char)(x)) | |
68 | #endif | |
69 | ||
70 | #ifndef SEXTCHAR | |
71 | #define SEXTCHAR(x) ((x & 0x80) ? (x | ~0xff):x) | |
72 | #endif | |
73 | ||
74 | #define UEXTCHAR(x) ((x) & 0xff) | |
75 | #define UEXTSHORT(x) ((x) & 0xffff) | |
76 | #define SEXTSHORT(x) ((short)(x)) | |
77 | ||
78 | static cpu_state_type cpu; | |
79 | ||
28655f00 | 80 | int h8300hmode = 0; |
ce51bde6 DE |
81 | |
82 | ||
83 | static int | |
84 | get_now () | |
85 | { | |
7478904c | 86 | #ifndef WIN32 |
ce51bde6 | 87 | struct tms b; |
0693d363 DE |
88 | |
89 | return time (0); | |
28655f00 | 90 | #endif |
7478904c | 91 | return 0; |
ce51bde6 DE |
92 | } |
93 | ||
94 | static int | |
95 | now_persec () | |
96 | { | |
28655f00 | 97 | return 1; |
ce51bde6 DE |
98 | } |
99 | ||
100 | ||
101 | static int | |
102 | bitfrom (x) | |
103 | { | |
ce51bde6 DE |
104 | switch (x & SIZE) |
105 | { | |
106 | case L_8: | |
107 | return SB; | |
108 | case L_16: | |
109 | return SW; | |
110 | case L_32: | |
111 | return SL; | |
112 | case L_P: | |
28655f00 | 113 | return h8300hmode ? SL : SW; |
ce51bde6 | 114 | } |
ce51bde6 DE |
115 | } |
116 | ||
117 | static | |
118 | unsigned int | |
119 | lvalue (x, rn) | |
120 | { | |
121 | switch (x / 4) | |
122 | { | |
123 | case OP_DISP: | |
0693d363 | 124 | if (rn == 8) |
ce51bde6 | 125 | { |
0693d363 | 126 | return X (OP_IMM, SP); |
ce51bde6 | 127 | } |
0693d363 DE |
128 | return X (OP_REG, SP); |
129 | ||
ce51bde6 DE |
130 | case OP_MEM: |
131 | ||
132 | return X (OP_MEM, SP); | |
133 | default: | |
134 | abort (); | |
135 | } | |
136 | } | |
137 | ||
138 | static unsigned int | |
139 | decode (addr, data, dst) | |
140 | int addr; | |
141 | unsigned char *data; | |
142 | decoded_inst *dst; | |
143 | ||
144 | { | |
145 | int rs = 0; | |
146 | int rd = 0; | |
147 | int rdisp = 0; | |
148 | int abs = 0; | |
149 | int plen = 0; | |
150 | ||
151 | struct h8_opcode *q = h8_opcodes; | |
152 | int size = 0; | |
153 | dst->dst.type = -1; | |
154 | dst->src.type = -1; | |
155 | /* Find the exact opcode/arg combo */ | |
156 | while (q->name) | |
157 | { | |
158 | op_type *nib; | |
159 | unsigned int len = 0; | |
160 | ||
161 | nib = q->data.nib; | |
162 | ||
163 | while (1) | |
164 | { | |
165 | op_type looking_for = *nib; | |
166 | int thisnib = data[len >> 1]; | |
167 | ||
168 | thisnib = (len & 1) ? (thisnib & 0xf) : ((thisnib >> 4) & 0xf); | |
169 | ||
0693d363 | 170 | if (looking_for < 16 && looking_for >= 0) |
ce51bde6 | 171 | { |
ce51bde6 DE |
172 | if (looking_for != thisnib) |
173 | goto fail; | |
174 | } | |
175 | else | |
176 | { | |
ce51bde6 DE |
177 | if ((int) looking_for & (int) B31) |
178 | { | |
179 | if (!(((int) thisnib & 0x8) != 0)) | |
180 | goto fail; | |
181 | looking_for = (op_type) ((int) looking_for & ~(int) | |
182 | B31); | |
183 | thisnib &= 0x7; | |
ce51bde6 DE |
184 | } |
185 | if ((int) looking_for & (int) B30) | |
186 | { | |
187 | if (!(((int) thisnib & 0x8) == 0)) | |
188 | goto fail; | |
189 | looking_for = (op_type) ((int) looking_for & ~(int) B30); | |
190 | } | |
191 | if (looking_for & DBIT) | |
192 | { | |
0693d363 DE |
193 | if ((looking_for & 5) != (thisnib & 5)) |
194 | goto fail; | |
ce51bde6 DE |
195 | abs = (thisnib & 0x8) ? 2 : 1; |
196 | } | |
197 | else if (looking_for & (REG | IND | INC | DEC)) | |
198 | { | |
199 | if (looking_for & REG) | |
200 | { | |
201 | /* | |
202 | * Can work out size from the | |
203 | * register | |
204 | */ | |
205 | size = bitfrom (looking_for); | |
206 | } | |
207 | if (looking_for & SRC) | |
208 | { | |
209 | rs = thisnib; | |
210 | } | |
211 | else | |
212 | { | |
213 | rd = thisnib; | |
214 | } | |
215 | } | |
216 | else if (looking_for & L_16) | |
217 | { | |
218 | abs = (data[len >> 1]) * 256 + data[(len + 2) >> 1]; | |
219 | plen = 16; | |
0693d363 | 220 | if (looking_for & (PCREL | DISP)) |
ce51bde6 DE |
221 | { |
222 | abs = (short) (abs); | |
223 | } | |
224 | } | |
225 | else if (looking_for & ABSJMP) | |
226 | { | |
227 | abs = | |
228 | (data[1] << 16) | |
229 | | (data[2] << 8) | |
230 | | (data[3]); | |
231 | } | |
0693d363 DE |
232 | else if (looking_for & MEMIND) |
233 | { | |
234 | abs = data[1]; | |
235 | } | |
ce51bde6 DE |
236 | else if (looking_for & L_32) |
237 | { | |
238 | int i = len >> 1; | |
239 | abs = (data[i] << 24) | |
240 | | (data[i + 1] << 16) | |
241 | | (data[i + 2] << 8) | |
242 | | (data[i + 3]); | |
243 | ||
244 | plen = 32; | |
ce51bde6 DE |
245 | } |
246 | else if (looking_for & L_24) | |
247 | { | |
248 | int i = len >> 1; | |
0693d363 | 249 | abs = (data[i] << 16) | (data[i + 1] << 8) | (data[i + 2]); |
ce51bde6 DE |
250 | plen = 24; |
251 | } | |
252 | else if (looking_for & IGNORE) | |
253 | { | |
0693d363 | 254 | /* nothing to do */ |
ce51bde6 DE |
255 | } |
256 | else if (looking_for & DISPREG) | |
257 | { | |
258 | rdisp = thisnib & 0x7; | |
259 | } | |
260 | else if (looking_for & KBIT) | |
261 | { | |
262 | switch (thisnib) | |
263 | { | |
264 | case 9: | |
265 | abs = 4; | |
266 | break; | |
267 | case 8: | |
268 | abs = 2; | |
269 | break; | |
270 | case 0: | |
271 | abs = 1; | |
272 | break; | |
273 | } | |
274 | } | |
275 | else if (looking_for & L_8) | |
276 | { | |
277 | plen = 8; | |
278 | ||
279 | if (looking_for & PCREL) | |
280 | { | |
281 | abs = SEXTCHAR (data[len >> 1]); | |
282 | } | |
283 | else | |
284 | { | |
285 | abs = data[len >> 1] & 0xff; | |
286 | } | |
287 | } | |
288 | else if (looking_for & L_3) | |
289 | { | |
290 | plen = 3; | |
291 | ||
292 | abs = thisnib; | |
293 | } | |
294 | else if (looking_for == E) | |
295 | { | |
296 | dst->op = q; | |
297 | ||
298 | /* Fill in the args */ | |
299 | { | |
300 | op_type *args = q->args.nib; | |
301 | int hadone = 0; | |
302 | ||
ce51bde6 DE |
303 | while (*args != E) |
304 | { | |
305 | int x = *args; | |
306 | int rn = (x & DST) ? rd : rs; | |
307 | ea_type *p; | |
308 | ||
309 | if (x & DST) | |
310 | { | |
311 | p = &(dst->dst); | |
312 | } | |
313 | else | |
314 | { | |
315 | p = &(dst->src); | |
316 | } | |
317 | ||
ce51bde6 DE |
318 | if (x & (IMM | KBIT | DBIT)) |
319 | { | |
320 | p->type = X (OP_IMM, size); | |
321 | p->literal = abs; | |
322 | } | |
323 | else if (x & REG) | |
324 | { | |
0693d363 DE |
325 | /* Reset the size, some |
326 | ops (like mul) have two sizes */ | |
327 | ||
ce51bde6 DE |
328 | size = bitfrom (x); |
329 | p->type = X (OP_REG, size); | |
330 | p->reg = rn; | |
331 | } | |
332 | else if (x & INC) | |
333 | { | |
334 | p->type = X (OP_INC, size); | |
335 | p->reg = rn & 0x7; | |
336 | } | |
337 | else if (x & DEC) | |
338 | { | |
339 | p->type = X (OP_DEC, size); | |
340 | p->reg = rn & 0x7; | |
341 | } | |
342 | else if (x & IND) | |
343 | { | |
344 | p->type = X (OP_DISP, size); | |
345 | p->reg = rn & 0x7; | |
346 | p->literal = 0; | |
347 | } | |
348 | else if (x & (ABS | ABSJMP | ABSMOV)) | |
349 | { | |
350 | p->type = X (OP_DISP, size); | |
351 | p->literal = abs; | |
352 | p->reg = 8; | |
353 | } | |
354 | else if (x & MEMIND) | |
355 | { | |
356 | p->type = X (OP_MEM, size); | |
357 | p->literal = abs; | |
358 | } | |
359 | else if (x & PCREL) | |
360 | { | |
361 | p->type = X (OP_PCREL, size); | |
362 | p->literal = abs + addr + 2; | |
0693d363 DE |
363 | if (x & L_16) |
364 | p->literal += 2; | |
ce51bde6 DE |
365 | } |
366 | else if (x & ABSJMP) | |
367 | { | |
368 | p->type = X (OP_IMM, SP); | |
369 | p->literal = abs; | |
370 | } | |
371 | else if (x & DISP) | |
372 | { | |
373 | p->type = X (OP_DISP, size); | |
374 | p->literal = abs; | |
375 | p->reg = rdisp & 0x7; | |
376 | } | |
377 | else if (x & CCR) | |
378 | { | |
379 | p->type = OP_CCR; | |
380 | } | |
381 | else | |
382 | printf ("Hmmmm %x", x); | |
383 | ||
ce51bde6 DE |
384 | args++; |
385 | } | |
386 | } | |
387 | ||
388 | /* | |
0693d363 DE |
389 | * But a jmp or a jsr gets |
390 | * automagically lvalued, since we | |
391 | * branch to their address not their | |
392 | * contents | |
393 | */ | |
ce51bde6 DE |
394 | if (q->how == O (O_JSR, SB) |
395 | || q->how == O (O_JMP, SB)) | |
396 | { | |
397 | dst->src.type = lvalue (dst->src.type, dst->src.reg); | |
398 | } | |
399 | ||
ce51bde6 DE |
400 | if (dst->dst.type == -1) |
401 | dst->dst = dst->src; | |
0693d363 | 402 | |
ce51bde6 DE |
403 | dst->opcode = q->how; |
404 | dst->cycles = q->time; | |
405 | ||
406 | /* And a jsr to 0xc4 is turned into a magic trap */ | |
0693d363 DE |
407 | |
408 | if (dst->opcode == O (O_JSR, SB)) | |
ce51bde6 | 409 | { |
0693d363 | 410 | if (dst->src.literal == 0xc4) |
ce51bde6 | 411 | { |
0693d363 | 412 | dst->opcode = O (O_SYSCALL, SB); |
ce51bde6 DE |
413 | } |
414 | } | |
0693d363 | 415 | |
ce51bde6 DE |
416 | dst->next_pc = addr + len / 2; |
417 | return; | |
418 | } | |
419 | else | |
420 | { | |
421 | printf ("Dont understand %x \n", looking_for); | |
422 | } | |
423 | } | |
0693d363 | 424 | |
ce51bde6 DE |
425 | len++; |
426 | nib++; | |
427 | } | |
0693d363 | 428 | |
ce51bde6 DE |
429 | fail: |
430 | q++; | |
431 | } | |
0693d363 | 432 | |
ce51bde6 DE |
433 | dst->opcode = O (O_ILL, SB); |
434 | } | |
435 | ||
436 | ||
437 | static void | |
438 | compile (pc) | |
439 | { | |
440 | int idx; | |
0693d363 | 441 | |
ce51bde6 | 442 | /* find the next cache entry to use */ |
0693d363 | 443 | |
ce51bde6 DE |
444 | idx = cpu.cache_top + 1; |
445 | cpu.compiles++; | |
446 | if (idx >= cpu.csize) | |
447 | { | |
448 | idx = 1; | |
449 | } | |
450 | cpu.cache_top = idx; | |
0693d363 | 451 | |
ce51bde6 DE |
452 | /* Throw away its old meaning */ |
453 | cpu.cache_idx[cpu.cache[idx].oldpc] = 0; | |
0693d363 | 454 | |
ce51bde6 DE |
455 | /* set to new address */ |
456 | cpu.cache[idx].oldpc = pc; | |
0693d363 | 457 | |
ce51bde6 DE |
458 | /* fill in instruction info */ |
459 | decode (pc, cpu.memory + pc, cpu.cache + idx); | |
0693d363 | 460 | |
ce51bde6 DE |
461 | /* point to new cache entry */ |
462 | cpu.cache_idx[pc] = idx; | |
463 | } | |
464 | ||
465 | ||
466 | static unsigned char *breg[18]; | |
467 | static unsigned short *wreg[18]; | |
468 | static unsigned int *lreg[18]; | |
469 | ||
470 | #define GET_B_REG(x) *(breg[x]) | |
471 | #define SET_B_REG(x,y) (*(breg[x])) = (y) | |
472 | #define GET_W_REG(x) *(wreg[x]) | |
473 | #define SET_W_REG(x,y) (*(wreg[x])) = (y) | |
474 | ||
475 | #define GET_L_REG(x) *(lreg[x]) | |
476 | #define SET_L_REG(x,y) (*(lreg[x])) = (y) | |
477 | ||
478 | #define GET_MEMORY_L(x) \ | |
479 | ((cpu.memory[x+0] << 24) | (cpu.memory[x+1] << 16) | (cpu.memory[x+2] << 8) | cpu.memory[x+3]) | |
480 | ||
481 | #define GET_MEMORY_W(x) \ | |
482 | ((cpu.memory[x+0] << 8) | (cpu.memory[x+1] << 0)) | |
483 | ||
484 | ||
485 | #define SET_MEMORY_B(x,y) \ | |
486 | (cpu.memory[(x)] = y) | |
487 | ||
488 | #define SET_MEMORY_W(x,y) \ | |
489 | {register unsigned char *_p = cpu.memory+x;\ | |
490 | register int __y = y;\ | |
491 | _p[0] = (__y)>>8;\ | |
492 | _p[1] =(__y); } | |
493 | ||
494 | #define SET_MEMORY_L(x,y) \ | |
495 | {register unsigned char *_p = cpu.memory+x;register int __y = y;\ | |
496 | _p[0] = (__y)>>24; _p[1] = (__y)>>16; _p[2] = (__y)>>8; _p[3] = (__y)>>0;} | |
497 | ||
498 | #define GET_MEMORY_B(x) (cpu.memory[x]) | |
499 | ||
500 | int | |
89a2c4fd | 501 | fetch (arg, n) |
0693d363 | 502 | ea_type *arg; |
ce51bde6 DE |
503 | { |
504 | int rn = arg->reg; | |
505 | int abs = arg->literal; | |
506 | int r; | |
507 | int t; | |
0693d363 | 508 | |
ce51bde6 DE |
509 | switch (arg->type) |
510 | { | |
511 | case X (OP_REG, SB): | |
512 | return GET_B_REG (rn); | |
513 | case X (OP_REG, SW): | |
514 | return GET_W_REG (rn); | |
515 | case X (OP_REG, SL): | |
516 | return GET_L_REG (rn); | |
517 | case X (OP_IMM, SB): | |
518 | case X (OP_IMM, SW): | |
519 | case X (OP_IMM, SL): | |
520 | return abs; | |
521 | case X (OP_DEC, SB): | |
0693d363 | 522 | abort (); |
ce51bde6 | 523 | |
0693d363 DE |
524 | case X (OP_INC, SB): |
525 | t = GET_L_REG (rn); | |
ce51bde6 | 526 | t &= cpu.mask; |
0693d363 DE |
527 | r = GET_MEMORY_B (t); |
528 | t++; | |
ce51bde6 | 529 | t = t & cpu.mask; |
0693d363 | 530 | SET_L_REG (rn, t); |
ce51bde6 DE |
531 | return r; |
532 | break; | |
0693d363 DE |
533 | case X (OP_INC, SW): |
534 | t = GET_L_REG (rn); | |
ce51bde6 | 535 | t &= cpu.mask; |
0693d363 DE |
536 | r = GET_MEMORY_W (t); |
537 | t += 2; | |
ce51bde6 | 538 | t = t & cpu.mask; |
0693d363 | 539 | SET_L_REG (rn, t); |
ce51bde6 | 540 | return r; |
0693d363 DE |
541 | case X (OP_INC, SL): |
542 | t = GET_L_REG (rn); | |
ce51bde6 | 543 | t &= cpu.mask; |
0693d363 DE |
544 | r = GET_MEMORY_L (t); |
545 | ||
546 | t += 4; | |
ce51bde6 | 547 | t = t & cpu.mask; |
0693d363 | 548 | SET_L_REG (rn, t); |
ce51bde6 | 549 | return r; |
0693d363 | 550 | |
ce51bde6 DE |
551 | case X (OP_DISP, SB): |
552 | t = GET_L_REG (rn) + abs; | |
553 | t &= cpu.mask; | |
554 | return GET_MEMORY_B (t); | |
0693d363 | 555 | |
ce51bde6 DE |
556 | case X (OP_DISP, SW): |
557 | t = GET_L_REG (rn) + abs; | |
558 | t &= cpu.mask; | |
559 | return GET_MEMORY_W (t); | |
0693d363 | 560 | |
ce51bde6 DE |
561 | case X (OP_DISP, SL): |
562 | t = GET_L_REG (rn) + abs; | |
563 | t &= cpu.mask; | |
564 | return GET_MEMORY_L (t); | |
0693d363 DE |
565 | |
566 | case X (OP_MEM, SL): | |
567 | t = GET_MEMORY_L (abs); | |
568 | t &= cpu.mask; | |
569 | return t; | |
570 | ||
ce51bde6 DE |
571 | default: |
572 | abort (); | |
0693d363 | 573 | |
ce51bde6 DE |
574 | } |
575 | } | |
576 | ||
577 | ||
0693d363 DE |
578 | static |
579 | void | |
580 | store (arg, n) | |
581 | ea_type *arg; | |
582 | int n; | |
ce51bde6 DE |
583 | { |
584 | int rn = arg->reg; | |
585 | int abs = arg->literal; | |
586 | int t; | |
0693d363 | 587 | |
ce51bde6 DE |
588 | switch (arg->type) |
589 | { | |
590 | case X (OP_REG, SB): | |
591 | SET_B_REG (rn, n); | |
592 | break; | |
593 | case X (OP_REG, SW): | |
594 | SET_W_REG (rn, n); | |
595 | break; | |
596 | case X (OP_REG, SL): | |
597 | SET_L_REG (rn, n); | |
598 | break; | |
0693d363 | 599 | |
ce51bde6 | 600 | case X (OP_DEC, SB): |
0693d363 | 601 | t = GET_L_REG (rn) - 1; |
ce51bde6 | 602 | t &= cpu.mask; |
0693d363 | 603 | SET_L_REG (rn, t); |
ce51bde6 DE |
604 | SET_MEMORY_B (t, n); |
605 | ||
606 | break; | |
607 | case X (OP_DEC, SW): | |
0693d363 | 608 | t = (GET_L_REG (rn) - 2) & cpu.mask; |
ce51bde6 DE |
609 | SET_L_REG (rn, t); |
610 | SET_MEMORY_W (t, n); | |
611 | break; | |
612 | ||
613 | case X (OP_DEC, SL): | |
0693d363 | 614 | t = (GET_L_REG (rn) - 4) & cpu.mask; |
89a2c4fd | 615 | SET_L_REG (rn, t); |
0693d363 | 616 | SET_MEMORY_L (t, n); |
ce51bde6 DE |
617 | break; |
618 | ||
ce51bde6 DE |
619 | case X (OP_DISP, SB): |
620 | t = GET_L_REG (rn) + abs; | |
621 | t &= cpu.mask; | |
622 | SET_MEMORY_B (t, n); | |
623 | break; | |
624 | ||
625 | case X (OP_DISP, SW): | |
626 | t = GET_L_REG (rn) + abs; | |
627 | t &= cpu.mask; | |
628 | SET_MEMORY_W (t, n); | |
629 | break; | |
630 | ||
631 | case X (OP_DISP, SL): | |
632 | t = GET_L_REG (rn) + abs; | |
633 | t &= cpu.mask; | |
634 | SET_MEMORY_L (t, n); | |
635 | break; | |
636 | default: | |
637 | abort (); | |
638 | } | |
639 | } | |
640 | ||
641 | ||
642 | static union | |
0693d363 DE |
643 | { |
644 | short int i; | |
645 | struct | |
646 | { | |
647 | char low; | |
648 | char high; | |
649 | } | |
650 | u; | |
651 | } | |
ce51bde6 DE |
652 | |
653 | littleendian; | |
654 | ||
655 | static | |
656 | void | |
657 | init_pointers () | |
658 | { | |
659 | static int init; | |
660 | ||
661 | if (!init) | |
662 | { | |
663 | int i; | |
664 | ||
665 | init = 1; | |
666 | littleendian.i = 1; | |
667 | ||
668 | cpu.memory = (unsigned char *) calloc (sizeof (char), MSIZE); | |
669 | cpu.cache_idx = (unsigned short *) calloc (sizeof (short), MSIZE); | |
0693d363 | 670 | |
7478904c | 671 | cpu.mask = (1 << MPOWER) - 1; |
ce51bde6 DE |
672 | for (i = 0; i < 9; i++) |
673 | { | |
674 | cpu.regs[i] = 0; | |
675 | } | |
676 | ||
677 | for (i = 0; i < 8; i++) | |
678 | { | |
679 | unsigned char *p = (unsigned char *) (cpu.regs + i); | |
680 | unsigned char *e = (unsigned char *) (cpu.regs + i + 1); | |
681 | unsigned short *q = (unsigned short *) (cpu.regs + i); | |
682 | unsigned short *u = (unsigned short *) (cpu.regs + i + 1); | |
683 | cpu.regs[i] = 0x00112233; | |
684 | while (p < e) | |
685 | { | |
686 | if (*p == 0x22) | |
687 | { | |
688 | breg[i] = p; | |
689 | } | |
690 | if (*p == 0x33) | |
691 | { | |
0693d363 | 692 | breg[i + 8] = p; |
ce51bde6 DE |
693 | } |
694 | p++; | |
695 | } | |
696 | while (q < u) | |
697 | { | |
698 | if (*q == 0x2233) | |
699 | { | |
700 | wreg[i] = q; | |
701 | } | |
702 | if (*q == 0x0011) | |
703 | { | |
704 | wreg[i + 8] = q; | |
705 | } | |
706 | q++; | |
707 | } | |
708 | cpu.regs[i] = 0; | |
709 | lreg[i] = &cpu.regs[i]; | |
710 | } | |
711 | ||
ce51bde6 | 712 | lreg[8] = &cpu.regs[8]; |
0693d363 | 713 | |
ce51bde6 DE |
714 | /* initialize the seg registers */ |
715 | if (!cpu.cache) | |
716 | sim_csize (CSIZE); | |
ce51bde6 DE |
717 | } |
718 | } | |
719 | ||
720 | static void | |
721 | control_c (sig, code, scp, addr) | |
722 | int sig; | |
723 | int code; | |
724 | char *scp; | |
725 | char *addr; | |
726 | { | |
727 | cpu.exception = SIGINT; | |
728 | } | |
729 | ||
730 | #define C (c != 0) | |
731 | #define Z (nz == 0) | |
732 | #define V (v != 0) | |
733 | #define N (n != 0) | |
734 | ||
28655f00 | 735 | static int |
0693d363 | 736 | mop (code, bsize, sign) |
28655f00 SC |
737 | decoded_inst *code; |
738 | int bsize; | |
0693d363 DE |
739 | int sign; |
740 | { | |
741 | int multiplier; | |
742 | int multiplicand; | |
743 | int result; | |
744 | int n, nz; | |
745 | ||
746 | if (sign) | |
747 | { | |
748 | multiplicand = | |
749 | bsize ? SEXTCHAR (GET_W_REG (code->dst.reg)) : | |
750 | SEXTSHORT (GET_W_REG (code->dst.reg)); | |
751 | multiplier = | |
752 | bsize ? SEXTCHAR (GET_B_REG (code->src.reg)) : | |
753 | SEXTSHORT (GET_W_REG (code->src.reg)); | |
754 | } | |
755 | else | |
756 | { | |
757 | multiplicand = bsize ? UEXTCHAR (GET_W_REG (code->dst.reg)) : | |
758 | UEXTSHORT (GET_W_REG (code->dst.reg)); | |
759 | multiplier = | |
760 | bsize ? UEXTCHAR (GET_B_REG (code->src.reg)) : | |
761 | UEXTSHORT (GET_W_REG (code->src.reg)); | |
762 | ||
763 | } | |
764 | result = multiplier * multiplicand; | |
765 | ||
766 | if (sign) | |
767 | { | |
768 | n = result & (bsize ? 0x8000 : 0x80000000); | |
769 | nz = result & (bsize ? 0xffff : 0xffffffff); | |
770 | } | |
771 | if (bsize) | |
772 | { | |
773 | SET_W_REG (code->dst.reg, result); | |
774 | } | |
775 | else | |
776 | { | |
777 | SET_L_REG (code->dst.reg, result); | |
778 | } | |
779 | /* return ((n==1) << 1) | (nz==1); */ | |
780 | ||
781 | } | |
782 | ||
783 | #define OSHIFTS(name, how) \ | |
784 | case O(name, SB): \ | |
785 | { \ | |
786 | int t; \ | |
787 | int hm = 0x80; \ | |
788 | rd = GET_B_REG (code->src.reg); \ | |
789 | how; \ | |
790 | goto shift8; \ | |
791 | } \ | |
792 | case O(name, SW): \ | |
793 | { \ | |
794 | int t; \ | |
795 | int hm = 0x8000; \ | |
796 | rd = GET_W_REG (code->src.reg); \ | |
797 | how; \ | |
798 | goto shift16; \ | |
799 | } \ | |
800 | case O(name, SL): \ | |
801 | { \ | |
802 | int t; \ | |
803 | int hm = 0x80000000; \ | |
804 | rd = GET_L_REG (code->src.reg); \ | |
805 | how; \ | |
806 | goto shift32; \ | |
807 | } | |
808 | ||
809 | #define OBITOP(name,f, s, op) \ | |
810 | case O(name, SB): \ | |
811 | { \ | |
812 | int m; \ | |
813 | int b; \ | |
814 | if (f) ea = fetch (&code->dst); \ | |
815 | m=1<< fetch(&code->src); \ | |
816 | op; \ | |
817 | if(s) store (&code->dst,ea); goto next; \ | |
818 | } | |
28655f00 | 819 | |
7478904c | 820 | void |
a415cf0a | 821 | sim_resume (step, siggnal) |
ce51bde6 DE |
822 | { |
823 | static int init1; | |
824 | int cycles = 0; | |
825 | int insts = 0; | |
826 | int tick_start = get_now (); | |
827 | void (*prev) (); | |
0693d363 | 828 | int poll_count = 0; |
ce51bde6 DE |
829 | int res; |
830 | int tmp; | |
831 | int rd; | |
832 | int ea; | |
833 | int bit; | |
834 | int pc; | |
835 | int c, nz, v, n; | |
7478904c | 836 | int oldmask; |
ce51bde6 DE |
837 | init_pointers (); |
838 | ||
839 | prev = signal (SIGINT, control_c); | |
840 | ||
841 | if (step) | |
842 | { | |
843 | cpu.exception = SIGTRAP; | |
844 | } | |
845 | else | |
846 | { | |
847 | cpu.exception = 0; | |
848 | } | |
849 | ||
850 | pc = cpu.pc; | |
851 | ||
852 | GETSR (); | |
7478904c SC |
853 | oldmask = cpu.mask; |
854 | if (!h8300hmode) | |
855 | cpu.mask = 0xffff; | |
ce51bde6 DE |
856 | do |
857 | { | |
858 | int cidx; | |
859 | decoded_inst *code; | |
860 | ||
861 | top: | |
862 | cidx = cpu.cache_idx[pc]; | |
863 | code = cpu.cache + cidx; | |
864 | ||
865 | ||
866 | #define ALUOP(STORE, NAME, HOW) \ | |
867 | case O(NAME,SB): HOW; if(STORE)goto alu8;else goto just_flags_alu8; \ | |
868 | case O(NAME, SW): HOW; if(STORE)goto alu16;else goto just_flags_alu16; \ | |
869 | case O(NAME,SL): HOW; if(STORE)goto alu32;else goto just_flags_alu32; | |
870 | ||
871 | ||
872 | #define LOGOP(NAME, HOW) \ | |
873 | case O(NAME,SB): HOW; goto log8;\ | |
874 | case O(NAME, SW): HOW; goto log16;\ | |
875 | case O(NAME,SL): HOW; goto log32; | |
876 | ||
877 | ||
878 | ||
879 | #if ADEBUG | |
880 | if (debug) | |
881 | { | |
882 | printf ("%x %d %s\n", pc, code->opcode, | |
883 | code->op ? code->op->name : "**"); | |
884 | } | |
885 | cpu.stats[code->opcode]++; | |
0693d363 | 886 | |
ce51bde6 DE |
887 | #endif |
888 | ||
889 | cycles += code->cycles; | |
890 | insts++; | |
891 | switch (code->opcode) | |
892 | { | |
893 | case 0: | |
894 | /* | |
895 | * This opcode is a fake for when we get to an | |
896 | * instruction which hasnt been compiled | |
897 | */ | |
898 | compile (pc); | |
899 | goto top; | |
900 | break; | |
901 | ||
902 | ||
903 | case O (O_SUBX, SB): | |
904 | rd = fetch (&code->dst); | |
905 | ea = fetch (&code->src); | |
0693d363 | 906 | ea = -(ea + C); |
ce51bde6 DE |
907 | res = rd + ea; |
908 | goto alu8; | |
909 | ||
910 | case O (O_ADDX, SB): | |
911 | rd = fetch (&code->dst); | |
912 | ea = fetch (&code->src); | |
913 | ea = C + ea; | |
914 | res = rd + ea; | |
915 | goto alu8; | |
916 | ||
cf5b4aa6 DE |
917 | #define EA ea = fetch(&code->src); |
918 | #define RD_EA ea = fetch(&code->src); rd = fetch(&code->dst); | |
ce51bde6 | 919 | |
0693d363 DE |
920 | ALUOP (1, O_SUB, RD_EA; |
921 | ea = -ea; | |
922 | res = rd + ea); | |
923 | ALUOP (1, O_NEG, EA; | |
924 | ea = -ea; | |
925 | rd = 0; | |
926 | res = rd + ea); | |
ce51bde6 | 927 | |
0693d363 DE |
928 | case O (O_ADD, SB): |
929 | rd = GET_B_REG (code->dst.reg); | |
930 | ea = fetch (&code->src); | |
ce51bde6 DE |
931 | res = rd + ea; |
932 | goto alu8; | |
0693d363 DE |
933 | case O (O_ADD, SW): |
934 | rd = GET_W_REG (code->dst.reg); | |
935 | ea = fetch (&code->src); | |
ce51bde6 DE |
936 | res = rd + ea; |
937 | goto alu16; | |
0693d363 DE |
938 | case O (O_ADD, SL): |
939 | rd = GET_L_REG (code->dst.reg); | |
940 | ea = fetch (&code->src); | |
ce51bde6 DE |
941 | res = rd + ea; |
942 | goto alu32; | |
ce51bde6 | 943 | |
ce51bde6 | 944 | |
0693d363 DE |
945 | LOGOP (O_AND, RD_EA; |
946 | res = rd & ea); | |
947 | ||
948 | LOGOP (O_OR, RD_EA; | |
949 | res = rd | ea); | |
ce51bde6 | 950 | |
0693d363 DE |
951 | LOGOP (O_XOR, RD_EA; |
952 | res = rd ^ ea); | |
ce51bde6 DE |
953 | |
954 | ||
0693d363 DE |
955 | case O (O_MOV_TO_MEM, SB): |
956 | res = GET_B_REG (code->src.reg); | |
ce51bde6 | 957 | goto log8; |
0693d363 DE |
958 | case O (O_MOV_TO_MEM, SW): |
959 | res = GET_W_REG (code->src.reg); | |
ce51bde6 | 960 | goto log16; |
0693d363 DE |
961 | case O (O_MOV_TO_MEM, SL): |
962 | res = GET_L_REG (code->src.reg); | |
ce51bde6 DE |
963 | goto log32; |
964 | ||
965 | ||
0693d363 DE |
966 | case O (O_MOV_TO_REG, SB): |
967 | res = fetch (&code->src); | |
968 | SET_B_REG (code->dst.reg, res); | |
ce51bde6 | 969 | goto just_flags_log8; |
0693d363 DE |
970 | case O (O_MOV_TO_REG, SW): |
971 | res = fetch (&code->src); | |
972 | SET_W_REG (code->dst.reg, res); | |
ce51bde6 | 973 | goto just_flags_log16; |
0693d363 DE |
974 | case O (O_MOV_TO_REG, SL): |
975 | res = fetch (&code->src); | |
976 | SET_L_REG (code->dst.reg, res); | |
ce51bde6 DE |
977 | goto just_flags_log32; |
978 | ||
979 | ||
0693d363 DE |
980 | case O (O_ADDS, SL): |
981 | SET_L_REG (code->dst.reg, | |
982 | GET_L_REG (code->dst.reg) | |
983 | + code->src.literal); | |
984 | ||
ce51bde6 DE |
985 | goto next; |
986 | ||
0693d363 DE |
987 | case O (O_SUBS, SL): |
988 | SET_L_REG (code->dst.reg, | |
989 | GET_L_REG (code->dst.reg) | |
990 | - code->src.literal); | |
ce51bde6 | 991 | goto next; |
0693d363 | 992 | |
ce51bde6 DE |
993 | case O (O_CMP, SB): |
994 | rd = fetch (&code->dst); | |
995 | ea = fetch (&code->src); | |
996 | ea = -ea; | |
997 | res = rd + ea; | |
998 | goto just_flags_alu8; | |
999 | ||
1000 | case O (O_CMP, SW): | |
1001 | rd = fetch (&code->dst); | |
1002 | ea = fetch (&code->src); | |
1003 | ea = -ea; | |
1004 | res = rd + ea; | |
1005 | goto just_flags_alu16; | |
1006 | ||
1007 | case O (O_CMP, SL): | |
1008 | rd = fetch (&code->dst); | |
1009 | ea = fetch (&code->src); | |
1010 | ea = -ea; | |
1011 | res = rd + ea; | |
1012 | goto just_flags_alu32; | |
1013 | ||
1014 | ||
1015 | case O (O_DEC, SB): | |
1016 | rd = GET_B_REG (code->src.reg); | |
1017 | ea = -1; | |
1018 | res = rd + ea; | |
1019 | SET_B_REG (code->src.reg, res); | |
1020 | goto just_flags_inc8; | |
1021 | ||
1022 | case O (O_DEC, SW): | |
1023 | rd = GET_W_REG (code->dst.reg); | |
0693d363 | 1024 | ea = -code->src.literal; |
ce51bde6 DE |
1025 | res = rd + ea; |
1026 | SET_W_REG (code->dst.reg, res); | |
1027 | goto just_flags_inc16; | |
1028 | ||
1029 | case O (O_DEC, SL): | |
1030 | rd = GET_L_REG (code->dst.reg); | |
1031 | ea = -code->src.literal; | |
1032 | res = rd + ea; | |
1033 | SET_L_REG (code->dst.reg, res); | |
1034 | goto just_flags_inc32; | |
1035 | ||
1036 | ||
1037 | case O (O_INC, SB): | |
1038 | rd = GET_B_REG (code->src.reg); | |
1039 | ea = 1; | |
1040 | res = rd + ea; | |
1041 | SET_B_REG (code->src.reg, res); | |
1042 | goto just_flags_inc8; | |
1043 | ||
1044 | case O (O_INC, SW): | |
1045 | rd = GET_W_REG (code->dst.reg); | |
1046 | ea = code->src.literal; | |
1047 | res = rd + ea; | |
1048 | SET_W_REG (code->dst.reg, res); | |
1049 | goto just_flags_inc16; | |
1050 | ||
1051 | case O (O_INC, SL): | |
1052 | rd = GET_L_REG (code->dst.reg); | |
1053 | ea = code->src.literal; | |
1054 | res = rd + ea; | |
1055 | SET_L_REG (code->dst.reg, res); | |
1056 | goto just_flags_inc32; | |
1057 | ||
1058 | ||
1059 | #define GET_CCR(x) BUILDSR();x = cpu.ccr | |
0693d363 | 1060 | |
ce51bde6 DE |
1061 | case O (O_ANDC, SB): |
1062 | GET_CCR (rd); | |
1063 | ea = code->src.literal; | |
1064 | res = rd & ea; | |
1065 | goto setc; | |
1066 | ||
0693d363 DE |
1067 | case O (O_ORC, SB): |
1068 | GET_CCR (rd); | |
1069 | ea = code->src.literal; | |
1070 | res = rd | ea; | |
1071 | goto setc; | |
1072 | ||
1073 | case O (O_XORC, SB): | |
1074 | GET_CCR (rd); | |
1075 | ea = code->src.literal; | |
1076 | res = rd ^ ea; | |
1077 | goto setc; | |
1078 | ||
ce51bde6 DE |
1079 | |
1080 | case O (O_BRA, SB): | |
1081 | if (1) | |
1082 | goto condtrue; | |
1083 | goto next; | |
1084 | ||
1085 | case O (O_BRN, SB): | |
1086 | if (0) | |
1087 | goto condtrue; | |
1088 | goto next; | |
1089 | ||
1090 | case O (O_BHI, SB): | |
1091 | if ((C || Z) == 0) | |
1092 | goto condtrue; | |
1093 | goto next; | |
1094 | ||
1095 | ||
1096 | case O (O_BLS, SB): | |
1097 | if ((C || Z)) | |
1098 | goto condtrue; | |
1099 | goto next; | |
1100 | ||
1101 | case O (O_BCS, SB): | |
1102 | if ((C == 1)) | |
1103 | goto condtrue; | |
1104 | goto next; | |
1105 | ||
1106 | case O (O_BCC, SB): | |
1107 | if ((C == 0)) | |
1108 | goto condtrue; | |
1109 | goto next; | |
1110 | ||
1111 | case O (O_BEQ, SB): | |
1112 | if (Z) | |
1113 | goto condtrue; | |
1114 | goto next; | |
1115 | case O (O_BGT, SB): | |
1116 | if (((Z || (N ^ V)) == 0)) | |
1117 | goto condtrue; | |
1118 | goto next; | |
1119 | ||
1120 | ||
1121 | case O (O_BLE, SB): | |
1122 | if (((Z || (N ^ V)) == 1)) | |
1123 | goto condtrue; | |
1124 | goto next; | |
1125 | ||
1126 | case O (O_BGE, SB): | |
1127 | if ((N ^ V) == 0) | |
1128 | goto condtrue; | |
1129 | goto next; | |
1130 | case O (O_BLT, SB): | |
1131 | if ((N ^ V)) | |
1132 | goto condtrue; | |
1133 | goto next; | |
1134 | case O (O_BMI, SB): | |
1135 | if ((N)) | |
1136 | goto condtrue; | |
1137 | goto next; | |
1138 | case O (O_BNE, SB): | |
1139 | if ((Z == 0)) | |
1140 | goto condtrue; | |
1141 | goto next; | |
1142 | ||
1143 | case O (O_BPL, SB): | |
1144 | if (N == 0) | |
1145 | goto condtrue; | |
1146 | goto next; | |
1147 | case O (O_BVC, SB): | |
1148 | if ((V == 0)) | |
1149 | goto condtrue; | |
1150 | goto next; | |
1151 | case O (O_BVS, SB): | |
1152 | if ((V == 1)) | |
1153 | goto condtrue; | |
1154 | goto next; | |
1155 | ||
0693d363 DE |
1156 | case O (O_SYSCALL, SB): |
1157 | printf ("%c", cpu.regs[2]); | |
ce51bde6 | 1158 | goto next; |
ce51bde6 | 1159 | |
0693d363 DE |
1160 | OSHIFTS (O_NOT, rd = ~rd); |
1161 | OSHIFTS (O_SHLL, c = rd & hm; | |
1162 | rd <<= 1); | |
1163 | OSHIFTS (O_SHLR, c = rd & 1; | |
1164 | rd = (unsigned int) rd >> 1); | |
1165 | OSHIFTS (O_SHAL, c = rd & hm; | |
1166 | rd <<= 1); | |
1167 | OSHIFTS (O_SHAR, t = rd & hm; | |
1168 | c = rd & 1; | |
1169 | rd >>= 1; | |
1170 | rd |= t; | |
7478904c | 1171 | ); |
0693d363 DE |
1172 | OSHIFTS (O_ROTL, c = rd & hm; |
1173 | rd <<= 1; | |
1174 | rd |= C); | |
1175 | OSHIFTS (O_ROTR, c = rd & 1; | |
1176 | rd = (unsigned int) rd >> 1; | |
1177 | if (c) rd |= hm;); | |
1178 | OSHIFTS (O_ROTXL, t = rd & hm; | |
1179 | rd <<= 1; | |
1180 | rd |= C; | |
1181 | c = t; | |
7478904c | 1182 | ); |
0693d363 DE |
1183 | OSHIFTS (O_ROTXR, t = rd & 1; |
1184 | rd = (unsigned int) rd >> 1; | |
1185 | if (C) rd |= hm; c = t;); | |
1186 | ||
1187 | case O (O_JMP, SB): | |
ce51bde6 DE |
1188 | { |
1189 | pc = fetch (&code->src); | |
1190 | goto end; | |
0693d363 | 1191 | |
ce51bde6 | 1192 | } |
0693d363 | 1193 | |
ce51bde6 DE |
1194 | case O (O_JSR, SB): |
1195 | { | |
1196 | int tmp; | |
1197 | pc = fetch (&code->src); | |
1198 | call: | |
1199 | tmp = cpu.regs[7]; | |
1200 | ||
28655f00 | 1201 | if (h8300hmode) |
ce51bde6 DE |
1202 | { |
1203 | tmp -= 4; | |
1204 | SET_MEMORY_L (tmp, code->next_pc); | |
1205 | } | |
1206 | else | |
1207 | { | |
1208 | tmp -= 2; | |
1209 | SET_MEMORY_W (tmp, code->next_pc); | |
1210 | } | |
1211 | cpu.regs[7] = tmp; | |
1212 | ||
1213 | goto end; | |
1214 | } | |
0693d363 | 1215 | case O (O_BSR, SB): |
ce51bde6 DE |
1216 | pc = code->src.literal; |
1217 | goto call; | |
0693d363 | 1218 | |
ce51bde6 DE |
1219 | case O (O_RTS, SB): |
1220 | { | |
1221 | int tmp; | |
1222 | ||
ce51bde6 DE |
1223 | tmp = cpu.regs[7]; |
1224 | ||
28655f00 | 1225 | if (h8300hmode) |
ce51bde6 DE |
1226 | { |
1227 | pc = GET_MEMORY_L (tmp); | |
1228 | tmp += 4; | |
ce51bde6 DE |
1229 | } |
1230 | else | |
1231 | { | |
1232 | pc = GET_MEMORY_W (tmp); | |
1233 | tmp += 2; | |
1234 | } | |
1235 | ||
1236 | cpu.regs[7] = tmp; | |
1237 | goto end; | |
1238 | } | |
1239 | ||
1240 | case O (O_ILL, SB): | |
1241 | cpu.exception = SIGILL; | |
1242 | goto end; | |
0693d363 DE |
1243 | case O (O_SLEEP, SB): |
1244 | case O (O_BPT, SB): | |
ce51bde6 DE |
1245 | cpu.exception = SIGTRAP; |
1246 | goto end; | |
1247 | ||
0693d363 DE |
1248 | OBITOP (O_BNOT, 1, 1, ea ^= m); |
1249 | OBITOP (O_BTST, 1, 0, nz = ea & m); | |
1250 | OBITOP (O_BCLR, 1, 1, ea &= ~m); | |
1251 | OBITOP (O_BSET, 1, 1, ea |= m); | |
1252 | OBITOP (O_BLD, 1, 0, c = ea & m); | |
1253 | OBITOP (O_BILD, 1, 0, c = !(ea & m)); | |
1254 | OBITOP (O_BST, 1, 1, ea &= ~m; | |
1255 | if (C) ea |= m); | |
1256 | OBITOP (O_BIST, 1, 1, ea &= ~m; | |
1257 | if (!C) ea |= m); | |
1258 | OBITOP (O_BAND, 1, 0, c = (ea & m) && C); | |
1259 | OBITOP (O_BIAND, 1, 0, c = !(ea & m) && C); | |
1260 | OBITOP (O_BOR, 1, 0, c = (ea & m) || C); | |
1261 | OBITOP (O_BIOR, 1, 0, c = !(ea & m) || C); | |
1262 | OBITOP (O_BXOR, 1, 0, c = (ea & m) != C); | |
1263 | OBITOP (O_BIXOR, 1, 0, c = !(ea & m) != C); | |
ce51bde6 DE |
1264 | |
1265 | ||
28655f00 | 1266 | #define MOP(bsize, signed) mop(code, bsize,signed); goto next; |
ce51bde6 | 1267 | |
0693d363 DE |
1268 | case O (O_MULS, SB): |
1269 | MOP (1, 1); | |
1270 | break; | |
1271 | case O (O_MULS, SW): | |
1272 | MOP (0, 1); | |
1273 | break; | |
1274 | case O (O_MULU, SB): | |
1275 | MOP (1, 0); | |
1276 | break; | |
1277 | case O (O_MULU, SW): | |
1278 | MOP (0, 0); | |
1279 | break; | |
ce51bde6 | 1280 | |
ce51bde6 | 1281 | |
0693d363 DE |
1282 | case O (O_DIVU, SB): |
1283 | { | |
1284 | rd = GET_W_REG (code->dst.reg); | |
1285 | ea = GET_B_REG (code->src.reg); | |
1286 | if (ea) | |
1287 | { | |
1288 | tmp = rd % ea; | |
1289 | rd = rd / ea; | |
1290 | } | |
1291 | SET_W_REG (code->dst.reg, (rd & 0xff) | (tmp << 8)); | |
1292 | n = ea & 0x80; | |
1293 | nz = ea & 0xff; | |
ce51bde6 | 1294 | |
0693d363 DE |
1295 | goto next; |
1296 | } | |
1297 | case O (O_DIVU, SW): | |
1298 | { | |
1299 | rd = GET_L_REG (code->dst.reg); | |
1300 | ea = GET_W_REG (code->src.reg); | |
1301 | n = ea & 0x8000; | |
1302 | nz = ea & 0xffff; | |
1303 | if (ea) | |
1304 | { | |
1305 | tmp = rd % ea; | |
1306 | rd = rd / ea; | |
1307 | } | |
1308 | SET_L_REG (code->dst.reg, (rd & 0xffff) | (tmp << 16)); | |
1309 | goto next; | |
1310 | } | |
ce51bde6 | 1311 | |
0693d363 DE |
1312 | case O (O_DIVS, SB): |
1313 | { | |
ce51bde6 | 1314 | |
0693d363 DE |
1315 | rd = SEXTSHORT (GET_W_REG (code->dst.reg)); |
1316 | ea = SEXTCHAR (GET_B_REG (code->src.reg)); | |
1317 | if (ea) | |
1318 | { | |
1319 | tmp = (int) rd % (int) ea; | |
1320 | rd = (int) rd / (int) ea; | |
1321 | n = rd & 0x8000; | |
1322 | nz = 1; | |
1323 | } | |
1324 | else | |
1325 | nz = 0; | |
1326 | SET_W_REG (code->dst.reg, (rd & 0xff) | (tmp << 8)); | |
1327 | goto next; | |
1328 | } | |
1329 | case O (O_DIVS, SW): | |
1330 | { | |
1331 | rd = GET_L_REG (code->dst.reg); | |
1332 | ea = SEXTSHORT (GET_W_REG (code->src.reg)); | |
1333 | if (ea) | |
1334 | { | |
1335 | tmp = (int) rd % (int) ea; | |
1336 | rd = (int) rd / (int) ea; | |
1337 | n = rd & 0x80000000; | |
1338 | nz = 1; | |
1339 | } | |
1340 | else | |
1341 | nz = 0; | |
1342 | SET_L_REG (code->dst.reg, (rd & 0xffff) | (tmp << 16)); | |
1343 | goto next; | |
1344 | } | |
1345 | case O (O_EXTS, SW): | |
7478904c | 1346 | rd = GET_B_REG (code->src.reg + 8) & 0xff; /* Yes, src, not dst. */ |
0693d363 DE |
1347 | ea = rd & 0x80 ? -256 : 0; |
1348 | res = rd + ea; | |
1349 | goto log16; | |
1350 | case O (O_EXTS, SL): | |
1351 | rd = GET_W_REG (code->src.reg) & 0xffff; | |
1352 | ea = rd & 0x8000 ? -65536 : 0; | |
1353 | res = rd + ea; | |
1354 | goto log32; | |
1355 | case O (O_EXTU, SW): | |
1356 | rd = GET_B_REG (code->src.reg + 8) & 0xff; | |
1357 | ea = 0; | |
1358 | res = rd + ea; | |
1359 | goto log16; | |
1360 | case O (O_EXTU, SL): | |
1361 | rd = GET_W_REG (code->src.reg) & 0xffff; | |
1362 | ea = 0; | |
1363 | res = rd + ea; | |
1364 | goto log32; | |
ce51bde6 | 1365 | |
0693d363 DE |
1366 | case O (O_NOP, SB): |
1367 | goto next; | |
ce51bde6 | 1368 | |
0693d363 | 1369 | default: |
7478904c | 1370 | cpu.exception = SIGILL; |
0693d363 | 1371 | goto end; |
ce51bde6 DE |
1372 | |
1373 | } | |
0693d363 DE |
1374 | abort (); |
1375 | ||
1376 | setc: | |
1377 | cpu.ccr = res; | |
1378 | GETSR (); | |
28655f00 SC |
1379 | goto next; |
1380 | ||
0693d363 DE |
1381 | condtrue: |
1382 | /* When a branch works */ | |
1383 | pc = code->src.literal; | |
ce51bde6 DE |
1384 | goto end; |
1385 | ||
0693d363 DE |
1386 | /* Set the cond codes from res */ |
1387 | bitop: | |
ce51bde6 | 1388 | |
0693d363 DE |
1389 | /* Set the flags after an 8 bit inc/dec operation */ |
1390 | just_flags_inc8: | |
1391 | n = res & 0x80; | |
1392 | nz = res & 0xff; | |
1393 | v = (rd & 0x7f) == 0x7f; | |
1394 | goto next; | |
ce51bde6 | 1395 | |
ce51bde6 | 1396 | |
0693d363 DE |
1397 | /* Set the flags after an 16 bit inc/dec operation */ |
1398 | just_flags_inc16: | |
1399 | n = res & 0x8000; | |
1400 | nz = res & 0xffff; | |
1401 | v = (rd & 0x7fff) == 0x7fff; | |
1402 | goto next; | |
1403 | ||
1404 | ||
1405 | /* Set the flags after an 32 bit inc/dec operation */ | |
1406 | just_flags_inc32: | |
1407 | n = res & 0x80000000; | |
1408 | nz = res & 0xffffffff; | |
1409 | v = (rd & 0x7fffffff) == 0x7fffffff; | |
1410 | goto next; | |
1411 | ||
1412 | ||
1413 | shift8: | |
1414 | /* Set flags after an 8 bit shift op, carry set in insn */ | |
1415 | n = (rd & 0x80); | |
1416 | v = 0; | |
1417 | nz = rd & 0xff; | |
1418 | SET_B_REG (code->src.reg, rd); | |
1419 | goto next; | |
1420 | ||
1421 | ||
1422 | shift16: | |
1423 | /* Set flags after an 16 bit shift op, carry set in insn */ | |
1424 | n = (rd & 0x8000); | |
1425 | v = 0; | |
1426 | nz = rd & 0xffff; | |
1427 | ||
1428 | SET_W_REG (code->src.reg, rd); | |
1429 | goto next; | |
1430 | ||
1431 | shift32: | |
1432 | /* Set flags after an 32 bit shift op, carry set in insn */ | |
1433 | n = (rd & 0x80000000); | |
1434 | v = 0; | |
1435 | nz = rd & 0xffffffff; | |
1436 | SET_L_REG (code->src.reg, rd); | |
1437 | goto next; | |
1438 | ||
1439 | log32: | |
1440 | store (&code->dst, res); | |
1441 | just_flags_log32: | |
1442 | /* flags after a 32bit logical operation */ | |
1443 | n = res & 0x80000000; | |
1444 | nz = res & 0xffffffff; | |
1445 | v = 0; | |
1446 | goto next; | |
1447 | ||
1448 | log16: | |
1449 | store (&code->dst, res); | |
1450 | just_flags_log16: | |
1451 | /* flags after a 16bit logical operation */ | |
1452 | n = res & 0x8000; | |
1453 | nz = res & 0xffff; | |
1454 | v = 0; | |
1455 | goto next; | |
1456 | ||
1457 | ||
1458 | log8: | |
1459 | store (&code->dst, res); | |
1460 | just_flags_log8: | |
1461 | n = res & 0x80; | |
1462 | nz = res & 0xff; | |
1463 | v = 0; | |
1464 | goto next; | |
1465 | ||
1466 | alu8: | |
1467 | SET_B_REG (code->dst.reg, res); | |
1468 | just_flags_alu8: | |
1469 | n = res & 0x80; | |
1470 | nz = res & 0xff; | |
1471 | v = ((ea & 0x80) == (rd & 0x80)) && ((ea & 0x80) != (res & 0x80)); | |
1472 | c = (res & 0x100); | |
1473 | goto next; | |
1474 | ||
1475 | alu16: | |
1476 | SET_W_REG (code->dst.reg, res); | |
1477 | just_flags_alu16: | |
1478 | n = res & 0x8000; | |
1479 | nz = res & 0xffff; | |
1480 | v = ((ea & 0x8000) == (rd & 0x8000)) && ((ea & 0x8000) != (res & 0x8000)); | |
1481 | c = (res & 0x10000); | |
1482 | goto next; | |
1483 | ||
1484 | alu32: | |
1485 | SET_L_REG (code->dst.reg, res); | |
1486 | just_flags_alu32: | |
1487 | n = res & 0x80000000; | |
1488 | nz = res & 0xffffffff; | |
1489 | v = ((ea & 0x80000000) == (rd & 0x80000000)) | |
1490 | && ((ea & 0x80000000) != (res & 0x80000000)); | |
1491 | switch (code->opcode / 4) | |
1492 | { | |
1493 | case O_ADD: | |
1494 | c = ((unsigned) res < (unsigned) rd) || ((unsigned) res < (unsigned) ea); | |
1495 | break; | |
1496 | case O_SUB: | |
1497 | case O_CMP: | |
1498 | c = (unsigned) rd < (unsigned) -ea; | |
1499 | break; | |
1500 | case O_NEG: | |
1501 | c = res != 0; | |
1502 | break; | |
1503 | } | |
1504 | goto next; | |
1505 | ||
1506 | next:; | |
1507 | pc = code->next_pc; | |
1508 | ||
1509 | end: | |
1510 | ; | |
1511 | /* if (cpu.regs[8] ) abort(); */ | |
1512 | ||
7478904c SC |
1513 | #if defined (WIN32) |
1514 | /* Poll after every 100th insn, */ | |
1515 | if (poll_count++ > 100) | |
1516 | { | |
1517 | poll_count = 0; | |
1518 | if (win32pollquit()) | |
1519 | { | |
1520 | control_c(); | |
1521 | } | |
1522 | } | |
1523 | #endif | |
1524 | #if defined(__GO32__) | |
0693d363 DE |
1525 | /* Poll after every 100th insn, */ |
1526 | if (poll_count++ > 100) | |
1527 | { | |
1528 | poll_count = 0; | |
1529 | if (kbhit ()) | |
1530 | { | |
1531 | int c = getkey (); | |
1532 | control_c (); | |
1533 | } | |
1534 | } | |
1535 | #endif | |
1536 | ||
1537 | } | |
ce51bde6 DE |
1538 | while (!cpu.exception); |
1539 | cpu.ticks += get_now () - tick_start; | |
1540 | cpu.cycles += cycles; | |
1541 | cpu.insts += insts; | |
7478904c | 1542 | |
ce51bde6 DE |
1543 | cpu.pc = pc; |
1544 | BUILDSR (); | |
7478904c | 1545 | cpu.mask = oldmask; |
ce51bde6 DE |
1546 | signal (SIGINT, prev); |
1547 | } | |
1548 | ||
1549 | ||
28655f00 | 1550 | int |
ce51bde6 | 1551 | sim_write (addr, buffer, size) |
a415cf0a | 1552 | SIM_ADDR addr; |
ce51bde6 DE |
1553 | unsigned char *buffer; |
1554 | int size; | |
1555 | { | |
1556 | int i; | |
1557 | ||
1558 | init_pointers (); | |
1559 | if (addr < 0 || addr + size > MSIZE) | |
a415cf0a | 1560 | return 0; |
ce51bde6 DE |
1561 | for (i = 0; i < size; i++) |
1562 | { | |
1563 | cpu.memory[addr + i] = buffer[i]; | |
1564 | cpu.cache_idx[addr + i] = 0; | |
1565 | } | |
a415cf0a | 1566 | return size; |
ce51bde6 DE |
1567 | } |
1568 | ||
28655f00 | 1569 | int |
ce51bde6 | 1570 | sim_read (addr, buffer, size) |
a415cf0a DE |
1571 | SIM_ADDR addr; |
1572 | unsigned char *buffer; | |
ce51bde6 DE |
1573 | int size; |
1574 | { | |
1575 | init_pointers (); | |
1576 | if (addr < 0 || addr + size > MSIZE) | |
a415cf0a | 1577 | return 0; |
ce51bde6 | 1578 | memcpy (buffer, cpu.memory + addr, size); |
28655f00 | 1579 | return size; |
ce51bde6 DE |
1580 | } |
1581 | ||
1582 | ||
ce51bde6 DE |
1583 | #define R0_REGNUM 0 |
1584 | #define R1_REGNUM 1 | |
1585 | #define R2_REGNUM 2 | |
1586 | #define R3_REGNUM 3 | |
1587 | #define R4_REGNUM 4 | |
1588 | #define R5_REGNUM 5 | |
1589 | #define R6_REGNUM 6 | |
1590 | #define R7_REGNUM 7 | |
1591 | ||
1592 | #define SP_REGNUM R7_REGNUM /* Contains address of top of stack */ | |
1593 | #define FP_REGNUM R6_REGNUM /* Contains address of executing | |
0693d363 | 1594 | * stack frame */ |
ce51bde6 DE |
1595 | |
1596 | #define CCR_REGNUM 8 /* Contains processor status */ | |
1597 | #define PC_REGNUM 9 /* Contains program counter */ | |
1598 | ||
1599 | #define CYCLE_REGNUM 10 | |
1600 | #define INST_REGNUM 11 | |
1601 | #define TICK_REGNUM 12 | |
1602 | ||
1603 | ||
7478904c | 1604 | void |
ce51bde6 DE |
1605 | sim_store_register (rn, value) |
1606 | int rn; | |
28655f00 | 1607 | unsigned char *value; |
ce51bde6 | 1608 | { |
28655f00 SC |
1609 | int longval; |
1610 | int shortval; | |
1611 | int intval; | |
0693d363 DE |
1612 | longval = (value[0] << 24) | (value[1] << 16) | (value[2] << 8) | value[3]; |
1613 | shortval = (value[0] << 8) | (value[1]); | |
28655f00 | 1614 | intval = h8300hmode ? longval : shortval; |
ce51bde6 DE |
1615 | |
1616 | init_pointers (); | |
1617 | switch (rn) | |
1618 | { | |
1619 | case PC_REGNUM: | |
28655f00 | 1620 | cpu.pc = intval; |
ce51bde6 DE |
1621 | break; |
1622 | default: | |
1623 | abort (); | |
1624 | case R0_REGNUM: | |
1625 | case R1_REGNUM: | |
1626 | case R2_REGNUM: | |
1627 | case R3_REGNUM: | |
1628 | case R4_REGNUM: | |
1629 | case R5_REGNUM: | |
1630 | case R6_REGNUM: | |
1631 | case R7_REGNUM: | |
28655f00 | 1632 | cpu.regs[rn] = intval; |
ce51bde6 DE |
1633 | break; |
1634 | case CCR_REGNUM: | |
28655f00 | 1635 | cpu.ccr = intval; |
ce51bde6 DE |
1636 | break; |
1637 | case CYCLE_REGNUM: | |
28655f00 | 1638 | cpu.cycles = longval; |
ce51bde6 DE |
1639 | break; |
1640 | ||
1641 | case INST_REGNUM: | |
28655f00 | 1642 | cpu.insts = longval; |
ce51bde6 DE |
1643 | break; |
1644 | ||
1645 | case TICK_REGNUM: | |
28655f00 | 1646 | cpu.ticks = longval; |
ce51bde6 DE |
1647 | break; |
1648 | } | |
1649 | } | |
1650 | ||
7478904c | 1651 | void |
ce51bde6 DE |
1652 | sim_fetch_register (rn, buf) |
1653 | int rn; | |
a415cf0a | 1654 | unsigned char *buf; |
ce51bde6 DE |
1655 | { |
1656 | int v; | |
1657 | int longreg = 0; | |
1658 | ||
1659 | init_pointers (); | |
1660 | ||
1661 | switch (rn) | |
1662 | { | |
1663 | default: | |
1664 | abort (); | |
1665 | case 8: | |
1666 | v = cpu.ccr; | |
1667 | break; | |
1668 | case 9: | |
1669 | v = cpu.pc; | |
1670 | break; | |
1671 | case R0_REGNUM: | |
1672 | case R1_REGNUM: | |
1673 | case R2_REGNUM: | |
1674 | case R3_REGNUM: | |
1675 | case R4_REGNUM: | |
1676 | case R5_REGNUM: | |
1677 | case R6_REGNUM: | |
1678 | case R7_REGNUM: | |
1679 | v = cpu.regs[rn]; | |
1680 | break; | |
1681 | case 10: | |
1682 | v = cpu.cycles; | |
1683 | longreg = 1; | |
ce51bde6 DE |
1684 | break; |
1685 | case 11: | |
1686 | v = cpu.ticks; | |
1687 | longreg = 1; | |
1688 | break; | |
1689 | case 12: | |
1690 | v = cpu.insts; | |
1691 | longreg = 1; | |
1692 | break; | |
ce51bde6 | 1693 | } |
28655f00 | 1694 | if (h8300hmode || longreg) |
ce51bde6 DE |
1695 | { |
1696 | buf[0] = v >> 24; | |
1697 | buf[1] = v >> 16; | |
1698 | buf[2] = v >> 8; | |
1699 | buf[3] = v >> 0; | |
1700 | } | |
1701 | else | |
1702 | { | |
1703 | buf[0] = v >> 8; | |
1704 | buf[1] = v; | |
1705 | } | |
1706 | } | |
1707 | ||
7478904c | 1708 | void |
a415cf0a DE |
1709 | sim_stop_reason (reason, sigrc) |
1710 | enum sim_stop *reason; | |
1711 | int *sigrc; | |
ce51bde6 | 1712 | { |
a415cf0a | 1713 | *reason = sim_stopped; |
7db9345b | 1714 | *sigrc = cpu.exception; |
ce51bde6 DE |
1715 | } |
1716 | ||
ce51bde6 DE |
1717 | sim_csize (n) |
1718 | { | |
1719 | if (cpu.cache) | |
1720 | free (cpu.cache); | |
1721 | if (n < 2) | |
1722 | n = 2; | |
1723 | cpu.cache = (decoded_inst *) malloc (sizeof (decoded_inst) * n); | |
1724 | memset (cpu.cache, 0, sizeof (decoded_inst) * n); | |
1725 | cpu.csize = n; | |
1726 | } | |
1727 | ||
1728 | ||
7478904c SC |
1729 | void |
1730 | sim_info (verbose) | |
ce51bde6 | 1731 | int verbose; |
ce51bde6 DE |
1732 | { |
1733 | double timetaken = (double) cpu.ticks / (double) now_persec (); | |
1734 | double virttime = cpu.cycles / 10.0e6; | |
1735 | ||
7478904c SC |
1736 | printf_filtered ("\n\n#instructions executed %10d\n", cpu.insts); |
1737 | printf_filtered ("#cycles (v approximate) %10d\n", cpu.cycles); | |
1738 | printf_filtered ("#real time taken %10.4f\n", timetaken); | |
1739 | printf_filtered ("#virtual time taked %10.4f\n", virttime); | |
0693d363 | 1740 | if (timetaken != 0.0) |
7478904c SC |
1741 | printf_filtered ("#simulation ratio %10.4f\n", virttime / timetaken); |
1742 | printf_filtered ("#compiles %10d\n", cpu.compiles); | |
1743 | printf_filtered ("#cache size %10d\n", cpu.csize); | |
ce51bde6 DE |
1744 | |
1745 | #ifdef ADEBUG | |
0693d363 | 1746 | if (verbose) |
ce51bde6 DE |
1747 | { |
1748 | int i; | |
0693d363 | 1749 | for (i = 0; i < O_LAST; i++) |
ce51bde6 DE |
1750 | { |
1751 | if (cpu.stats[i]) | |
7478904c | 1752 | printf_filtered ("%d: %d\n", i, cpu.stats[i]); |
ce51bde6 DE |
1753 | } |
1754 | } | |
1755 | #endif | |
1756 | } | |
1757 | ||
7478904c SC |
1758 | /* Indicate whether the cpu is an h8/300 or h8/300h. |
1759 | FLAG is non-zero for the h8/300h. */ | |
1760 | ||
89a2c4fd | 1761 | void |
7478904c SC |
1762 | set_h8300h (flag) |
1763 | int flag; | |
89a2c4fd | 1764 | { |
7478904c | 1765 | h8300hmode = flag; |
89a2c4fd | 1766 | } |
28655f00 | 1767 | |
7478904c | 1768 | void |
0693d363 | 1769 | sim_kill () |
7db9345b | 1770 | { |
7478904c | 1771 | /* nothing to do */ |
7db9345b DE |
1772 | } |
1773 | ||
7478904c SC |
1774 | void |
1775 | sim_open (args) | |
1776 | char *args; | |
7db9345b | 1777 | { |
7478904c | 1778 | /* nothing to do */ |
7db9345b DE |
1779 | } |
1780 | ||
7478904c SC |
1781 | void |
1782 | sim_close (quitting) | |
1783 | int quitting; | |
1784 | { | |
1785 | /* nothing to do */ | |
1786 | } | |
1787 | ||
1788 | /* Called by gdb to load a program into memory. */ | |
1789 | ||
1790 | int | |
1791 | sim_load (prog, from_tty) | |
1792 | char *prog; | |
1793 | int from_tty; | |
1794 | { | |
1795 | bfd *abfd; | |
1796 | ||
1797 | /* See if the file is for the h8/300 or h8/300h. */ | |
1798 | /* ??? This may not be the most efficient way. The z8k simulator | |
1799 | does this via a different mechanism (INIT_EXTRA_SYMTAB_INFO). */ | |
1800 | if ((abfd = bfd_openr (prog, "coff-h8300")) != 0) | |
1801 | { | |
1802 | if (bfd_check_format (abfd, bfd_object)) | |
1803 | set_h8300h (abfd->arch_info->mach == bfd_mach_h8300h); | |
1804 | bfd_close (abfd); | |
1805 | } | |
1806 | ||
1807 | /* Return non-zero so gdb will handle it. */ | |
1808 | return 1; | |
1809 | } | |
1810 | ||
1811 | void | |
1812 | sim_create_inferior (start_address, argv, env) | |
1813 | SIM_ADDR start_address; | |
a415cf0a DE |
1814 | char **argv; |
1815 | char **env; | |
7db9345b | 1816 | { |
7478904c | 1817 | cpu.pc = start_address; |
7db9345b | 1818 | } |