Commit | Line | Data |
---|---|---|
c906108c SS |
1 | /* |
2 | * Simulator for the Hitachi H8/300 architecture. | |
3 | * | |
4 | * Written by Steve Chamberlain of Cygnus Support. sac@cygnus.com | |
5 | * | |
6 | * This file is part of H8/300 sim | |
7 | * | |
8 | * | |
9 | * THIS SOFTWARE IS NOT COPYRIGHTED | |
10 | * | |
11 | * Cygnus offers the following for use in the public domain. Cygnus makes no | |
12 | * warranty with regard to the software or its performance and the user | |
13 | * accepts the software "AS IS" with all faults. | |
14 | * | |
15 | * CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO THIS | |
16 | * SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY | |
17 | * AND FITNESS FOR A PARTICULAR PURPOSE. | |
18 | */ | |
19 | ||
20 | #include "config.h" | |
21 | ||
22 | #include <stdio.h> | |
23 | #include <signal.h> | |
24 | #ifdef HAVE_TIME_H | |
25 | #include <time.h> | |
26 | #endif | |
27 | #ifdef HAVE_STDLIB_H | |
28 | #include <stdlib.h> | |
29 | #endif | |
30 | #ifdef HAVE_SYS_PARAM_H | |
31 | #include <sys/param.h> | |
32 | #endif | |
c906108c SS |
33 | #include "ansidecl.h" |
34 | #include "bfd.h" | |
35 | #include "callback.h" | |
36 | #include "remote-sim.h" | |
37 | ||
38 | #ifndef SIGTRAP | |
39 | # define SIGTRAP 5 | |
40 | #endif | |
41 | ||
42 | int debug; | |
43 | ||
44 | host_callback *sim_callback; | |
45 | ||
46 | static SIM_OPEN_KIND sim_kind; | |
47 | static char *myname; | |
48 | ||
49 | /* FIXME: Needs to live in header file. | |
50 | This header should also include the things in remote-sim.h. | |
51 | One could move this to remote-sim.h but this function isn't needed | |
52 | by gdb. */ | |
53 | void sim_set_simcache_size PARAMS ((int)); | |
54 | ||
de9b1892 | 55 | #define X(op, size) op * 4 + size |
c906108c | 56 | |
de9b1892 | 57 | #define SP (h8300hmode ? SL : SW) |
c906108c SS |
58 | #define SB 0 |
59 | #define SW 1 | |
60 | #define SL 2 | |
61 | #define OP_REG 1 | |
62 | #define OP_DEC 2 | |
63 | #define OP_DISP 3 | |
64 | #define OP_INC 4 | |
65 | #define OP_PCREL 5 | |
66 | #define OP_MEM 6 | |
67 | #define OP_CCR 7 | |
68 | #define OP_IMM 8 | |
69 | #define OP_ABS 10 | |
70 | #define h8_opcodes ops | |
71 | #define DEFINE_TABLE | |
72 | #include "opcode/h8300.h" | |
73 | ||
74 | #include "inst.h" | |
75 | ||
0ef9643e | 76 | /* The rate at which to call the host's poll_quit callback. */ |
7a292a7a SS |
77 | |
78 | #define POLL_QUIT_INTERVAL 0x80000 | |
79 | ||
c906108c | 80 | #define LOW_BYTE(x) ((x) & 0xff) |
de9b1892 KH |
81 | #define HIGH_BYTE(x) (((x) >> 8) & 0xff) |
82 | #define P(X,Y) ((X << 8) | Y) | |
c906108c | 83 | |
f6225c96 AV |
84 | #define BUILDSR() cpu.ccr = (I << 7) | (UI << 6)| (H<<5) | (U<<4) | \ |
85 | (N << 3) | (Z << 2) | (V<<1) | C; | |
c906108c SS |
86 | |
87 | #define GETSR() \ | |
88 | c = (cpu.ccr >> 0) & 1;\ | |
89 | v = (cpu.ccr >> 1) & 1;\ | |
90 | nz = !((cpu.ccr >> 2) & 1);\ | |
f6225c96 AV |
91 | n = (cpu.ccr >> 3) & 1;\ |
92 | u = (cpu.ccr >> 4) & 1;\ | |
93 | h = (cpu.ccr >> 5) & 1;\ | |
94 | ui = ((cpu.ccr >> 6) & 1);\ | |
95 | intMaskBit = (cpu.ccr >> 7) & 1; | |
c906108c SS |
96 | |
97 | #ifdef __CHAR_IS_SIGNED__ | |
de9b1892 | 98 | #define SEXTCHAR(x) ((char) (x)) |
c906108c SS |
99 | #endif |
100 | ||
101 | #ifndef SEXTCHAR | |
102 | #define SEXTCHAR(x) ((x & 0x80) ? (x | ~0xff): x & 0xff) | |
103 | #endif | |
104 | ||
105 | #define UEXTCHAR(x) ((x) & 0xff) | |
106 | #define UEXTSHORT(x) ((x) & 0xffff) | |
de9b1892 | 107 | #define SEXTSHORT(x) ((short) (x)) |
c906108c SS |
108 | |
109 | static cpu_state_type cpu; | |
110 | ||
111 | int h8300hmode = 0; | |
112 | int h8300smode = 0; | |
113 | ||
114 | static int memory_size; | |
115 | ||
c906108c SS |
116 | static int |
117 | get_now () | |
118 | { | |
3b02cf92 | 119 | return time (0); /* WinXX HAS UNIX like 'time', so why not using it? */ |
c906108c SS |
120 | } |
121 | ||
122 | static int | |
123 | now_persec () | |
124 | { | |
125 | return 1; | |
126 | } | |
127 | ||
c906108c SS |
128 | static int |
129 | bitfrom (x) | |
130 | { | |
131 | switch (x & SIZE) | |
132 | { | |
133 | case L_8: | |
134 | return SB; | |
135 | case L_16: | |
136 | return SW; | |
137 | case L_32: | |
138 | return SL; | |
139 | case L_P: | |
140 | return h8300hmode ? SL : SW; | |
141 | } | |
142 | } | |
143 | ||
0ef9643e | 144 | static unsigned int |
c906108c SS |
145 | lvalue (x, rn) |
146 | { | |
147 | switch (x / 4) | |
148 | { | |
149 | case OP_DISP: | |
150 | if (rn == 8) | |
151 | { | |
152 | return X (OP_IMM, SP); | |
153 | } | |
154 | return X (OP_REG, SP); | |
155 | ||
156 | case OP_MEM: | |
c906108c | 157 | return X (OP_MEM, SP); |
0ef9643e | 158 | |
c906108c | 159 | default: |
3b02cf92 | 160 | abort (); /* ?? May be something more usefull? */ |
c906108c SS |
161 | } |
162 | } | |
163 | ||
164 | static unsigned int | |
165 | decode (addr, data, dst) | |
166 | int addr; | |
167 | unsigned char *data; | |
168 | decoded_inst *dst; | |
169 | ||
170 | { | |
171 | int rs = 0; | |
172 | int rd = 0; | |
173 | int rdisp = 0; | |
174 | int abs = 0; | |
c906108c | 175 | int bit = 0; |
0ef9643e | 176 | int plen = 0; |
6d028502 | 177 | struct h8_opcode *q; |
c906108c | 178 | int size = 0; |
0ef9643e | 179 | |
c906108c SS |
180 | dst->dst.type = -1; |
181 | dst->src.type = -1; | |
0ef9643e JL |
182 | |
183 | /* Find the exact opcode/arg combo. */ | |
6d028502 | 184 | for (q = h8_opcodes; q->name; q++) |
c906108c | 185 | { |
6d028502 | 186 | op_type *nib = q->data.nib; |
c906108c SS |
187 | unsigned int len = 0; |
188 | ||
c906108c SS |
189 | while (1) |
190 | { | |
191 | op_type looking_for = *nib; | |
192 | int thisnib = data[len >> 1]; | |
193 | ||
194 | thisnib = (len & 1) ? (thisnib & 0xf) : ((thisnib >> 4) & 0xf); | |
195 | ||
196 | if (looking_for < 16 && looking_for >= 0) | |
197 | { | |
198 | if (looking_for != thisnib) | |
199 | goto fail; | |
200 | } | |
201 | else | |
202 | { | |
203 | if ((int) looking_for & (int) B31) | |
204 | { | |
205 | if (!(((int) thisnib & 0x8) != 0)) | |
206 | goto fail; | |
0ef9643e JL |
207 | |
208 | looking_for = (op_type) ((int) looking_for & ~(int) B31); | |
c906108c SS |
209 | thisnib &= 0x7; |
210 | } | |
0ef9643e | 211 | |
c906108c SS |
212 | if ((int) looking_for & (int) B30) |
213 | { | |
214 | if (!(((int) thisnib & 0x8) == 0)) | |
215 | goto fail; | |
0ef9643e | 216 | |
c906108c SS |
217 | looking_for = (op_type) ((int) looking_for & ~(int) B30); |
218 | } | |
0ef9643e | 219 | |
c906108c SS |
220 | if (looking_for & DBIT) |
221 | { | |
0a17cd59 AC |
222 | /* Exclude adds/subs by looking at bit 0 and 2, and |
223 | make sure the operand size, either w or l, | |
224 | matches by looking at bit 1. */ | |
225 | if ((looking_for & 7) != (thisnib & 7)) | |
c906108c | 226 | goto fail; |
0ef9643e | 227 | |
c906108c SS |
228 | abs = (thisnib & 0x8) ? 2 : 1; |
229 | } | |
230 | else if (looking_for & (REG | IND | INC | DEC)) | |
231 | { | |
232 | if (looking_for & REG) | |
233 | { | |
0ef9643e | 234 | /* Can work out size from the register. */ |
c906108c SS |
235 | size = bitfrom (looking_for); |
236 | } | |
237 | if (looking_for & SRC) | |
0ef9643e | 238 | rs = thisnib; |
c906108c | 239 | else |
0ef9643e | 240 | rd = thisnib; |
c906108c SS |
241 | } |
242 | else if (looking_for & L_16) | |
243 | { | |
244 | abs = (data[len >> 1]) * 256 + data[(len + 2) >> 1]; | |
245 | plen = 16; | |
246 | if (looking_for & (PCREL | DISP)) | |
247 | { | |
248 | abs = (short) (abs); | |
249 | } | |
250 | } | |
251 | else if (looking_for & ABSJMP) | |
252 | { | |
0ef9643e | 253 | abs = (data[1] << 16) | (data[2] << 8) | (data[3]); |
c906108c SS |
254 | } |
255 | else if (looking_for & MEMIND) | |
256 | { | |
257 | abs = data[1]; | |
258 | } | |
259 | else if (looking_for & L_32) | |
260 | { | |
261 | int i = len >> 1; | |
0ef9643e | 262 | |
c906108c SS |
263 | abs = (data[i] << 24) |
264 | | (data[i + 1] << 16) | |
265 | | (data[i + 2] << 8) | |
266 | | (data[i + 3]); | |
267 | ||
268 | plen = 32; | |
269 | } | |
270 | else if (looking_for & L_24) | |
271 | { | |
272 | int i = len >> 1; | |
0ef9643e | 273 | |
c906108c SS |
274 | abs = (data[i] << 16) | (data[i + 1] << 8) | (data[i + 2]); |
275 | plen = 24; | |
276 | } | |
277 | else if (looking_for & IGNORE) | |
278 | { | |
0ef9643e | 279 | ; |
c906108c SS |
280 | } |
281 | else if (looking_for & DISPREG) | |
282 | { | |
283 | rdisp = thisnib & 0x7; | |
284 | } | |
285 | else if (looking_for & KBIT) | |
286 | { | |
287 | switch (thisnib) | |
288 | { | |
289 | case 9: | |
290 | abs = 4; | |
291 | break; | |
292 | case 8: | |
293 | abs = 2; | |
294 | break; | |
295 | case 0: | |
296 | abs = 1; | |
297 | break; | |
0a17cd59 AC |
298 | default: |
299 | goto fail; | |
c906108c SS |
300 | } |
301 | } | |
302 | else if (looking_for & L_8) | |
303 | { | |
304 | plen = 8; | |
305 | ||
306 | if (looking_for & PCREL) | |
307 | { | |
308 | abs = SEXTCHAR (data[len >> 1]); | |
309 | } | |
310 | else if (looking_for & ABS8MEM) | |
311 | { | |
312 | plen = 8; | |
313 | abs = h8300hmode ? ~0xff0000ff : ~0xffff00ff; | |
0ef9643e | 314 | abs |= data[len >> 1] & 0xff; |
c906108c | 315 | } |
0ef9643e | 316 | else |
c906108c SS |
317 | { |
318 | abs = data[len >> 1] & 0xff; | |
319 | } | |
320 | } | |
321 | else if (looking_for & L_3) | |
322 | { | |
323 | plen = 3; | |
324 | ||
325 | bit = thisnib; | |
326 | } | |
327 | else if (looking_for == E) | |
328 | { | |
329 | dst->op = q; | |
330 | ||
0ef9643e | 331 | /* Fill in the args. */ |
c906108c SS |
332 | { |
333 | op_type *args = q->args.nib; | |
334 | int hadone = 0; | |
335 | ||
336 | while (*args != E) | |
337 | { | |
338 | int x = *args; | |
339 | int rn = (x & DST) ? rd : rs; | |
340 | ea_type *p; | |
341 | ||
342 | if (x & DST) | |
0ef9643e | 343 | p = &(dst->dst); |
c906108c | 344 | else |
0ef9643e | 345 | p = &(dst->src); |
c906108c | 346 | |
0ef9643e | 347 | if (x & L_3) |
c906108c SS |
348 | { |
349 | p->type = X (OP_IMM, size); | |
350 | p->literal = bit; | |
351 | } | |
352 | else if (x & (IMM | KBIT | DBIT)) | |
353 | { | |
354 | p->type = X (OP_IMM, size); | |
355 | p->literal = abs; | |
356 | } | |
357 | else if (x & REG) | |
358 | { | |
6d028502 KH |
359 | /* Reset the size. |
360 | Some ops (like mul) have two sizes. */ | |
c906108c SS |
361 | |
362 | size = bitfrom (x); | |
363 | p->type = X (OP_REG, size); | |
364 | p->reg = rn; | |
365 | } | |
366 | else if (x & INC) | |
367 | { | |
368 | p->type = X (OP_INC, size); | |
369 | p->reg = rn & 0x7; | |
370 | } | |
371 | else if (x & DEC) | |
372 | { | |
373 | p->type = X (OP_DEC, size); | |
374 | p->reg = rn & 0x7; | |
375 | } | |
376 | else if (x & IND) | |
377 | { | |
378 | p->type = X (OP_DISP, size); | |
379 | p->reg = rn & 0x7; | |
380 | p->literal = 0; | |
381 | } | |
382 | else if (x & (ABS | ABSJMP | ABS8MEM)) | |
383 | { | |
384 | p->type = X (OP_DISP, size); | |
385 | p->literal = abs; | |
386 | p->reg = 8; | |
387 | } | |
388 | else if (x & MEMIND) | |
389 | { | |
390 | p->type = X (OP_MEM, size); | |
391 | p->literal = abs; | |
392 | } | |
393 | else if (x & PCREL) | |
394 | { | |
395 | p->type = X (OP_PCREL, size); | |
396 | p->literal = abs + addr + 2; | |
397 | if (x & L_16) | |
398 | p->literal += 2; | |
399 | } | |
400 | else if (x & ABSJMP) | |
401 | { | |
402 | p->type = X (OP_IMM, SP); | |
403 | p->literal = abs; | |
404 | } | |
405 | else if (x & DISP) | |
406 | { | |
407 | p->type = X (OP_DISP, size); | |
408 | p->literal = abs; | |
409 | p->reg = rdisp & 0x7; | |
410 | } | |
411 | else if (x & CCR) | |
412 | { | |
413 | p->type = OP_CCR; | |
414 | } | |
415 | else | |
416 | printf ("Hmmmm %x", x); | |
417 | ||
418 | args++; | |
419 | } | |
420 | } | |
421 | ||
0ef9643e JL |
422 | /* But a jmp or a jsr gets automagically lvalued, |
423 | since we branch to their address not their | |
424 | contents. */ | |
c906108c SS |
425 | if (q->how == O (O_JSR, SB) |
426 | || q->how == O (O_JMP, SB)) | |
427 | { | |
428 | dst->src.type = lvalue (dst->src.type, dst->src.reg); | |
429 | } | |
430 | ||
431 | if (dst->dst.type == -1) | |
432 | dst->dst = dst->src; | |
433 | ||
434 | dst->opcode = q->how; | |
435 | dst->cycles = q->time; | |
436 | ||
0ef9643e | 437 | /* And a jsr to 0xc4 is turned into a magic trap. */ |
c906108c SS |
438 | |
439 | if (dst->opcode == O (O_JSR, SB)) | |
440 | { | |
441 | if (dst->src.literal == 0xc4) | |
442 | { | |
443 | dst->opcode = O (O_SYSCALL, SB); | |
444 | } | |
445 | } | |
446 | ||
447 | dst->next_pc = addr + len / 2; | |
448 | return; | |
449 | } | |
450 | else | |
98ecb0a7 | 451 | printf ("Don't understand %x \n", looking_for); |
c906108c SS |
452 | } |
453 | ||
454 | len++; | |
455 | nib++; | |
456 | } | |
457 | ||
458 | fail: | |
6d028502 | 459 | ; |
c906108c SS |
460 | } |
461 | ||
0ef9643e | 462 | /* Fell off the end. */ |
c906108c SS |
463 | dst->opcode = O (O_ILL, SB); |
464 | } | |
465 | ||
c906108c SS |
466 | static void |
467 | compile (pc) | |
468 | { | |
469 | int idx; | |
470 | ||
2ea716f6 | 471 | /* Find the next cache entry to use. */ |
c906108c SS |
472 | idx = cpu.cache_top + 1; |
473 | cpu.compiles++; | |
474 | if (idx >= cpu.csize) | |
475 | { | |
476 | idx = 1; | |
477 | } | |
478 | cpu.cache_top = idx; | |
479 | ||
2ea716f6 | 480 | /* Throw away its old meaning. */ |
c906108c SS |
481 | cpu.cache_idx[cpu.cache[idx].oldpc] = 0; |
482 | ||
2ea716f6 | 483 | /* Set to new address. */ |
c906108c SS |
484 | cpu.cache[idx].oldpc = pc; |
485 | ||
2ea716f6 | 486 | /* Fill in instruction info. */ |
c906108c SS |
487 | decode (pc, cpu.memory + pc, cpu.cache + idx); |
488 | ||
2ea716f6 | 489 | /* Point to new cache entry. */ |
c906108c SS |
490 | cpu.cache_idx[pc] = idx; |
491 | } | |
492 | ||
493 | ||
494 | static unsigned char *breg[18]; | |
495 | static unsigned short *wreg[18]; | |
496 | static unsigned int *lreg[18]; | |
497 | ||
498 | #define GET_B_REG(x) *(breg[x]) | |
499 | #define SET_B_REG(x,y) (*(breg[x])) = (y) | |
500 | #define GET_W_REG(x) *(wreg[x]) | |
501 | #define SET_W_REG(x,y) (*(wreg[x])) = (y) | |
502 | ||
503 | #define GET_L_REG(x) *(lreg[x]) | |
504 | #define SET_L_REG(x,y) (*(lreg[x])) = (y) | |
505 | ||
506 | #define GET_MEMORY_L(x) \ | |
507 | (x < memory_size \ | |
508 | ? ((cpu.memory[x+0] << 24) | (cpu.memory[x+1] << 16) \ | |
509 | | (cpu.memory[x+2] << 8) | cpu.memory[x+3]) \ | |
510 | : ((cpu.eightbit[(x+0) & 0xff] << 24) | (cpu.eightbit[(x+1) & 0xff] << 16) \ | |
511 | | (cpu.eightbit[(x+2) & 0xff] << 8) | cpu.eightbit[(x+3) & 0xff])) | |
512 | ||
513 | #define GET_MEMORY_W(x) \ | |
514 | (x < memory_size \ | |
515 | ? ((cpu.memory[x+0] << 8) | (cpu.memory[x+1] << 0)) \ | |
516 | : ((cpu.eightbit[(x+0) & 0xff] << 8) | (cpu.eightbit[(x+1) & 0xff] << 0))) | |
517 | ||
518 | ||
519 | #define GET_MEMORY_B(x) \ | |
520 | (x < memory_size ? (cpu.memory[x]) : (cpu.eightbit[x & 0xff])) | |
521 | ||
522 | #define SET_MEMORY_L(x,y) \ | |
523 | { register unsigned char *_p; register int __y = y; \ | |
524 | _p = (x < memory_size ? cpu.memory+x : cpu.eightbit + (x & 0xff)); \ | |
525 | _p[0] = (__y)>>24; _p[1] = (__y)>>16; \ | |
526 | _p[2] = (__y)>>8; _p[3] = (__y)>>0;} | |
527 | ||
528 | #define SET_MEMORY_W(x,y) \ | |
529 | { register unsigned char *_p; register int __y = y; \ | |
530 | _p = (x < memory_size ? cpu.memory+x : cpu.eightbit + (x & 0xff)); \ | |
531 | _p[0] = (__y)>>8; _p[1] =(__y);} | |
532 | ||
533 | #define SET_MEMORY_B(x,y) \ | |
534 | (x < memory_size ? (cpu.memory[(x)] = y) : (cpu.eightbit[x & 0xff] = y)) | |
535 | ||
536 | int | |
537 | fetch (arg, n) | |
538 | ea_type *arg; | |
539 | { | |
540 | int rn = arg->reg; | |
541 | int abs = arg->literal; | |
542 | int r; | |
543 | int t; | |
544 | ||
545 | switch (arg->type) | |
546 | { | |
547 | case X (OP_REG, SB): | |
548 | return GET_B_REG (rn); | |
549 | case X (OP_REG, SW): | |
550 | return GET_W_REG (rn); | |
551 | case X (OP_REG, SL): | |
552 | return GET_L_REG (rn); | |
553 | case X (OP_IMM, SB): | |
554 | case X (OP_IMM, SW): | |
555 | case X (OP_IMM, SL): | |
556 | return abs; | |
557 | case X (OP_DEC, SB): | |
558 | abort (); | |
559 | ||
560 | case X (OP_INC, SB): | |
561 | t = GET_L_REG (rn); | |
562 | t &= cpu.mask; | |
563 | r = GET_MEMORY_B (t); | |
564 | t++; | |
565 | t = t & cpu.mask; | |
566 | SET_L_REG (rn, t); | |
567 | return r; | |
568 | break; | |
569 | case X (OP_INC, SW): | |
570 | t = GET_L_REG (rn); | |
571 | t &= cpu.mask; | |
572 | r = GET_MEMORY_W (t); | |
573 | t += 2; | |
574 | t = t & cpu.mask; | |
575 | SET_L_REG (rn, t); | |
576 | return r; | |
577 | case X (OP_INC, SL): | |
578 | t = GET_L_REG (rn); | |
579 | t &= cpu.mask; | |
580 | r = GET_MEMORY_L (t); | |
581 | ||
582 | t += 4; | |
583 | t = t & cpu.mask; | |
584 | SET_L_REG (rn, t); | |
585 | return r; | |
586 | ||
587 | case X (OP_DISP, SB): | |
588 | t = GET_L_REG (rn) + abs; | |
589 | t &= cpu.mask; | |
590 | return GET_MEMORY_B (t); | |
591 | ||
592 | case X (OP_DISP, SW): | |
593 | t = GET_L_REG (rn) + abs; | |
594 | t &= cpu.mask; | |
595 | return GET_MEMORY_W (t); | |
596 | ||
597 | case X (OP_DISP, SL): | |
598 | t = GET_L_REG (rn) + abs; | |
599 | t &= cpu.mask; | |
600 | return GET_MEMORY_L (t); | |
601 | ||
602 | case X (OP_MEM, SL): | |
603 | t = GET_MEMORY_L (abs); | |
604 | t &= cpu.mask; | |
605 | return t; | |
606 | ||
607 | case X (OP_MEM, SW): | |
608 | t = GET_MEMORY_W (abs); | |
609 | t &= cpu.mask; | |
610 | return t; | |
611 | ||
612 | default: | |
3b02cf92 | 613 | abort (); /* ?? May be something more usefull? */ |
c906108c SS |
614 | |
615 | } | |
616 | } | |
617 | ||
618 | ||
de9b1892 | 619 | static void |
c906108c SS |
620 | store (arg, n) |
621 | ea_type *arg; | |
622 | int n; | |
623 | { | |
624 | int rn = arg->reg; | |
625 | int abs = arg->literal; | |
626 | int t; | |
627 | ||
628 | switch (arg->type) | |
629 | { | |
630 | case X (OP_REG, SB): | |
631 | SET_B_REG (rn, n); | |
632 | break; | |
633 | case X (OP_REG, SW): | |
634 | SET_W_REG (rn, n); | |
635 | break; | |
636 | case X (OP_REG, SL): | |
637 | SET_L_REG (rn, n); | |
638 | break; | |
639 | ||
640 | case X (OP_DEC, SB): | |
641 | t = GET_L_REG (rn) - 1; | |
642 | t &= cpu.mask; | |
643 | SET_L_REG (rn, t); | |
644 | SET_MEMORY_B (t, n); | |
645 | ||
646 | break; | |
647 | case X (OP_DEC, SW): | |
648 | t = (GET_L_REG (rn) - 2) & cpu.mask; | |
649 | SET_L_REG (rn, t); | |
650 | SET_MEMORY_W (t, n); | |
651 | break; | |
652 | ||
653 | case X (OP_DEC, SL): | |
654 | t = (GET_L_REG (rn) - 4) & cpu.mask; | |
655 | SET_L_REG (rn, t); | |
656 | SET_MEMORY_L (t, n); | |
657 | break; | |
658 | ||
659 | case X (OP_DISP, SB): | |
660 | t = GET_L_REG (rn) + abs; | |
661 | t &= cpu.mask; | |
662 | SET_MEMORY_B (t, n); | |
663 | break; | |
664 | ||
665 | case X (OP_DISP, SW): | |
666 | t = GET_L_REG (rn) + abs; | |
667 | t &= cpu.mask; | |
668 | SET_MEMORY_W (t, n); | |
669 | break; | |
670 | ||
671 | case X (OP_DISP, SL): | |
672 | t = GET_L_REG (rn) + abs; | |
673 | t &= cpu.mask; | |
674 | SET_MEMORY_L (t, n); | |
675 | break; | |
676 | default: | |
677 | abort (); | |
678 | } | |
679 | } | |
680 | ||
681 | ||
682 | static union | |
683 | { | |
684 | short int i; | |
685 | struct | |
686 | { | |
687 | char low; | |
688 | char high; | |
689 | } | |
690 | u; | |
691 | } | |
692 | ||
693 | littleendian; | |
694 | ||
de9b1892 | 695 | static void |
c906108c SS |
696 | init_pointers () |
697 | { | |
698 | static int init; | |
699 | ||
700 | if (!init) | |
701 | { | |
702 | int i; | |
703 | ||
704 | init = 1; | |
705 | littleendian.i = 1; | |
706 | ||
a8cdafbd AV |
707 | if (h8300smode) |
708 | memory_size = H8300S_MSIZE; | |
709 | else if (h8300hmode) | |
c906108c SS |
710 | memory_size = H8300H_MSIZE; |
711 | else | |
712 | memory_size = H8300_MSIZE; | |
713 | cpu.memory = (unsigned char *) calloc (sizeof (char), memory_size); | |
714 | cpu.cache_idx = (unsigned short *) calloc (sizeof (short), memory_size); | |
715 | cpu.eightbit = (unsigned char *) calloc (sizeof (char), 256); | |
716 | ||
2ea716f6 | 717 | /* `msize' must be a power of two. */ |
c906108c SS |
718 | if ((memory_size & (memory_size - 1)) != 0) |
719 | abort (); | |
720 | cpu.mask = memory_size - 1; | |
721 | ||
722 | for (i = 0; i < 9; i++) | |
723 | { | |
724 | cpu.regs[i] = 0; | |
725 | } | |
726 | ||
727 | for (i = 0; i < 8; i++) | |
728 | { | |
729 | unsigned char *p = (unsigned char *) (cpu.regs + i); | |
730 | unsigned char *e = (unsigned char *) (cpu.regs + i + 1); | |
731 | unsigned short *q = (unsigned short *) (cpu.regs + i); | |
732 | unsigned short *u = (unsigned short *) (cpu.regs + i + 1); | |
733 | cpu.regs[i] = 0x00112233; | |
734 | while (p < e) | |
735 | { | |
736 | if (*p == 0x22) | |
737 | { | |
738 | breg[i] = p; | |
739 | } | |
740 | if (*p == 0x33) | |
741 | { | |
742 | breg[i + 8] = p; | |
743 | } | |
744 | p++; | |
745 | } | |
746 | while (q < u) | |
747 | { | |
748 | if (*q == 0x2233) | |
749 | { | |
750 | wreg[i] = q; | |
751 | } | |
752 | if (*q == 0x0011) | |
753 | { | |
754 | wreg[i + 8] = q; | |
755 | } | |
756 | q++; | |
757 | } | |
758 | cpu.regs[i] = 0; | |
759 | lreg[i] = &cpu.regs[i]; | |
760 | } | |
761 | ||
762 | lreg[8] = &cpu.regs[8]; | |
763 | ||
2ea716f6 | 764 | /* Initialize the seg registers. */ |
c906108c SS |
765 | if (!cpu.cache) |
766 | sim_set_simcache_size (CSIZE); | |
767 | } | |
768 | } | |
769 | ||
770 | static void | |
771 | control_c (sig, code, scp, addr) | |
772 | int sig; | |
773 | int code; | |
774 | char *scp; | |
775 | char *addr; | |
776 | { | |
777 | cpu.state = SIM_STATE_STOPPED; | |
778 | cpu.exception = SIGINT; | |
779 | } | |
780 | ||
781 | #define C (c != 0) | |
782 | #define Z (nz == 0) | |
783 | #define V (v != 0) | |
784 | #define N (n != 0) | |
f6225c96 AV |
785 | #define U (u != 0) |
786 | #define H (h != 0) | |
787 | #define UI (ui != 0) | |
788 | #define I (intMaskBit != 0) | |
c906108c SS |
789 | |
790 | static int | |
791 | mop (code, bsize, sign) | |
792 | decoded_inst *code; | |
793 | int bsize; | |
794 | int sign; | |
795 | { | |
796 | int multiplier; | |
797 | int multiplicand; | |
798 | int result; | |
799 | int n, nz; | |
800 | ||
801 | if (sign) | |
802 | { | |
803 | multiplicand = | |
804 | bsize ? SEXTCHAR (GET_W_REG (code->dst.reg)) : | |
805 | SEXTSHORT (GET_W_REG (code->dst.reg)); | |
806 | multiplier = | |
807 | bsize ? SEXTCHAR (GET_B_REG (code->src.reg)) : | |
808 | SEXTSHORT (GET_W_REG (code->src.reg)); | |
809 | } | |
810 | else | |
811 | { | |
812 | multiplicand = bsize ? UEXTCHAR (GET_W_REG (code->dst.reg)) : | |
813 | UEXTSHORT (GET_W_REG (code->dst.reg)); | |
814 | multiplier = | |
815 | bsize ? UEXTCHAR (GET_B_REG (code->src.reg)) : | |
816 | UEXTSHORT (GET_W_REG (code->src.reg)); | |
817 | ||
818 | } | |
819 | result = multiplier * multiplicand; | |
820 | ||
821 | if (sign) | |
822 | { | |
823 | n = result & (bsize ? 0x8000 : 0x80000000); | |
824 | nz = result & (bsize ? 0xffff : 0xffffffff); | |
825 | } | |
826 | if (bsize) | |
827 | { | |
828 | SET_W_REG (code->dst.reg, result); | |
829 | } | |
830 | else | |
831 | { | |
832 | SET_L_REG (code->dst.reg, result); | |
833 | } | |
de9b1892 KH |
834 | #if 0 |
835 | return ((n == 1) << 1) | (nz == 1); | |
836 | #endif | |
c906108c SS |
837 | } |
838 | ||
839 | #define ONOT(name, how) \ | |
840 | case O(name, SB): \ | |
841 | { \ | |
842 | int t; \ | |
843 | int hm = 0x80; \ | |
844 | rd = GET_B_REG (code->src.reg); \ | |
845 | how; \ | |
846 | goto shift8; \ | |
847 | } \ | |
848 | case O(name, SW): \ | |
849 | { \ | |
850 | int t; \ | |
851 | int hm = 0x8000; \ | |
852 | rd = GET_W_REG (code->src.reg); \ | |
853 | how; \ | |
854 | goto shift16; \ | |
855 | } \ | |
856 | case O(name, SL): \ | |
857 | { \ | |
858 | int t; \ | |
859 | int hm = 0x80000000; \ | |
860 | rd = GET_L_REG (code->src.reg); \ | |
861 | how; \ | |
862 | goto shift32; \ | |
863 | } | |
864 | ||
865 | #define OSHIFTS(name, how1, how2) \ | |
866 | case O(name, SB): \ | |
867 | { \ | |
868 | int t; \ | |
869 | int hm = 0x80; \ | |
870 | rd = GET_B_REG (code->src.reg); \ | |
871 | if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \ | |
872 | { \ | |
873 | how1; \ | |
874 | } \ | |
875 | else \ | |
876 | { \ | |
877 | how2; \ | |
878 | } \ | |
879 | goto shift8; \ | |
880 | } \ | |
881 | case O(name, SW): \ | |
882 | { \ | |
883 | int t; \ | |
884 | int hm = 0x8000; \ | |
885 | rd = GET_W_REG (code->src.reg); \ | |
886 | if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \ | |
887 | { \ | |
888 | how1; \ | |
889 | } \ | |
890 | else \ | |
891 | { \ | |
892 | how2; \ | |
893 | } \ | |
894 | goto shift16; \ | |
895 | } \ | |
896 | case O(name, SL): \ | |
897 | { \ | |
898 | int t; \ | |
899 | int hm = 0x80000000; \ | |
900 | rd = GET_L_REG (code->src.reg); \ | |
901 | if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \ | |
902 | { \ | |
903 | how1; \ | |
904 | } \ | |
905 | else \ | |
906 | { \ | |
907 | how2; \ | |
908 | } \ | |
909 | goto shift32; \ | |
910 | } | |
911 | ||
912 | #define OBITOP(name,f, s, op) \ | |
913 | case O(name, SB): \ | |
914 | { \ | |
915 | int m; \ | |
916 | int b; \ | |
917 | if (f) ea = fetch (&code->dst); \ | |
918 | m=1<< fetch(&code->src); \ | |
919 | op; \ | |
920 | if(s) store (&code->dst,ea); goto next; \ | |
921 | } | |
922 | ||
923 | int | |
924 | sim_stop (sd) | |
925 | SIM_DESC sd; | |
926 | { | |
927 | cpu.state = SIM_STATE_STOPPED; | |
928 | cpu.exception = SIGINT; | |
929 | return 1; | |
930 | } | |
931 | ||
932 | void | |
933 | sim_resume (sd, step, siggnal) | |
934 | SIM_DESC sd; | |
935 | { | |
936 | static int init1; | |
937 | int cycles = 0; | |
938 | int insts = 0; | |
939 | int tick_start = get_now (); | |
940 | void (*prev) (); | |
941 | int poll_count = 0; | |
942 | int res; | |
943 | int tmp; | |
944 | int rd; | |
945 | int ea; | |
946 | int bit; | |
947 | int pc; | |
f6225c96 | 948 | int c, nz, v, n, u, h, ui, intMaskBit; |
c906108c SS |
949 | int oldmask; |
950 | init_pointers (); | |
951 | ||
952 | prev = signal (SIGINT, control_c); | |
953 | ||
954 | if (step) | |
955 | { | |
956 | cpu.state = SIM_STATE_STOPPED; | |
957 | cpu.exception = SIGTRAP; | |
958 | } | |
959 | else | |
960 | { | |
961 | cpu.state = SIM_STATE_RUNNING; | |
962 | cpu.exception = 0; | |
963 | } | |
964 | ||
965 | pc = cpu.pc; | |
966 | ||
967 | /* The PC should never be odd. */ | |
968 | if (pc & 0x1) | |
969 | abort (); | |
970 | ||
971 | GETSR (); | |
972 | oldmask = cpu.mask; | |
973 | if (!h8300hmode) | |
974 | cpu.mask = 0xffff; | |
975 | do | |
976 | { | |
977 | int cidx; | |
978 | decoded_inst *code; | |
979 | ||
980 | top: | |
981 | cidx = cpu.cache_idx[pc]; | |
982 | code = cpu.cache + cidx; | |
983 | ||
984 | ||
985 | #define ALUOP(STORE, NAME, HOW) \ | |
986 | case O(NAME,SB): HOW; if(STORE)goto alu8;else goto just_flags_alu8; \ | |
987 | case O(NAME, SW): HOW; if(STORE)goto alu16;else goto just_flags_alu16; \ | |
988 | case O(NAME,SL): HOW; if(STORE)goto alu32;else goto just_flags_alu32; | |
989 | ||
990 | ||
991 | #define LOGOP(NAME, HOW) \ | |
992 | case O(NAME,SB): HOW; goto log8;\ | |
993 | case O(NAME, SW): HOW; goto log16;\ | |
994 | case O(NAME,SL): HOW; goto log32; | |
995 | ||
996 | ||
997 | ||
998 | #if ADEBUG | |
999 | if (debug) | |
1000 | { | |
1001 | printf ("%x %d %s\n", pc, code->opcode, | |
1002 | code->op ? code->op->name : "**"); | |
1003 | } | |
1004 | cpu.stats[code->opcode]++; | |
1005 | ||
1006 | #endif | |
1007 | ||
3b02cf92 AV |
1008 | if (code->opcode) |
1009 | { | |
1010 | cycles += code->cycles; | |
1011 | insts++; | |
1012 | } | |
1013 | ||
c906108c SS |
1014 | switch (code->opcode) |
1015 | { | |
1016 | case 0: | |
1017 | /* | |
1018 | * This opcode is a fake for when we get to an | |
1019 | * instruction which hasnt been compiled | |
1020 | */ | |
1021 | compile (pc); | |
1022 | goto top; | |
1023 | break; | |
1024 | ||
1025 | ||
1026 | case O (O_SUBX, SB): | |
1027 | rd = fetch (&code->dst); | |
1028 | ea = fetch (&code->src); | |
1029 | ea = -(ea + C); | |
1030 | res = rd + ea; | |
1031 | goto alu8; | |
1032 | ||
1033 | case O (O_ADDX, SB): | |
1034 | rd = fetch (&code->dst); | |
1035 | ea = fetch (&code->src); | |
1036 | ea = C + ea; | |
1037 | res = rd + ea; | |
1038 | goto alu8; | |
1039 | ||
1040 | #define EA ea = fetch(&code->src); | |
1041 | #define RD_EA ea = fetch(&code->src); rd = fetch(&code->dst); | |
1042 | ||
1043 | ALUOP (1, O_SUB, RD_EA; | |
1044 | ea = -ea; | |
1045 | res = rd + ea); | |
1046 | ALUOP (1, O_NEG, EA; | |
1047 | ea = -ea; | |
1048 | rd = 0; | |
1049 | res = rd + ea); | |
1050 | ||
1051 | case O (O_ADD, SB): | |
1052 | rd = GET_B_REG (code->dst.reg); | |
1053 | ea = fetch (&code->src); | |
1054 | res = rd + ea; | |
1055 | goto alu8; | |
1056 | case O (O_ADD, SW): | |
1057 | rd = GET_W_REG (code->dst.reg); | |
1058 | ea = fetch (&code->src); | |
1059 | res = rd + ea; | |
1060 | goto alu16; | |
1061 | case O (O_ADD, SL): | |
1062 | rd = GET_L_REG (code->dst.reg); | |
1063 | ea = fetch (&code->src); | |
1064 | res = rd + ea; | |
1065 | goto alu32; | |
1066 | ||
1067 | ||
1068 | LOGOP (O_AND, RD_EA; | |
1069 | res = rd & ea); | |
1070 | ||
1071 | LOGOP (O_OR, RD_EA; | |
1072 | res = rd | ea); | |
1073 | ||
1074 | LOGOP (O_XOR, RD_EA; | |
1075 | res = rd ^ ea); | |
1076 | ||
1077 | ||
1078 | case O (O_MOV_TO_MEM, SB): | |
1079 | res = GET_B_REG (code->src.reg); | |
1080 | goto log8; | |
1081 | case O (O_MOV_TO_MEM, SW): | |
1082 | res = GET_W_REG (code->src.reg); | |
1083 | goto log16; | |
1084 | case O (O_MOV_TO_MEM, SL): | |
1085 | res = GET_L_REG (code->src.reg); | |
1086 | goto log32; | |
1087 | ||
1088 | ||
1089 | case O (O_MOV_TO_REG, SB): | |
1090 | res = fetch (&code->src); | |
1091 | SET_B_REG (code->dst.reg, res); | |
1092 | goto just_flags_log8; | |
1093 | case O (O_MOV_TO_REG, SW): | |
1094 | res = fetch (&code->src); | |
1095 | SET_W_REG (code->dst.reg, res); | |
1096 | goto just_flags_log16; | |
1097 | case O (O_MOV_TO_REG, SL): | |
1098 | res = fetch (&code->src); | |
1099 | SET_L_REG (code->dst.reg, res); | |
1100 | goto just_flags_log32; | |
1101 | ||
1102 | ||
1103 | case O (O_ADDS, SL): | |
1104 | SET_L_REG (code->dst.reg, | |
1105 | GET_L_REG (code->dst.reg) | |
1106 | + code->src.literal); | |
1107 | ||
1108 | goto next; | |
1109 | ||
1110 | case O (O_SUBS, SL): | |
1111 | SET_L_REG (code->dst.reg, | |
1112 | GET_L_REG (code->dst.reg) | |
1113 | - code->src.literal); | |
1114 | goto next; | |
1115 | ||
1116 | case O (O_CMP, SB): | |
1117 | rd = fetch (&code->dst); | |
1118 | ea = fetch (&code->src); | |
1119 | ea = -ea; | |
1120 | res = rd + ea; | |
1121 | goto just_flags_alu8; | |
1122 | ||
1123 | case O (O_CMP, SW): | |
1124 | rd = fetch (&code->dst); | |
1125 | ea = fetch (&code->src); | |
1126 | ea = -ea; | |
1127 | res = rd + ea; | |
1128 | goto just_flags_alu16; | |
1129 | ||
1130 | case O (O_CMP, SL): | |
1131 | rd = fetch (&code->dst); | |
1132 | ea = fetch (&code->src); | |
1133 | ea = -ea; | |
1134 | res = rd + ea; | |
1135 | goto just_flags_alu32; | |
1136 | ||
1137 | ||
1138 | case O (O_DEC, SB): | |
1139 | rd = GET_B_REG (code->src.reg); | |
1140 | ea = -1; | |
1141 | res = rd + ea; | |
1142 | SET_B_REG (code->src.reg, res); | |
1143 | goto just_flags_inc8; | |
1144 | ||
1145 | case O (O_DEC, SW): | |
1146 | rd = GET_W_REG (code->dst.reg); | |
1147 | ea = -code->src.literal; | |
1148 | res = rd + ea; | |
1149 | SET_W_REG (code->dst.reg, res); | |
1150 | goto just_flags_inc16; | |
1151 | ||
1152 | case O (O_DEC, SL): | |
1153 | rd = GET_L_REG (code->dst.reg); | |
1154 | ea = -code->src.literal; | |
1155 | res = rd + ea; | |
1156 | SET_L_REG (code->dst.reg, res); | |
1157 | goto just_flags_inc32; | |
1158 | ||
1159 | ||
1160 | case O (O_INC, SB): | |
1161 | rd = GET_B_REG (code->src.reg); | |
1162 | ea = 1; | |
1163 | res = rd + ea; | |
1164 | SET_B_REG (code->src.reg, res); | |
1165 | goto just_flags_inc8; | |
1166 | ||
1167 | case O (O_INC, SW): | |
1168 | rd = GET_W_REG (code->dst.reg); | |
1169 | ea = code->src.literal; | |
1170 | res = rd + ea; | |
1171 | SET_W_REG (code->dst.reg, res); | |
1172 | goto just_flags_inc16; | |
1173 | ||
1174 | case O (O_INC, SL): | |
1175 | rd = GET_L_REG (code->dst.reg); | |
1176 | ea = code->src.literal; | |
1177 | res = rd + ea; | |
1178 | SET_L_REG (code->dst.reg, res); | |
1179 | goto just_flags_inc32; | |
1180 | ||
1181 | ||
1182 | #define GET_CCR(x) BUILDSR();x = cpu.ccr | |
1183 | ||
1184 | case O (O_ANDC, SB): | |
1185 | GET_CCR (rd); | |
1186 | ea = code->src.literal; | |
1187 | res = rd & ea; | |
1188 | goto setc; | |
1189 | ||
1190 | case O (O_ORC, SB): | |
1191 | GET_CCR (rd); | |
1192 | ea = code->src.literal; | |
1193 | res = rd | ea; | |
1194 | goto setc; | |
1195 | ||
1196 | case O (O_XORC, SB): | |
1197 | GET_CCR (rd); | |
1198 | ea = code->src.literal; | |
1199 | res = rd ^ ea; | |
1200 | goto setc; | |
1201 | ||
1202 | ||
1203 | case O (O_BRA, SB): | |
1204 | if (1) | |
1205 | goto condtrue; | |
1206 | goto next; | |
1207 | ||
1208 | case O (O_BRN, SB): | |
1209 | if (0) | |
1210 | goto condtrue; | |
1211 | goto next; | |
1212 | ||
1213 | case O (O_BHI, SB): | |
1214 | if ((C || Z) == 0) | |
1215 | goto condtrue; | |
1216 | goto next; | |
1217 | ||
1218 | ||
1219 | case O (O_BLS, SB): | |
1220 | if ((C || Z)) | |
1221 | goto condtrue; | |
1222 | goto next; | |
1223 | ||
1224 | case O (O_BCS, SB): | |
1225 | if ((C == 1)) | |
1226 | goto condtrue; | |
1227 | goto next; | |
1228 | ||
1229 | case O (O_BCC, SB): | |
1230 | if ((C == 0)) | |
1231 | goto condtrue; | |
1232 | goto next; | |
1233 | ||
1234 | case O (O_BEQ, SB): | |
1235 | if (Z) | |
1236 | goto condtrue; | |
1237 | goto next; | |
1238 | case O (O_BGT, SB): | |
1239 | if (((Z || (N ^ V)) == 0)) | |
1240 | goto condtrue; | |
1241 | goto next; | |
1242 | ||
1243 | ||
1244 | case O (O_BLE, SB): | |
1245 | if (((Z || (N ^ V)) == 1)) | |
1246 | goto condtrue; | |
1247 | goto next; | |
1248 | ||
1249 | case O (O_BGE, SB): | |
1250 | if ((N ^ V) == 0) | |
1251 | goto condtrue; | |
1252 | goto next; | |
1253 | case O (O_BLT, SB): | |
1254 | if ((N ^ V)) | |
1255 | goto condtrue; | |
1256 | goto next; | |
1257 | case O (O_BMI, SB): | |
1258 | if ((N)) | |
1259 | goto condtrue; | |
1260 | goto next; | |
1261 | case O (O_BNE, SB): | |
1262 | if ((Z == 0)) | |
1263 | goto condtrue; | |
1264 | goto next; | |
1265 | ||
1266 | case O (O_BPL, SB): | |
1267 | if (N == 0) | |
1268 | goto condtrue; | |
1269 | goto next; | |
1270 | case O (O_BVC, SB): | |
1271 | if ((V == 0)) | |
1272 | goto condtrue; | |
1273 | goto next; | |
1274 | case O (O_BVS, SB): | |
1275 | if ((V == 1)) | |
1276 | goto condtrue; | |
1277 | goto next; | |
1278 | ||
1279 | case O (O_SYSCALL, SB): | |
1280 | { | |
1281 | char c = cpu.regs[2]; | |
1282 | sim_callback->write_stdout (sim_callback, &c, 1); | |
1283 | } | |
1284 | goto next; | |
1285 | ||
1286 | ONOT (O_NOT, rd = ~rd; v = 0;); | |
1287 | OSHIFTS (O_SHLL, | |
1288 | c = rd & hm; v = 0; rd <<= 1, | |
1289 | c = rd & (hm >> 1); v = 0; rd <<= 2); | |
1290 | OSHIFTS (O_SHLR, | |
1291 | c = rd & 1; v = 0; rd = (unsigned int) rd >> 1, | |
1292 | c = rd & 2; v = 0; rd = (unsigned int) rd >> 2); | |
1293 | OSHIFTS (O_SHAL, | |
1294 | c = rd & hm; v = (rd & hm) != ((rd & (hm >> 1)) << 1); rd <<= 1, | |
1295 | c = rd & (hm >> 1); v = (rd & (hm >> 1)) != ((rd & (hm >> 2)) << 2); rd <<= 2); | |
1296 | OSHIFTS (O_SHAR, | |
1297 | t = rd & hm; c = rd & 1; v = 0; rd >>= 1; rd |= t, | |
1298 | t = rd & hm; c = rd & 2; v = 0; rd >>= 2; rd |= t | t >> 1 ); | |
1299 | OSHIFTS (O_ROTL, | |
1300 | c = rd & hm; v = 0; rd <<= 1; rd |= C, | |
1301 | c = rd & hm; v = 0; rd <<= 1; rd |= C; c = rd & hm; rd <<= 1; rd |= C); | |
1302 | OSHIFTS (O_ROTR, | |
1303 | c = rd & 1; v = 0; rd = (unsigned int) rd >> 1; if (c) rd |= hm, | |
1304 | c = rd & 1; v = 0; rd = (unsigned int) rd >> 1; if (c) rd |= hm; c = rd & 1; rd = (unsigned int) rd >> 1; if (c) rd |= hm); | |
1305 | OSHIFTS (O_ROTXL, | |
1306 | t = rd & hm; rd <<= 1; rd |= C; c = t; v = 0, | |
1307 | t = rd & hm; rd <<= 1; rd |= C; c = t; v = 0; t = rd & hm; rd <<= 1; rd |= C; c = t); | |
1308 | OSHIFTS (O_ROTXR, | |
1309 | t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd |= hm; c = t; v = 0, | |
1310 | t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd |= hm; c = t; v = 0; t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd |= hm; c = t); | |
1311 | ||
1312 | case O (O_JMP, SB): | |
1313 | { | |
1314 | pc = fetch (&code->src); | |
1315 | goto end; | |
1316 | ||
1317 | } | |
1318 | ||
1319 | case O (O_JSR, SB): | |
1320 | { | |
1321 | int tmp; | |
1322 | pc = fetch (&code->src); | |
1323 | call: | |
1324 | tmp = cpu.regs[7]; | |
1325 | ||
1326 | if (h8300hmode) | |
1327 | { | |
1328 | tmp -= 4; | |
1329 | SET_MEMORY_L (tmp, code->next_pc); | |
1330 | } | |
1331 | else | |
1332 | { | |
1333 | tmp -= 2; | |
1334 | SET_MEMORY_W (tmp, code->next_pc); | |
1335 | } | |
1336 | cpu.regs[7] = tmp; | |
1337 | ||
1338 | goto end; | |
1339 | } | |
1340 | case O (O_BSR, SB): | |
1341 | pc = code->src.literal; | |
1342 | goto call; | |
1343 | ||
1344 | case O (O_RTS, SN): | |
1345 | { | |
1346 | int tmp; | |
1347 | ||
1348 | tmp = cpu.regs[7]; | |
1349 | ||
1350 | if (h8300hmode) | |
1351 | { | |
1352 | pc = GET_MEMORY_L (tmp); | |
1353 | tmp += 4; | |
1354 | } | |
1355 | else | |
1356 | { | |
1357 | pc = GET_MEMORY_W (tmp); | |
1358 | tmp += 2; | |
1359 | } | |
1360 | ||
1361 | cpu.regs[7] = tmp; | |
1362 | goto end; | |
1363 | } | |
1364 | ||
1365 | case O (O_ILL, SB): | |
1366 | cpu.state = SIM_STATE_STOPPED; | |
1367 | cpu.exception = SIGILL; | |
1368 | goto end; | |
1369 | case O (O_SLEEP, SN): | |
c906108c SS |
1370 | /* FIXME: Doesn't this break for breakpoints when r0 |
1371 | contains just the right (er, wrong) value? */ | |
1372 | cpu.state = SIM_STATE_STOPPED; | |
97ee9e5a FCE |
1373 | /* The format of r0 is defined by target newlib. Expand |
1374 | the macros here instead of looking for .../sys/wait.h. */ | |
1375 | #define SIM_WIFEXITED(v) (((v) & 0xff) == 0) | |
1376 | #define SIM_WIFSIGNALED(v) (((v) & 0x7f) > 0 && (((v) & 0x7f) < 0x7f)) | |
1377 | if (! SIM_WIFEXITED (cpu.regs[0]) && SIM_WIFSIGNALED (cpu.regs[0])) | |
c906108c SS |
1378 | cpu.exception = SIGILL; |
1379 | else | |
1380 | cpu.exception = SIGTRAP; | |
c906108c SS |
1381 | goto end; |
1382 | case O (O_BPT, SN): | |
1383 | cpu.state = SIM_STATE_STOPPED; | |
1384 | cpu.exception = SIGTRAP; | |
1385 | goto end; | |
1386 | ||
1387 | OBITOP (O_BNOT, 1, 1, ea ^= m); | |
1388 | OBITOP (O_BTST, 1, 0, nz = ea & m); | |
1389 | OBITOP (O_BCLR, 1, 1, ea &= ~m); | |
1390 | OBITOP (O_BSET, 1, 1, ea |= m); | |
1391 | OBITOP (O_BLD, 1, 0, c = ea & m); | |
1392 | OBITOP (O_BILD, 1, 0, c = !(ea & m)); | |
1393 | OBITOP (O_BST, 1, 1, ea &= ~m; | |
1394 | if (C) ea |= m); | |
1395 | OBITOP (O_BIST, 1, 1, ea &= ~m; | |
1396 | if (!C) ea |= m); | |
1397 | OBITOP (O_BAND, 1, 0, c = (ea & m) && C); | |
1398 | OBITOP (O_BIAND, 1, 0, c = !(ea & m) && C); | |
1399 | OBITOP (O_BOR, 1, 0, c = (ea & m) || C); | |
1400 | OBITOP (O_BIOR, 1, 0, c = !(ea & m) || C); | |
1401 | OBITOP (O_BXOR, 1, 0, c = (ea & m) != C); | |
1402 | OBITOP (O_BIXOR, 1, 0, c = !(ea & m) != C); | |
1403 | ||
de9b1892 KH |
1404 | #define MOP(bsize, signed) \ |
1405 | mop (code, bsize, signed); \ | |
1406 | goto next; | |
c906108c SS |
1407 | |
1408 | case O (O_MULS, SB): | |
1409 | MOP (1, 1); | |
1410 | break; | |
1411 | case O (O_MULS, SW): | |
1412 | MOP (0, 1); | |
1413 | break; | |
1414 | case O (O_MULU, SB): | |
1415 | MOP (1, 0); | |
1416 | break; | |
1417 | case O (O_MULU, SW): | |
1418 | MOP (0, 0); | |
1419 | break; | |
1420 | ||
1421 | ||
1422 | case O (O_DIVU, SB): | |
1423 | { | |
1424 | rd = GET_W_REG (code->dst.reg); | |
1425 | ea = GET_B_REG (code->src.reg); | |
1426 | if (ea) | |
1427 | { | |
de9b1892 KH |
1428 | tmp = (unsigned) rd % ea; |
1429 | rd = (unsigned) rd / ea; | |
c906108c SS |
1430 | } |
1431 | SET_W_REG (code->dst.reg, (rd & 0xff) | (tmp << 8)); | |
1432 | n = ea & 0x80; | |
1433 | nz = ea & 0xff; | |
1434 | ||
1435 | goto next; | |
1436 | } | |
1437 | case O (O_DIVU, SW): | |
1438 | { | |
1439 | rd = GET_L_REG (code->dst.reg); | |
1440 | ea = GET_W_REG (code->src.reg); | |
1441 | n = ea & 0x8000; | |
1442 | nz = ea & 0xffff; | |
1443 | if (ea) | |
1444 | { | |
de9b1892 KH |
1445 | tmp = (unsigned) rd % ea; |
1446 | rd = (unsigned) rd / ea; | |
c906108c SS |
1447 | } |
1448 | SET_L_REG (code->dst.reg, (rd & 0xffff) | (tmp << 16)); | |
1449 | goto next; | |
1450 | } | |
1451 | ||
1452 | case O (O_DIVS, SB): | |
1453 | { | |
1454 | ||
1455 | rd = SEXTSHORT (GET_W_REG (code->dst.reg)); | |
1456 | ea = SEXTCHAR (GET_B_REG (code->src.reg)); | |
1457 | if (ea) | |
1458 | { | |
1459 | tmp = (int) rd % (int) ea; | |
1460 | rd = (int) rd / (int) ea; | |
1461 | n = rd & 0x8000; | |
1462 | nz = 1; | |
1463 | } | |
1464 | else | |
1465 | nz = 0; | |
1466 | SET_W_REG (code->dst.reg, (rd & 0xff) | (tmp << 8)); | |
1467 | goto next; | |
1468 | } | |
1469 | case O (O_DIVS, SW): | |
1470 | { | |
1471 | rd = GET_L_REG (code->dst.reg); | |
1472 | ea = SEXTSHORT (GET_W_REG (code->src.reg)); | |
1473 | if (ea) | |
1474 | { | |
1475 | tmp = (int) rd % (int) ea; | |
1476 | rd = (int) rd / (int) ea; | |
1477 | n = rd & 0x80000000; | |
1478 | nz = 1; | |
1479 | } | |
1480 | else | |
1481 | nz = 0; | |
1482 | SET_L_REG (code->dst.reg, (rd & 0xffff) | (tmp << 16)); | |
1483 | goto next; | |
1484 | } | |
1485 | case O (O_EXTS, SW): | |
1486 | rd = GET_B_REG (code->src.reg + 8) & 0xff; /* Yes, src, not dst. */ | |
1487 | ea = rd & 0x80 ? -256 : 0; | |
1488 | res = rd + ea; | |
1489 | goto log16; | |
1490 | case O (O_EXTS, SL): | |
1491 | rd = GET_W_REG (code->src.reg) & 0xffff; | |
1492 | ea = rd & 0x8000 ? -65536 : 0; | |
1493 | res = rd + ea; | |
1494 | goto log32; | |
1495 | case O (O_EXTU, SW): | |
1496 | rd = GET_B_REG (code->src.reg + 8) & 0xff; | |
1497 | ea = 0; | |
1498 | res = rd + ea; | |
1499 | goto log16; | |
1500 | case O (O_EXTU, SL): | |
1501 | rd = GET_W_REG (code->src.reg) & 0xffff; | |
1502 | ea = 0; | |
1503 | res = rd + ea; | |
1504 | goto log32; | |
1505 | ||
1506 | case O (O_NOP, SN): | |
1507 | goto next; | |
1508 | ||
1509 | case O (O_STM, SL): | |
1510 | { | |
1511 | int nregs, firstreg, i; | |
1512 | ||
1513 | nregs = GET_MEMORY_B (pc + 1); | |
1514 | nregs >>= 4; | |
1515 | nregs &= 0xf; | |
1516 | firstreg = GET_MEMORY_B (pc + 3); | |
1517 | firstreg &= 0xf; | |
1518 | for (i = firstreg; i <= firstreg + nregs; i++) | |
1519 | { | |
1520 | cpu.regs[7] -= 4; | |
1521 | SET_MEMORY_L (cpu.regs[7], cpu.regs[i]); | |
1522 | } | |
1523 | } | |
1524 | goto next; | |
1525 | ||
1526 | case O (O_LDM, SL): | |
1527 | { | |
1528 | int nregs, firstreg, i; | |
1529 | ||
1530 | nregs = GET_MEMORY_B (pc + 1); | |
1531 | nregs >>= 4; | |
1532 | nregs &= 0xf; | |
1533 | firstreg = GET_MEMORY_B (pc + 3); | |
1534 | firstreg &= 0xf; | |
1535 | for (i = firstreg; i >= firstreg - nregs; i--) | |
1536 | { | |
1537 | cpu.regs[i] = GET_MEMORY_L (cpu.regs[7]); | |
1538 | cpu.regs[7] += 4; | |
1539 | } | |
1540 | } | |
1541 | goto next; | |
1542 | ||
1543 | default: | |
1544 | cpu.state = SIM_STATE_STOPPED; | |
1545 | cpu.exception = SIGILL; | |
1546 | goto end; | |
1547 | ||
1548 | } | |
1549 | abort (); | |
1550 | ||
1551 | setc: | |
1552 | cpu.ccr = res; | |
1553 | GETSR (); | |
1554 | goto next; | |
1555 | ||
1556 | condtrue: | |
1557 | /* When a branch works */ | |
1558 | pc = code->src.literal; | |
1559 | goto end; | |
1560 | ||
1561 | /* Set the cond codes from res */ | |
1562 | bitop: | |
1563 | ||
1564 | /* Set the flags after an 8 bit inc/dec operation */ | |
1565 | just_flags_inc8: | |
1566 | n = res & 0x80; | |
1567 | nz = res & 0xff; | |
1568 | v = (rd & 0x7f) == 0x7f; | |
1569 | goto next; | |
1570 | ||
1571 | ||
1572 | /* Set the flags after an 16 bit inc/dec operation */ | |
1573 | just_flags_inc16: | |
1574 | n = res & 0x8000; | |
1575 | nz = res & 0xffff; | |
1576 | v = (rd & 0x7fff) == 0x7fff; | |
1577 | goto next; | |
1578 | ||
1579 | ||
1580 | /* Set the flags after an 32 bit inc/dec operation */ | |
1581 | just_flags_inc32: | |
1582 | n = res & 0x80000000; | |
1583 | nz = res & 0xffffffff; | |
1584 | v = (rd & 0x7fffffff) == 0x7fffffff; | |
1585 | goto next; | |
1586 | ||
1587 | ||
1588 | shift8: | |
1589 | /* Set flags after an 8 bit shift op, carry,overflow set in insn */ | |
1590 | n = (rd & 0x80); | |
1591 | nz = rd & 0xff; | |
1592 | SET_B_REG (code->src.reg, rd); | |
1593 | goto next; | |
1594 | ||
1595 | shift16: | |
1596 | /* Set flags after an 16 bit shift op, carry,overflow set in insn */ | |
1597 | n = (rd & 0x8000); | |
1598 | nz = rd & 0xffff; | |
1599 | SET_W_REG (code->src.reg, rd); | |
1600 | goto next; | |
1601 | ||
1602 | shift32: | |
1603 | /* Set flags after an 32 bit shift op, carry,overflow set in insn */ | |
1604 | n = (rd & 0x80000000); | |
1605 | nz = rd & 0xffffffff; | |
1606 | SET_L_REG (code->src.reg, rd); | |
1607 | goto next; | |
1608 | ||
1609 | log32: | |
1610 | store (&code->dst, res); | |
1611 | just_flags_log32: | |
1612 | /* flags after a 32bit logical operation */ | |
1613 | n = res & 0x80000000; | |
1614 | nz = res & 0xffffffff; | |
1615 | v = 0; | |
1616 | goto next; | |
1617 | ||
1618 | log16: | |
1619 | store (&code->dst, res); | |
1620 | just_flags_log16: | |
1621 | /* flags after a 16bit logical operation */ | |
1622 | n = res & 0x8000; | |
1623 | nz = res & 0xffff; | |
1624 | v = 0; | |
1625 | goto next; | |
1626 | ||
1627 | ||
1628 | log8: | |
1629 | store (&code->dst, res); | |
1630 | just_flags_log8: | |
1631 | n = res & 0x80; | |
1632 | nz = res & 0xff; | |
1633 | v = 0; | |
1634 | goto next; | |
1635 | ||
1636 | alu8: | |
1637 | SET_B_REG (code->dst.reg, res); | |
1638 | just_flags_alu8: | |
1639 | n = res & 0x80; | |
1640 | nz = res & 0xff; | |
1641 | c = (res & 0x100); | |
1642 | switch (code->opcode / 4) | |
1643 | { | |
1644 | case O_ADD: | |
1645 | v = ((rd & 0x80) == (ea & 0x80) | |
1646 | && (rd & 0x80) != (res & 0x80)); | |
1647 | break; | |
1648 | case O_SUB: | |
1649 | case O_CMP: | |
1650 | v = ((rd & 0x80) != (-ea & 0x80) | |
1651 | && (rd & 0x80) != (res & 0x80)); | |
1652 | break; | |
1653 | case O_NEG: | |
1654 | v = (rd == 0x80); | |
1655 | break; | |
1656 | } | |
1657 | goto next; | |
1658 | ||
1659 | alu16: | |
1660 | SET_W_REG (code->dst.reg, res); | |
1661 | just_flags_alu16: | |
1662 | n = res & 0x8000; | |
1663 | nz = res & 0xffff; | |
1664 | c = (res & 0x10000); | |
1665 | switch (code->opcode / 4) | |
1666 | { | |
1667 | case O_ADD: | |
1668 | v = ((rd & 0x8000) == (ea & 0x8000) | |
1669 | && (rd & 0x8000) != (res & 0x8000)); | |
1670 | break; | |
1671 | case O_SUB: | |
1672 | case O_CMP: | |
1673 | v = ((rd & 0x8000) != (-ea & 0x8000) | |
1674 | && (rd & 0x8000) != (res & 0x8000)); | |
1675 | break; | |
1676 | case O_NEG: | |
1677 | v = (rd == 0x8000); | |
1678 | break; | |
1679 | } | |
1680 | goto next; | |
1681 | ||
1682 | alu32: | |
1683 | SET_L_REG (code->dst.reg, res); | |
1684 | just_flags_alu32: | |
1685 | n = res & 0x80000000; | |
1686 | nz = res & 0xffffffff; | |
1687 | switch (code->opcode / 4) | |
1688 | { | |
1689 | case O_ADD: | |
1690 | v = ((rd & 0x80000000) == (ea & 0x80000000) | |
1691 | && (rd & 0x80000000) != (res & 0x80000000)); | |
1692 | c = ((unsigned) res < (unsigned) rd) || ((unsigned) res < (unsigned) ea); | |
1693 | break; | |
1694 | case O_SUB: | |
1695 | case O_CMP: | |
1696 | v = ((rd & 0x80000000) != (-ea & 0x80000000) | |
1697 | && (rd & 0x80000000) != (res & 0x80000000)); | |
1698 | c = (unsigned) rd < (unsigned) -ea; | |
1699 | break; | |
1700 | case O_NEG: | |
1701 | v = (rd == 0x80000000); | |
1702 | c = res != 0; | |
1703 | break; | |
1704 | } | |
1705 | goto next; | |
1706 | ||
1707 | next:; | |
1708 | pc = code->next_pc; | |
1709 | ||
1710 | end: | |
1711 | ; | |
de9b1892 KH |
1712 | #if 0 |
1713 | if (cpu.regs[8]) | |
1714 | abort (); | |
1715 | #endif | |
c906108c SS |
1716 | |
1717 | if (--poll_count < 0) | |
1718 | { | |
7a292a7a | 1719 | poll_count = POLL_QUIT_INTERVAL; |
c906108c SS |
1720 | if ((*sim_callback->poll_quit) != NULL |
1721 | && (*sim_callback->poll_quit) (sim_callback)) | |
1722 | sim_stop (sd); | |
1723 | } | |
1724 | ||
1725 | } | |
1726 | while (cpu.state == SIM_STATE_RUNNING); | |
1727 | cpu.ticks += get_now () - tick_start; | |
1728 | cpu.cycles += cycles; | |
1729 | cpu.insts += insts; | |
de9b1892 | 1730 | |
c906108c SS |
1731 | cpu.pc = pc; |
1732 | BUILDSR (); | |
1733 | cpu.mask = oldmask; | |
1734 | signal (SIGINT, prev); | |
1735 | } | |
1736 | ||
1737 | int | |
1738 | sim_trace (sd) | |
1739 | SIM_DESC sd; | |
1740 | { | |
2ea716f6 | 1741 | /* FIXME: Unfinished. */ |
c906108c SS |
1742 | abort (); |
1743 | } | |
1744 | ||
1745 | int | |
1746 | sim_write (sd, addr, buffer, size) | |
1747 | SIM_DESC sd; | |
1748 | SIM_ADDR addr; | |
1749 | unsigned char *buffer; | |
1750 | int size; | |
1751 | { | |
1752 | int i; | |
1753 | ||
1754 | init_pointers (); | |
1755 | if (addr < 0) | |
1756 | return 0; | |
1757 | for (i = 0; i < size; i++) | |
1758 | { | |
1759 | if (addr < memory_size) | |
1760 | { | |
1761 | cpu.memory[addr + i] = buffer[i]; | |
1762 | cpu.cache_idx[addr + i] = 0; | |
1763 | } | |
1764 | else | |
1765 | cpu.eightbit[(addr + i) & 0xff] = buffer[i]; | |
1766 | } | |
1767 | return size; | |
1768 | } | |
1769 | ||
1770 | int | |
1771 | sim_read (sd, addr, buffer, size) | |
1772 | SIM_DESC sd; | |
1773 | SIM_ADDR addr; | |
1774 | unsigned char *buffer; | |
1775 | int size; | |
1776 | { | |
1777 | init_pointers (); | |
1778 | if (addr < 0) | |
1779 | return 0; | |
1780 | if (addr < memory_size) | |
1781 | memcpy (buffer, cpu.memory + addr, size); | |
1782 | else | |
1783 | memcpy (buffer, cpu.eightbit + (addr & 0xff), size); | |
1784 | return size; | |
1785 | } | |
1786 | ||
1787 | ||
1788 | #define R0_REGNUM 0 | |
1789 | #define R1_REGNUM 1 | |
1790 | #define R2_REGNUM 2 | |
1791 | #define R3_REGNUM 3 | |
1792 | #define R4_REGNUM 4 | |
1793 | #define R5_REGNUM 5 | |
1794 | #define R6_REGNUM 6 | |
1795 | #define R7_REGNUM 7 | |
1796 | ||
1797 | #define SP_REGNUM R7_REGNUM /* Contains address of top of stack */ | |
1798 | #define FP_REGNUM R6_REGNUM /* Contains address of executing | |
2ea716f6 | 1799 | * stack frame */ |
c906108c SS |
1800 | |
1801 | #define CCR_REGNUM 8 /* Contains processor status */ | |
1802 | #define PC_REGNUM 9 /* Contains program counter */ | |
1803 | ||
1804 | #define CYCLE_REGNUM 10 | |
1805 | #define INST_REGNUM 11 | |
1806 | #define TICK_REGNUM 12 | |
1807 | ||
1808 | ||
1809 | int | |
1810 | sim_store_register (sd, rn, value, length) | |
1811 | SIM_DESC sd; | |
1812 | int rn; | |
1813 | unsigned char *value; | |
1814 | int length; | |
1815 | { | |
1816 | int longval; | |
1817 | int shortval; | |
1818 | int intval; | |
1819 | longval = (value[0] << 24) | (value[1] << 16) | (value[2] << 8) | value[3]; | |
1820 | shortval = (value[0] << 8) | (value[1]); | |
1821 | intval = h8300hmode ? longval : shortval; | |
1822 | ||
1823 | init_pointers (); | |
1824 | switch (rn) | |
1825 | { | |
1826 | case PC_REGNUM: | |
1827 | cpu.pc = intval; | |
1828 | break; | |
1829 | default: | |
1830 | abort (); | |
1831 | case R0_REGNUM: | |
1832 | case R1_REGNUM: | |
1833 | case R2_REGNUM: | |
1834 | case R3_REGNUM: | |
1835 | case R4_REGNUM: | |
1836 | case R5_REGNUM: | |
1837 | case R6_REGNUM: | |
1838 | case R7_REGNUM: | |
1839 | cpu.regs[rn] = intval; | |
1840 | break; | |
1841 | case CCR_REGNUM: | |
1842 | cpu.ccr = intval; | |
1843 | break; | |
1844 | case CYCLE_REGNUM: | |
1845 | cpu.cycles = longval; | |
1846 | break; | |
1847 | ||
1848 | case INST_REGNUM: | |
1849 | cpu.insts = longval; | |
1850 | break; | |
1851 | ||
1852 | case TICK_REGNUM: | |
1853 | cpu.ticks = longval; | |
1854 | break; | |
1855 | } | |
1856 | return -1; | |
1857 | } | |
1858 | ||
1859 | int | |
1860 | sim_fetch_register (sd, rn, buf, length) | |
1861 | SIM_DESC sd; | |
1862 | int rn; | |
1863 | unsigned char *buf; | |
1864 | int length; | |
1865 | { | |
1866 | int v; | |
1867 | int longreg = 0; | |
1868 | ||
1869 | init_pointers (); | |
1870 | ||
1871 | switch (rn) | |
1872 | { | |
1873 | default: | |
1874 | abort (); | |
3b02cf92 | 1875 | case CCR_REGNUM: |
c906108c SS |
1876 | v = cpu.ccr; |
1877 | break; | |
3b02cf92 | 1878 | case PC_REGNUM: |
c906108c SS |
1879 | v = cpu.pc; |
1880 | break; | |
1881 | case R0_REGNUM: | |
1882 | case R1_REGNUM: | |
1883 | case R2_REGNUM: | |
1884 | case R3_REGNUM: | |
1885 | case R4_REGNUM: | |
1886 | case R5_REGNUM: | |
1887 | case R6_REGNUM: | |
1888 | case R7_REGNUM: | |
1889 | v = cpu.regs[rn]; | |
1890 | break; | |
3b02cf92 | 1891 | case CYCLE_REGNUM: |
c906108c SS |
1892 | v = cpu.cycles; |
1893 | longreg = 1; | |
1894 | break; | |
3b02cf92 | 1895 | case TICK_REGNUM: |
c906108c SS |
1896 | v = cpu.ticks; |
1897 | longreg = 1; | |
1898 | break; | |
3b02cf92 | 1899 | case INST_REGNUM: |
c906108c SS |
1900 | v = cpu.insts; |
1901 | longreg = 1; | |
1902 | break; | |
1903 | } | |
1904 | if (h8300hmode || longreg) | |
1905 | { | |
1906 | buf[0] = v >> 24; | |
1907 | buf[1] = v >> 16; | |
1908 | buf[2] = v >> 8; | |
1909 | buf[3] = v >> 0; | |
1910 | } | |
1911 | else | |
1912 | { | |
1913 | buf[0] = v >> 8; | |
1914 | buf[1] = v; | |
1915 | } | |
1916 | return -1; | |
1917 | } | |
1918 | ||
1919 | void | |
1920 | sim_stop_reason (sd, reason, sigrc) | |
1921 | SIM_DESC sd; | |
1922 | enum sim_stop *reason; | |
1923 | int *sigrc; | |
1924 | { | |
1925 | #if 0 /* FIXME: This should work but we can't use it. | |
1926 | grep for SLEEP above. */ | |
1927 | switch (cpu.state) | |
1928 | { | |
1929 | case SIM_STATE_EXITED : *reason = sim_exited; break; | |
1930 | case SIM_STATE_SIGNALLED : *reason = sim_signalled; break; | |
1931 | case SIM_STATE_STOPPED : *reason = sim_stopped; break; | |
1932 | default : abort (); | |
1933 | } | |
1934 | #else | |
1935 | *reason = sim_stopped; | |
1936 | #endif | |
1937 | *sigrc = cpu.exception; | |
1938 | } | |
1939 | ||
1940 | /* FIXME: Rename to sim_set_mem_size. */ | |
1941 | ||
1942 | void | |
1943 | sim_size (n) | |
1944 | int n; | |
1945 | { | |
1946 | /* Memory size is fixed. */ | |
1947 | } | |
1948 | ||
1949 | void | |
1950 | sim_set_simcache_size (n) | |
1951 | { | |
1952 | if (cpu.cache) | |
1953 | free (cpu.cache); | |
1954 | if (n < 2) | |
1955 | n = 2; | |
1956 | cpu.cache = (decoded_inst *) malloc (sizeof (decoded_inst) * n); | |
1957 | memset (cpu.cache, 0, sizeof (decoded_inst) * n); | |
1958 | cpu.csize = n; | |
1959 | } | |
1960 | ||
1961 | ||
1962 | void | |
1963 | sim_info (sd, verbose) | |
1964 | SIM_DESC sd; | |
1965 | int verbose; | |
1966 | { | |
1967 | double timetaken = (double) cpu.ticks / (double) now_persec (); | |
1968 | double virttime = cpu.cycles / 10.0e6; | |
1969 | ||
1970 | (*sim_callback->printf_filtered) (sim_callback, | |
1971 | "\n\n#instructions executed %10d\n", | |
1972 | cpu.insts); | |
1973 | (*sim_callback->printf_filtered) (sim_callback, | |
1974 | "#cycles (v approximate) %10d\n", | |
1975 | cpu.cycles); | |
1976 | (*sim_callback->printf_filtered) (sim_callback, | |
1977 | "#real time taken %10.4f\n", | |
1978 | timetaken); | |
1979 | (*sim_callback->printf_filtered) (sim_callback, | |
1980 | "#virtual time taked %10.4f\n", | |
1981 | virttime); | |
1982 | if (timetaken != 0.0) | |
1983 | (*sim_callback->printf_filtered) (sim_callback, | |
1984 | "#simulation ratio %10.4f\n", | |
1985 | virttime / timetaken); | |
1986 | (*sim_callback->printf_filtered) (sim_callback, | |
1987 | "#compiles %10d\n", | |
1988 | cpu.compiles); | |
1989 | (*sim_callback->printf_filtered) (sim_callback, | |
1990 | "#cache size %10d\n", | |
1991 | cpu.csize); | |
1992 | ||
1993 | #ifdef ADEBUG | |
1994 | /* This to be conditional on `what' (aka `verbose'), | |
1995 | however it was never passed as non-zero. */ | |
1996 | if (1) | |
1997 | { | |
1998 | int i; | |
1999 | for (i = 0; i < O_LAST; i++) | |
2000 | { | |
2001 | if (cpu.stats[i]) | |
2002 | (*sim_callback->printf_filtered) (sim_callback, | |
2003 | "%d: %d\n", i, cpu.stats[i]); | |
2004 | } | |
2005 | } | |
2006 | #endif | |
2007 | } | |
2008 | ||
2ea716f6 KH |
2009 | /* Indicate whether the cpu is an H8/300 or H8/300H. |
2010 | FLAG is non-zero for the H8/300H. */ | |
c906108c SS |
2011 | |
2012 | void | |
a8cdafbd AV |
2013 | set_h8300h (h_flag, s_flag) |
2014 | int h_flag, s_flag; | |
c906108c SS |
2015 | { |
2016 | /* FIXME: Much of the code in sim_load can be moved to sim_open. | |
2017 | This function being replaced by a sim_open:ARGV configuration | |
2ea716f6 | 2018 | option. */ |
a8cdafbd AV |
2019 | h8300hmode = h_flag; |
2020 | h8300smode = s_flag; | |
c906108c SS |
2021 | } |
2022 | ||
2023 | SIM_DESC | |
2024 | sim_open (kind, ptr, abfd, argv) | |
2025 | SIM_OPEN_KIND kind; | |
2026 | struct host_callback_struct *ptr; | |
2027 | struct _bfd *abfd; | |
2028 | char **argv; | |
2029 | { | |
2ea716f6 | 2030 | /* FIXME: Much of the code in sim_load can be moved here. */ |
c906108c SS |
2031 | |
2032 | sim_kind = kind; | |
2033 | myname = argv[0]; | |
2034 | sim_callback = ptr; | |
2ea716f6 | 2035 | /* Fudge our descriptor. */ |
c906108c SS |
2036 | return (SIM_DESC) 1; |
2037 | } | |
2038 | ||
2039 | void | |
2040 | sim_close (sd, quitting) | |
2041 | SIM_DESC sd; | |
2042 | int quitting; | |
2043 | { | |
2ea716f6 | 2044 | /* Nothing to do. */ |
c906108c SS |
2045 | } |
2046 | ||
2047 | /* Called by gdb to load a program into memory. */ | |
2048 | ||
2049 | SIM_RC | |
2050 | sim_load (sd, prog, abfd, from_tty) | |
2051 | SIM_DESC sd; | |
2052 | char *prog; | |
2053 | bfd *abfd; | |
2054 | int from_tty; | |
2055 | { | |
2056 | bfd *prog_bfd; | |
2057 | ||
2ea716f6 KH |
2058 | /* FIXME: The code below that sets a specific variant of the H8/300 |
2059 | being simulated should be moved to sim_open(). */ | |
c906108c | 2060 | |
2ea716f6 | 2061 | /* See if the file is for the H8/300 or H8/300H. */ |
c906108c SS |
2062 | /* ??? This may not be the most efficient way. The z8k simulator |
2063 | does this via a different mechanism (INIT_EXTRA_SYMTAB_INFO). */ | |
2064 | if (abfd != NULL) | |
2065 | prog_bfd = abfd; | |
2066 | else | |
2067 | prog_bfd = bfd_openr (prog, "coff-h8300"); | |
2068 | if (prog_bfd != NULL) | |
2069 | { | |
2070 | /* Set the cpu type. We ignore failure from bfd_check_format | |
2071 | and bfd_openr as sim_load_file checks too. */ | |
de9b1892 | 2072 | if (bfd_check_format (prog_bfd, bfd_object)) |
c906108c SS |
2073 | { |
2074 | unsigned long mach = bfd_get_mach (prog_bfd); | |
a8cdafbd AV |
2075 | set_h8300h (mach == bfd_mach_h8300h || mach == bfd_mach_h8300s, |
2076 | mach == bfd_mach_h8300s); | |
c906108c SS |
2077 | } |
2078 | } | |
2079 | ||
2080 | /* If we're using gdb attached to the simulator, then we have to | |
2081 | reallocate memory for the simulator. | |
2082 | ||
2083 | When gdb first starts, it calls fetch_registers (among other | |
2084 | functions), which in turn calls init_pointers, which allocates | |
2085 | simulator memory. | |
2086 | ||
2087 | The problem is when we do that, we don't know whether we're | |
2ea716f6 | 2088 | debugging an H8/300 or H8/300H program. |
c906108c SS |
2089 | |
2090 | This is the first point at which we can make that determination, | |
2091 | so we just reallocate memory now; this will also allow us to handle | |
2ea716f6 | 2092 | switching between H8/300 and H8/300H programs without exiting |
c906108c | 2093 | gdb. */ |
a8cdafbd AV |
2094 | |
2095 | if (h8300smode) | |
2096 | memory_size = H8300S_MSIZE; | |
2097 | else if (h8300hmode) | |
c906108c SS |
2098 | memory_size = H8300H_MSIZE; |
2099 | else | |
2100 | memory_size = H8300_MSIZE; | |
2101 | ||
2102 | if (cpu.memory) | |
2103 | free (cpu.memory); | |
2104 | if (cpu.cache_idx) | |
2105 | free (cpu.cache_idx); | |
2106 | if (cpu.eightbit) | |
2107 | free (cpu.eightbit); | |
2108 | ||
2109 | cpu.memory = (unsigned char *) calloc (sizeof (char), memory_size); | |
2110 | cpu.cache_idx = (unsigned short *) calloc (sizeof (short), memory_size); | |
2111 | cpu.eightbit = (unsigned char *) calloc (sizeof (char), 256); | |
2112 | ||
2ea716f6 | 2113 | /* `msize' must be a power of two. */ |
c906108c SS |
2114 | if ((memory_size & (memory_size - 1)) != 0) |
2115 | abort (); | |
2116 | cpu.mask = memory_size - 1; | |
2117 | ||
2118 | if (sim_load_file (sd, myname, sim_callback, prog, prog_bfd, | |
2119 | sim_kind == SIM_OPEN_DEBUG, | |
2120 | 0, sim_write) | |
2121 | == NULL) | |
2122 | { | |
2123 | /* Close the bfd if we opened it. */ | |
2124 | if (abfd == NULL && prog_bfd != NULL) | |
2125 | bfd_close (prog_bfd); | |
2126 | return SIM_RC_FAIL; | |
2127 | } | |
2128 | ||
2129 | /* Close the bfd if we opened it. */ | |
2130 | if (abfd == NULL && prog_bfd != NULL) | |
2131 | bfd_close (prog_bfd); | |
2132 | return SIM_RC_OK; | |
2133 | } | |
2134 | ||
2135 | SIM_RC | |
2136 | sim_create_inferior (sd, abfd, argv, env) | |
2137 | SIM_DESC sd; | |
2138 | struct _bfd *abfd; | |
2139 | char **argv; | |
2140 | char **env; | |
2141 | { | |
2142 | if (abfd != NULL) | |
2143 | cpu.pc = bfd_get_start_address (abfd); | |
2144 | else | |
2145 | cpu.pc = 0; | |
2146 | return SIM_RC_OK; | |
2147 | } | |
2148 | ||
2149 | void | |
2150 | sim_do_command (sd, cmd) | |
2151 | SIM_DESC sd; | |
2152 | char *cmd; | |
2153 | { | |
2154 | (*sim_callback->printf_filtered) (sim_callback, | |
2155 | "This simulator does not accept any commands.\n"); | |
2156 | } | |
2157 | ||
2158 | void | |
2159 | sim_set_callbacks (ptr) | |
2160 | struct host_callback_struct *ptr; | |
2161 | { | |
2162 | sim_callback = ptr; | |
2163 | } |