Commit | Line | Data |
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ce51bde6 DE |
1 | /* |
2 | * Simulator for the Hitachi H8/300 architecture. | |
3 | * | |
4 | * Written by Steve Chamberlain of Cygnus Support. sac@cygnus.com | |
5 | * | |
6 | * This file is part of H8/300 sim | |
7 | * | |
8 | * | |
9 | * THIS SOFTWARE IS NOT COPYRIGHTED | |
10 | * | |
11 | * Cygnus offers the following for use in the public domain. Cygnus makes no | |
12 | * warranty with regard to the software or its performance and the user | |
13 | * accepts the software "AS IS" with all faults. | |
14 | * | |
15 | * CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO THIS | |
16 | * SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY | |
17 | * AND FITNESS FOR A PARTICULAR PURPOSE. | |
ce51bde6 DE |
18 | */ |
19 | ||
e656ecf9 DE |
20 | #include "config.h" |
21 | ||
ce51bde6 | 22 | #include <signal.h> |
e656ecf9 DE |
23 | #ifdef HAVE_TIME_H |
24 | #include <time.h> | |
25 | #endif | |
26 | #ifdef HAVE_STDLIB_H | |
27 | #include <stdlib.h> | |
7478904c | 28 | #endif |
ce51bde6 | 29 | #include <sys/param.h> |
4dfb4ffc | 30 | #include "wait.h" |
0693d363 | 31 | #include "ansidecl.h" |
46337270 | 32 | #include "bfd.h" |
e656ecf9 | 33 | #include "callback.h" |
a415cf0a | 34 | #include "remote-sim.h" |
ce51bde6 DE |
35 | |
36 | int debug; | |
37 | ||
46337270 DE |
38 | host_callback *sim_callback; |
39 | ||
40 | static SIM_OPEN_KIND sim_kind; | |
41 | static char *myname; | |
42 | ||
43 | /* FIXME: Needs to live in header file. | |
44 | This header should also include the things in remote-sim.h. | |
45 | One could move this to remote-sim.h but this function isn't needed | |
46 | by gdb. */ | |
47 | void sim_set_simcache_size PARAMS ((int)); | |
ce51bde6 DE |
48 | |
49 | #define X(op, size) op*4+size | |
50 | ||
28655f00 | 51 | #define SP (h8300hmode ? SL:SW) |
ce51bde6 DE |
52 | #define SB 0 |
53 | #define SW 1 | |
54 | #define SL 2 | |
55 | #define OP_REG 1 | |
56 | #define OP_DEC 2 | |
57 | #define OP_DISP 3 | |
58 | #define OP_INC 4 | |
59 | #define OP_PCREL 5 | |
60 | #define OP_MEM 6 | |
61 | #define OP_CCR 7 | |
62 | #define OP_IMM 8 | |
63 | #define OP_ABS 10 | |
64 | #define h8_opcodes ops | |
65 | #define DEFINE_TABLE | |
66 | #include "opcode/h8300.h" | |
67 | ||
68 | #include "inst.h" | |
69 | ||
70 | #define LOW_BYTE(x) ((x) & 0xff) | |
71 | #define HIGH_BYTE(x) (((x)>>8) & 0xff) | |
72 | #define P(X,Y) ((X<<8) | Y) | |
73 | ||
74 | #define BUILDSR() cpu.ccr = (N << 3) | (Z << 2) | (V<<1) | C; | |
75 | ||
76 | #define GETSR() \ | |
77 | c = (cpu.ccr >> 0) & 1;\ | |
78 | v = (cpu.ccr >> 1) & 1;\ | |
79 | nz = !((cpu.ccr >> 2) & 1);\ | |
80 | n = (cpu.ccr >> 3) & 1; | |
81 | ||
82 | #ifdef __CHAR_IS_SIGNED__ | |
83 | #define SEXTCHAR(x) ((char)(x)) | |
84 | #endif | |
85 | ||
86 | #ifndef SEXTCHAR | |
171f4664 | 87 | #define SEXTCHAR(x) ((x & 0x80) ? (x | ~0xff): x & 0xff) |
ce51bde6 DE |
88 | #endif |
89 | ||
90 | #define UEXTCHAR(x) ((x) & 0xff) | |
91 | #define UEXTSHORT(x) ((x) & 0xffff) | |
92 | #define SEXTSHORT(x) ((short)(x)) | |
93 | ||
94 | static cpu_state_type cpu; | |
95 | ||
28655f00 | 96 | int h8300hmode = 0; |
171f4664 | 97 | int h8300smode = 0; |
ce51bde6 | 98 | |
e656ecf9 DE |
99 | static int memory_size; |
100 | ||
ce51bde6 DE |
101 | |
102 | static int | |
103 | get_now () | |
104 | { | |
7478904c | 105 | #ifndef WIN32 |
0693d363 | 106 | return time (0); |
28655f00 | 107 | #endif |
7478904c | 108 | return 0; |
ce51bde6 DE |
109 | } |
110 | ||
111 | static int | |
112 | now_persec () | |
113 | { | |
28655f00 | 114 | return 1; |
ce51bde6 DE |
115 | } |
116 | ||
117 | ||
118 | static int | |
119 | bitfrom (x) | |
120 | { | |
ce51bde6 DE |
121 | switch (x & SIZE) |
122 | { | |
123 | case L_8: | |
124 | return SB; | |
125 | case L_16: | |
126 | return SW; | |
127 | case L_32: | |
128 | return SL; | |
129 | case L_P: | |
28655f00 | 130 | return h8300hmode ? SL : SW; |
ce51bde6 | 131 | } |
ce51bde6 DE |
132 | } |
133 | ||
134 | static | |
135 | unsigned int | |
136 | lvalue (x, rn) | |
137 | { | |
138 | switch (x / 4) | |
139 | { | |
140 | case OP_DISP: | |
0693d363 | 141 | if (rn == 8) |
ce51bde6 | 142 | { |
0693d363 | 143 | return X (OP_IMM, SP); |
ce51bde6 | 144 | } |
0693d363 DE |
145 | return X (OP_REG, SP); |
146 | ||
ce51bde6 DE |
147 | case OP_MEM: |
148 | ||
149 | return X (OP_MEM, SP); | |
150 | default: | |
151 | abort (); | |
152 | } | |
153 | } | |
154 | ||
155 | static unsigned int | |
156 | decode (addr, data, dst) | |
157 | int addr; | |
158 | unsigned char *data; | |
159 | decoded_inst *dst; | |
160 | ||
161 | { | |
162 | int rs = 0; | |
163 | int rd = 0; | |
164 | int rdisp = 0; | |
165 | int abs = 0; | |
166 | int plen = 0; | |
e24146ec | 167 | int bit = 0; |
ce51bde6 DE |
168 | |
169 | struct h8_opcode *q = h8_opcodes; | |
170 | int size = 0; | |
171 | dst->dst.type = -1; | |
172 | dst->src.type = -1; | |
173 | /* Find the exact opcode/arg combo */ | |
174 | while (q->name) | |
175 | { | |
176 | op_type *nib; | |
177 | unsigned int len = 0; | |
178 | ||
179 | nib = q->data.nib; | |
180 | ||
181 | while (1) | |
182 | { | |
183 | op_type looking_for = *nib; | |
184 | int thisnib = data[len >> 1]; | |
185 | ||
186 | thisnib = (len & 1) ? (thisnib & 0xf) : ((thisnib >> 4) & 0xf); | |
187 | ||
0693d363 | 188 | if (looking_for < 16 && looking_for >= 0) |
ce51bde6 | 189 | { |
ce51bde6 DE |
190 | if (looking_for != thisnib) |
191 | goto fail; | |
192 | } | |
193 | else | |
194 | { | |
ce51bde6 DE |
195 | if ((int) looking_for & (int) B31) |
196 | { | |
197 | if (!(((int) thisnib & 0x8) != 0)) | |
198 | goto fail; | |
199 | looking_for = (op_type) ((int) looking_for & ~(int) | |
200 | B31); | |
201 | thisnib &= 0x7; | |
ce51bde6 DE |
202 | } |
203 | if ((int) looking_for & (int) B30) | |
204 | { | |
205 | if (!(((int) thisnib & 0x8) == 0)) | |
206 | goto fail; | |
207 | looking_for = (op_type) ((int) looking_for & ~(int) B30); | |
208 | } | |
209 | if (looking_for & DBIT) | |
210 | { | |
0693d363 DE |
211 | if ((looking_for & 5) != (thisnib & 5)) |
212 | goto fail; | |
ce51bde6 DE |
213 | abs = (thisnib & 0x8) ? 2 : 1; |
214 | } | |
215 | else if (looking_for & (REG | IND | INC | DEC)) | |
216 | { | |
217 | if (looking_for & REG) | |
218 | { | |
219 | /* | |
220 | * Can work out size from the | |
221 | * register | |
222 | */ | |
223 | size = bitfrom (looking_for); | |
224 | } | |
225 | if (looking_for & SRC) | |
226 | { | |
227 | rs = thisnib; | |
228 | } | |
229 | else | |
230 | { | |
231 | rd = thisnib; | |
232 | } | |
233 | } | |
234 | else if (looking_for & L_16) | |
235 | { | |
236 | abs = (data[len >> 1]) * 256 + data[(len + 2) >> 1]; | |
237 | plen = 16; | |
0693d363 | 238 | if (looking_for & (PCREL | DISP)) |
ce51bde6 DE |
239 | { |
240 | abs = (short) (abs); | |
241 | } | |
242 | } | |
243 | else if (looking_for & ABSJMP) | |
244 | { | |
245 | abs = | |
246 | (data[1] << 16) | |
247 | | (data[2] << 8) | |
248 | | (data[3]); | |
249 | } | |
0693d363 DE |
250 | else if (looking_for & MEMIND) |
251 | { | |
252 | abs = data[1]; | |
253 | } | |
ce51bde6 DE |
254 | else if (looking_for & L_32) |
255 | { | |
256 | int i = len >> 1; | |
257 | abs = (data[i] << 24) | |
258 | | (data[i + 1] << 16) | |
259 | | (data[i + 2] << 8) | |
260 | | (data[i + 3]); | |
261 | ||
262 | plen = 32; | |
ce51bde6 DE |
263 | } |
264 | else if (looking_for & L_24) | |
265 | { | |
266 | int i = len >> 1; | |
0693d363 | 267 | abs = (data[i] << 16) | (data[i + 1] << 8) | (data[i + 2]); |
ce51bde6 DE |
268 | plen = 24; |
269 | } | |
270 | else if (looking_for & IGNORE) | |
271 | { | |
0693d363 | 272 | /* nothing to do */ |
ce51bde6 DE |
273 | } |
274 | else if (looking_for & DISPREG) | |
275 | { | |
276 | rdisp = thisnib & 0x7; | |
277 | } | |
278 | else if (looking_for & KBIT) | |
279 | { | |
280 | switch (thisnib) | |
281 | { | |
282 | case 9: | |
283 | abs = 4; | |
284 | break; | |
285 | case 8: | |
286 | abs = 2; | |
287 | break; | |
288 | case 0: | |
289 | abs = 1; | |
290 | break; | |
291 | } | |
292 | } | |
293 | else if (looking_for & L_8) | |
294 | { | |
295 | plen = 8; | |
296 | ||
297 | if (looking_for & PCREL) | |
298 | { | |
299 | abs = SEXTCHAR (data[len >> 1]); | |
300 | } | |
e24146ec JL |
301 | else if (looking_for & ABS8MEM) |
302 | { | |
303 | plen = 8; | |
304 | abs = h8300hmode ? ~0xff0000ff : ~0xffff00ff; | |
305 | abs |= data[len >> 1] & 0xff ; | |
306 | } | |
307 | else | |
ce51bde6 DE |
308 | { |
309 | abs = data[len >> 1] & 0xff; | |
310 | } | |
311 | } | |
312 | else if (looking_for & L_3) | |
313 | { | |
314 | plen = 3; | |
315 | ||
e24146ec | 316 | bit = thisnib; |
ce51bde6 DE |
317 | } |
318 | else if (looking_for == E) | |
319 | { | |
320 | dst->op = q; | |
321 | ||
322 | /* Fill in the args */ | |
323 | { | |
324 | op_type *args = q->args.nib; | |
325 | int hadone = 0; | |
326 | ||
ce51bde6 DE |
327 | while (*args != E) |
328 | { | |
329 | int x = *args; | |
330 | int rn = (x & DST) ? rd : rs; | |
331 | ea_type *p; | |
332 | ||
333 | if (x & DST) | |
334 | { | |
335 | p = &(dst->dst); | |
336 | } | |
337 | else | |
338 | { | |
339 | p = &(dst->src); | |
340 | } | |
341 | ||
e24146ec JL |
342 | if (x & (L_3)) |
343 | { | |
344 | p->type = X (OP_IMM, size); | |
345 | p->literal = bit; | |
346 | } | |
347 | else if (x & (IMM | KBIT | DBIT)) | |
ce51bde6 DE |
348 | { |
349 | p->type = X (OP_IMM, size); | |
350 | p->literal = abs; | |
351 | } | |
352 | else if (x & REG) | |
353 | { | |
0693d363 DE |
354 | /* Reset the size, some |
355 | ops (like mul) have two sizes */ | |
356 | ||
ce51bde6 DE |
357 | size = bitfrom (x); |
358 | p->type = X (OP_REG, size); | |
359 | p->reg = rn; | |
360 | } | |
361 | else if (x & INC) | |
362 | { | |
363 | p->type = X (OP_INC, size); | |
364 | p->reg = rn & 0x7; | |
365 | } | |
366 | else if (x & DEC) | |
367 | { | |
368 | p->type = X (OP_DEC, size); | |
369 | p->reg = rn & 0x7; | |
370 | } | |
371 | else if (x & IND) | |
372 | { | |
373 | p->type = X (OP_DISP, size); | |
374 | p->reg = rn & 0x7; | |
375 | p->literal = 0; | |
376 | } | |
e24146ec | 377 | else if (x & (ABS | ABSJMP | ABS8MEM)) |
ce51bde6 DE |
378 | { |
379 | p->type = X (OP_DISP, size); | |
380 | p->literal = abs; | |
381 | p->reg = 8; | |
382 | } | |
383 | else if (x & MEMIND) | |
384 | { | |
385 | p->type = X (OP_MEM, size); | |
386 | p->literal = abs; | |
387 | } | |
388 | else if (x & PCREL) | |
389 | { | |
390 | p->type = X (OP_PCREL, size); | |
391 | p->literal = abs + addr + 2; | |
0693d363 DE |
392 | if (x & L_16) |
393 | p->literal += 2; | |
ce51bde6 DE |
394 | } |
395 | else if (x & ABSJMP) | |
396 | { | |
397 | p->type = X (OP_IMM, SP); | |
398 | p->literal = abs; | |
399 | } | |
400 | else if (x & DISP) | |
401 | { | |
402 | p->type = X (OP_DISP, size); | |
403 | p->literal = abs; | |
404 | p->reg = rdisp & 0x7; | |
405 | } | |
406 | else if (x & CCR) | |
407 | { | |
408 | p->type = OP_CCR; | |
409 | } | |
410 | else | |
411 | printf ("Hmmmm %x", x); | |
412 | ||
ce51bde6 DE |
413 | args++; |
414 | } | |
415 | } | |
416 | ||
417 | /* | |
0693d363 DE |
418 | * But a jmp or a jsr gets |
419 | * automagically lvalued, since we | |
420 | * branch to their address not their | |
421 | * contents | |
422 | */ | |
ce51bde6 DE |
423 | if (q->how == O (O_JSR, SB) |
424 | || q->how == O (O_JMP, SB)) | |
425 | { | |
426 | dst->src.type = lvalue (dst->src.type, dst->src.reg); | |
427 | } | |
428 | ||
ce51bde6 DE |
429 | if (dst->dst.type == -1) |
430 | dst->dst = dst->src; | |
0693d363 | 431 | |
ce51bde6 DE |
432 | dst->opcode = q->how; |
433 | dst->cycles = q->time; | |
434 | ||
435 | /* And a jsr to 0xc4 is turned into a magic trap */ | |
0693d363 DE |
436 | |
437 | if (dst->opcode == O (O_JSR, SB)) | |
ce51bde6 | 438 | { |
0693d363 | 439 | if (dst->src.literal == 0xc4) |
ce51bde6 | 440 | { |
0693d363 | 441 | dst->opcode = O (O_SYSCALL, SB); |
ce51bde6 DE |
442 | } |
443 | } | |
0693d363 | 444 | |
ce51bde6 DE |
445 | dst->next_pc = addr + len / 2; |
446 | return; | |
447 | } | |
448 | else | |
449 | { | |
450 | printf ("Dont understand %x \n", looking_for); | |
451 | } | |
452 | } | |
0693d363 | 453 | |
ce51bde6 DE |
454 | len++; |
455 | nib++; | |
456 | } | |
0693d363 | 457 | |
ce51bde6 DE |
458 | fail: |
459 | q++; | |
460 | } | |
0693d363 | 461 | |
ce51bde6 DE |
462 | dst->opcode = O (O_ILL, SB); |
463 | } | |
464 | ||
465 | ||
466 | static void | |
467 | compile (pc) | |
468 | { | |
469 | int idx; | |
0693d363 | 470 | |
ce51bde6 | 471 | /* find the next cache entry to use */ |
0693d363 | 472 | |
ce51bde6 DE |
473 | idx = cpu.cache_top + 1; |
474 | cpu.compiles++; | |
475 | if (idx >= cpu.csize) | |
476 | { | |
477 | idx = 1; | |
478 | } | |
479 | cpu.cache_top = idx; | |
0693d363 | 480 | |
ce51bde6 DE |
481 | /* Throw away its old meaning */ |
482 | cpu.cache_idx[cpu.cache[idx].oldpc] = 0; | |
0693d363 | 483 | |
ce51bde6 DE |
484 | /* set to new address */ |
485 | cpu.cache[idx].oldpc = pc; | |
0693d363 | 486 | |
ce51bde6 DE |
487 | /* fill in instruction info */ |
488 | decode (pc, cpu.memory + pc, cpu.cache + idx); | |
0693d363 | 489 | |
ce51bde6 DE |
490 | /* point to new cache entry */ |
491 | cpu.cache_idx[pc] = idx; | |
492 | } | |
493 | ||
494 | ||
495 | static unsigned char *breg[18]; | |
496 | static unsigned short *wreg[18]; | |
497 | static unsigned int *lreg[18]; | |
498 | ||
499 | #define GET_B_REG(x) *(breg[x]) | |
500 | #define SET_B_REG(x,y) (*(breg[x])) = (y) | |
501 | #define GET_W_REG(x) *(wreg[x]) | |
502 | #define SET_W_REG(x,y) (*(wreg[x])) = (y) | |
503 | ||
504 | #define GET_L_REG(x) *(lreg[x]) | |
505 | #define SET_L_REG(x,y) (*(lreg[x])) = (y) | |
506 | ||
507 | #define GET_MEMORY_L(x) \ | |
7e1e013f JL |
508 | (x < memory_size \ |
509 | ? ((cpu.memory[x+0] << 24) | (cpu.memory[x+1] << 16) \ | |
510 | | (cpu.memory[x+2] << 8) | cpu.memory[x+3]) \ | |
511 | : ((cpu.eightbit[(x+0) & 0xff] << 24) | (cpu.eightbit[(x+1) & 0xff] << 16) \ | |
512 | | (cpu.eightbit[(x+2) & 0xff] << 8) | cpu.eightbit[(x+3) & 0xff])) | |
ce51bde6 DE |
513 | |
514 | #define GET_MEMORY_W(x) \ | |
7e1e013f JL |
515 | (x < memory_size \ |
516 | ? ((cpu.memory[x+0] << 8) | (cpu.memory[x+1] << 0)) \ | |
517 | : ((cpu.eightbit[(x+0) & 0xff] << 8) | (cpu.eightbit[(x+1) & 0xff] << 0))) | |
ce51bde6 DE |
518 | |
519 | ||
7e1e013f JL |
520 | #define GET_MEMORY_B(x) \ |
521 | (x < memory_size ? (cpu.memory[x]) : (cpu.eightbit[x & 0xff])) | |
ce51bde6 DE |
522 | |
523 | #define SET_MEMORY_L(x,y) \ | |
7e1e013f JL |
524 | { register unsigned char *_p; register int __y = y; \ |
525 | _p = (x < memory_size ? cpu.memory+x : cpu.eightbit + (x & 0xff)); \ | |
526 | _p[0] = (__y)>>24; _p[1] = (__y)>>16; \ | |
527 | _p[2] = (__y)>>8; _p[3] = (__y)>>0;} | |
ce51bde6 | 528 | |
7e1e013f JL |
529 | #define SET_MEMORY_W(x,y) \ |
530 | { register unsigned char *_p; register int __y = y; \ | |
531 | _p = (x < memory_size ? cpu.memory+x : cpu.eightbit + (x & 0xff)); \ | |
532 | _p[0] = (__y)>>8; _p[1] =(__y);} | |
533 | ||
534 | #define SET_MEMORY_B(x,y) \ | |
535 | (x < memory_size ? (cpu.memory[(x)] = y) : (cpu.eightbit[x & 0xff] = y)) | |
ce51bde6 DE |
536 | |
537 | int | |
89a2c4fd | 538 | fetch (arg, n) |
0693d363 | 539 | ea_type *arg; |
ce51bde6 DE |
540 | { |
541 | int rn = arg->reg; | |
542 | int abs = arg->literal; | |
543 | int r; | |
544 | int t; | |
0693d363 | 545 | |
ce51bde6 DE |
546 | switch (arg->type) |
547 | { | |
548 | case X (OP_REG, SB): | |
549 | return GET_B_REG (rn); | |
550 | case X (OP_REG, SW): | |
551 | return GET_W_REG (rn); | |
552 | case X (OP_REG, SL): | |
553 | return GET_L_REG (rn); | |
554 | case X (OP_IMM, SB): | |
555 | case X (OP_IMM, SW): | |
556 | case X (OP_IMM, SL): | |
557 | return abs; | |
558 | case X (OP_DEC, SB): | |
0693d363 | 559 | abort (); |
ce51bde6 | 560 | |
0693d363 DE |
561 | case X (OP_INC, SB): |
562 | t = GET_L_REG (rn); | |
ce51bde6 | 563 | t &= cpu.mask; |
0693d363 DE |
564 | r = GET_MEMORY_B (t); |
565 | t++; | |
ce51bde6 | 566 | t = t & cpu.mask; |
0693d363 | 567 | SET_L_REG (rn, t); |
ce51bde6 DE |
568 | return r; |
569 | break; | |
0693d363 DE |
570 | case X (OP_INC, SW): |
571 | t = GET_L_REG (rn); | |
ce51bde6 | 572 | t &= cpu.mask; |
0693d363 DE |
573 | r = GET_MEMORY_W (t); |
574 | t += 2; | |
ce51bde6 | 575 | t = t & cpu.mask; |
0693d363 | 576 | SET_L_REG (rn, t); |
ce51bde6 | 577 | return r; |
0693d363 DE |
578 | case X (OP_INC, SL): |
579 | t = GET_L_REG (rn); | |
ce51bde6 | 580 | t &= cpu.mask; |
0693d363 DE |
581 | r = GET_MEMORY_L (t); |
582 | ||
583 | t += 4; | |
ce51bde6 | 584 | t = t & cpu.mask; |
0693d363 | 585 | SET_L_REG (rn, t); |
ce51bde6 | 586 | return r; |
0693d363 | 587 | |
ce51bde6 DE |
588 | case X (OP_DISP, SB): |
589 | t = GET_L_REG (rn) + abs; | |
590 | t &= cpu.mask; | |
591 | return GET_MEMORY_B (t); | |
0693d363 | 592 | |
ce51bde6 DE |
593 | case X (OP_DISP, SW): |
594 | t = GET_L_REG (rn) + abs; | |
595 | t &= cpu.mask; | |
596 | return GET_MEMORY_W (t); | |
0693d363 | 597 | |
ce51bde6 DE |
598 | case X (OP_DISP, SL): |
599 | t = GET_L_REG (rn) + abs; | |
600 | t &= cpu.mask; | |
601 | return GET_MEMORY_L (t); | |
0693d363 DE |
602 | |
603 | case X (OP_MEM, SL): | |
604 | t = GET_MEMORY_L (abs); | |
605 | t &= cpu.mask; | |
606 | return t; | |
607 | ||
e24146ec JL |
608 | case X (OP_MEM, SW): |
609 | t = GET_MEMORY_W (abs); | |
610 | t &= cpu.mask; | |
611 | return t; | |
612 | ||
ce51bde6 DE |
613 | default: |
614 | abort (); | |
0693d363 | 615 | |
ce51bde6 DE |
616 | } |
617 | } | |
618 | ||
619 | ||
0693d363 DE |
620 | static |
621 | void | |
622 | store (arg, n) | |
623 | ea_type *arg; | |
624 | int n; | |
ce51bde6 DE |
625 | { |
626 | int rn = arg->reg; | |
627 | int abs = arg->literal; | |
628 | int t; | |
0693d363 | 629 | |
ce51bde6 DE |
630 | switch (arg->type) |
631 | { | |
632 | case X (OP_REG, SB): | |
633 | SET_B_REG (rn, n); | |
634 | break; | |
635 | case X (OP_REG, SW): | |
636 | SET_W_REG (rn, n); | |
637 | break; | |
638 | case X (OP_REG, SL): | |
639 | SET_L_REG (rn, n); | |
640 | break; | |
0693d363 | 641 | |
ce51bde6 | 642 | case X (OP_DEC, SB): |
0693d363 | 643 | t = GET_L_REG (rn) - 1; |
ce51bde6 | 644 | t &= cpu.mask; |
0693d363 | 645 | SET_L_REG (rn, t); |
ce51bde6 DE |
646 | SET_MEMORY_B (t, n); |
647 | ||
648 | break; | |
649 | case X (OP_DEC, SW): | |
0693d363 | 650 | t = (GET_L_REG (rn) - 2) & cpu.mask; |
ce51bde6 DE |
651 | SET_L_REG (rn, t); |
652 | SET_MEMORY_W (t, n); | |
653 | break; | |
654 | ||
655 | case X (OP_DEC, SL): | |
0693d363 | 656 | t = (GET_L_REG (rn) - 4) & cpu.mask; |
89a2c4fd | 657 | SET_L_REG (rn, t); |
0693d363 | 658 | SET_MEMORY_L (t, n); |
ce51bde6 DE |
659 | break; |
660 | ||
ce51bde6 DE |
661 | case X (OP_DISP, SB): |
662 | t = GET_L_REG (rn) + abs; | |
663 | t &= cpu.mask; | |
664 | SET_MEMORY_B (t, n); | |
665 | break; | |
666 | ||
667 | case X (OP_DISP, SW): | |
668 | t = GET_L_REG (rn) + abs; | |
669 | t &= cpu.mask; | |
670 | SET_MEMORY_W (t, n); | |
671 | break; | |
672 | ||
673 | case X (OP_DISP, SL): | |
674 | t = GET_L_REG (rn) + abs; | |
675 | t &= cpu.mask; | |
676 | SET_MEMORY_L (t, n); | |
677 | break; | |
678 | default: | |
679 | abort (); | |
680 | } | |
681 | } | |
682 | ||
683 | ||
684 | static union | |
0693d363 DE |
685 | { |
686 | short int i; | |
687 | struct | |
688 | { | |
689 | char low; | |
690 | char high; | |
691 | } | |
692 | u; | |
693 | } | |
ce51bde6 DE |
694 | |
695 | littleendian; | |
696 | ||
697 | static | |
698 | void | |
699 | init_pointers () | |
700 | { | |
701 | static int init; | |
702 | ||
703 | if (!init) | |
704 | { | |
705 | int i; | |
706 | ||
707 | init = 1; | |
708 | littleendian.i = 1; | |
709 | ||
e656ecf9 DE |
710 | if (h8300hmode) |
711 | memory_size = H8300H_MSIZE; | |
712 | else | |
713 | memory_size = H8300_MSIZE; | |
714 | cpu.memory = (unsigned char *) calloc (sizeof (char), memory_size); | |
715 | cpu.cache_idx = (unsigned short *) calloc (sizeof (short), memory_size); | |
7e1e013f | 716 | cpu.eightbit = (unsigned char *) calloc (sizeof (char), 256); |
e656ecf9 DE |
717 | |
718 | /* `msize' must be a power of two */ | |
719 | if ((memory_size & (memory_size - 1)) != 0) | |
720 | abort (); | |
721 | cpu.mask = memory_size - 1; | |
0693d363 | 722 | |
ce51bde6 DE |
723 | for (i = 0; i < 9; i++) |
724 | { | |
725 | cpu.regs[i] = 0; | |
726 | } | |
727 | ||
728 | for (i = 0; i < 8; i++) | |
729 | { | |
730 | unsigned char *p = (unsigned char *) (cpu.regs + i); | |
731 | unsigned char *e = (unsigned char *) (cpu.regs + i + 1); | |
732 | unsigned short *q = (unsigned short *) (cpu.regs + i); | |
733 | unsigned short *u = (unsigned short *) (cpu.regs + i + 1); | |
734 | cpu.regs[i] = 0x00112233; | |
735 | while (p < e) | |
736 | { | |
737 | if (*p == 0x22) | |
738 | { | |
739 | breg[i] = p; | |
740 | } | |
741 | if (*p == 0x33) | |
742 | { | |
0693d363 | 743 | breg[i + 8] = p; |
ce51bde6 DE |
744 | } |
745 | p++; | |
746 | } | |
747 | while (q < u) | |
748 | { | |
749 | if (*q == 0x2233) | |
750 | { | |
751 | wreg[i] = q; | |
752 | } | |
753 | if (*q == 0x0011) | |
754 | { | |
755 | wreg[i + 8] = q; | |
756 | } | |
757 | q++; | |
758 | } | |
759 | cpu.regs[i] = 0; | |
760 | lreg[i] = &cpu.regs[i]; | |
761 | } | |
762 | ||
ce51bde6 | 763 | lreg[8] = &cpu.regs[8]; |
0693d363 | 764 | |
ce51bde6 DE |
765 | /* initialize the seg registers */ |
766 | if (!cpu.cache) | |
46337270 | 767 | sim_set_simcache_size (CSIZE); |
ce51bde6 DE |
768 | } |
769 | } | |
770 | ||
771 | static void | |
772 | control_c (sig, code, scp, addr) | |
773 | int sig; | |
774 | int code; | |
775 | char *scp; | |
776 | char *addr; | |
777 | { | |
46337270 | 778 | cpu.state = SIM_STATE_STOPPED; |
ce51bde6 DE |
779 | cpu.exception = SIGINT; |
780 | } | |
781 | ||
782 | #define C (c != 0) | |
783 | #define Z (nz == 0) | |
784 | #define V (v != 0) | |
785 | #define N (n != 0) | |
786 | ||
28655f00 | 787 | static int |
0693d363 | 788 | mop (code, bsize, sign) |
28655f00 SC |
789 | decoded_inst *code; |
790 | int bsize; | |
0693d363 DE |
791 | int sign; |
792 | { | |
793 | int multiplier; | |
794 | int multiplicand; | |
795 | int result; | |
796 | int n, nz; | |
797 | ||
798 | if (sign) | |
799 | { | |
800 | multiplicand = | |
801 | bsize ? SEXTCHAR (GET_W_REG (code->dst.reg)) : | |
802 | SEXTSHORT (GET_W_REG (code->dst.reg)); | |
803 | multiplier = | |
804 | bsize ? SEXTCHAR (GET_B_REG (code->src.reg)) : | |
805 | SEXTSHORT (GET_W_REG (code->src.reg)); | |
806 | } | |
807 | else | |
808 | { | |
809 | multiplicand = bsize ? UEXTCHAR (GET_W_REG (code->dst.reg)) : | |
810 | UEXTSHORT (GET_W_REG (code->dst.reg)); | |
811 | multiplier = | |
812 | bsize ? UEXTCHAR (GET_B_REG (code->src.reg)) : | |
813 | UEXTSHORT (GET_W_REG (code->src.reg)); | |
814 | ||
815 | } | |
816 | result = multiplier * multiplicand; | |
817 | ||
818 | if (sign) | |
819 | { | |
820 | n = result & (bsize ? 0x8000 : 0x80000000); | |
821 | nz = result & (bsize ? 0xffff : 0xffffffff); | |
822 | } | |
823 | if (bsize) | |
824 | { | |
825 | SET_W_REG (code->dst.reg, result); | |
826 | } | |
827 | else | |
828 | { | |
829 | SET_L_REG (code->dst.reg, result); | |
830 | } | |
831 | /* return ((n==1) << 1) | (nz==1); */ | |
832 | ||
833 | } | |
834 | ||
7647e0dd | 835 | #define ONOT(name, how) \ |
0693d363 DE |
836 | case O(name, SB): \ |
837 | { \ | |
838 | int t; \ | |
839 | int hm = 0x80; \ | |
840 | rd = GET_B_REG (code->src.reg); \ | |
841 | how; \ | |
842 | goto shift8; \ | |
843 | } \ | |
844 | case O(name, SW): \ | |
845 | { \ | |
846 | int t; \ | |
847 | int hm = 0x8000; \ | |
848 | rd = GET_W_REG (code->src.reg); \ | |
849 | how; \ | |
850 | goto shift16; \ | |
851 | } \ | |
852 | case O(name, SL): \ | |
853 | { \ | |
854 | int t; \ | |
855 | int hm = 0x80000000; \ | |
856 | rd = GET_L_REG (code->src.reg); \ | |
857 | how; \ | |
858 | goto shift32; \ | |
859 | } | |
860 | ||
7647e0dd JL |
861 | #define OSHIFTS(name, how1, how2) \ |
862 | case O(name, SB): \ | |
863 | { \ | |
864 | int t; \ | |
865 | int hm = 0x80; \ | |
866 | rd = GET_B_REG (code->src.reg); \ | |
867 | if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \ | |
868 | { \ | |
869 | how1; \ | |
870 | } \ | |
871 | else \ | |
872 | { \ | |
873 | how2; \ | |
874 | } \ | |
875 | goto shift8; \ | |
876 | } \ | |
877 | case O(name, SW): \ | |
878 | { \ | |
879 | int t; \ | |
880 | int hm = 0x8000; \ | |
881 | rd = GET_W_REG (code->src.reg); \ | |
882 | if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \ | |
883 | { \ | |
884 | how1; \ | |
885 | } \ | |
886 | else \ | |
887 | { \ | |
888 | how2; \ | |
889 | } \ | |
890 | goto shift16; \ | |
891 | } \ | |
892 | case O(name, SL): \ | |
893 | { \ | |
894 | int t; \ | |
895 | int hm = 0x80000000; \ | |
896 | rd = GET_L_REG (code->src.reg); \ | |
897 | if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \ | |
898 | { \ | |
899 | how1; \ | |
900 | } \ | |
901 | else \ | |
902 | { \ | |
903 | how2; \ | |
904 | } \ | |
905 | goto shift32; \ | |
906 | } | |
907 | ||
0693d363 DE |
908 | #define OBITOP(name,f, s, op) \ |
909 | case O(name, SB): \ | |
910 | { \ | |
911 | int m; \ | |
912 | int b; \ | |
913 | if (f) ea = fetch (&code->dst); \ | |
914 | m=1<< fetch(&code->src); \ | |
915 | op; \ | |
916 | if(s) store (&code->dst,ea); goto next; \ | |
917 | } | |
28655f00 | 918 | |
247fccde AC |
919 | int |
920 | sim_stop (sd) | |
921 | SIM_DESC sd; | |
922 | { | |
923 | cpu.state = SIM_STATE_STOPPED; | |
924 | cpu.exception = SIGINT; | |
925 | return 1; | |
926 | } | |
927 | ||
7478904c | 928 | void |
46337270 DE |
929 | sim_resume (sd, step, siggnal) |
930 | SIM_DESC sd; | |
ce51bde6 DE |
931 | { |
932 | static int init1; | |
933 | int cycles = 0; | |
934 | int insts = 0; | |
935 | int tick_start = get_now (); | |
936 | void (*prev) (); | |
0693d363 | 937 | int poll_count = 0; |
ce51bde6 DE |
938 | int res; |
939 | int tmp; | |
940 | int rd; | |
941 | int ea; | |
942 | int bit; | |
943 | int pc; | |
944 | int c, nz, v, n; | |
7478904c | 945 | int oldmask; |
ce51bde6 DE |
946 | init_pointers (); |
947 | ||
948 | prev = signal (SIGINT, control_c); | |
949 | ||
950 | if (step) | |
951 | { | |
46337270 | 952 | cpu.state = SIM_STATE_STOPPED; |
ce51bde6 DE |
953 | cpu.exception = SIGTRAP; |
954 | } | |
955 | else | |
956 | { | |
46337270 | 957 | cpu.state = SIM_STATE_RUNNING; |
ce51bde6 DE |
958 | cpu.exception = 0; |
959 | } | |
960 | ||
961 | pc = cpu.pc; | |
962 | ||
7e1e013f JL |
963 | /* The PC should never be odd. */ |
964 | if (pc & 0x1) | |
965 | abort (); | |
966 | ||
ce51bde6 | 967 | GETSR (); |
7478904c SC |
968 | oldmask = cpu.mask; |
969 | if (!h8300hmode) | |
970 | cpu.mask = 0xffff; | |
ce51bde6 DE |
971 | do |
972 | { | |
973 | int cidx; | |
974 | decoded_inst *code; | |
975 | ||
976 | top: | |
977 | cidx = cpu.cache_idx[pc]; | |
978 | code = cpu.cache + cidx; | |
979 | ||
980 | ||
981 | #define ALUOP(STORE, NAME, HOW) \ | |
982 | case O(NAME,SB): HOW; if(STORE)goto alu8;else goto just_flags_alu8; \ | |
983 | case O(NAME, SW): HOW; if(STORE)goto alu16;else goto just_flags_alu16; \ | |
984 | case O(NAME,SL): HOW; if(STORE)goto alu32;else goto just_flags_alu32; | |
985 | ||
986 | ||
987 | #define LOGOP(NAME, HOW) \ | |
988 | case O(NAME,SB): HOW; goto log8;\ | |
989 | case O(NAME, SW): HOW; goto log16;\ | |
990 | case O(NAME,SL): HOW; goto log32; | |
991 | ||
992 | ||
993 | ||
994 | #if ADEBUG | |
995 | if (debug) | |
996 | { | |
997 | printf ("%x %d %s\n", pc, code->opcode, | |
998 | code->op ? code->op->name : "**"); | |
999 | } | |
1000 | cpu.stats[code->opcode]++; | |
0693d363 | 1001 | |
ce51bde6 DE |
1002 | #endif |
1003 | ||
1004 | cycles += code->cycles; | |
1005 | insts++; | |
1006 | switch (code->opcode) | |
1007 | { | |
1008 | case 0: | |
1009 | /* | |
1010 | * This opcode is a fake for when we get to an | |
1011 | * instruction which hasnt been compiled | |
1012 | */ | |
1013 | compile (pc); | |
1014 | goto top; | |
1015 | break; | |
1016 | ||
1017 | ||
1018 | case O (O_SUBX, SB): | |
1019 | rd = fetch (&code->dst); | |
1020 | ea = fetch (&code->src); | |
0693d363 | 1021 | ea = -(ea + C); |
ce51bde6 DE |
1022 | res = rd + ea; |
1023 | goto alu8; | |
1024 | ||
1025 | case O (O_ADDX, SB): | |
1026 | rd = fetch (&code->dst); | |
1027 | ea = fetch (&code->src); | |
1028 | ea = C + ea; | |
1029 | res = rd + ea; | |
1030 | goto alu8; | |
1031 | ||
cf5b4aa6 DE |
1032 | #define EA ea = fetch(&code->src); |
1033 | #define RD_EA ea = fetch(&code->src); rd = fetch(&code->dst); | |
ce51bde6 | 1034 | |
0693d363 DE |
1035 | ALUOP (1, O_SUB, RD_EA; |
1036 | ea = -ea; | |
1037 | res = rd + ea); | |
1038 | ALUOP (1, O_NEG, EA; | |
1039 | ea = -ea; | |
1040 | rd = 0; | |
1041 | res = rd + ea); | |
ce51bde6 | 1042 | |
0693d363 DE |
1043 | case O (O_ADD, SB): |
1044 | rd = GET_B_REG (code->dst.reg); | |
1045 | ea = fetch (&code->src); | |
ce51bde6 DE |
1046 | res = rd + ea; |
1047 | goto alu8; | |
0693d363 DE |
1048 | case O (O_ADD, SW): |
1049 | rd = GET_W_REG (code->dst.reg); | |
1050 | ea = fetch (&code->src); | |
ce51bde6 DE |
1051 | res = rd + ea; |
1052 | goto alu16; | |
0693d363 DE |
1053 | case O (O_ADD, SL): |
1054 | rd = GET_L_REG (code->dst.reg); | |
1055 | ea = fetch (&code->src); | |
ce51bde6 DE |
1056 | res = rd + ea; |
1057 | goto alu32; | |
ce51bde6 | 1058 | |
ce51bde6 | 1059 | |
0693d363 DE |
1060 | LOGOP (O_AND, RD_EA; |
1061 | res = rd & ea); | |
1062 | ||
1063 | LOGOP (O_OR, RD_EA; | |
1064 | res = rd | ea); | |
ce51bde6 | 1065 | |
0693d363 DE |
1066 | LOGOP (O_XOR, RD_EA; |
1067 | res = rd ^ ea); | |
ce51bde6 DE |
1068 | |
1069 | ||
0693d363 DE |
1070 | case O (O_MOV_TO_MEM, SB): |
1071 | res = GET_B_REG (code->src.reg); | |
ce51bde6 | 1072 | goto log8; |
0693d363 DE |
1073 | case O (O_MOV_TO_MEM, SW): |
1074 | res = GET_W_REG (code->src.reg); | |
ce51bde6 | 1075 | goto log16; |
0693d363 DE |
1076 | case O (O_MOV_TO_MEM, SL): |
1077 | res = GET_L_REG (code->src.reg); | |
ce51bde6 DE |
1078 | goto log32; |
1079 | ||
1080 | ||
0693d363 DE |
1081 | case O (O_MOV_TO_REG, SB): |
1082 | res = fetch (&code->src); | |
1083 | SET_B_REG (code->dst.reg, res); | |
ce51bde6 | 1084 | goto just_flags_log8; |
0693d363 DE |
1085 | case O (O_MOV_TO_REG, SW): |
1086 | res = fetch (&code->src); | |
1087 | SET_W_REG (code->dst.reg, res); | |
ce51bde6 | 1088 | goto just_flags_log16; |
0693d363 DE |
1089 | case O (O_MOV_TO_REG, SL): |
1090 | res = fetch (&code->src); | |
1091 | SET_L_REG (code->dst.reg, res); | |
ce51bde6 DE |
1092 | goto just_flags_log32; |
1093 | ||
1094 | ||
0693d363 DE |
1095 | case O (O_ADDS, SL): |
1096 | SET_L_REG (code->dst.reg, | |
1097 | GET_L_REG (code->dst.reg) | |
1098 | + code->src.literal); | |
1099 | ||
ce51bde6 DE |
1100 | goto next; |
1101 | ||
0693d363 DE |
1102 | case O (O_SUBS, SL): |
1103 | SET_L_REG (code->dst.reg, | |
1104 | GET_L_REG (code->dst.reg) | |
1105 | - code->src.literal); | |
ce51bde6 | 1106 | goto next; |
0693d363 | 1107 | |
ce51bde6 DE |
1108 | case O (O_CMP, SB): |
1109 | rd = fetch (&code->dst); | |
1110 | ea = fetch (&code->src); | |
1111 | ea = -ea; | |
1112 | res = rd + ea; | |
1113 | goto just_flags_alu8; | |
1114 | ||
1115 | case O (O_CMP, SW): | |
1116 | rd = fetch (&code->dst); | |
1117 | ea = fetch (&code->src); | |
1118 | ea = -ea; | |
1119 | res = rd + ea; | |
1120 | goto just_flags_alu16; | |
1121 | ||
1122 | case O (O_CMP, SL): | |
1123 | rd = fetch (&code->dst); | |
1124 | ea = fetch (&code->src); | |
1125 | ea = -ea; | |
1126 | res = rd + ea; | |
1127 | goto just_flags_alu32; | |
1128 | ||
1129 | ||
1130 | case O (O_DEC, SB): | |
1131 | rd = GET_B_REG (code->src.reg); | |
1132 | ea = -1; | |
1133 | res = rd + ea; | |
1134 | SET_B_REG (code->src.reg, res); | |
1135 | goto just_flags_inc8; | |
1136 | ||
1137 | case O (O_DEC, SW): | |
1138 | rd = GET_W_REG (code->dst.reg); | |
0693d363 | 1139 | ea = -code->src.literal; |
ce51bde6 DE |
1140 | res = rd + ea; |
1141 | SET_W_REG (code->dst.reg, res); | |
1142 | goto just_flags_inc16; | |
1143 | ||
1144 | case O (O_DEC, SL): | |
1145 | rd = GET_L_REG (code->dst.reg); | |
1146 | ea = -code->src.literal; | |
1147 | res = rd + ea; | |
1148 | SET_L_REG (code->dst.reg, res); | |
1149 | goto just_flags_inc32; | |
1150 | ||
1151 | ||
1152 | case O (O_INC, SB): | |
1153 | rd = GET_B_REG (code->src.reg); | |
1154 | ea = 1; | |
1155 | res = rd + ea; | |
1156 | SET_B_REG (code->src.reg, res); | |
1157 | goto just_flags_inc8; | |
1158 | ||
1159 | case O (O_INC, SW): | |
1160 | rd = GET_W_REG (code->dst.reg); | |
1161 | ea = code->src.literal; | |
1162 | res = rd + ea; | |
1163 | SET_W_REG (code->dst.reg, res); | |
1164 | goto just_flags_inc16; | |
1165 | ||
1166 | case O (O_INC, SL): | |
1167 | rd = GET_L_REG (code->dst.reg); | |
1168 | ea = code->src.literal; | |
1169 | res = rd + ea; | |
1170 | SET_L_REG (code->dst.reg, res); | |
1171 | goto just_flags_inc32; | |
1172 | ||
1173 | ||
1174 | #define GET_CCR(x) BUILDSR();x = cpu.ccr | |
0693d363 | 1175 | |
ce51bde6 DE |
1176 | case O (O_ANDC, SB): |
1177 | GET_CCR (rd); | |
1178 | ea = code->src.literal; | |
1179 | res = rd & ea; | |
1180 | goto setc; | |
1181 | ||
0693d363 DE |
1182 | case O (O_ORC, SB): |
1183 | GET_CCR (rd); | |
1184 | ea = code->src.literal; | |
1185 | res = rd | ea; | |
1186 | goto setc; | |
1187 | ||
1188 | case O (O_XORC, SB): | |
1189 | GET_CCR (rd); | |
1190 | ea = code->src.literal; | |
1191 | res = rd ^ ea; | |
1192 | goto setc; | |
1193 | ||
ce51bde6 DE |
1194 | |
1195 | case O (O_BRA, SB): | |
1196 | if (1) | |
1197 | goto condtrue; | |
1198 | goto next; | |
1199 | ||
1200 | case O (O_BRN, SB): | |
1201 | if (0) | |
1202 | goto condtrue; | |
1203 | goto next; | |
1204 | ||
1205 | case O (O_BHI, SB): | |
1206 | if ((C || Z) == 0) | |
1207 | goto condtrue; | |
1208 | goto next; | |
1209 | ||
1210 | ||
1211 | case O (O_BLS, SB): | |
1212 | if ((C || Z)) | |
1213 | goto condtrue; | |
1214 | goto next; | |
1215 | ||
1216 | case O (O_BCS, SB): | |
1217 | if ((C == 1)) | |
1218 | goto condtrue; | |
1219 | goto next; | |
1220 | ||
1221 | case O (O_BCC, SB): | |
1222 | if ((C == 0)) | |
1223 | goto condtrue; | |
1224 | goto next; | |
1225 | ||
1226 | case O (O_BEQ, SB): | |
1227 | if (Z) | |
1228 | goto condtrue; | |
1229 | goto next; | |
1230 | case O (O_BGT, SB): | |
1231 | if (((Z || (N ^ V)) == 0)) | |
1232 | goto condtrue; | |
1233 | goto next; | |
1234 | ||
1235 | ||
1236 | case O (O_BLE, SB): | |
1237 | if (((Z || (N ^ V)) == 1)) | |
1238 | goto condtrue; | |
1239 | goto next; | |
1240 | ||
1241 | case O (O_BGE, SB): | |
1242 | if ((N ^ V) == 0) | |
1243 | goto condtrue; | |
1244 | goto next; | |
1245 | case O (O_BLT, SB): | |
1246 | if ((N ^ V)) | |
1247 | goto condtrue; | |
1248 | goto next; | |
1249 | case O (O_BMI, SB): | |
1250 | if ((N)) | |
1251 | goto condtrue; | |
1252 | goto next; | |
1253 | case O (O_BNE, SB): | |
1254 | if ((Z == 0)) | |
1255 | goto condtrue; | |
1256 | goto next; | |
1257 | ||
1258 | case O (O_BPL, SB): | |
1259 | if (N == 0) | |
1260 | goto condtrue; | |
1261 | goto next; | |
1262 | case O (O_BVC, SB): | |
1263 | if ((V == 0)) | |
1264 | goto condtrue; | |
1265 | goto next; | |
1266 | case O (O_BVS, SB): | |
1267 | if ((V == 1)) | |
1268 | goto condtrue; | |
1269 | goto next; | |
1270 | ||
0693d363 DE |
1271 | case O (O_SYSCALL, SB): |
1272 | printf ("%c", cpu.regs[2]); | |
ce51bde6 | 1273 | goto next; |
ce51bde6 | 1274 | |
7647e0dd JL |
1275 | ONOT (O_NOT, rd = ~rd; v = 0;); |
1276 | OSHIFTS (O_SHLL, | |
1277 | c = rd & hm; v = 0; rd <<= 1, | |
1278 | c = rd & (hm >> 1); v = 0; rd <<= 2); | |
1279 | OSHIFTS (O_SHLR, | |
1280 | c = rd & 1; v = 0; rd = (unsigned int) rd >> 1, | |
1281 | c = rd & 2; v = 0; rd = (unsigned int) rd >> 2); | |
1282 | OSHIFTS (O_SHAL, | |
1283 | c = rd & hm; v = (rd & hm) != ((rd & (hm >> 1)) << 1); rd <<= 1, | |
1284 | c = rd & (hm >> 1); v = (rd & (hm >> 1)) != ((rd & (hm >> 2)) << 2); rd <<= 2); | |
1285 | OSHIFTS (O_SHAR, | |
1286 | t = rd & hm; c = rd & 1; v = 0; rd >>= 1; rd |= t, | |
1287 | t = rd & hm; c = rd & 2; v = 0; rd >>= 2; rd |= t | t >> 1 ); | |
1288 | OSHIFTS (O_ROTL, | |
1289 | c = rd & hm; v = 0; rd <<= 1; rd |= C, | |
9745c593 | 1290 | c = rd & hm; v = 0; rd <<= 1; rd |= C; c = rd & hm; rd <<= 1; rd |= C); |
7647e0dd JL |
1291 | OSHIFTS (O_ROTR, |
1292 | c = rd & 1; v = 0; rd = (unsigned int) rd >> 1; if (c) rd |= hm, | |
9745c593 | 1293 | c = rd & 1; v = 0; rd = (unsigned int) rd >> 1; if (c) rd |= hm; c = rd & 1; rd = (unsigned int) rd >> 1; if (c) rd |= hm); |
7647e0dd JL |
1294 | OSHIFTS (O_ROTXL, |
1295 | t = rd & hm; rd <<= 1; rd |= C; c = t; v = 0, | |
9745c593 | 1296 | t = rd & hm; rd <<= 1; rd |= C; c = t; v = 0; t = rd & hm; rd <<= 1; rd |= C; c = t); |
7647e0dd JL |
1297 | OSHIFTS (O_ROTXR, |
1298 | t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd |= hm; c = t; v = 0, | |
9745c593 | 1299 | t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd |= hm; c = t; v = 0; t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd |= hm; c = t); |
0693d363 DE |
1300 | |
1301 | case O (O_JMP, SB): | |
ce51bde6 DE |
1302 | { |
1303 | pc = fetch (&code->src); | |
1304 | goto end; | |
0693d363 | 1305 | |
ce51bde6 | 1306 | } |
0693d363 | 1307 | |
ce51bde6 DE |
1308 | case O (O_JSR, SB): |
1309 | { | |
1310 | int tmp; | |
1311 | pc = fetch (&code->src); | |
1312 | call: | |
1313 | tmp = cpu.regs[7]; | |
1314 | ||
28655f00 | 1315 | if (h8300hmode) |
ce51bde6 DE |
1316 | { |
1317 | tmp -= 4; | |
1318 | SET_MEMORY_L (tmp, code->next_pc); | |
1319 | } | |
1320 | else | |
1321 | { | |
1322 | tmp -= 2; | |
1323 | SET_MEMORY_W (tmp, code->next_pc); | |
1324 | } | |
1325 | cpu.regs[7] = tmp; | |
1326 | ||
1327 | goto end; | |
1328 | } | |
0693d363 | 1329 | case O (O_BSR, SB): |
ce51bde6 DE |
1330 | pc = code->src.literal; |
1331 | goto call; | |
0693d363 | 1332 | |
46337270 | 1333 | case O (O_RTS, SN): |
ce51bde6 DE |
1334 | { |
1335 | int tmp; | |
1336 | ||
ce51bde6 DE |
1337 | tmp = cpu.regs[7]; |
1338 | ||
28655f00 | 1339 | if (h8300hmode) |
ce51bde6 DE |
1340 | { |
1341 | pc = GET_MEMORY_L (tmp); | |
1342 | tmp += 4; | |
ce51bde6 DE |
1343 | } |
1344 | else | |
1345 | { | |
1346 | pc = GET_MEMORY_W (tmp); | |
1347 | tmp += 2; | |
1348 | } | |
1349 | ||
1350 | cpu.regs[7] = tmp; | |
1351 | goto end; | |
1352 | } | |
1353 | ||
1354 | case O (O_ILL, SB): | |
46337270 | 1355 | cpu.state = SIM_STATE_STOPPED; |
ce51bde6 DE |
1356 | cpu.exception = SIGILL; |
1357 | goto end; | |
46337270 DE |
1358 | case O (O_SLEEP, SN): |
1359 | /* The format of r0 is defined by devo/include/wait.h. */ | |
1360 | #if 0 /* FIXME: Ugh. A breakpoint is the sleep insn. */ | |
1361 | if (WIFEXITED (cpu.regs[0])) | |
1362 | { | |
1363 | cpu.state = SIM_STATE_EXITED; | |
1364 | cpu.exception = WEXITSTATUS (cpu.regs[0]); | |
1365 | } | |
1366 | else if (WIFSTOPPED (cpu.regs[0])) | |
1367 | { | |
1368 | cpu.state = SIM_STATE_STOPPED; | |
1369 | cpu.exception = WSTOPSIG (cpu.regs[0]); | |
1370 | } | |
1371 | else | |
1372 | { | |
1373 | cpu.state = SIM_STATE_SIGNALLED; | |
1374 | cpu.exception = WTERMSIG (cpu.regs[0]); | |
1375 | } | |
1376 | #else | |
1377 | /* FIXME: Doesn't this break for breakpoints when r0 | |
1378 | contains just the right (er, wrong) value? */ | |
1379 | cpu.state = SIM_STATE_STOPPED; | |
4dfb4ffc | 1380 | if (! WIFEXITED (cpu.regs[0]) && WIFSIGNALED (cpu.regs[0])) |
e656ecf9 DE |
1381 | cpu.exception = SIGILL; |
1382 | else | |
1383 | cpu.exception = SIGTRAP; | |
46337270 | 1384 | #endif |
e656ecf9 | 1385 | goto end; |
46337270 DE |
1386 | case O (O_BPT, SN): |
1387 | cpu.state = SIM_STATE_STOPPED; | |
ce51bde6 DE |
1388 | cpu.exception = SIGTRAP; |
1389 | goto end; | |
1390 | ||
0693d363 DE |
1391 | OBITOP (O_BNOT, 1, 1, ea ^= m); |
1392 | OBITOP (O_BTST, 1, 0, nz = ea & m); | |
1393 | OBITOP (O_BCLR, 1, 1, ea &= ~m); | |
1394 | OBITOP (O_BSET, 1, 1, ea |= m); | |
1395 | OBITOP (O_BLD, 1, 0, c = ea & m); | |
1396 | OBITOP (O_BILD, 1, 0, c = !(ea & m)); | |
1397 | OBITOP (O_BST, 1, 1, ea &= ~m; | |
1398 | if (C) ea |= m); | |
1399 | OBITOP (O_BIST, 1, 1, ea &= ~m; | |
1400 | if (!C) ea |= m); | |
1401 | OBITOP (O_BAND, 1, 0, c = (ea & m) && C); | |
1402 | OBITOP (O_BIAND, 1, 0, c = !(ea & m) && C); | |
1403 | OBITOP (O_BOR, 1, 0, c = (ea & m) || C); | |
1404 | OBITOP (O_BIOR, 1, 0, c = !(ea & m) || C); | |
1405 | OBITOP (O_BXOR, 1, 0, c = (ea & m) != C); | |
1406 | OBITOP (O_BIXOR, 1, 0, c = !(ea & m) != C); | |
ce51bde6 DE |
1407 | |
1408 | ||
28655f00 | 1409 | #define MOP(bsize, signed) mop(code, bsize,signed); goto next; |
ce51bde6 | 1410 | |
0693d363 DE |
1411 | case O (O_MULS, SB): |
1412 | MOP (1, 1); | |
1413 | break; | |
1414 | case O (O_MULS, SW): | |
1415 | MOP (0, 1); | |
1416 | break; | |
1417 | case O (O_MULU, SB): | |
1418 | MOP (1, 0); | |
1419 | break; | |
1420 | case O (O_MULU, SW): | |
1421 | MOP (0, 0); | |
1422 | break; | |
ce51bde6 | 1423 | |
ce51bde6 | 1424 | |
0693d363 DE |
1425 | case O (O_DIVU, SB): |
1426 | { | |
1427 | rd = GET_W_REG (code->dst.reg); | |
1428 | ea = GET_B_REG (code->src.reg); | |
1429 | if (ea) | |
1430 | { | |
7e1e013f JL |
1431 | tmp = (unsigned)rd % ea; |
1432 | rd = (unsigned)rd / ea; | |
0693d363 DE |
1433 | } |
1434 | SET_W_REG (code->dst.reg, (rd & 0xff) | (tmp << 8)); | |
1435 | n = ea & 0x80; | |
1436 | nz = ea & 0xff; | |
ce51bde6 | 1437 | |
0693d363 DE |
1438 | goto next; |
1439 | } | |
1440 | case O (O_DIVU, SW): | |
1441 | { | |
1442 | rd = GET_L_REG (code->dst.reg); | |
1443 | ea = GET_W_REG (code->src.reg); | |
1444 | n = ea & 0x8000; | |
1445 | nz = ea & 0xffff; | |
1446 | if (ea) | |
1447 | { | |
7e1e013f JL |
1448 | tmp = (unsigned)rd % ea; |
1449 | rd = (unsigned)rd / ea; | |
0693d363 DE |
1450 | } |
1451 | SET_L_REG (code->dst.reg, (rd & 0xffff) | (tmp << 16)); | |
1452 | goto next; | |
1453 | } | |
ce51bde6 | 1454 | |
0693d363 DE |
1455 | case O (O_DIVS, SB): |
1456 | { | |
ce51bde6 | 1457 | |
0693d363 DE |
1458 | rd = SEXTSHORT (GET_W_REG (code->dst.reg)); |
1459 | ea = SEXTCHAR (GET_B_REG (code->src.reg)); | |
1460 | if (ea) | |
1461 | { | |
1462 | tmp = (int) rd % (int) ea; | |
1463 | rd = (int) rd / (int) ea; | |
1464 | n = rd & 0x8000; | |
1465 | nz = 1; | |
1466 | } | |
1467 | else | |
1468 | nz = 0; | |
1469 | SET_W_REG (code->dst.reg, (rd & 0xff) | (tmp << 8)); | |
1470 | goto next; | |
1471 | } | |
1472 | case O (O_DIVS, SW): | |
1473 | { | |
1474 | rd = GET_L_REG (code->dst.reg); | |
1475 | ea = SEXTSHORT (GET_W_REG (code->src.reg)); | |
1476 | if (ea) | |
1477 | { | |
1478 | tmp = (int) rd % (int) ea; | |
1479 | rd = (int) rd / (int) ea; | |
1480 | n = rd & 0x80000000; | |
1481 | nz = 1; | |
1482 | } | |
1483 | else | |
1484 | nz = 0; | |
1485 | SET_L_REG (code->dst.reg, (rd & 0xffff) | (tmp << 16)); | |
1486 | goto next; | |
1487 | } | |
1488 | case O (O_EXTS, SW): | |
7478904c | 1489 | rd = GET_B_REG (code->src.reg + 8) & 0xff; /* Yes, src, not dst. */ |
0693d363 DE |
1490 | ea = rd & 0x80 ? -256 : 0; |
1491 | res = rd + ea; | |
1492 | goto log16; | |
1493 | case O (O_EXTS, SL): | |
1494 | rd = GET_W_REG (code->src.reg) & 0xffff; | |
1495 | ea = rd & 0x8000 ? -65536 : 0; | |
1496 | res = rd + ea; | |
1497 | goto log32; | |
1498 | case O (O_EXTU, SW): | |
1499 | rd = GET_B_REG (code->src.reg + 8) & 0xff; | |
1500 | ea = 0; | |
1501 | res = rd + ea; | |
1502 | goto log16; | |
1503 | case O (O_EXTU, SL): | |
1504 | rd = GET_W_REG (code->src.reg) & 0xffff; | |
1505 | ea = 0; | |
1506 | res = rd + ea; | |
1507 | goto log32; | |
ce51bde6 | 1508 | |
46337270 | 1509 | case O (O_NOP, SN): |
0693d363 | 1510 | goto next; |
ce51bde6 | 1511 | |
171f4664 JL |
1512 | case O (O_STM, SL): |
1513 | { | |
1514 | int nregs, firstreg, i; | |
1515 | ||
1516 | nregs = GET_MEMORY_B (pc + 1); | |
1517 | nregs >>= 4; | |
1518 | nregs &= 0xf; | |
1519 | firstreg = GET_MEMORY_B (pc + 3); | |
1520 | firstreg &= 0xf; | |
1521 | for (i = firstreg; i <= firstreg + nregs; i++) | |
1522 | { | |
1523 | cpu.regs[7] -= 4; | |
1524 | SET_MEMORY_L (cpu.regs[7], cpu.regs[i]); | |
1525 | } | |
1526 | } | |
1527 | goto next; | |
1528 | ||
1529 | case O (O_LDM, SL): | |
1530 | { | |
1531 | int nregs, firstreg, i; | |
1532 | ||
1533 | nregs = GET_MEMORY_B (pc + 1); | |
1534 | nregs >>= 4; | |
1535 | nregs &= 0xf; | |
1536 | firstreg = GET_MEMORY_B (pc + 3); | |
1537 | firstreg &= 0xf; | |
1538 | for (i = firstreg; i >= firstreg - nregs; i--) | |
1539 | { | |
1540 | cpu.regs[i] = GET_MEMORY_L (cpu.regs[7]); | |
1541 | cpu.regs[7] += 4; | |
1542 | } | |
1543 | } | |
1544 | goto next; | |
1545 | ||
0693d363 | 1546 | default: |
46337270 | 1547 | cpu.state = SIM_STATE_STOPPED; |
7478904c | 1548 | cpu.exception = SIGILL; |
0693d363 | 1549 | goto end; |
ce51bde6 DE |
1550 | |
1551 | } | |
0693d363 DE |
1552 | abort (); |
1553 | ||
1554 | setc: | |
1555 | cpu.ccr = res; | |
1556 | GETSR (); | |
28655f00 SC |
1557 | goto next; |
1558 | ||
0693d363 DE |
1559 | condtrue: |
1560 | /* When a branch works */ | |
1561 | pc = code->src.literal; | |
ce51bde6 DE |
1562 | goto end; |
1563 | ||
0693d363 DE |
1564 | /* Set the cond codes from res */ |
1565 | bitop: | |
ce51bde6 | 1566 | |
0693d363 DE |
1567 | /* Set the flags after an 8 bit inc/dec operation */ |
1568 | just_flags_inc8: | |
1569 | n = res & 0x80; | |
1570 | nz = res & 0xff; | |
1571 | v = (rd & 0x7f) == 0x7f; | |
1572 | goto next; | |
ce51bde6 | 1573 | |
ce51bde6 | 1574 | |
0693d363 DE |
1575 | /* Set the flags after an 16 bit inc/dec operation */ |
1576 | just_flags_inc16: | |
1577 | n = res & 0x8000; | |
1578 | nz = res & 0xffff; | |
1579 | v = (rd & 0x7fff) == 0x7fff; | |
1580 | goto next; | |
1581 | ||
1582 | ||
1583 | /* Set the flags after an 32 bit inc/dec operation */ | |
1584 | just_flags_inc32: | |
1585 | n = res & 0x80000000; | |
1586 | nz = res & 0xffffffff; | |
1587 | v = (rd & 0x7fffffff) == 0x7fffffff; | |
1588 | goto next; | |
1589 | ||
1590 | ||
1591 | shift8: | |
5d06fa80 | 1592 | /* Set flags after an 8 bit shift op, carry,overflow set in insn */ |
0693d363 | 1593 | n = (rd & 0x80); |
0693d363 DE |
1594 | nz = rd & 0xff; |
1595 | SET_B_REG (code->src.reg, rd); | |
1596 | goto next; | |
1597 | ||
0693d363 | 1598 | shift16: |
5d06fa80 | 1599 | /* Set flags after an 16 bit shift op, carry,overflow set in insn */ |
0693d363 | 1600 | n = (rd & 0x8000); |
0693d363 | 1601 | nz = rd & 0xffff; |
0693d363 DE |
1602 | SET_W_REG (code->src.reg, rd); |
1603 | goto next; | |
1604 | ||
1605 | shift32: | |
5d06fa80 | 1606 | /* Set flags after an 32 bit shift op, carry,overflow set in insn */ |
0693d363 | 1607 | n = (rd & 0x80000000); |
0693d363 DE |
1608 | nz = rd & 0xffffffff; |
1609 | SET_L_REG (code->src.reg, rd); | |
1610 | goto next; | |
1611 | ||
1612 | log32: | |
1613 | store (&code->dst, res); | |
1614 | just_flags_log32: | |
1615 | /* flags after a 32bit logical operation */ | |
1616 | n = res & 0x80000000; | |
1617 | nz = res & 0xffffffff; | |
1618 | v = 0; | |
1619 | goto next; | |
1620 | ||
1621 | log16: | |
1622 | store (&code->dst, res); | |
1623 | just_flags_log16: | |
1624 | /* flags after a 16bit logical operation */ | |
1625 | n = res & 0x8000; | |
1626 | nz = res & 0xffff; | |
1627 | v = 0; | |
1628 | goto next; | |
1629 | ||
1630 | ||
1631 | log8: | |
1632 | store (&code->dst, res); | |
1633 | just_flags_log8: | |
1634 | n = res & 0x80; | |
1635 | nz = res & 0xff; | |
1636 | v = 0; | |
1637 | goto next; | |
1638 | ||
1639 | alu8: | |
1640 | SET_B_REG (code->dst.reg, res); | |
1641 | just_flags_alu8: | |
1642 | n = res & 0x80; | |
1643 | nz = res & 0xff; | |
0693d363 | 1644 | c = (res & 0x100); |
50d45d1b JL |
1645 | switch (code->opcode / 4) |
1646 | { | |
1647 | case O_ADD: | |
1648 | v = ((rd & 0x80) == (ea & 0x80) | |
1649 | && (rd & 0x80) != (res & 0x80)); | |
1650 | break; | |
1651 | case O_SUB: | |
1652 | case O_CMP: | |
1653 | v = ((rd & 0x80) != (-ea & 0x80) | |
1654 | && (rd & 0x80) != (res & 0x80)); | |
1655 | break; | |
1656 | case O_NEG: | |
1657 | v = (rd == 0x80); | |
1658 | break; | |
1659 | } | |
0693d363 DE |
1660 | goto next; |
1661 | ||
1662 | alu16: | |
1663 | SET_W_REG (code->dst.reg, res); | |
1664 | just_flags_alu16: | |
1665 | n = res & 0x8000; | |
1666 | nz = res & 0xffff; | |
0693d363 | 1667 | c = (res & 0x10000); |
50d45d1b JL |
1668 | switch (code->opcode / 4) |
1669 | { | |
1670 | case O_ADD: | |
1671 | v = ((rd & 0x8000) == (ea & 0x8000) | |
1672 | && (rd & 0x8000) != (res & 0x8000)); | |
1673 | break; | |
1674 | case O_SUB: | |
1675 | case O_CMP: | |
1676 | v = ((rd & 0x8000) != (-ea & 0x8000) | |
1677 | && (rd & 0x8000) != (res & 0x8000)); | |
1678 | break; | |
1679 | case O_NEG: | |
1680 | v = (rd == 0x8000); | |
1681 | break; | |
1682 | } | |
0693d363 DE |
1683 | goto next; |
1684 | ||
1685 | alu32: | |
1686 | SET_L_REG (code->dst.reg, res); | |
1687 | just_flags_alu32: | |
1688 | n = res & 0x80000000; | |
1689 | nz = res & 0xffffffff; | |
50d45d1b JL |
1690 | switch (code->opcode / 4) |
1691 | { | |
1692 | case O_ADD: | |
1693 | v = ((rd & 0x80000000) == (ea & 0x80000000) | |
1694 | && (rd & 0x80000000) != (res & 0x80000000)); | |
9b127161 | 1695 | c = ((unsigned) res < (unsigned) rd) || ((unsigned) res < (unsigned) ea); |
50d45d1b JL |
1696 | break; |
1697 | case O_SUB: | |
1698 | case O_CMP: | |
1699 | v = ((rd & 0x80000000) != (-ea & 0x80000000) | |
1700 | && (rd & 0x80000000) != (res & 0x80000000)); | |
0693d363 DE |
1701 | c = (unsigned) rd < (unsigned) -ea; |
1702 | break; | |
1703 | case O_NEG: | |
9b127161 | 1704 | v = (rd == 0x80000000); |
0693d363 DE |
1705 | c = res != 0; |
1706 | break; | |
1707 | } | |
1708 | goto next; | |
1709 | ||
1710 | next:; | |
1711 | pc = code->next_pc; | |
1712 | ||
1713 | end: | |
1714 | ; | |
1715 | /* if (cpu.regs[8] ) abort(); */ | |
1716 | ||
7478904c SC |
1717 | if (poll_count++ > 100) |
1718 | { | |
1719 | poll_count = 0; | |
247fccde AC |
1720 | if ((*sim_callback->poll_quit) != NULL |
1721 | && (*sim_callback->poll_quit) (sim_callback)) | |
1722 | sim_stop (sd); | |
7478904c | 1723 | } |
0693d363 DE |
1724 | |
1725 | } | |
46337270 | 1726 | while (cpu.state == SIM_STATE_RUNNING); |
ce51bde6 DE |
1727 | cpu.ticks += get_now () - tick_start; |
1728 | cpu.cycles += cycles; | |
1729 | cpu.insts += insts; | |
7478904c | 1730 | |
ce51bde6 DE |
1731 | cpu.pc = pc; |
1732 | BUILDSR (); | |
7478904c | 1733 | cpu.mask = oldmask; |
ce51bde6 DE |
1734 | signal (SIGINT, prev); |
1735 | } | |
1736 | ||
46337270 DE |
1737 | int |
1738 | sim_trace (sd) | |
1739 | SIM_DESC sd; | |
1740 | { | |
1741 | /* FIXME: unfinished */ | |
1742 | abort (); | |
1743 | } | |
ce51bde6 | 1744 | |
28655f00 | 1745 | int |
46337270 DE |
1746 | sim_write (sd, addr, buffer, size) |
1747 | SIM_DESC sd; | |
a415cf0a | 1748 | SIM_ADDR addr; |
ce51bde6 DE |
1749 | unsigned char *buffer; |
1750 | int size; | |
1751 | { | |
1752 | int i; | |
1753 | ||
1754 | init_pointers (); | |
7e1e013f | 1755 | if (addr < 0) |
a415cf0a | 1756 | return 0; |
ce51bde6 DE |
1757 | for (i = 0; i < size; i++) |
1758 | { | |
7e1e013f JL |
1759 | if (addr < memory_size) |
1760 | { | |
1761 | cpu.memory[addr + i] = buffer[i]; | |
1762 | cpu.cache_idx[addr + i] = 0; | |
1763 | } | |
1764 | else | |
1765 | cpu.eightbit[(addr + i) & 0xff] = buffer[i]; | |
ce51bde6 | 1766 | } |
a415cf0a | 1767 | return size; |
ce51bde6 DE |
1768 | } |
1769 | ||
28655f00 | 1770 | int |
46337270 DE |
1771 | sim_read (sd, addr, buffer, size) |
1772 | SIM_DESC sd; | |
a415cf0a DE |
1773 | SIM_ADDR addr; |
1774 | unsigned char *buffer; | |
ce51bde6 DE |
1775 | int size; |
1776 | { | |
1777 | init_pointers (); | |
7e1e013f | 1778 | if (addr < 0) |
a415cf0a | 1779 | return 0; |
7e1e013f JL |
1780 | if (addr < memory_size) |
1781 | memcpy (buffer, cpu.memory + addr, size); | |
1782 | else | |
1783 | memcpy (buffer, cpu.eightbit + (addr & 0xff), size); | |
28655f00 | 1784 | return size; |
ce51bde6 DE |
1785 | } |
1786 | ||
1787 | ||
ce51bde6 DE |
1788 | #define R0_REGNUM 0 |
1789 | #define R1_REGNUM 1 | |
1790 | #define R2_REGNUM 2 | |
1791 | #define R3_REGNUM 3 | |
1792 | #define R4_REGNUM 4 | |
1793 | #define R5_REGNUM 5 | |
1794 | #define R6_REGNUM 6 | |
1795 | #define R7_REGNUM 7 | |
1796 | ||
1797 | #define SP_REGNUM R7_REGNUM /* Contains address of top of stack */ | |
1798 | #define FP_REGNUM R6_REGNUM /* Contains address of executing | |
0693d363 | 1799 | * stack frame */ |
ce51bde6 DE |
1800 | |
1801 | #define CCR_REGNUM 8 /* Contains processor status */ | |
1802 | #define PC_REGNUM 9 /* Contains program counter */ | |
1803 | ||
1804 | #define CYCLE_REGNUM 10 | |
1805 | #define INST_REGNUM 11 | |
1806 | #define TICK_REGNUM 12 | |
1807 | ||
1808 | ||
7478904c | 1809 | void |
46337270 DE |
1810 | sim_store_register (sd, rn, value) |
1811 | SIM_DESC sd; | |
ce51bde6 | 1812 | int rn; |
28655f00 | 1813 | unsigned char *value; |
ce51bde6 | 1814 | { |
28655f00 SC |
1815 | int longval; |
1816 | int shortval; | |
1817 | int intval; | |
0693d363 DE |
1818 | longval = (value[0] << 24) | (value[1] << 16) | (value[2] << 8) | value[3]; |
1819 | shortval = (value[0] << 8) | (value[1]); | |
28655f00 | 1820 | intval = h8300hmode ? longval : shortval; |
ce51bde6 DE |
1821 | |
1822 | init_pointers (); | |
1823 | switch (rn) | |
1824 | { | |
1825 | case PC_REGNUM: | |
28655f00 | 1826 | cpu.pc = intval; |
ce51bde6 DE |
1827 | break; |
1828 | default: | |
1829 | abort (); | |
1830 | case R0_REGNUM: | |
1831 | case R1_REGNUM: | |
1832 | case R2_REGNUM: | |
1833 | case R3_REGNUM: | |
1834 | case R4_REGNUM: | |
1835 | case R5_REGNUM: | |
1836 | case R6_REGNUM: | |
1837 | case R7_REGNUM: | |
28655f00 | 1838 | cpu.regs[rn] = intval; |
ce51bde6 DE |
1839 | break; |
1840 | case CCR_REGNUM: | |
28655f00 | 1841 | cpu.ccr = intval; |
ce51bde6 DE |
1842 | break; |
1843 | case CYCLE_REGNUM: | |
28655f00 | 1844 | cpu.cycles = longval; |
ce51bde6 DE |
1845 | break; |
1846 | ||
1847 | case INST_REGNUM: | |
28655f00 | 1848 | cpu.insts = longval; |
ce51bde6 DE |
1849 | break; |
1850 | ||
1851 | case TICK_REGNUM: | |
28655f00 | 1852 | cpu.ticks = longval; |
ce51bde6 DE |
1853 | break; |
1854 | } | |
1855 | } | |
1856 | ||
7478904c | 1857 | void |
46337270 DE |
1858 | sim_fetch_register (sd, rn, buf) |
1859 | SIM_DESC sd; | |
ce51bde6 | 1860 | int rn; |
a415cf0a | 1861 | unsigned char *buf; |
ce51bde6 DE |
1862 | { |
1863 | int v; | |
1864 | int longreg = 0; | |
1865 | ||
1866 | init_pointers (); | |
1867 | ||
1868 | switch (rn) | |
1869 | { | |
1870 | default: | |
1871 | abort (); | |
1872 | case 8: | |
1873 | v = cpu.ccr; | |
1874 | break; | |
1875 | case 9: | |
1876 | v = cpu.pc; | |
1877 | break; | |
1878 | case R0_REGNUM: | |
1879 | case R1_REGNUM: | |
1880 | case R2_REGNUM: | |
1881 | case R3_REGNUM: | |
1882 | case R4_REGNUM: | |
1883 | case R5_REGNUM: | |
1884 | case R6_REGNUM: | |
1885 | case R7_REGNUM: | |
1886 | v = cpu.regs[rn]; | |
1887 | break; | |
1888 | case 10: | |
1889 | v = cpu.cycles; | |
1890 | longreg = 1; | |
ce51bde6 DE |
1891 | break; |
1892 | case 11: | |
1893 | v = cpu.ticks; | |
1894 | longreg = 1; | |
1895 | break; | |
1896 | case 12: | |
1897 | v = cpu.insts; | |
1898 | longreg = 1; | |
1899 | break; | |
ce51bde6 | 1900 | } |
28655f00 | 1901 | if (h8300hmode || longreg) |
ce51bde6 DE |
1902 | { |
1903 | buf[0] = v >> 24; | |
1904 | buf[1] = v >> 16; | |
1905 | buf[2] = v >> 8; | |
1906 | buf[3] = v >> 0; | |
1907 | } | |
1908 | else | |
1909 | { | |
1910 | buf[0] = v >> 8; | |
1911 | buf[1] = v; | |
1912 | } | |
1913 | } | |
1914 | ||
7478904c | 1915 | void |
46337270 DE |
1916 | sim_stop_reason (sd, reason, sigrc) |
1917 | SIM_DESC sd; | |
a415cf0a DE |
1918 | enum sim_stop *reason; |
1919 | int *sigrc; | |
ce51bde6 | 1920 | { |
46337270 DE |
1921 | #if 0 /* FIXME: This should work but we can't use it. |
1922 | grep for SLEEP above. */ | |
1923 | switch (cpu.state) | |
1924 | { | |
1925 | case SIM_STATE_EXITED : *reason = sim_exited; break; | |
1926 | case SIM_STATE_SIGNALLED : *reason = sim_signalled; break; | |
1927 | case SIM_STATE_STOPPED : *reason = sim_stopped; break; | |
1928 | default : abort (); | |
1929 | } | |
1930 | #else | |
a415cf0a | 1931 | *reason = sim_stopped; |
46337270 | 1932 | #endif |
7db9345b | 1933 | *sigrc = cpu.exception; |
ce51bde6 DE |
1934 | } |
1935 | ||
46337270 DE |
1936 | /* FIXME: Rename to sim_set_mem_size. */ |
1937 | ||
1938 | void | |
1939 | sim_size (n) | |
1940 | int n; | |
1941 | { | |
1942 | /* Memory size is fixed. */ | |
1943 | } | |
1944 | ||
1945 | void | |
1946 | sim_set_simcache_size (n) | |
ce51bde6 DE |
1947 | { |
1948 | if (cpu.cache) | |
1949 | free (cpu.cache); | |
1950 | if (n < 2) | |
1951 | n = 2; | |
1952 | cpu.cache = (decoded_inst *) malloc (sizeof (decoded_inst) * n); | |
1953 | memset (cpu.cache, 0, sizeof (decoded_inst) * n); | |
1954 | cpu.csize = n; | |
1955 | } | |
1956 | ||
1957 | ||
7478904c | 1958 | void |
46337270 DE |
1959 | sim_info (sd, verbose) |
1960 | SIM_DESC sd; | |
ce51bde6 | 1961 | int verbose; |
ce51bde6 DE |
1962 | { |
1963 | double timetaken = (double) cpu.ticks / (double) now_persec (); | |
1964 | double virttime = cpu.cycles / 10.0e6; | |
1965 | ||
46337270 DE |
1966 | (*sim_callback->printf_filtered) (sim_callback, |
1967 | "\n\n#instructions executed %10d\n", | |
1968 | cpu.insts); | |
1969 | (*sim_callback->printf_filtered) (sim_callback, | |
1970 | "#cycles (v approximate) %10d\n", | |
1971 | cpu.cycles); | |
1972 | (*sim_callback->printf_filtered) (sim_callback, | |
1973 | "#real time taken %10.4f\n", | |
1974 | timetaken); | |
1975 | (*sim_callback->printf_filtered) (sim_callback, | |
1976 | "#virtual time taked %10.4f\n", | |
1977 | virttime); | |
0693d363 | 1978 | if (timetaken != 0.0) |
46337270 DE |
1979 | (*sim_callback->printf_filtered) (sim_callback, |
1980 | "#simulation ratio %10.4f\n", | |
1981 | virttime / timetaken); | |
1982 | (*sim_callback->printf_filtered) (sim_callback, | |
1983 | "#compiles %10d\n", | |
1984 | cpu.compiles); | |
1985 | (*sim_callback->printf_filtered) (sim_callback, | |
1986 | "#cache size %10d\n", | |
1987 | cpu.csize); | |
ce51bde6 DE |
1988 | |
1989 | #ifdef ADEBUG | |
46337270 DE |
1990 | /* This to be conditional on `what' (aka `verbose'), |
1991 | however it was never passed as non-zero. */ | |
1992 | if (1) | |
ce51bde6 DE |
1993 | { |
1994 | int i; | |
0693d363 | 1995 | for (i = 0; i < O_LAST; i++) |
ce51bde6 DE |
1996 | { |
1997 | if (cpu.stats[i]) | |
46337270 DE |
1998 | (*sim_callback->printf_filtered) (sim_callback, |
1999 | "%d: %d\n", i, cpu.stats[i]); | |
ce51bde6 DE |
2000 | } |
2001 | } | |
2002 | #endif | |
2003 | } | |
2004 | ||
7478904c SC |
2005 | /* Indicate whether the cpu is an h8/300 or h8/300h. |
2006 | FLAG is non-zero for the h8/300h. */ | |
2007 | ||
89a2c4fd | 2008 | void |
7478904c SC |
2009 | set_h8300h (flag) |
2010 | int flag; | |
89a2c4fd | 2011 | { |
fafce69a AC |
2012 | /* FIXME: Much of the code in sim_load can be moved to sim_open. |
2013 | This function being replaced by a sim_open:ARGV configuration | |
2014 | option */ | |
7478904c | 2015 | h8300hmode = flag; |
89a2c4fd | 2016 | } |
28655f00 | 2017 | |
46337270 | 2018 | SIM_DESC |
247fccde | 2019 | sim_open (kind, ptr, abfd, argv) |
46337270 | 2020 | SIM_OPEN_KIND kind; |
247fccde AC |
2021 | struct host_callback_struct *ptr; |
2022 | struct _bfd *abfd; | |
46337270 | 2023 | char **argv; |
7db9345b | 2024 | { |
fafce69a AC |
2025 | /* FIXME: Much of the code in sim_load can be moved here */ |
2026 | ||
46337270 DE |
2027 | sim_kind = kind; |
2028 | myname = argv[0]; | |
247fccde | 2029 | sim_callback = ptr; |
46337270 DE |
2030 | /* fudge our descriptor */ |
2031 | return (SIM_DESC) 1; | |
7db9345b DE |
2032 | } |
2033 | ||
7478904c | 2034 | void |
46337270 DE |
2035 | sim_close (sd, quitting) |
2036 | SIM_DESC sd; | |
7478904c SC |
2037 | int quitting; |
2038 | { | |
2039 | /* nothing to do */ | |
2040 | } | |
2041 | ||
2042 | /* Called by gdb to load a program into memory. */ | |
2043 | ||
46337270 DE |
2044 | SIM_RC |
2045 | sim_load (sd, prog, abfd, from_tty) | |
2046 | SIM_DESC sd; | |
7478904c | 2047 | char *prog; |
46337270 | 2048 | bfd *abfd; |
7478904c SC |
2049 | int from_tty; |
2050 | { | |
46337270 | 2051 | bfd *prog_bfd; |
7478904c | 2052 | |
fafce69a AC |
2053 | /* FIXME: The code below that sets a specific variant of the h8/300 |
2054 | being simulated should be moved to sim_open(). */ | |
2055 | ||
7478904c SC |
2056 | /* See if the file is for the h8/300 or h8/300h. */ |
2057 | /* ??? This may not be the most efficient way. The z8k simulator | |
2058 | does this via a different mechanism (INIT_EXTRA_SYMTAB_INFO). */ | |
46337270 DE |
2059 | if (abfd != NULL) |
2060 | prog_bfd = abfd; | |
2061 | else | |
2062 | prog_bfd = bfd_openr (prog, "coff-h8300"); | |
2063 | if (prog_bfd != NULL) | |
7478904c | 2064 | { |
247fccde AC |
2065 | /* Set the cpu type. We ignore failure from bfd_check_format |
2066 | and bfd_openr as sim_load_file checks too. */ | |
46337270 | 2067 | if (bfd_check_format (prog_bfd, bfd_object)) |
171f4664 | 2068 | { |
247fccde AC |
2069 | unsigned long mach = bfd_get_mach (prog_bfd); |
2070 | set_h8300h (mach == bfd_mach_h8300h | |
2071 | || mach == bfd_mach_h8300s); | |
171f4664 | 2072 | } |
7478904c SC |
2073 | } |
2074 | ||
132fdcb9 JL |
2075 | /* If we're using gdb attached to the simulator, then we have to |
2076 | reallocate memory for the simulator. | |
2077 | ||
2078 | When gdb first starts, it calls fetch_registers (among other | |
2079 | functions), which in turn calls init_pointers, which allocates | |
2080 | simulator memory. | |
2081 | ||
2082 | The problem is when we do that, we don't know whether we're | |
2083 | debugging an h8/300 or h8/300h program. | |
2084 | ||
2085 | This is the first point at which we can make that determination, | |
2086 | so we just reallocate memory now; this will also allow us to handle | |
2087 | switching between h8/300 and h8/300h programs without exiting | |
2088 | gdb. */ | |
2089 | if (h8300hmode) | |
2090 | memory_size = H8300H_MSIZE; | |
2091 | else | |
2092 | memory_size = H8300_MSIZE; | |
2093 | ||
2094 | if (cpu.memory) | |
2095 | free (cpu.memory); | |
2096 | if (cpu.cache_idx) | |
2097 | free (cpu.cache_idx); | |
7e1e013f JL |
2098 | if (cpu.eightbit) |
2099 | free (cpu.eightbit); | |
132fdcb9 JL |
2100 | |
2101 | cpu.memory = (unsigned char *) calloc (sizeof (char), memory_size); | |
2102 | cpu.cache_idx = (unsigned short *) calloc (sizeof (short), memory_size); | |
2103 | cpu.eightbit = (unsigned char *) calloc (sizeof (char), 256); | |
2104 | ||
2105 | /* `msize' must be a power of two */ | |
2106 | if ((memory_size & (memory_size - 1)) != 0) | |
2107 | abort (); | |
2108 | cpu.mask = memory_size - 1; | |
2109 | ||
46337270 DE |
2110 | if (sim_load_file (sd, myname, sim_callback, prog, prog_bfd, |
2111 | sim_kind == SIM_OPEN_DEBUG) | |
2112 | == NULL) | |
2113 | { | |
2114 | /* Close the bfd if we opened it. */ | |
2115 | if (abfd == NULL && prog_bfd != NULL) | |
2116 | bfd_close (prog_bfd); | |
2117 | return SIM_RC_FAIL; | |
2118 | } | |
2119 | ||
46337270 DE |
2120 | /* Close the bfd if we opened it. */ |
2121 | if (abfd == NULL && prog_bfd != NULL) | |
2122 | bfd_close (prog_bfd); | |
2123 | return SIM_RC_OK; | |
7478904c SC |
2124 | } |
2125 | ||
46337270 | 2126 | SIM_RC |
fafce69a | 2127 | sim_create_inferior (sd, abfd, argv, env) |
46337270 | 2128 | SIM_DESC sd; |
fafce69a | 2129 | struct _bfd *abfd; |
a415cf0a DE |
2130 | char **argv; |
2131 | char **env; | |
7db9345b | 2132 | { |
fafce69a AC |
2133 | if (abfd != NULL) |
2134 | cpu.pc = bfd_get_start_address (abfd); | |
2135 | else | |
2136 | cpu.pc = 0; | |
46337270 | 2137 | return SIM_RC_OK; |
7db9345b | 2138 | } |
e656ecf9 DE |
2139 | |
2140 | void | |
46337270 DE |
2141 | sim_do_command (sd, cmd) |
2142 | SIM_DESC sd; | |
e656ecf9 DE |
2143 | char *cmd; |
2144 | { | |
46337270 DE |
2145 | (*sim_callback->printf_filtered) (sim_callback, |
2146 | "This simulator does not accept any commands.\n"); | |
e656ecf9 DE |
2147 | } |
2148 | ||
e656ecf9 | 2149 | void |
247fccde | 2150 | sim_set_callbacks (ptr) |
46337270 | 2151 | struct host_callback_struct *ptr; |
e656ecf9 | 2152 | { |
46337270 | 2153 | sim_callback = ptr; |
e656ecf9 | 2154 | } |