Commit | Line | Data |
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ea6bbfba | 1 | /* Interpreter fragment for the Hitachi H8/300 architecture simulator. |
19139515 | 2 | |
ea6bbfba SC |
3 | Written by Steve Chamberlain of Cygnus Support. |
4 | sac@cygnus.com | |
19139515 | 5 | |
ea6bbfba | 6 | This file is part of H8/300 sim |
19139515 | 7 | |
19139515 | 8 | |
ea6bbfba | 9 | THIS SOFTWARE IS NOT COPYRIGHTED |
19139515 | 10 | |
ea6bbfba SC |
11 | Cygnus offers the following for use in the public domain. Cygnus |
12 | makes no warranty with regard to the software or it's performance | |
13 | and the user accepts the software "AS IS" with all faults. | |
14 | ||
15 | CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO | |
16 | THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
17 | MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. | |
18 | ||
19 | */ | |
19139515 SC |
20 | |
21 | #include <stdio.h> | |
22 | #include <stdlib.h> | |
23 | #include <signal.h> | |
62b66d6d | 24 | #include "state.h" |
19139515 SC |
25 | |
26 | #define V (v!=0) | |
27 | #define C (c!=0) | |
28 | #define N (n!=0) | |
29 | #define Z (z!=0) | |
30 | ||
62b66d6d SC |
31 | #define SET_CCR(x) n = x & 0x8; v = x & 0x2; z = x & 0x4; c = x & 0x1;saved_state.ienable=x&0x80; |
32 | #define GET_CCR() ((N << 3) | (Z<<2) | (V<<1) | C) | ((!saved_state.ienable)<<7) | |
19139515 | 33 | |
19139515 | 34 | |
19139515 SC |
35 | |
36 | static union | |
37 | { | |
38 | short int i; | |
39 | struct | |
40 | { | |
41 | char low; | |
42 | char high; | |
43 | } | |
44 | ||
45 | u; | |
46 | } | |
47 | ||
48 | littleendian; | |
49 | ||
50 | static void | |
51 | meminit () | |
52 | { | |
a082325b | 53 | if (saved_state.mem == 0) |
19139515 SC |
54 | { |
55 | int tmp; | |
56 | ||
a082325b | 57 | saved_state.mem = (unsigned short *)calloc (1024, 64); |
19139515 | 58 | littleendian.i = 1; |
19139515 SC |
59 | /* initialze the array of pointers to byte registers */ |
60 | for (tmp = 0; tmp < 8; tmp++) | |
61 | { | |
62 | if (littleendian.u.high) | |
63 | { | |
64 | saved_state.bregp[tmp] = (unsigned char *) (saved_state.reg + tmp); | |
65 | saved_state.bregp[tmp + 8] = saved_state.bregp[tmp] + 1; | |
66 | } | |
67 | else | |
68 | { | |
69 | saved_state.bregp[tmp + 8] = (unsigned char *) (saved_state.reg + tmp); | |
70 | saved_state.bregp[tmp] = saved_state.bregp[tmp + 8] + 1; | |
71 | } | |
72 | } | |
73 | ||
74 | /* we keep two 256 sized pointers to byte regs, one for when we | |
75 | want to look at the reg descibed by bits NNNNxxxx and one for | |
76 | when we want to look at xxxxNNNN */ | |
77 | for (tmp = 0; tmp < 256; tmp++) | |
78 | { | |
79 | saved_state.bregp_NNNNxxxx[tmp] = saved_state.bregp[(tmp >> 4) & 0xf]; | |
80 | saved_state.bregp_xxxxNNNN[tmp] = saved_state.bregp[tmp & 0xf]; | |
81 | } | |
82 | /* We keep two 256 sized pointers to word regs, one for regs in | |
83 | xNNNxxxx and one for regs in xxxxxNNNN */ | |
84 | for (tmp = 0; tmp < 256; tmp++) | |
85 | { | |
86 | saved_state.wregp_xNNNxxxx[tmp] = &saved_state.reg[(tmp >> 4) & 0x7]; | |
87 | saved_state.wregp_xxxxxNNN[tmp] = &saved_state.reg[tmp & 0x7]; | |
88 | } | |
89 | ||
62b66d6d SC |
90 | saved_state.reg[HCHECK] = 10000000; /* don't check the hardware |
91 | often */ | |
19139515 | 92 | } |
62b66d6d | 93 | |
19139515 SC |
94 | } |
95 | ||
06137fcb SC |
96 | |
97 | void | |
98 | control_c (sig, code, scp, addr) | |
99 | int sig; | |
100 | int code; | |
101 | char *scp; | |
102 | char *addr; | |
103 | { | |
62b66d6d | 104 | saved_state.exception = SIGINT; |
06137fcb SC |
105 | } |
106 | ||
107 | void | |
108 | sim_store_register (reg, val) | |
109 | int reg; | |
110 | int val; | |
111 | { | |
112 | saved_state.reg[reg] = val; | |
113 | } | |
114 | ||
115 | void | |
116 | sim_fetch_register (reg, buf) | |
117 | int reg; | |
118 | char *buf; | |
119 | { | |
120 | meminit(); | |
121 | buf[0] = saved_state.reg[reg] >> 8; | |
122 | buf[1] = saved_state.reg[reg]; | |
123 | } | |
124 | ||
19139515 SC |
125 | void |
126 | sim_write (to, from, len) | |
127 | int to; | |
128 | char *from; | |
129 | int len; | |
130 | { | |
62b66d6d | 131 | int i; |
19139515 | 132 | meminit (); |
62b66d6d SC |
133 | |
134 | for ( i = 0; i < len; i++) | |
135 | SET_BYTE_MEM(to + i, from[i]); | |
19139515 SC |
136 | } |
137 | ||
138 | void | |
139 | sim_read (from, to, len) | |
140 | int from; | |
141 | char *to; | |
142 | ||
143 | int len; | |
144 | { | |
62b66d6d | 145 | int i; |
19139515 | 146 | meminit (); |
62b66d6d SC |
147 | for (i = 0; i < len; i++) { |
148 | to[i] = BYTE_MEM(from + i); | |
149 | } | |
19139515 SC |
150 | } |
151 | ||
152 | int | |
153 | sim_stop_signal () | |
154 | { | |
62b66d6d SC |
155 | return saved_state.exception; |
156 | } | |
157 | ||
158 | void | |
159 | load_timer_state_from_mem() | |
160 | { | |
161 | ||
162 | saved_state.reg[TIER] = BYTE_MEM(0xff90); | |
163 | saved_state.reg[TCSR] = BYTE_MEM(0xff91); | |
164 | saved_state.reg[FRC] = WORD_MEM(0xff92); | |
165 | saved_state.reg[TCR] = BYTE_MEM(0xff96); | |
166 | saved_state.reg[TOCR] = BYTE_MEM(0xff97); | |
167 | ||
168 | ||
169 | if ((saved_state.reg[TOCR] & OCRS) == 0) | |
170 | { | |
171 | saved_state.reg[OCRA] = WORD_MEM(0xff94); | |
172 | } | |
173 | else | |
174 | { | |
175 | saved_state.reg[OCRB] = WORD_MEM(0xff94); | |
176 | } | |
177 | } | |
178 | ||
179 | void | |
180 | store_timer_state_to_mem() | |
181 | { | |
182 | ||
183 | BYTE_MEM(0xff91) = saved_state.reg[TCSR]; | |
184 | SET_WORD_MEM(0xff92, saved_state.reg[FRC]); | |
19139515 SC |
185 | } |
186 | ||
187 | void | |
188 | sim_resume (step, sig) | |
189 | int step; | |
190 | int sig; | |
191 | { | |
192 | int lval; | |
193 | int tmp; | |
194 | int b0; | |
195 | int b1; | |
62b66d6d SC |
196 | int checkfreq; |
197 | int ni; /* Number of insts to execute before checking hw state */ | |
19139515 SC |
198 | unsigned char **blow; |
199 | unsigned char **bhigh; | |
200 | unsigned short **wlow; | |
201 | unsigned short **whigh; | |
62b66d6d | 202 | unsigned short *npc; |
19139515 SC |
203 | int rn; |
204 | unsigned short int *reg; | |
205 | unsigned char **bregp; | |
206 | void (*prev) (); | |
62b66d6d | 207 | unsigned short *pc; |
19139515 SC |
208 | |
209 | int srca; | |
210 | int srcb; | |
211 | int dst; | |
62b66d6d | 212 | int cycles ; |
19139515 SC |
213 | |
214 | int n; | |
215 | int v; | |
216 | int z; | |
217 | int c; | |
218 | ||
19139515 | 219 | |
62b66d6d | 220 | /* Set up pointers to areas */ |
19139515 SC |
221 | reg = saved_state.reg; |
222 | bregp = saved_state.bregp; | |
223 | blow = saved_state.bregp_xxxxNNNN; | |
224 | bhigh = saved_state.bregp_NNNNxxxx; | |
225 | ||
226 | wlow = saved_state.wregp_xxxxxNNN; | |
227 | whigh = saved_state.wregp_xNNNxxxx; | |
228 | ||
62b66d6d | 229 | |
19139515 SC |
230 | prev = signal (SIGINT, control_c); |
231 | meminit(); | |
62b66d6d | 232 | LOAD_INTERPRETER_STATE(); |
19139515 | 233 | if (step) |
62b66d6d | 234 | saved_state.exception = SIGTRAP; |
19139515 SC |
235 | else |
236 | { | |
62b66d6d | 237 | saved_state.exception = sig; |
19139515 SC |
238 | } |
239 | do | |
240 | { | |
62b66d6d SC |
241 | b1 = pc[0]; |
242 | b0 = b1>> 8; | |
243 | b1 &= 0xff; | |
244 | ||
19139515 SC |
245 | |
246 |