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b0c9f026 SC |
1 | /* H8/300 simulator |
2 | Copyright 1993 Free Software Foundation, Inc. | |
3 | ||
4 | Contributed by Cygnus Support. | |
5 | Written by Steve Chamberlain (sac@cygnus.com). | |
6 | ||
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2 of the License, or | |
11 | (at your option) any later version. | |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program; if not, write to the Free Software | |
20 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ | |
62b66d6d SC |
21 | |
22 | /* Fake peripherals for the H8/330 */ | |
23 | #include "state.h" | |
24 | perifs( ) | |
25 | /* This routine is called every few instructions to see if some sort | |
26 | of hardware event is needed */ | |
27 | { | |
28 | int interrupt = 0; | |
29 | int lval; | |
30 | int tmp; | |
31 | /* What to do about the 16 bit timer */ | |
32 | ||
33 | ||
34 | /* Free running counter same as reg a */ | |
35 | if (saved_state.reg[OCRA] == saved_state.reg[FRC]) | |
36 | { | |
37 | /* Set the counter A overflow bit */ | |
38 | saved_state.reg[TCSR] |= OCFA; | |
39 | ||
40 | if (saved_state.reg[TCSR] & CCLRA) | |
41 | { | |
42 | saved_state.reg[FRC] = 0; | |
43 | } | |
44 | ||
45 | if (saved_state.reg[TIER] & OCIEA) | |
46 | { | |
47 | interrupt = 16; | |
48 | } | |
49 | } | |
50 | ||
51 | /* Free running counter same as reg b */ | |
52 | if (saved_state.reg[OCRB] == saved_state.reg[FRC]) | |
53 | { | |
54 | saved_state.reg[TCSR] |= OCFB; | |
55 | if (saved_state.reg[TIER] & OCIEB) | |
56 | { | |
57 | interrupt = 17; | |
58 | } | |
59 | } | |
60 | ||
61 | /* inc free runnning counter */ | |
62 | saved_state.reg[FRC]++; | |
63 | ||
64 | if (saved_state.reg[FRC] == 0) | |
65 | { | |
66 | /* Must have overflowed */ | |
67 | saved_state.reg[TCSR] |= OVF; | |
68 | if (BYTE_MEM(TIER) & OVIE) | |
69 | interrupt = 18; | |
70 | } | |
71 | ||
72 | /* If we've had an interrupt and the bit is on */ | |
73 | if (interrupt && saved_state.ienable) | |
74 | { | |
75 | ||
76 | int ccr; | |
77 | ||
78 | saved_state.ienable = 0; | |
79 | ccr = saved_state.reg[CCR]; | |
80 | lval = WORD_MEM((interrupt)<<1); | |
81 | lval = WORD_MEM(lval); | |
82 | { | |
83 | /* Push PC */ | |
84 | saved_state.reg[7] -= 2; | |
85 | tmp = saved_state.reg[7]; | |
86 | SET_WORD_MEM (tmp, saved_state.reg[PC]); | |
87 | /* Push CCR twice */ | |
88 | saved_state.reg[7] -=2 ; | |
89 | tmp = saved_state.reg[7]; | |
90 | SET_BYTE_MEM(tmp,ccr); | |
91 | SET_BYTE_MEM(tmp+1,ccr); | |
92 | ||
93 | /* Set pc to point to first instruction of i vector */ | |
94 | saved_state.reg[PC] = lval; | |
95 | } | |
96 | } | |
97 | ||
98 | } |