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c28c63d8 JB |
1 | /* CPU family header for lm32bf. |
2 | ||
3 | THIS FILE IS MACHINE GENERATED WITH CGEN. | |
4 | ||
fb067cad | 5 | Copyright 1996-2009 Free Software Foundation, Inc. |
c28c63d8 JB |
6 | |
7 | This file is part of the GNU simulators. | |
8 | ||
fb067cad DE |
9 | This file is free software; you can redistribute it and/or modify |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 3, or (at your option) | |
12 | any later version. | |
c28c63d8 | 13 | |
fb067cad DE |
14 | It is distributed in the hope that it will be useful, but WITHOUT |
15 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
16 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
17 | License for more details. | |
c28c63d8 | 18 | |
fb067cad DE |
19 | You should have received a copy of the GNU General Public License along |
20 | with this program; if not, write to the Free Software Foundation, Inc., | |
21 | 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. | |
c28c63d8 JB |
22 | |
23 | */ | |
24 | ||
25 | #ifndef CPU_LM32BF_H | |
26 | #define CPU_LM32BF_H | |
27 | ||
28 | /* Maximum number of instructions that are fetched at a time. | |
29 | This is for LIW type instructions sets (e.g. m32r). */ | |
30 | #define MAX_LIW_INSNS 1 | |
31 | ||
32 | /* Maximum number of instructions that can be executed in parallel. */ | |
33 | #define MAX_PARALLEL_INSNS 1 | |
34 | ||
35 | /* CPU state information. */ | |
36 | typedef struct { | |
37 | /* Hardware elements. */ | |
38 | struct { | |
39 | /* Program counter */ | |
40 | USI h_pc; | |
41 | #define GET_H_PC() CPU (h_pc) | |
42 | #define SET_H_PC(x) (CPU (h_pc) = (x)) | |
43 | /* General purpose registers */ | |
44 | SI h_gr[32]; | |
45 | #define GET_H_GR(a1) CPU (h_gr)[a1] | |
46 | #define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x)) | |
47 | /* Control and status registers */ | |
48 | SI h_csr[32]; | |
49 | #define GET_H_CSR(a1) CPU (h_csr)[a1] | |
50 | #define SET_H_CSR(a1, x) (CPU (h_csr)[a1] = (x)) | |
51 | } hardware; | |
52 | #define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware) | |
53 | } LM32BF_CPU_DATA; | |
54 | ||
55 | /* Cover fns for register access. */ | |
56 | USI lm32bf_h_pc_get (SIM_CPU *); | |
57 | void lm32bf_h_pc_set (SIM_CPU *, USI); | |
58 | SI lm32bf_h_gr_get (SIM_CPU *, UINT); | |
59 | void lm32bf_h_gr_set (SIM_CPU *, UINT, SI); | |
60 | SI lm32bf_h_csr_get (SIM_CPU *, UINT); | |
61 | void lm32bf_h_csr_set (SIM_CPU *, UINT, SI); | |
62 | ||
63 | /* These must be hand-written. */ | |
64 | extern CPUREG_FETCH_FN lm32bf_fetch_register; | |
65 | extern CPUREG_STORE_FN lm32bf_store_register; | |
66 | ||
67 | typedef struct { | |
68 | int empty; | |
69 | } MODEL_LM32_DATA; | |
70 | ||
71 | /* Instruction argument buffer. */ | |
72 | ||
73 | union sem_fields { | |
74 | struct { /* no operands */ | |
75 | int empty; | |
76 | } fmt_empty; | |
77 | struct { /* */ | |
78 | IADDR i_call; | |
79 | } sfmt_bi; | |
80 | struct { /* */ | |
81 | UINT f_csr; | |
82 | UINT f_r1; | |
83 | } sfmt_wcsr; | |
84 | struct { /* */ | |
85 | UINT f_csr; | |
86 | UINT f_r2; | |
87 | } sfmt_rcsr; | |
88 | struct { /* */ | |
89 | IADDR i_branch; | |
90 | UINT f_r0; | |
91 | UINT f_r1; | |
92 | } sfmt_be; | |
93 | struct { /* */ | |
94 | UINT f_r0; | |
95 | UINT f_r1; | |
96 | UINT f_uimm; | |
97 | } sfmt_andi; | |
98 | struct { /* */ | |
99 | INT f_imm; | |
100 | UINT f_r0; | |
101 | UINT f_r1; | |
102 | } sfmt_addi; | |
103 | struct { /* */ | |
104 | UINT f_r0; | |
105 | UINT f_r1; | |
106 | UINT f_r2; | |
107 | UINT f_user; | |
108 | } sfmt_user; | |
109 | #if WITH_SCACHE_PBB | |
110 | /* Writeback handler. */ | |
111 | struct { | |
112 | /* Pointer to argbuf entry for insn whose results need writing back. */ | |
113 | const struct argbuf *abuf; | |
114 | } write; | |
115 | /* x-before handler */ | |
116 | struct { | |
117 | /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/ | |
118 | int first_p; | |
119 | } before; | |
120 | /* x-after handler */ | |
121 | struct { | |
122 | int empty; | |
123 | } after; | |
124 | /* This entry is used to terminate each pbb. */ | |
125 | struct { | |
126 | /* Number of insns in pbb. */ | |
127 | int insn_count; | |
128 | /* Next pbb to execute. */ | |
129 | SCACHE *next; | |
130 | SCACHE *branch_target; | |
131 | } chain; | |
132 | #endif | |
133 | }; | |
134 | ||
135 | /* The ARGBUF struct. */ | |
136 | struct argbuf { | |
137 | /* These are the baseclass definitions. */ | |
138 | IADDR addr; | |
139 | const IDESC *idesc; | |
140 | char trace_p; | |
141 | char profile_p; | |
142 | /* ??? Temporary hack for skip insns. */ | |
143 | char skip_count; | |
144 | char unused; | |
145 | /* cpu specific data follows */ | |
146 | union sem semantic; | |
147 | int written; | |
148 | union sem_fields fields; | |
149 | }; | |
150 | ||
151 | /* A cached insn. | |
152 | ||
153 | ??? SCACHE used to contain more than just argbuf. We could delete the | |
154 | type entirely and always just use ARGBUF, but for future concerns and as | |
155 | a level of abstraction it is left in. */ | |
156 | ||
157 | struct scache { | |
158 | struct argbuf argbuf; | |
159 | }; | |
160 | ||
161 | /* Macros to simplify extraction, reading and semantic code. | |
162 | These define and assign the local vars that contain the insn's fields. */ | |
163 | ||
164 | #define EXTRACT_IFMT_EMPTY_VARS \ | |
165 | unsigned int length; | |
166 | #define EXTRACT_IFMT_EMPTY_CODE \ | |
167 | length = 0; \ | |
168 | ||
169 | #define EXTRACT_IFMT_ADD_VARS \ | |
170 | UINT f_opcode; \ | |
171 | UINT f_r0; \ | |
172 | UINT f_r1; \ | |
173 | UINT f_r2; \ | |
174 | UINT f_resv0; \ | |
175 | unsigned int length; | |
176 | #define EXTRACT_IFMT_ADD_CODE \ | |
177 | length = 4; \ | |
178 | f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ | |
179 | f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \ | |
180 | f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \ | |
181 | f_r2 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \ | |
182 | f_resv0 = EXTRACT_LSB0_UINT (insn, 32, 10, 11); \ | |
183 | ||
184 | #define EXTRACT_IFMT_ADDI_VARS \ | |
185 | UINT f_opcode; \ | |
186 | UINT f_r0; \ | |
187 | UINT f_r1; \ | |
188 | INT f_imm; \ | |
189 | unsigned int length; | |
190 | #define EXTRACT_IFMT_ADDI_CODE \ | |
191 | length = 4; \ | |
192 | f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ | |
193 | f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \ | |
194 | f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \ | |
195 | f_imm = EXTRACT_LSB0_INT (insn, 32, 15, 16); \ | |
196 | ||
197 | #define EXTRACT_IFMT_ANDI_VARS \ | |
198 | UINT f_opcode; \ | |
199 | UINT f_r0; \ | |
200 | UINT f_r1; \ | |
201 | UINT f_uimm; \ | |
202 | unsigned int length; | |
203 | #define EXTRACT_IFMT_ANDI_CODE \ | |
204 | length = 4; \ | |
205 | f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ | |
206 | f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \ | |
207 | f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \ | |
208 | f_uimm = EXTRACT_LSB0_UINT (insn, 32, 15, 16); \ | |
209 | ||
210 | #define EXTRACT_IFMT_ANDHII_VARS \ | |
211 | UINT f_opcode; \ | |
212 | UINT f_r0; \ | |
213 | UINT f_r1; \ | |
214 | UINT f_uimm; \ | |
215 | unsigned int length; | |
216 | #define EXTRACT_IFMT_ANDHII_CODE \ | |
217 | length = 4; \ | |
218 | f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ | |
219 | f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \ | |
220 | f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \ | |
221 | f_uimm = EXTRACT_LSB0_UINT (insn, 32, 15, 16); \ | |
222 | ||
223 | #define EXTRACT_IFMT_B_VARS \ | |
224 | UINT f_opcode; \ | |
225 | UINT f_r0; \ | |
226 | UINT f_r1; \ | |
227 | UINT f_r2; \ | |
228 | UINT f_resv0; \ | |
229 | unsigned int length; | |
230 | #define EXTRACT_IFMT_B_CODE \ | |
231 | length = 4; \ | |
232 | f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ | |
233 | f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \ | |
234 | f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \ | |
235 | f_r2 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \ | |
236 | f_resv0 = EXTRACT_LSB0_UINT (insn, 32, 10, 11); \ | |
237 | ||
238 | #define EXTRACT_IFMT_BI_VARS \ | |
239 | UINT f_opcode; \ | |
240 | SI f_call; \ | |
241 | unsigned int length; | |
242 | #define EXTRACT_IFMT_BI_CODE \ | |
243 | length = 4; \ | |
244 | f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ | |
245 | f_call = ((pc) + (((int) (((EXTRACT_LSB0_INT (insn, 32, 25, 26)) << (6))) >> (4)))); \ | |
246 | ||
247 | #define EXTRACT_IFMT_BE_VARS \ | |
248 | UINT f_opcode; \ | |
249 | UINT f_r0; \ | |
250 | UINT f_r1; \ | |
251 | SI f_branch; \ | |
252 | unsigned int length; | |
253 | #define EXTRACT_IFMT_BE_CODE \ | |
254 | length = 4; \ | |
255 | f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ | |
256 | f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \ | |
257 | f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \ | |
258 | f_branch = ((pc) + (((int) (((EXTRACT_LSB0_INT (insn, 32, 15, 16)) << (16))) >> (14)))); \ | |
259 | ||
260 | #define EXTRACT_IFMT_ORI_VARS \ | |
261 | UINT f_opcode; \ | |
262 | UINT f_r0; \ | |
263 | UINT f_r1; \ | |
264 | UINT f_uimm; \ | |
265 | unsigned int length; | |
266 | #define EXTRACT_IFMT_ORI_CODE \ | |
267 | length = 4; \ | |
268 | f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ | |
269 | f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \ | |
270 | f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \ | |
271 | f_uimm = EXTRACT_LSB0_UINT (insn, 32, 15, 16); \ | |
272 | ||
273 | #define EXTRACT_IFMT_RCSR_VARS \ | |
274 | UINT f_opcode; \ | |
275 | UINT f_csr; \ | |
276 | UINT f_r1; \ | |
277 | UINT f_r2; \ | |
278 | UINT f_resv0; \ | |
279 | unsigned int length; | |
280 | #define EXTRACT_IFMT_RCSR_CODE \ | |
281 | length = 4; \ | |
282 | f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ | |
283 | f_csr = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \ | |
284 | f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \ | |
285 | f_r2 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \ | |
286 | f_resv0 = EXTRACT_LSB0_UINT (insn, 32, 10, 11); \ | |
287 | ||
288 | #define EXTRACT_IFMT_SEXTB_VARS \ | |
289 | UINT f_opcode; \ | |
290 | UINT f_r0; \ | |
291 | UINT f_r1; \ | |
292 | UINT f_r2; \ | |
293 | UINT f_resv0; \ | |
294 | unsigned int length; | |
295 | #define EXTRACT_IFMT_SEXTB_CODE \ | |
296 | length = 4; \ | |
297 | f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ | |
298 | f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \ | |
299 | f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \ | |
300 | f_r2 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \ | |
301 | f_resv0 = EXTRACT_LSB0_UINT (insn, 32, 10, 11); \ | |
302 | ||
303 | #define EXTRACT_IFMT_USER_VARS \ | |
304 | UINT f_opcode; \ | |
305 | UINT f_r0; \ | |
306 | UINT f_r1; \ | |
307 | UINT f_r2; \ | |
308 | UINT f_user; \ | |
309 | unsigned int length; | |
310 | #define EXTRACT_IFMT_USER_CODE \ | |
311 | length = 4; \ | |
312 | f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ | |
313 | f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \ | |
314 | f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \ | |
315 | f_r2 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \ | |
316 | f_user = EXTRACT_LSB0_UINT (insn, 32, 10, 11); \ | |
317 | ||
318 | #define EXTRACT_IFMT_WCSR_VARS \ | |
319 | UINT f_opcode; \ | |
320 | UINT f_csr; \ | |
321 | UINT f_r1; \ | |
322 | UINT f_r2; \ | |
323 | UINT f_resv0; \ | |
324 | unsigned int length; | |
325 | #define EXTRACT_IFMT_WCSR_CODE \ | |
326 | length = 4; \ | |
327 | f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ | |
328 | f_csr = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \ | |
329 | f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \ | |
330 | f_r2 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \ | |
331 | f_resv0 = EXTRACT_LSB0_UINT (insn, 32, 10, 11); \ | |
332 | ||
333 | #define EXTRACT_IFMT_BREAK_VARS \ | |
334 | UINT f_opcode; \ | |
335 | UINT f_exception; \ | |
336 | unsigned int length; | |
337 | #define EXTRACT_IFMT_BREAK_CODE \ | |
338 | length = 4; \ | |
339 | f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ | |
340 | f_exception = EXTRACT_LSB0_UINT (insn, 32, 25, 26); \ | |
341 | ||
342 | /* Collection of various things for the trace handler to use. */ | |
343 | ||
344 | typedef struct trace_record { | |
345 | IADDR pc; | |
346 | /* FIXME:wip */ | |
347 | } TRACE_RECORD; | |
348 | ||
349 | #endif /* CPU_LM32BF_H */ |