Commit | Line | Data |
---|---|---|
c28c63d8 JB |
1 | /* Simulator instruction decoder for lm32bf. |
2 | ||
3 | THIS FILE IS MACHINE GENERATED WITH CGEN. | |
4 | ||
ecd75fc8 | 5 | Copyright 1996-2014 Free Software Foundation, Inc. |
c28c63d8 JB |
6 | |
7 | This file is part of the GNU simulators. | |
8 | ||
fb067cad DE |
9 | This file is free software; you can redistribute it and/or modify |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 3, or (at your option) | |
12 | any later version. | |
c28c63d8 | 13 | |
fb067cad DE |
14 | It is distributed in the hope that it will be useful, but WITHOUT |
15 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
16 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
17 | License for more details. | |
c28c63d8 | 18 | |
fb067cad | 19 | You should have received a copy of the GNU General Public License along |
51b318de | 20 | with this program; if not, see <http://www.gnu.org/licenses/>. |
c28c63d8 JB |
21 | |
22 | */ | |
23 | ||
24 | #define WANT_CPU lm32bf | |
25 | #define WANT_CPU_LM32BF | |
26 | ||
27 | #include "sim-main.h" | |
28 | #include "sim-assert.h" | |
29 | ||
30 | /* The instruction descriptor array. | |
31 | This is computed at runtime. Space for it is not malloc'd to save a | |
32 | teensy bit of cpu in the decoder. Moving it to malloc space is trivial | |
33 | but won't be done until necessary (we don't currently support the runtime | |
34 | addition of instructions nor an SMP machine with different cpus). */ | |
35 | static IDESC lm32bf_insn_data[LM32BF_INSN__MAX]; | |
36 | ||
37 | /* Commas between elements are contained in the macros. | |
38 | Some of these are conditionally compiled out. */ | |
39 | ||
40 | static const struct insn_sem lm32bf_insn_sem[] = | |
41 | { | |
42 | { VIRTUAL_INSN_X_INVALID, LM32BF_INSN_X_INVALID, LM32BF_SFMT_EMPTY }, | |
43 | { VIRTUAL_INSN_X_AFTER, LM32BF_INSN_X_AFTER, LM32BF_SFMT_EMPTY }, | |
44 | { VIRTUAL_INSN_X_BEFORE, LM32BF_INSN_X_BEFORE, LM32BF_SFMT_EMPTY }, | |
45 | { VIRTUAL_INSN_X_CTI_CHAIN, LM32BF_INSN_X_CTI_CHAIN, LM32BF_SFMT_EMPTY }, | |
46 | { VIRTUAL_INSN_X_CHAIN, LM32BF_INSN_X_CHAIN, LM32BF_SFMT_EMPTY }, | |
47 | { VIRTUAL_INSN_X_BEGIN, LM32BF_INSN_X_BEGIN, LM32BF_SFMT_EMPTY }, | |
48 | { LM32_INSN_ADD, LM32BF_INSN_ADD, LM32BF_SFMT_ADD }, | |
49 | { LM32_INSN_ADDI, LM32BF_INSN_ADDI, LM32BF_SFMT_ADDI }, | |
50 | { LM32_INSN_AND, LM32BF_INSN_AND, LM32BF_SFMT_ADD }, | |
51 | { LM32_INSN_ANDI, LM32BF_INSN_ANDI, LM32BF_SFMT_ANDI }, | |
52 | { LM32_INSN_ANDHII, LM32BF_INSN_ANDHII, LM32BF_SFMT_ANDHII }, | |
53 | { LM32_INSN_B, LM32BF_INSN_B, LM32BF_SFMT_B }, | |
54 | { LM32_INSN_BI, LM32BF_INSN_BI, LM32BF_SFMT_BI }, | |
55 | { LM32_INSN_BE, LM32BF_INSN_BE, LM32BF_SFMT_BE }, | |
56 | { LM32_INSN_BG, LM32BF_INSN_BG, LM32BF_SFMT_BE }, | |
57 | { LM32_INSN_BGE, LM32BF_INSN_BGE, LM32BF_SFMT_BE }, | |
58 | { LM32_INSN_BGEU, LM32BF_INSN_BGEU, LM32BF_SFMT_BE }, | |
59 | { LM32_INSN_BGU, LM32BF_INSN_BGU, LM32BF_SFMT_BE }, | |
60 | { LM32_INSN_BNE, LM32BF_INSN_BNE, LM32BF_SFMT_BE }, | |
61 | { LM32_INSN_CALL, LM32BF_INSN_CALL, LM32BF_SFMT_CALL }, | |
62 | { LM32_INSN_CALLI, LM32BF_INSN_CALLI, LM32BF_SFMT_CALLI }, | |
63 | { LM32_INSN_CMPE, LM32BF_INSN_CMPE, LM32BF_SFMT_ADD }, | |
64 | { LM32_INSN_CMPEI, LM32BF_INSN_CMPEI, LM32BF_SFMT_ADDI }, | |
65 | { LM32_INSN_CMPG, LM32BF_INSN_CMPG, LM32BF_SFMT_ADD }, | |
66 | { LM32_INSN_CMPGI, LM32BF_INSN_CMPGI, LM32BF_SFMT_ADDI }, | |
67 | { LM32_INSN_CMPGE, LM32BF_INSN_CMPGE, LM32BF_SFMT_ADD }, | |
68 | { LM32_INSN_CMPGEI, LM32BF_INSN_CMPGEI, LM32BF_SFMT_ADDI }, | |
69 | { LM32_INSN_CMPGEU, LM32BF_INSN_CMPGEU, LM32BF_SFMT_ADD }, | |
70 | { LM32_INSN_CMPGEUI, LM32BF_INSN_CMPGEUI, LM32BF_SFMT_ANDI }, | |
71 | { LM32_INSN_CMPGU, LM32BF_INSN_CMPGU, LM32BF_SFMT_ADD }, | |
72 | { LM32_INSN_CMPGUI, LM32BF_INSN_CMPGUI, LM32BF_SFMT_ANDI }, | |
73 | { LM32_INSN_CMPNE, LM32BF_INSN_CMPNE, LM32BF_SFMT_ADD }, | |
74 | { LM32_INSN_CMPNEI, LM32BF_INSN_CMPNEI, LM32BF_SFMT_ADDI }, | |
75 | { LM32_INSN_DIVU, LM32BF_INSN_DIVU, LM32BF_SFMT_DIVU }, | |
76 | { LM32_INSN_LB, LM32BF_INSN_LB, LM32BF_SFMT_LB }, | |
77 | { LM32_INSN_LBU, LM32BF_INSN_LBU, LM32BF_SFMT_LB }, | |
78 | { LM32_INSN_LH, LM32BF_INSN_LH, LM32BF_SFMT_LH }, | |
79 | { LM32_INSN_LHU, LM32BF_INSN_LHU, LM32BF_SFMT_LH }, | |
80 | { LM32_INSN_LW, LM32BF_INSN_LW, LM32BF_SFMT_LW }, | |
81 | { LM32_INSN_MODU, LM32BF_INSN_MODU, LM32BF_SFMT_DIVU }, | |
82 | { LM32_INSN_MUL, LM32BF_INSN_MUL, LM32BF_SFMT_ADD }, | |
83 | { LM32_INSN_MULI, LM32BF_INSN_MULI, LM32BF_SFMT_ADDI }, | |
84 | { LM32_INSN_NOR, LM32BF_INSN_NOR, LM32BF_SFMT_ADD }, | |
85 | { LM32_INSN_NORI, LM32BF_INSN_NORI, LM32BF_SFMT_ANDI }, | |
86 | { LM32_INSN_OR, LM32BF_INSN_OR, LM32BF_SFMT_ADD }, | |
87 | { LM32_INSN_ORI, LM32BF_INSN_ORI, LM32BF_SFMT_ORI }, | |
88 | { LM32_INSN_ORHII, LM32BF_INSN_ORHII, LM32BF_SFMT_ANDHII }, | |
89 | { LM32_INSN_RCSR, LM32BF_INSN_RCSR, LM32BF_SFMT_RCSR }, | |
90 | { LM32_INSN_SB, LM32BF_INSN_SB, LM32BF_SFMT_SB }, | |
91 | { LM32_INSN_SEXTB, LM32BF_INSN_SEXTB, LM32BF_SFMT_SEXTB }, | |
92 | { LM32_INSN_SEXTH, LM32BF_INSN_SEXTH, LM32BF_SFMT_SEXTB }, | |
93 | { LM32_INSN_SH, LM32BF_INSN_SH, LM32BF_SFMT_SH }, | |
fb067cad | 94 | { LM32_INSN_SL, LM32BF_INSN_SL, LM32BF_SFMT_ADD }, |
c28c63d8 | 95 | { LM32_INSN_SLI, LM32BF_INSN_SLI, LM32BF_SFMT_ADDI }, |
fb067cad | 96 | { LM32_INSN_SR, LM32BF_INSN_SR, LM32BF_SFMT_ADD }, |
c28c63d8 | 97 | { LM32_INSN_SRI, LM32BF_INSN_SRI, LM32BF_SFMT_ADDI }, |
fb067cad | 98 | { LM32_INSN_SRU, LM32BF_INSN_SRU, LM32BF_SFMT_ADD }, |
c28c63d8 JB |
99 | { LM32_INSN_SRUI, LM32BF_INSN_SRUI, LM32BF_SFMT_ADDI }, |
100 | { LM32_INSN_SUB, LM32BF_INSN_SUB, LM32BF_SFMT_ADD }, | |
101 | { LM32_INSN_SW, LM32BF_INSN_SW, LM32BF_SFMT_SW }, | |
102 | { LM32_INSN_USER, LM32BF_INSN_USER, LM32BF_SFMT_USER }, | |
103 | { LM32_INSN_WCSR, LM32BF_INSN_WCSR, LM32BF_SFMT_WCSR }, | |
104 | { LM32_INSN_XOR, LM32BF_INSN_XOR, LM32BF_SFMT_ADD }, | |
105 | { LM32_INSN_XORI, LM32BF_INSN_XORI, LM32BF_SFMT_ANDI }, | |
106 | { LM32_INSN_XNOR, LM32BF_INSN_XNOR, LM32BF_SFMT_ADD }, | |
107 | { LM32_INSN_XNORI, LM32BF_INSN_XNORI, LM32BF_SFMT_ANDI }, | |
108 | { LM32_INSN_BREAK, LM32BF_INSN_BREAK, LM32BF_SFMT_BREAK }, | |
109 | { LM32_INSN_SCALL, LM32BF_INSN_SCALL, LM32BF_SFMT_BREAK }, | |
110 | }; | |
111 | ||
2310652a DE |
112 | static const struct insn_sem lm32bf_insn_sem_invalid = |
113 | { | |
c28c63d8 JB |
114 | VIRTUAL_INSN_X_INVALID, LM32BF_INSN_X_INVALID, LM32BF_SFMT_EMPTY |
115 | }; | |
116 | ||
117 | /* Initialize an IDESC from the compile-time computable parts. */ | |
118 | ||
119 | static INLINE void | |
120 | init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t) | |
121 | { | |
122 | const CGEN_INSN *insn_table = CGEN_CPU_INSN_TABLE (CPU_CPU_DESC (cpu))->init_entries; | |
123 | ||
124 | id->num = t->index; | |
125 | id->sfmt = t->sfmt; | |
126 | if ((int) t->type <= 0) | |
127 | id->idata = & cgen_virtual_insn_table[- (int) t->type]; | |
128 | else | |
129 | id->idata = & insn_table[t->type]; | |
130 | id->attrs = CGEN_INSN_ATTRS (id->idata); | |
131 | /* Oh my god, a magic number. */ | |
132 | id->length = CGEN_INSN_BITSIZE (id->idata) / 8; | |
133 | ||
134 | #if WITH_PROFILE_MODEL_P | |
135 | id->timing = & MODEL_TIMING (CPU_MODEL (cpu)) [t->index]; | |
136 | { | |
137 | SIM_DESC sd = CPU_STATE (cpu); | |
138 | SIM_ASSERT (t->index == id->timing->num); | |
139 | } | |
140 | #endif | |
141 | ||
142 | /* Semantic pointers are initialized elsewhere. */ | |
143 | } | |
144 | ||
145 | /* Initialize the instruction descriptor table. */ | |
146 | ||
147 | void | |
148 | lm32bf_init_idesc_table (SIM_CPU *cpu) | |
149 | { | |
150 | IDESC *id,*tabend; | |
151 | const struct insn_sem *t,*tend; | |
152 | int tabsize = LM32BF_INSN__MAX; | |
153 | IDESC *table = lm32bf_insn_data; | |
154 | ||
155 | memset (table, 0, tabsize * sizeof (IDESC)); | |
156 | ||
157 | /* First set all entries to the `invalid insn'. */ | |
158 | t = & lm32bf_insn_sem_invalid; | |
159 | for (id = table, tabend = table + tabsize; id < tabend; ++id) | |
160 | init_idesc (cpu, id, t); | |
161 | ||
162 | /* Now fill in the values for the chosen cpu. */ | |
163 | for (t = lm32bf_insn_sem, tend = t + sizeof (lm32bf_insn_sem) / sizeof (*t); | |
164 | t != tend; ++t) | |
165 | { | |
166 | init_idesc (cpu, & table[t->index], t); | |
167 | } | |
168 | ||
169 | /* Link the IDESC table into the cpu. */ | |
170 | CPU_IDESC (cpu) = table; | |
171 | } | |
172 | ||
173 | /* Given an instruction, return a pointer to its IDESC entry. */ | |
174 | ||
175 | const IDESC * | |
176 | lm32bf_decode (SIM_CPU *current_cpu, IADDR pc, | |
197fa1aa | 177 | CGEN_INSN_WORD base_insn, CGEN_INSN_WORD entire_insn, |
c28c63d8 JB |
178 | ARGBUF *abuf) |
179 | { | |
180 | /* Result of decoder. */ | |
181 | LM32BF_INSN_TYPE itype; | |
182 | ||
183 | { | |
197fa1aa | 184 | CGEN_INSN_WORD insn = base_insn; |
c28c63d8 JB |
185 | |
186 | { | |
187 | unsigned int val = (((insn >> 26) & (63 << 0))); | |
188 | switch (val) | |
189 | { | |
fb067cad DE |
190 | case 0 : itype = LM32BF_INSN_SRUI; goto extract_sfmt_addi; |
191 | case 1 : itype = LM32BF_INSN_NORI; goto extract_sfmt_andi; | |
192 | case 2 : itype = LM32BF_INSN_MULI; goto extract_sfmt_addi; | |
193 | case 3 : itype = LM32BF_INSN_SH; goto extract_sfmt_sh; | |
194 | case 4 : itype = LM32BF_INSN_LB; goto extract_sfmt_lb; | |
195 | case 5 : itype = LM32BF_INSN_SRI; goto extract_sfmt_addi; | |
196 | case 6 : itype = LM32BF_INSN_XORI; goto extract_sfmt_andi; | |
197 | case 7 : itype = LM32BF_INSN_LH; goto extract_sfmt_lh; | |
198 | case 8 : itype = LM32BF_INSN_ANDI; goto extract_sfmt_andi; | |
199 | case 9 : itype = LM32BF_INSN_XNORI; goto extract_sfmt_andi; | |
200 | case 10 : itype = LM32BF_INSN_LW; goto extract_sfmt_lw; | |
201 | case 11 : itype = LM32BF_INSN_LHU; goto extract_sfmt_lh; | |
202 | case 12 : itype = LM32BF_INSN_SB; goto extract_sfmt_sb; | |
203 | case 13 : itype = LM32BF_INSN_ADDI; goto extract_sfmt_addi; | |
204 | case 14 : itype = LM32BF_INSN_ORI; goto extract_sfmt_ori; | |
205 | case 15 : itype = LM32BF_INSN_SLI; goto extract_sfmt_addi; | |
206 | case 16 : itype = LM32BF_INSN_LBU; goto extract_sfmt_lb; | |
207 | case 17 : itype = LM32BF_INSN_BE; goto extract_sfmt_be; | |
208 | case 18 : itype = LM32BF_INSN_BG; goto extract_sfmt_be; | |
209 | case 19 : itype = LM32BF_INSN_BGE; goto extract_sfmt_be; | |
210 | case 20 : itype = LM32BF_INSN_BGEU; goto extract_sfmt_be; | |
211 | case 21 : itype = LM32BF_INSN_BGU; goto extract_sfmt_be; | |
212 | case 22 : itype = LM32BF_INSN_SW; goto extract_sfmt_sw; | |
213 | case 23 : itype = LM32BF_INSN_BNE; goto extract_sfmt_be; | |
214 | case 24 : itype = LM32BF_INSN_ANDHII; goto extract_sfmt_andhii; | |
215 | case 25 : itype = LM32BF_INSN_CMPEI; goto extract_sfmt_addi; | |
216 | case 26 : itype = LM32BF_INSN_CMPGI; goto extract_sfmt_addi; | |
217 | case 27 : itype = LM32BF_INSN_CMPGEI; goto extract_sfmt_addi; | |
218 | case 28 : itype = LM32BF_INSN_CMPGEUI; goto extract_sfmt_andi; | |
219 | case 29 : itype = LM32BF_INSN_CMPGUI; goto extract_sfmt_andi; | |
220 | case 30 : itype = LM32BF_INSN_ORHII; goto extract_sfmt_andhii; | |
221 | case 31 : itype = LM32BF_INSN_CMPNEI; goto extract_sfmt_addi; | |
c28c63d8 JB |
222 | case 32 : |
223 | if ((entire_insn & 0xfc0007ff) == 0x80000000) | |
fb067cad | 224 | { itype = LM32BF_INSN_SRU; goto extract_sfmt_add; } |
c28c63d8 JB |
225 | itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty; |
226 | case 33 : | |
227 | if ((entire_insn & 0xfc0007ff) == 0x84000000) | |
228 | { itype = LM32BF_INSN_NOR; goto extract_sfmt_add; } | |
229 | itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty; | |
230 | case 34 : | |
231 | if ((entire_insn & 0xfc0007ff) == 0x88000000) | |
232 | { itype = LM32BF_INSN_MUL; goto extract_sfmt_add; } | |
233 | itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty; | |
234 | case 35 : | |
235 | if ((entire_insn & 0xfc0007ff) == 0x8c000000) | |
236 | { itype = LM32BF_INSN_DIVU; goto extract_sfmt_divu; } | |
237 | itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty; | |
238 | case 36 : | |
239 | if ((entire_insn & 0xfc1f07ff) == 0x90000000) | |
240 | { itype = LM32BF_INSN_RCSR; goto extract_sfmt_rcsr; } | |
241 | itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty; | |
242 | case 37 : | |
243 | if ((entire_insn & 0xfc0007ff) == 0x94000000) | |
fb067cad | 244 | { itype = LM32BF_INSN_SR; goto extract_sfmt_add; } |
c28c63d8 JB |
245 | itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty; |
246 | case 38 : | |
247 | if ((entire_insn & 0xfc0007ff) == 0x98000000) | |
248 | { itype = LM32BF_INSN_XOR; goto extract_sfmt_add; } | |
249 | itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty; | |
250 | case 40 : | |
251 | if ((entire_insn & 0xfc0007ff) == 0xa0000000) | |
252 | { itype = LM32BF_INSN_AND; goto extract_sfmt_add; } | |
253 | itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty; | |
254 | case 41 : | |
255 | if ((entire_insn & 0xfc0007ff) == 0xa4000000) | |
256 | { itype = LM32BF_INSN_XNOR; goto extract_sfmt_add; } | |
257 | itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty; | |
258 | case 43 : | |
259 | { | |
260 | unsigned int val = (((insn >> 1) & (1 << 1)) | ((insn >> 0) & (1 << 0))); | |
261 | switch (val) | |
262 | { | |
263 | case 0 : | |
264 | if ((entire_insn & 0xffffffff) == 0xac000002) | |
265 | { itype = LM32BF_INSN_BREAK; goto extract_sfmt_break; } | |
266 | itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty; | |
267 | case 3 : | |
268 | if ((entire_insn & 0xffffffff) == 0xac000007) | |
269 | { itype = LM32BF_INSN_SCALL; goto extract_sfmt_break; } | |
270 | itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty; | |
271 | default : itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty; | |
272 | } | |
273 | } | |
274 | case 44 : | |
275 | if ((entire_insn & 0xfc1f07ff) == 0xb0000000) | |
276 | { itype = LM32BF_INSN_SEXTB; goto extract_sfmt_sextb; } | |
277 | itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty; | |
278 | case 45 : | |
279 | if ((entire_insn & 0xfc0007ff) == 0xb4000000) | |
280 | { itype = LM32BF_INSN_ADD; goto extract_sfmt_add; } | |
281 | itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty; | |
282 | case 46 : | |
283 | if ((entire_insn & 0xfc0007ff) == 0xb8000000) | |
284 | { itype = LM32BF_INSN_OR; goto extract_sfmt_add; } | |
285 | itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty; | |
286 | case 47 : | |
287 | if ((entire_insn & 0xfc0007ff) == 0xbc000000) | |
fb067cad | 288 | { itype = LM32BF_INSN_SL; goto extract_sfmt_add; } |
c28c63d8 JB |
289 | itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty; |
290 | case 48 : | |
291 | if ((entire_insn & 0xfc1fffff) == 0xc0000000) | |
292 | { itype = LM32BF_INSN_B; goto extract_sfmt_b; } | |
293 | itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty; | |
294 | case 49 : | |
295 | if ((entire_insn & 0xfc0007ff) == 0xc4000000) | |
296 | { itype = LM32BF_INSN_MODU; goto extract_sfmt_divu; } | |
297 | itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty; | |
298 | case 50 : | |
299 | if ((entire_insn & 0xfc0007ff) == 0xc8000000) | |
300 | { itype = LM32BF_INSN_SUB; goto extract_sfmt_add; } | |
301 | itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty; | |
fb067cad | 302 | case 51 : itype = LM32BF_INSN_USER; goto extract_sfmt_user; |
c28c63d8 JB |
303 | case 52 : |
304 | if ((entire_insn & 0xfc00ffff) == 0xd0000000) | |
305 | { itype = LM32BF_INSN_WCSR; goto extract_sfmt_wcsr; } | |
306 | itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty; | |
307 | case 54 : | |
308 | if ((entire_insn & 0xfc1fffff) == 0xd8000000) | |
309 | { itype = LM32BF_INSN_CALL; goto extract_sfmt_call; } | |
310 | itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty; | |
311 | case 55 : | |
312 | if ((entire_insn & 0xfc1f07ff) == 0xdc000000) | |
313 | { itype = LM32BF_INSN_SEXTH; goto extract_sfmt_sextb; } | |
314 | itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty; | |
fb067cad | 315 | case 56 : itype = LM32BF_INSN_BI; goto extract_sfmt_bi; |
c28c63d8 JB |
316 | case 57 : |
317 | if ((entire_insn & 0xfc0007ff) == 0xe4000000) | |
318 | { itype = LM32BF_INSN_CMPE; goto extract_sfmt_add; } | |
319 | itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty; | |
320 | case 58 : | |
321 | if ((entire_insn & 0xfc0007ff) == 0xe8000000) | |
322 | { itype = LM32BF_INSN_CMPG; goto extract_sfmt_add; } | |
323 | itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty; | |
324 | case 59 : | |
325 | if ((entire_insn & 0xfc0007ff) == 0xec000000) | |
326 | { itype = LM32BF_INSN_CMPGE; goto extract_sfmt_add; } | |
327 | itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty; | |
328 | case 60 : | |
329 | if ((entire_insn & 0xfc0007ff) == 0xf0000000) | |
330 | { itype = LM32BF_INSN_CMPGEU; goto extract_sfmt_add; } | |
331 | itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty; | |
332 | case 61 : | |
333 | if ((entire_insn & 0xfc0007ff) == 0xf4000000) | |
334 | { itype = LM32BF_INSN_CMPGU; goto extract_sfmt_add; } | |
335 | itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty; | |
fb067cad | 336 | case 62 : itype = LM32BF_INSN_CALLI; goto extract_sfmt_calli; |
c28c63d8 JB |
337 | case 63 : |
338 | if ((entire_insn & 0xfc0007ff) == 0xfc000000) | |
339 | { itype = LM32BF_INSN_CMPNE; goto extract_sfmt_add; } | |
340 | itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty; | |
341 | default : itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty; | |
342 | } | |
343 | } | |
344 | } | |
345 | ||
346 | /* The instruction has been decoded, now extract the fields. */ | |
347 | ||
348 | extract_sfmt_empty: | |
349 | { | |
350 | const IDESC *idesc = &lm32bf_insn_data[itype]; | |
2310652a | 351 | #define FLD(f) abuf->fields.sfmt_empty.f |
c28c63d8 JB |
352 | |
353 | ||
354 | /* Record the fields for the semantic handler. */ | |
355 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_empty", (char *) 0)); | |
356 | ||
357 | #undef FLD | |
358 | return idesc; | |
359 | } | |
360 | ||
361 | extract_sfmt_add: | |
362 | { | |
363 | const IDESC *idesc = &lm32bf_insn_data[itype]; | |
197fa1aa | 364 | CGEN_INSN_WORD insn = entire_insn; |
c28c63d8 JB |
365 | #define FLD(f) abuf->fields.sfmt_user.f |
366 | UINT f_r0; | |
367 | UINT f_r1; | |
368 | UINT f_r2; | |
369 | ||
370 | f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); | |
371 | f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); | |
372 | f_r2 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); | |
373 | ||
374 | /* Record the fields for the semantic handler. */ | |
375 | FLD (f_r0) = f_r0; | |
376 | FLD (f_r1) = f_r1; | |
377 | FLD (f_r2) = f_r2; | |
378 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add", "f_r0 0x%x", 'x', f_r0, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, (char *) 0)); | |
379 | ||
380 | #undef FLD | |
381 | return idesc; | |
382 | } | |
383 | ||
384 | extract_sfmt_addi: | |
385 | { | |
386 | const IDESC *idesc = &lm32bf_insn_data[itype]; | |
197fa1aa | 387 | CGEN_INSN_WORD insn = entire_insn; |
c28c63d8 JB |
388 | #define FLD(f) abuf->fields.sfmt_addi.f |
389 | UINT f_r0; | |
390 | UINT f_r1; | |
391 | INT f_imm; | |
392 | ||
393 | f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); | |
394 | f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); | |
62836bf4 | 395 | f_imm = EXTRACT_LSB0_SINT (insn, 32, 15, 16); |
c28c63d8 JB |
396 | |
397 | /* Record the fields for the semantic handler. */ | |
398 | FLD (f_imm) = f_imm; | |
399 | FLD (f_r0) = f_r0; | |
400 | FLD (f_r1) = f_r1; | |
401 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addi", "f_imm 0x%x", 'x', f_imm, "f_r0 0x%x", 'x', f_r0, "f_r1 0x%x", 'x', f_r1, (char *) 0)); | |
402 | ||
403 | #undef FLD | |
404 | return idesc; | |
405 | } | |
406 | ||
407 | extract_sfmt_andi: | |
408 | { | |
409 | const IDESC *idesc = &lm32bf_insn_data[itype]; | |
197fa1aa | 410 | CGEN_INSN_WORD insn = entire_insn; |
c28c63d8 JB |
411 | #define FLD(f) abuf->fields.sfmt_andi.f |
412 | UINT f_r0; | |
413 | UINT f_r1; | |
414 | UINT f_uimm; | |
415 | ||
416 | f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); | |
417 | f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); | |
418 | f_uimm = EXTRACT_LSB0_UINT (insn, 32, 15, 16); | |
419 | ||
420 | /* Record the fields for the semantic handler. */ | |
421 | FLD (f_r0) = f_r0; | |
422 | FLD (f_uimm) = f_uimm; | |
423 | FLD (f_r1) = f_r1; | |
424 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_andi", "f_r0 0x%x", 'x', f_r0, "f_uimm 0x%x", 'x', f_uimm, "f_r1 0x%x", 'x', f_r1, (char *) 0)); | |
425 | ||
426 | #undef FLD | |
427 | return idesc; | |
428 | } | |
429 | ||
430 | extract_sfmt_andhii: | |
431 | { | |
432 | const IDESC *idesc = &lm32bf_insn_data[itype]; | |
197fa1aa | 433 | CGEN_INSN_WORD insn = entire_insn; |
c28c63d8 JB |
434 | #define FLD(f) abuf->fields.sfmt_andi.f |
435 | UINT f_r0; | |
436 | UINT f_r1; | |
437 | UINT f_uimm; | |
438 | ||
439 | f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); | |
440 | f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); | |
441 | f_uimm = EXTRACT_LSB0_UINT (insn, 32, 15, 16); | |
442 | ||
443 | /* Record the fields for the semantic handler. */ | |
444 | FLD (f_uimm) = f_uimm; | |
445 | FLD (f_r0) = f_r0; | |
446 | FLD (f_r1) = f_r1; | |
447 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_andhii", "f_uimm 0x%x", 'x', f_uimm, "f_r0 0x%x", 'x', f_r0, "f_r1 0x%x", 'x', f_r1, (char *) 0)); | |
448 | ||
449 | #undef FLD | |
450 | return idesc; | |
451 | } | |
452 | ||
453 | extract_sfmt_b: | |
454 | { | |
455 | const IDESC *idesc = &lm32bf_insn_data[itype]; | |
197fa1aa | 456 | CGEN_INSN_WORD insn = entire_insn; |
c28c63d8 JB |
457 | #define FLD(f) abuf->fields.sfmt_be.f |
458 | UINT f_r0; | |
459 | ||
460 | f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); | |
461 | ||
462 | /* Record the fields for the semantic handler. */ | |
463 | FLD (f_r0) = f_r0; | |
464 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_b", "f_r0 0x%x", 'x', f_r0, (char *) 0)); | |
465 | ||
466 | #undef FLD | |
467 | return idesc; | |
468 | } | |
469 | ||
470 | extract_sfmt_bi: | |
471 | { | |
472 | const IDESC *idesc = &lm32bf_insn_data[itype]; | |
197fa1aa | 473 | CGEN_INSN_WORD insn = entire_insn; |
c28c63d8 JB |
474 | #define FLD(f) abuf->fields.sfmt_bi.f |
475 | SI f_call; | |
476 | ||
68eeb703 | 477 | f_call = ((pc) + (((SI) (((EXTRACT_LSB0_SINT (insn, 32, 25, 26)) << (6))) >> (4)))); |
c28c63d8 JB |
478 | |
479 | /* Record the fields for the semantic handler. */ | |
480 | FLD (i_call) = f_call; | |
481 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bi", "call 0x%x", 'x', f_call, (char *) 0)); | |
482 | ||
483 | #undef FLD | |
484 | return idesc; | |
485 | } | |
486 | ||
487 | extract_sfmt_be: | |
488 | { | |
489 | const IDESC *idesc = &lm32bf_insn_data[itype]; | |
197fa1aa | 490 | CGEN_INSN_WORD insn = entire_insn; |
c28c63d8 JB |
491 | #define FLD(f) abuf->fields.sfmt_be.f |
492 | UINT f_r0; | |
493 | UINT f_r1; | |
494 | SI f_branch; | |
495 | ||
496 | f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); | |
497 | f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); | |
68eeb703 | 498 | f_branch = ((pc) + (((SI) (((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) << (16))) >> (14)))); |
c28c63d8 JB |
499 | |
500 | /* Record the fields for the semantic handler. */ | |
501 | FLD (f_r0) = f_r0; | |
502 | FLD (f_r1) = f_r1; | |
503 | FLD (i_branch) = f_branch; | |
504 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_be", "f_r0 0x%x", 'x', f_r0, "f_r1 0x%x", 'x', f_r1, "branch 0x%x", 'x', f_branch, (char *) 0)); | |
505 | ||
506 | #undef FLD | |
507 | return idesc; | |
508 | } | |
509 | ||
510 | extract_sfmt_call: | |
511 | { | |
512 | const IDESC *idesc = &lm32bf_insn_data[itype]; | |
197fa1aa | 513 | CGEN_INSN_WORD insn = entire_insn; |
c28c63d8 JB |
514 | #define FLD(f) abuf->fields.sfmt_be.f |
515 | UINT f_r0; | |
516 | ||
517 | f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); | |
518 | ||
519 | /* Record the fields for the semantic handler. */ | |
520 | FLD (f_r0) = f_r0; | |
521 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_call", "f_r0 0x%x", 'x', f_r0, (char *) 0)); | |
522 | ||
523 | #undef FLD | |
524 | return idesc; | |
525 | } | |
526 | ||
527 | extract_sfmt_calli: | |
528 | { | |
529 | const IDESC *idesc = &lm32bf_insn_data[itype]; | |
197fa1aa | 530 | CGEN_INSN_WORD insn = entire_insn; |
c28c63d8 JB |
531 | #define FLD(f) abuf->fields.sfmt_bi.f |
532 | SI f_call; | |
533 | ||
68eeb703 | 534 | f_call = ((pc) + (((SI) (((EXTRACT_LSB0_SINT (insn, 32, 25, 26)) << (6))) >> (4)))); |
c28c63d8 JB |
535 | |
536 | /* Record the fields for the semantic handler. */ | |
537 | FLD (i_call) = f_call; | |
538 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_calli", "call 0x%x", 'x', f_call, (char *) 0)); | |
539 | ||
540 | #undef FLD | |
541 | return idesc; | |
542 | } | |
543 | ||
544 | extract_sfmt_divu: | |
545 | { | |
546 | const IDESC *idesc = &lm32bf_insn_data[itype]; | |
197fa1aa | 547 | CGEN_INSN_WORD insn = entire_insn; |
c28c63d8 JB |
548 | #define FLD(f) abuf->fields.sfmt_user.f |
549 | UINT f_r0; | |
550 | UINT f_r1; | |
551 | UINT f_r2; | |
552 | ||
553 | f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); | |
554 | f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); | |
555 | f_r2 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); | |
556 | ||
557 | /* Record the fields for the semantic handler. */ | |
558 | FLD (f_r0) = f_r0; | |
559 | FLD (f_r1) = f_r1; | |
560 | FLD (f_r2) = f_r2; | |
561 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_divu", "f_r0 0x%x", 'x', f_r0, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, (char *) 0)); | |
562 | ||
563 | #undef FLD | |
564 | return idesc; | |
565 | } | |
566 | ||
567 | extract_sfmt_lb: | |
568 | { | |
569 | const IDESC *idesc = &lm32bf_insn_data[itype]; | |
197fa1aa | 570 | CGEN_INSN_WORD insn = entire_insn; |
c28c63d8 JB |
571 | #define FLD(f) abuf->fields.sfmt_addi.f |
572 | UINT f_r0; | |
573 | UINT f_r1; | |
574 | INT f_imm; | |
575 | ||
576 | f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); | |
577 | f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); | |
62836bf4 | 578 | f_imm = EXTRACT_LSB0_SINT (insn, 32, 15, 16); |
c28c63d8 JB |
579 | |
580 | /* Record the fields for the semantic handler. */ | |
581 | FLD (f_imm) = f_imm; | |
582 | FLD (f_r0) = f_r0; | |
583 | FLD (f_r1) = f_r1; | |
584 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lb", "f_imm 0x%x", 'x', f_imm, "f_r0 0x%x", 'x', f_r0, "f_r1 0x%x", 'x', f_r1, (char *) 0)); | |
585 | ||
586 | #undef FLD | |
587 | return idesc; | |
588 | } | |
589 | ||
590 | extract_sfmt_lh: | |
591 | { | |
592 | const IDESC *idesc = &lm32bf_insn_data[itype]; | |
197fa1aa | 593 | CGEN_INSN_WORD insn = entire_insn; |
c28c63d8 JB |
594 | #define FLD(f) abuf->fields.sfmt_addi.f |
595 | UINT f_r0; | |
596 | UINT f_r1; | |
597 | INT f_imm; | |
598 | ||
599 | f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); | |
600 | f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); | |
62836bf4 | 601 | f_imm = EXTRACT_LSB0_SINT (insn, 32, 15, 16); |
c28c63d8 JB |
602 | |
603 | /* Record the fields for the semantic handler. */ | |
604 | FLD (f_imm) = f_imm; | |
605 | FLD (f_r0) = f_r0; | |
606 | FLD (f_r1) = f_r1; | |
607 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lh", "f_imm 0x%x", 'x', f_imm, "f_r0 0x%x", 'x', f_r0, "f_r1 0x%x", 'x', f_r1, (char *) 0)); | |
608 | ||
609 | #undef FLD | |
610 | return idesc; | |
611 | } | |
612 | ||
613 | extract_sfmt_lw: | |
614 | { | |
615 | const IDESC *idesc = &lm32bf_insn_data[itype]; | |
197fa1aa | 616 | CGEN_INSN_WORD insn = entire_insn; |
c28c63d8 JB |
617 | #define FLD(f) abuf->fields.sfmt_addi.f |
618 | UINT f_r0; | |
619 | UINT f_r1; | |
620 | INT f_imm; | |
621 | ||
622 | f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); | |
623 | f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); | |
62836bf4 | 624 | f_imm = EXTRACT_LSB0_SINT (insn, 32, 15, 16); |
c28c63d8 JB |
625 | |
626 | /* Record the fields for the semantic handler. */ | |
627 | FLD (f_imm) = f_imm; | |
628 | FLD (f_r0) = f_r0; | |
629 | FLD (f_r1) = f_r1; | |
630 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lw", "f_imm 0x%x", 'x', f_imm, "f_r0 0x%x", 'x', f_r0, "f_r1 0x%x", 'x', f_r1, (char *) 0)); | |
631 | ||
632 | #undef FLD | |
633 | return idesc; | |
634 | } | |
635 | ||
636 | extract_sfmt_ori: | |
637 | { | |
638 | const IDESC *idesc = &lm32bf_insn_data[itype]; | |
197fa1aa | 639 | CGEN_INSN_WORD insn = entire_insn; |
c28c63d8 JB |
640 | #define FLD(f) abuf->fields.sfmt_andi.f |
641 | UINT f_r0; | |
642 | UINT f_r1; | |
643 | UINT f_uimm; | |
644 | ||
645 | f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); | |
646 | f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); | |
647 | f_uimm = EXTRACT_LSB0_UINT (insn, 32, 15, 16); | |
648 | ||
649 | /* Record the fields for the semantic handler. */ | |
650 | FLD (f_uimm) = f_uimm; | |
651 | FLD (f_r0) = f_r0; | |
652 | FLD (f_r1) = f_r1; | |
653 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ori", "f_uimm 0x%x", 'x', f_uimm, "f_r0 0x%x", 'x', f_r0, "f_r1 0x%x", 'x', f_r1, (char *) 0)); | |
654 | ||
655 | #undef FLD | |
656 | return idesc; | |
657 | } | |
658 | ||
659 | extract_sfmt_rcsr: | |
660 | { | |
661 | const IDESC *idesc = &lm32bf_insn_data[itype]; | |
197fa1aa | 662 | CGEN_INSN_WORD insn = entire_insn; |
c28c63d8 JB |
663 | #define FLD(f) abuf->fields.sfmt_rcsr.f |
664 | UINT f_csr; | |
665 | UINT f_r2; | |
666 | ||
667 | f_csr = EXTRACT_LSB0_UINT (insn, 32, 25, 5); | |
668 | f_r2 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); | |
669 | ||
670 | /* Record the fields for the semantic handler. */ | |
671 | FLD (f_csr) = f_csr; | |
672 | FLD (f_r2) = f_r2; | |
673 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rcsr", "f_csr 0x%x", 'x', f_csr, "f_r2 0x%x", 'x', f_r2, (char *) 0)); | |
674 | ||
675 | #undef FLD | |
676 | return idesc; | |
677 | } | |
678 | ||
679 | extract_sfmt_sb: | |
680 | { | |
681 | const IDESC *idesc = &lm32bf_insn_data[itype]; | |
197fa1aa | 682 | CGEN_INSN_WORD insn = entire_insn; |
c28c63d8 JB |
683 | #define FLD(f) abuf->fields.sfmt_addi.f |
684 | UINT f_r0; | |
685 | UINT f_r1; | |
686 | INT f_imm; | |
687 | ||
688 | f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); | |
689 | f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); | |
62836bf4 | 690 | f_imm = EXTRACT_LSB0_SINT (insn, 32, 15, 16); |
c28c63d8 JB |
691 | |
692 | /* Record the fields for the semantic handler. */ | |
693 | FLD (f_imm) = f_imm; | |
694 | FLD (f_r0) = f_r0; | |
695 | FLD (f_r1) = f_r1; | |
696 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sb", "f_imm 0x%x", 'x', f_imm, "f_r0 0x%x", 'x', f_r0, "f_r1 0x%x", 'x', f_r1, (char *) 0)); | |
697 | ||
698 | #undef FLD | |
699 | return idesc; | |
700 | } | |
701 | ||
702 | extract_sfmt_sextb: | |
703 | { | |
704 | const IDESC *idesc = &lm32bf_insn_data[itype]; | |
197fa1aa | 705 | CGEN_INSN_WORD insn = entire_insn; |
c28c63d8 JB |
706 | #define FLD(f) abuf->fields.sfmt_user.f |
707 | UINT f_r0; | |
708 | UINT f_r2; | |
709 | ||
710 | f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); | |
711 | f_r2 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); | |
712 | ||
713 | /* Record the fields for the semantic handler. */ | |
714 | FLD (f_r0) = f_r0; | |
715 | FLD (f_r2) = f_r2; | |
716 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sextb", "f_r0 0x%x", 'x', f_r0, "f_r2 0x%x", 'x', f_r2, (char *) 0)); | |
717 | ||
718 | #undef FLD | |
719 | return idesc; | |
720 | } | |
721 | ||
722 | extract_sfmt_sh: | |
723 | { | |
724 | const IDESC *idesc = &lm32bf_insn_data[itype]; | |
197fa1aa | 725 | CGEN_INSN_WORD insn = entire_insn; |
c28c63d8 JB |
726 | #define FLD(f) abuf->fields.sfmt_addi.f |
727 | UINT f_r0; | |
728 | UINT f_r1; | |
729 | INT f_imm; | |
730 | ||
731 | f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); | |
732 | f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); | |
62836bf4 | 733 | f_imm = EXTRACT_LSB0_SINT (insn, 32, 15, 16); |
c28c63d8 JB |
734 | |
735 | /* Record the fields for the semantic handler. */ | |
736 | FLD (f_imm) = f_imm; | |
737 | FLD (f_r0) = f_r0; | |
738 | FLD (f_r1) = f_r1; | |
739 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sh", "f_imm 0x%x", 'x', f_imm, "f_r0 0x%x", 'x', f_r0, "f_r1 0x%x", 'x', f_r1, (char *) 0)); | |
740 | ||
c28c63d8 JB |
741 | #undef FLD |
742 | return idesc; | |
743 | } | |
744 | ||
745 | extract_sfmt_sw: | |
746 | { | |
747 | const IDESC *idesc = &lm32bf_insn_data[itype]; | |
197fa1aa | 748 | CGEN_INSN_WORD insn = entire_insn; |
c28c63d8 JB |
749 | #define FLD(f) abuf->fields.sfmt_addi.f |
750 | UINT f_r0; | |
751 | UINT f_r1; | |
752 | INT f_imm; | |
753 | ||
754 | f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); | |
755 | f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); | |
62836bf4 | 756 | f_imm = EXTRACT_LSB0_SINT (insn, 32, 15, 16); |
c28c63d8 JB |
757 | |
758 | /* Record the fields for the semantic handler. */ | |
759 | FLD (f_imm) = f_imm; | |
760 | FLD (f_r0) = f_r0; | |
761 | FLD (f_r1) = f_r1; | |
762 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sw", "f_imm 0x%x", 'x', f_imm, "f_r0 0x%x", 'x', f_r0, "f_r1 0x%x", 'x', f_r1, (char *) 0)); | |
763 | ||
764 | #undef FLD | |
765 | return idesc; | |
766 | } | |
767 | ||
768 | extract_sfmt_user: | |
769 | { | |
770 | const IDESC *idesc = &lm32bf_insn_data[itype]; | |
197fa1aa | 771 | CGEN_INSN_WORD insn = entire_insn; |
c28c63d8 JB |
772 | #define FLD(f) abuf->fields.sfmt_user.f |
773 | UINT f_r0; | |
774 | UINT f_r1; | |
775 | UINT f_r2; | |
776 | UINT f_user; | |
777 | ||
778 | f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); | |
779 | f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); | |
780 | f_r2 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); | |
781 | f_user = EXTRACT_LSB0_UINT (insn, 32, 10, 11); | |
782 | ||
783 | /* Record the fields for the semantic handler. */ | |
784 | FLD (f_r0) = f_r0; | |
785 | FLD (f_r1) = f_r1; | |
786 | FLD (f_user) = f_user; | |
787 | FLD (f_r2) = f_r2; | |
788 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_user", "f_r0 0x%x", 'x', f_r0, "f_r1 0x%x", 'x', f_r1, "f_user 0x%x", 'x', f_user, "f_r2 0x%x", 'x', f_r2, (char *) 0)); | |
789 | ||
790 | #undef FLD | |
791 | return idesc; | |
792 | } | |
793 | ||
794 | extract_sfmt_wcsr: | |
795 | { | |
796 | const IDESC *idesc = &lm32bf_insn_data[itype]; | |
197fa1aa | 797 | CGEN_INSN_WORD insn = entire_insn; |
c28c63d8 JB |
798 | #define FLD(f) abuf->fields.sfmt_wcsr.f |
799 | UINT f_csr; | |
800 | UINT f_r1; | |
801 | ||
802 | f_csr = EXTRACT_LSB0_UINT (insn, 32, 25, 5); | |
803 | f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); | |
804 | ||
805 | /* Record the fields for the semantic handler. */ | |
806 | FLD (f_csr) = f_csr; | |
807 | FLD (f_r1) = f_r1; | |
808 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_wcsr", "f_csr 0x%x", 'x', f_csr, "f_r1 0x%x", 'x', f_r1, (char *) 0)); | |
809 | ||
810 | #undef FLD | |
811 | return idesc; | |
812 | } | |
813 | ||
814 | extract_sfmt_break: | |
815 | { | |
816 | const IDESC *idesc = &lm32bf_insn_data[itype]; | |
2310652a | 817 | #define FLD(f) abuf->fields.sfmt_empty.f |
c28c63d8 JB |
818 | |
819 | ||
820 | /* Record the fields for the semantic handler. */ | |
821 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_break", (char *) 0)); | |
822 | ||
823 | #undef FLD | |
824 | return idesc; | |
825 | } | |
826 | ||
827 | } |