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* arch.c: Regenerate.
[deliverable/binutils-gdb.git] / sim / lm32 / sem-switch.c
CommitLineData
c28c63d8
JB		 1/* Simulator instruction semantics for lm32bf.
2
3THIS FILE IS MACHINE GENERATED WITH CGEN.
4
fb067cad 5Copyright 1996-2009 Free Software Foundation, Inc.
c28c63d8
JB		 6
7This file is part of the GNU simulators.
8
fb067cad
DE		 9 This file is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
12 any later version.
c28c63d8 13
fb067cad
DE		 14 It is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
c28c63d8 18
fb067cad
DE		 19 You should have received a copy of the GNU General Public License along
20 with this program; if not, write to the Free Software Foundation, Inc.,
21 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
c28c63d8
JB		 22
23*/
24
25#ifdef DEFINE_LABELS
26
27 /* The labels have the case they have because the enum of insn types
28 is all uppercase and in the non-stdc case the insn symbol is built
29 into the enum name. */
30
31 static struct {
32 int index;
33 void *label;
34 } labels[] = {
35 { LM32BF_INSN_X_INVALID, && case_sem_INSN_X_INVALID },
36 { LM32BF_INSN_X_AFTER, && case_sem_INSN_X_AFTER },
37 { LM32BF_INSN_X_BEFORE, && case_sem_INSN_X_BEFORE },
38 { LM32BF_INSN_X_CTI_CHAIN, && case_sem_INSN_X_CTI_CHAIN },
39 { LM32BF_INSN_X_CHAIN, && case_sem_INSN_X_CHAIN },
40 { LM32BF_INSN_X_BEGIN, && case_sem_INSN_X_BEGIN },
41 { LM32BF_INSN_ADD, && case_sem_INSN_ADD },
42 { LM32BF_INSN_ADDI, && case_sem_INSN_ADDI },
43 { LM32BF_INSN_AND, && case_sem_INSN_AND },
44 { LM32BF_INSN_ANDI, && case_sem_INSN_ANDI },
45 { LM32BF_INSN_ANDHII, && case_sem_INSN_ANDHII },
46 { LM32BF_INSN_B, && case_sem_INSN_B },
47 { LM32BF_INSN_BI, && case_sem_INSN_BI },
48 { LM32BF_INSN_BE, && case_sem_INSN_BE },
49 { LM32BF_INSN_BG, && case_sem_INSN_BG },
50 { LM32BF_INSN_BGE, && case_sem_INSN_BGE },
51 { LM32BF_INSN_BGEU, && case_sem_INSN_BGEU },
52 { LM32BF_INSN_BGU, && case_sem_INSN_BGU },
53 { LM32BF_INSN_BNE, && case_sem_INSN_BNE },
54 { LM32BF_INSN_CALL, && case_sem_INSN_CALL },
55 { LM32BF_INSN_CALLI, && case_sem_INSN_CALLI },
56 { LM32BF_INSN_CMPE, && case_sem_INSN_CMPE },
57 { LM32BF_INSN_CMPEI, && case_sem_INSN_CMPEI },
58 { LM32BF_INSN_CMPG, && case_sem_INSN_CMPG },
59 { LM32BF_INSN_CMPGI, && case_sem_INSN_CMPGI },
60 { LM32BF_INSN_CMPGE, && case_sem_INSN_CMPGE },
61 { LM32BF_INSN_CMPGEI, && case_sem_INSN_CMPGEI },
62 { LM32BF_INSN_CMPGEU, && case_sem_INSN_CMPGEU },
63 { LM32BF_INSN_CMPGEUI, && case_sem_INSN_CMPGEUI },
64 { LM32BF_INSN_CMPGU, && case_sem_INSN_CMPGU },
65 { LM32BF_INSN_CMPGUI, && case_sem_INSN_CMPGUI },
66 { LM32BF_INSN_CMPNE, && case_sem_INSN_CMPNE },
67 { LM32BF_INSN_CMPNEI, && case_sem_INSN_CMPNEI },
68 { LM32BF_INSN_DIVU, && case_sem_INSN_DIVU },
69 { LM32BF_INSN_LB, && case_sem_INSN_LB },
70 { LM32BF_INSN_LBU, && case_sem_INSN_LBU },
71 { LM32BF_INSN_LH, && case_sem_INSN_LH },
72 { LM32BF_INSN_LHU, && case_sem_INSN_LHU },
73 { LM32BF_INSN_LW, && case_sem_INSN_LW },
74 { LM32BF_INSN_MODU, && case_sem_INSN_MODU },
75 { LM32BF_INSN_MUL, && case_sem_INSN_MUL },
76 { LM32BF_INSN_MULI, && case_sem_INSN_MULI },
77 { LM32BF_INSN_NOR, && case_sem_INSN_NOR },
78 { LM32BF_INSN_NORI, && case_sem_INSN_NORI },
79 { LM32BF_INSN_OR, && case_sem_INSN_OR },
80 { LM32BF_INSN_ORI, && case_sem_INSN_ORI },
81 { LM32BF_INSN_ORHII, && case_sem_INSN_ORHII },
82 { LM32BF_INSN_RCSR, && case_sem_INSN_RCSR },
83 { LM32BF_INSN_SB, && case_sem_INSN_SB },
84 { LM32BF_INSN_SEXTB, && case_sem_INSN_SEXTB },
85 { LM32BF_INSN_SEXTH, && case_sem_INSN_SEXTH },
86 { LM32BF_INSN_SH, && case_sem_INSN_SH },
87 { LM32BF_INSN_SL, && case_sem_INSN_SL },
88 { LM32BF_INSN_SLI, && case_sem_INSN_SLI },
89 { LM32BF_INSN_SR, && case_sem_INSN_SR },
90 { LM32BF_INSN_SRI, && case_sem_INSN_SRI },
91 { LM32BF_INSN_SRU, && case_sem_INSN_SRU },
92 { LM32BF_INSN_SRUI, && case_sem_INSN_SRUI },
93 { LM32BF_INSN_SUB, && case_sem_INSN_SUB },
94 { LM32BF_INSN_SW, && case_sem_INSN_SW },
95 { LM32BF_INSN_USER, && case_sem_INSN_USER },
96 { LM32BF_INSN_WCSR, && case_sem_INSN_WCSR },
97 { LM32BF_INSN_XOR, && case_sem_INSN_XOR },
98 { LM32BF_INSN_XORI, && case_sem_INSN_XORI },
99 { LM32BF_INSN_XNOR, && case_sem_INSN_XNOR },
100 { LM32BF_INSN_XNORI, && case_sem_INSN_XNORI },
101 { LM32BF_INSN_BREAK, && case_sem_INSN_BREAK },
102 { LM32BF_INSN_SCALL, && case_sem_INSN_SCALL },
103 { 0, 0 }
104 };
105 int i;
106
107 for (i = 0; labels[i].label != 0; ++i)
108 {
109#if FAST_P
110 CPU_IDESC (current_cpu) [labels[i].index].sem_fast_lab = labels[i].label;
111#else
112 CPU_IDESC (current_cpu) [labels[i].index].sem_full_lab = labels[i].label;
113#endif
114 }
115
116#undef DEFINE_LABELS
117#endif /* DEFINE_LABELS */
118
119#ifdef DEFINE_SWITCH
120
121/* If hyper-fast [well not unnecessarily slow] execution is selected, turn
122 off frills like tracing and profiling. */
123/* FIXME: A better way would be to have TRACE_RESULT check for something
124 that can cause it to be optimized out. Another way would be to emit
125 special handlers into the instruction "stream". */
126
127#if FAST_P
128#undef TRACE_RESULT
129#define TRACE_RESULT(cpu, abuf, name, type, val)
130#endif
131
132#undef GET_ATTR
133#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
134#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr)
135#else
136#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_/**/attr)
137#endif
138
139{
140
141#if WITH_SCACHE_PBB
142
143/* Branch to next handler without going around main loop. */
144#define NEXT(vpc) goto * SEM_ARGBUF (vpc) -> semantic.sem_case
145SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
146
147#else /* ! WITH_SCACHE_PBB */
148
149#define NEXT(vpc) BREAK (sem)
150#ifdef __GNUC__
151#if FAST_P
152 SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_fast_lab)
153#else
154 SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_full_lab)
155#endif
156#else
157 SWITCH (sem, SEM_ARGBUF (sc) -> idesc->num)
158#endif
159
160#endif /* ! WITH_SCACHE_PBB */
161
162 {
163
164 CASE (sem, INSN_X_INVALID) : /* --invalid-- */
165{
166 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
167 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
168#define FLD(f) abuf->fields.fmt_empty.f
169 int UNUSED written = 0;
170 IADDR UNUSED pc = abuf->addr;
171 vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
172
173 {
174 /* Update the recorded pc in the cpu state struct.
175 Only necessary for WITH_SCACHE case, but to avoid the
176 conditional compilation .... */
177 SET_H_PC (pc);
178 /* Virtual insns have zero size. Overwrite vpc with address of next insn
179 using the default-insn-bitsize spec. When executing insns in parallel
180 we may want to queue the fault and continue execution. */
181 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
182 vpc = sim_engine_invalid_insn (current_cpu, pc, vpc);
183 }
184
185#undef FLD
186}
187 NEXT (vpc);
188
189 CASE (sem, INSN_X_AFTER) : /* --after-- */
190{
191 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
192 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
193#define FLD(f) abuf->fields.fmt_empty.f
194 int UNUSED written = 0;
195 IADDR UNUSED pc = abuf->addr;
196 vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
197
198 {
199#if WITH_SCACHE_PBB_LM32BF
200 lm32bf_pbb_after (current_cpu, sem_arg);
201#endif
202 }
203
204#undef FLD
205}
206 NEXT (vpc);
207
208 CASE (sem, INSN_X_BEFORE) : /* --before-- */
209{
210 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
211 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
212#define FLD(f) abuf->fields.fmt_empty.f
213 int UNUSED written = 0;
214 IADDR UNUSED pc = abuf->addr;
215 vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
216
217 {
218#if WITH_SCACHE_PBB_LM32BF
219 lm32bf_pbb_before (current_cpu, sem_arg);
220#endif
221 }
222
223#undef FLD
224}
225 NEXT (vpc);
226
227 CASE (sem, INSN_X_CTI_CHAIN) : /* --cti-chain-- */
228{
229 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
230 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
231#define FLD(f) abuf->fields.fmt_empty.f
232 int UNUSED written = 0;
233 IADDR UNUSED pc = abuf->addr;
234 vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
235
236 {
237#if WITH_SCACHE_PBB_LM32BF
238#ifdef DEFINE_SWITCH
239 vpc = lm32bf_pbb_cti_chain (current_cpu, sem_arg,
240 pbb_br_type, pbb_br_npc);
241 BREAK (sem);
242#else
243 /* FIXME: Allow provision of explicit ifmt spec in insn spec. */
244 vpc = lm32bf_pbb_cti_chain (current_cpu, sem_arg,
245 CPU_PBB_BR_TYPE (current_cpu),
246 CPU_PBB_BR_NPC (current_cpu));
247#endif
248#endif
249 }
250
251#undef FLD
252}
253 NEXT (vpc);
254
255 CASE (sem, INSN_X_CHAIN) : /* --chain-- */
256{
257 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
258 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
259#define FLD(f) abuf->fields.fmt_empty.f
260 int UNUSED written = 0;
261 IADDR UNUSED pc = abuf->addr;
262 vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
263
264 {
265#if WITH_SCACHE_PBB_LM32BF
266 vpc = lm32bf_pbb_chain (current_cpu, sem_arg);
267#ifdef DEFINE_SWITCH
268 BREAK (sem);
269#endif
270#endif
271 }
272
273#undef FLD
274}
275 NEXT (vpc);
276
277 CASE (sem, INSN_X_BEGIN) : /* --begin-- */
278{
279 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
280 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
281#define FLD(f) abuf->fields.fmt_empty.f
282 int UNUSED written = 0;
283 IADDR UNUSED pc = abuf->addr;
284 vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
285
286 {
287#if WITH_SCACHE_PBB_LM32BF
288#if defined DEFINE_SWITCH || defined FAST_P
289 /* In the switch case FAST_P is a constant, allowing several optimizations
290 in any called inline functions. */
291 vpc = lm32bf_pbb_begin (current_cpu, FAST_P);
292#else
293#if 0 /* cgen engine can't handle dynamic fast/full switching yet. */
294 vpc = lm32bf_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu)));
295#else
296 vpc = lm32bf_pbb_begin (current_cpu, 0);
297#endif
298#endif
299#endif
300 }
301
302#undef FLD
303}
304 NEXT (vpc);
305
306 CASE (sem, INSN_ADD) : /* add $r2,$r0,$r1 */
307{
308 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
309 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
310#define FLD(f) abuf->fields.sfmt_user.f
311 int UNUSED written = 0;
312 IADDR UNUSED pc = abuf->addr;
313 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
314
315 {
316 SI opval = ADDSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));
317 CPU (h_gr[FLD (f_r2)]) = opval;
318 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
319 }
320
321#undef FLD
322}
323 NEXT (vpc);
324
325 CASE (sem, INSN_ADDI) : /* addi $r1,$r0,$imm */
326{
327 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
328 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
329#define FLD(f) abuf->fields.sfmt_addi.f
330 int UNUSED written = 0;
331 IADDR UNUSED pc = abuf->addr;
332 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
333
334 {
335 SI opval = ADDSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm))));
336 CPU (h_gr[FLD (f_r1)]) = opval;
337 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
338 }
339
340#undef FLD
341}
342 NEXT (vpc);
343
344 CASE (sem, INSN_AND) : /* and $r2,$r0,$r1 */
345{
346 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
347 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
348#define FLD(f) abuf->fields.sfmt_user.f
349 int UNUSED written = 0;
350 IADDR UNUSED pc = abuf->addr;
351 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
352
353 {
354 SI opval = ANDSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));
355 CPU (h_gr[FLD (f_r2)]) = opval;
356 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
357 }
358
359#undef FLD
360}
361 NEXT (vpc);
362
363 CASE (sem, INSN_ANDI) : /* andi $r1,$r0,$uimm */
364{
365 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
366 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
367#define FLD(f) abuf->fields.sfmt_andi.f
368 int UNUSED written = 0;
369 IADDR UNUSED pc = abuf->addr;
370 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
371
372 {
373 SI opval = ANDSI (CPU (h_gr[FLD (f_r0)]), ZEXTSISI (FLD (f_uimm)));
374 CPU (h_gr[FLD (f_r1)]) = opval;
375 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
376 }
377
378#undef FLD
379}
380 NEXT (vpc);
381
382 CASE (sem, INSN_ANDHII) : /* andhi $r1,$r0,$hi16 */
383{
384 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
385 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
386#define FLD(f) abuf->fields.sfmt_andi.f
387 int UNUSED written = 0;
388 IADDR UNUSED pc = abuf->addr;
389 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
390
391 {
392 SI opval = ANDSI (CPU (h_gr[FLD (f_r0)]), SLLSI (FLD (f_uimm), 16));
393 CPU (h_gr[FLD (f_r1)]) = opval;
394 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
395 }
396
397#undef FLD
398}
399 NEXT (vpc);
400
401 CASE (sem, INSN_B) : /* b $r0 */
402{
403 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
404 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
405#define FLD(f) abuf->fields.sfmt_be.f
406 int UNUSED written = 0;
407 IADDR UNUSED pc = abuf->addr;
408 SEM_BRANCH_INIT
409 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
410
411 {
412 USI opval = lm32bf_b_insn (current_cpu, CPU (h_gr[FLD (f_r0)]), FLD (f_r0));
413 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
414 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
415 }
416
417 SEM_BRANCH_FINI (vpc);
418#undef FLD
419}
420 NEXT (vpc);
421
422 CASE (sem, INSN_BI) : /* bi $call */
423{
424 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
425 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
426#define FLD(f) abuf->fields.sfmt_bi.f
427 int UNUSED written = 0;
428 IADDR UNUSED pc = abuf->addr;
429 SEM_BRANCH_INIT
430 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
431
432 {
433 USI opval = EXTSISI (FLD (i_call));
434 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
435 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
436 }
437
438 SEM_BRANCH_FINI (vpc);
439#undef FLD
440}
441 NEXT (vpc);
442
443 CASE (sem, INSN_BE) : /* be $r0,$r1,$branch */
444{
445 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
446 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
447#define FLD(f) abuf->fields.sfmt_be.f
448 int UNUSED written = 0;
449 IADDR UNUSED pc = abuf->addr;
450 SEM_BRANCH_INIT
451 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
452
453if (EQSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]))) {
454 {
455 USI opval = FLD (i_branch);
456 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
457 written |= (1 << 3);
458 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
459 }
460}
461
462 abuf->written = written;
463 SEM_BRANCH_FINI (vpc);
464#undef FLD
465}
466 NEXT (vpc);
467
468 CASE (sem, INSN_BG) : /* bg $r0,$r1,$branch */
469{
470 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
471 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
472#define FLD(f) abuf->fields.sfmt_be.f
473 int UNUSED written = 0;
474 IADDR UNUSED pc = abuf->addr;
475 SEM_BRANCH_INIT
476 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
477
478if (GTSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]))) {
479 {
480 USI opval = FLD (i_branch);
481 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
482 written |= (1 << 3);
483 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
484 }
485}
486
487 abuf->written = written;
488 SEM_BRANCH_FINI (vpc);
489#undef FLD
490}
491 NEXT (vpc);
492
493 CASE (sem, INSN_BGE) : /* bge $r0,$r1,$branch */
494{
495 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
496 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
497#define FLD(f) abuf->fields.sfmt_be.f
498 int UNUSED written = 0;
499 IADDR UNUSED pc = abuf->addr;
500 SEM_BRANCH_INIT
501 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
502
503if (GESI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]))) {
504 {
505 USI opval = FLD (i_branch);
506 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
507 written |= (1 << 3);
508 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
509 }
510}
511
512 abuf->written = written;
513 SEM_BRANCH_FINI (vpc);
514#undef FLD
515}
516 NEXT (vpc);
517
518 CASE (sem, INSN_BGEU) : /* bgeu $r0,$r1,$branch */
519{
520 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
521 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
522#define FLD(f) abuf->fields.sfmt_be.f
523 int UNUSED written = 0;
524 IADDR UNUSED pc = abuf->addr;
525 SEM_BRANCH_INIT
526 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
527
528if (GEUSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]))) {
529 {
530 USI opval = FLD (i_branch);
531 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
532 written |= (1 << 3);
533 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
534 }
535}
536
537 abuf->written = written;
538 SEM_BRANCH_FINI (vpc);
539#undef FLD
540}
541 NEXT (vpc);
542
543 CASE (sem, INSN_BGU) : /* bgu $r0,$r1,$branch */
544{
545 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
546 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
547#define FLD(f) abuf->fields.sfmt_be.f
548 int UNUSED written = 0;
549 IADDR UNUSED pc = abuf->addr;
550 SEM_BRANCH_INIT
551 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
552
553if (GTUSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]))) {
554 {
555 USI opval = FLD (i_branch);
556 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
557 written |= (1 << 3);
558 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
559 }
560}
561
562 abuf->written = written;
563 SEM_BRANCH_FINI (vpc);
564#undef FLD
565}
566 NEXT (vpc);
567
568 CASE (sem, INSN_BNE) : /* bne $r0,$r1,$branch */
569{
570 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
571 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
572#define FLD(f) abuf->fields.sfmt_be.f
573 int UNUSED written = 0;
574 IADDR UNUSED pc = abuf->addr;
575 SEM_BRANCH_INIT
576 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
577
578if (NESI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]))) {
579 {
580 USI opval = FLD (i_branch);
581 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
582 written |= (1 << 3);
583 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
584 }
585}
586
587 abuf->written = written;
588 SEM_BRANCH_FINI (vpc);
589#undef FLD
590}
591 NEXT (vpc);
592
593 CASE (sem, INSN_CALL) : /* call $r0 */
594{
595 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
596 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
597#define FLD(f) abuf->fields.sfmt_be.f
598 int UNUSED written = 0;
599 IADDR UNUSED pc = abuf->addr;
600 SEM_BRANCH_INIT
601 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
602
603{
604 {
605 SI opval = ADDSI (pc, 4);
606 CPU (h_gr[((UINT) 29)]) = opval;
607 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
608 }
609 {
610 USI opval = CPU (h_gr[FLD (f_r0)]);
611 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
612 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
613 }
614}
615
616 SEM_BRANCH_FINI (vpc);
617#undef FLD
618}
619 NEXT (vpc);
620
621 CASE (sem, INSN_CALLI) : /* calli $call */
622{
623 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
624 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
625#define FLD(f) abuf->fields.sfmt_bi.f
626 int UNUSED written = 0;
627 IADDR UNUSED pc = abuf->addr;
628 SEM_BRANCH_INIT
629 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
630
631{
632 {
633 SI opval = ADDSI (pc, 4);
634 CPU (h_gr[((UINT) 29)]) = opval;
635 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
636 }
637 {
638 USI opval = EXTSISI (FLD (i_call));
639 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
640 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
641 }
642}
643
644 SEM_BRANCH_FINI (vpc);
645#undef FLD
646}
647 NEXT (vpc);
648
649 CASE (sem, INSN_CMPE) : /* cmpe $r2,$r0,$r1 */
650{
651 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
652 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
653#define FLD(f) abuf->fields.sfmt_user.f
654 int UNUSED written = 0;
655 IADDR UNUSED pc = abuf->addr;
656 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
657
658 {
659 SI opval = EQSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));
660 CPU (h_gr[FLD (f_r2)]) = opval;
661 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
662 }
663
664#undef FLD
665}
666 NEXT (vpc);
667
668 CASE (sem, INSN_CMPEI) : /* cmpei $r1,$r0,$imm */
669{
670 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
671 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
672#define FLD(f) abuf->fields.sfmt_addi.f
673 int UNUSED written = 0;
674 IADDR UNUSED pc = abuf->addr;
675 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
676
677 {
678 SI opval = EQSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm))));
679 CPU (h_gr[FLD (f_r1)]) = opval;
680 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
681 }
682
683#undef FLD
684}
685 NEXT (vpc);
686
687 CASE (sem, INSN_CMPG) : /* cmpg $r2,$r0,$r1 */
688{
689 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
690 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
691#define FLD(f) abuf->fields.sfmt_user.f
692 int UNUSED written = 0;
693 IADDR UNUSED pc = abuf->addr;
694 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
695
696 {
697 SI opval = GTSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));
698 CPU (h_gr[FLD (f_r2)]) = opval;
699 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
700 }
701
702#undef FLD
703}
704 NEXT (vpc);
705
706 CASE (sem, INSN_CMPGI) : /* cmpgi $r1,$r0,$imm */
707{
708 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
709 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
710#define FLD(f) abuf->fields.sfmt_addi.f
711 int UNUSED written = 0;
712 IADDR UNUSED pc = abuf->addr;
713 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
714
715 {
716 SI opval = GTSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm))));
717 CPU (h_gr[FLD (f_r1)]) = opval;
718 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
719 }
720
721#undef FLD
722}
723 NEXT (vpc);
724
725 CASE (sem, INSN_CMPGE) : /* cmpge $r2,$r0,$r1 */
726{
727 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
728 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
729#define FLD(f) abuf->fields.sfmt_user.f
730 int UNUSED written = 0;
731 IADDR UNUSED pc = abuf->addr;
732 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
733
734 {
735 SI opval = GESI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));
736 CPU (h_gr[FLD (f_r2)]) = opval;
737 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
738 }
739
740#undef FLD
741}
742 NEXT (vpc);
743
744 CASE (sem, INSN_CMPGEI) : /* cmpgei $r1,$r0,$imm */
745{
746 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
747 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
748#define FLD(f) abuf->fields.sfmt_addi.f
749 int UNUSED written = 0;
750 IADDR UNUSED pc = abuf->addr;
751 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
752
753 {
754 SI opval = GESI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm))));
755 CPU (h_gr[FLD (f_r1)]) = opval;
756 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
757 }
758
759#undef FLD
760}
761 NEXT (vpc);
762
763 CASE (sem, INSN_CMPGEU) : /* cmpgeu $r2,$r0,$r1 */
764{
765 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
766 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
767#define FLD(f) abuf->fields.sfmt_user.f
768 int UNUSED written = 0;
769 IADDR UNUSED pc = abuf->addr;
770 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
771
772 {
773 SI opval = GEUSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));
774 CPU (h_gr[FLD (f_r2)]) = opval;
775 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
776 }
777
778#undef FLD
779}
780 NEXT (vpc);
781
782 CASE (sem, INSN_CMPGEUI) : /* cmpgeui $r1,$r0,$uimm */
783{
784 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
785 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
786#define FLD(f) abuf->fields.sfmt_andi.f
787 int UNUSED written = 0;
788 IADDR UNUSED pc = abuf->addr;
789 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
790
791 {
792 SI opval = GEUSI (CPU (h_gr[FLD (f_r0)]), ZEXTSISI (FLD (f_uimm)));
793 CPU (h_gr[FLD (f_r1)]) = opval;
794 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
795 }
796
797#undef FLD
798}
799 NEXT (vpc);
800
801 CASE (sem, INSN_CMPGU) : /* cmpgu $r2,$r0,$r1 */
802{
803 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
804 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
805#define FLD(f) abuf->fields.sfmt_user.f
806 int UNUSED written = 0;
807 IADDR UNUSED pc = abuf->addr;
808 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
809
810 {
811 SI opval = GTUSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));
812 CPU (h_gr[FLD (f_r2)]) = opval;
813 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
814 }
815
816#undef FLD
817}
818 NEXT (vpc);
819
820 CASE (sem, INSN_CMPGUI) : /* cmpgui $r1,$r0,$uimm */
821{
822 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
823 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
824#define FLD(f) abuf->fields.sfmt_andi.f
825 int UNUSED written = 0;
826 IADDR UNUSED pc = abuf->addr;
827 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
828
829 {
830 SI opval = GTUSI (CPU (h_gr[FLD (f_r0)]), ZEXTSISI (FLD (f_uimm)));
831 CPU (h_gr[FLD (f_r1)]) = opval;
832 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
833 }
834
835#undef FLD
836}
837 NEXT (vpc);
838
839 CASE (sem, INSN_CMPNE) : /* cmpne $r2,$r0,$r1 */
840{
841 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
842 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
843#define FLD(f) abuf->fields.sfmt_user.f
844 int UNUSED written = 0;
845 IADDR UNUSED pc = abuf->addr;
846 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
847
848 {
849 SI opval = NESI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));
850 CPU (h_gr[FLD (f_r2)]) = opval;
851 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
852 }
853
854#undef FLD
855}
856 NEXT (vpc);
857
858 CASE (sem, INSN_CMPNEI) : /* cmpnei $r1,$r0,$imm */
859{
860 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
861 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
862#define FLD(f) abuf->fields.sfmt_addi.f
863 int UNUSED written = 0;
864 IADDR UNUSED pc = abuf->addr;
865 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
866
867 {
868 SI opval = NESI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm))));
869 CPU (h_gr[FLD (f_r1)]) = opval;
870 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
871 }
872
873#undef FLD
874}
875 NEXT (vpc);
876
877 CASE (sem, INSN_DIVU) : /* divu $r2,$r0,$r1 */
878{
879 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
880 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
881#define FLD(f) abuf->fields.sfmt_user.f
882 int UNUSED written = 0;
883 IADDR UNUSED pc = abuf->addr;
884 SEM_BRANCH_INIT
885 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
886
887 {
888 USI opval = lm32bf_divu_insn (current_cpu, pc, FLD (f_r0), FLD (f_r1), FLD (f_r2));
889 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
890 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
891 }
892
893 SEM_BRANCH_FINI (vpc);
894#undef FLD
895}
896 NEXT (vpc);
897
898 CASE (sem, INSN_LB) : /* lb $r1,($r0+$imm) */
899{
900 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
901 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
902#define FLD(f) abuf->fields.sfmt_addi.f
903 int UNUSED written = 0;
904 IADDR UNUSED pc = abuf->addr;
905 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
906
907 {
908 SI opval = EXTQISI (GETMEMQI (current_cpu, pc, ADDSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm))))));
909 CPU (h_gr[FLD (f_r1)]) = opval;
910 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
911 }
912
913#undef FLD
914}
915 NEXT (vpc);
916
917 CASE (sem, INSN_LBU) : /* lbu $r1,($r0+$imm) */
918{
919 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
920 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
921#define FLD(f) abuf->fields.sfmt_addi.f
922 int UNUSED written = 0;
923 IADDR UNUSED pc = abuf->addr;
924 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
925
926 {
927 SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, ADDSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm))))));
928 CPU (h_gr[FLD (f_r1)]) = opval;
929 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
930 }
931
932#undef FLD
933}
934 NEXT (vpc);
935
936 CASE (sem, INSN_LH) : /* lh $r1,($r0+$imm) */
937{
938 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
939 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
940#define FLD(f) abuf->fields.sfmt_addi.f
941 int UNUSED written = 0;
942 IADDR UNUSED pc = abuf->addr;
943 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
944
945 {
946 SI opval = EXTHISI (GETMEMHI (current_cpu, pc, ADDSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm))))));
947 CPU (h_gr[FLD (f_r1)]) = opval;
948 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
949 }
950
951#undef FLD
952}
953 NEXT (vpc);
954
955 CASE (sem, INSN_LHU) : /* lhu $r1,($r0+$imm) */
956{
957 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
958 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
959#define FLD(f) abuf->fields.sfmt_addi.f
960 int UNUSED written = 0;
961 IADDR UNUSED pc = abuf->addr;
962 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
963
964 {
965 SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, ADDSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm))))));
966 CPU (h_gr[FLD (f_r1)]) = opval;
967 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
968 }
969
970#undef FLD
971}
972 NEXT (vpc);
973
974 CASE (sem, INSN_LW) : /* lw $r1,($r0+$imm) */
975{
976 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
977 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
978#define FLD(f) abuf->fields.sfmt_addi.f
979 int UNUSED written = 0;
980 IADDR UNUSED pc = abuf->addr;
981 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
982
983 {
984 SI opval = GETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm)))));
985 CPU (h_gr[FLD (f_r1)]) = opval;
986 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
987 }
988
989#undef FLD
990}
991 NEXT (vpc);
992
993 CASE (sem, INSN_MODU) : /* modu $r2,$r0,$r1 */
994{
995 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
996 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
997#define FLD(f) abuf->fields.sfmt_user.f
998 int UNUSED written = 0;
999 IADDR UNUSED pc = abuf->addr;
1000 SEM_BRANCH_INIT
1001 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1002
1003 {
1004 USI opval = lm32bf_modu_insn (current_cpu, pc, FLD (f_r0), FLD (f_r1), FLD (f_r2));
1005 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
1006 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
1007 }
1008
1009 SEM_BRANCH_FINI (vpc);
1010#undef FLD
1011}
1012 NEXT (vpc);
1013
1014 CASE (sem, INSN_MUL) : /* mul $r2,$r0,$r1 */
1015{
1016 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1017 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1018#define FLD(f) abuf->fields.sfmt_user.f
1019 int UNUSED written = 0;
1020 IADDR UNUSED pc = abuf->addr;
1021 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1022
1023 {
1024 SI opval = MULSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));
1025 CPU (h_gr[FLD (f_r2)]) = opval;
1026 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1027 }
1028
1029#undef FLD
1030}
1031 NEXT (vpc);
1032
1033 CASE (sem, INSN_MULI) : /* muli $r1,$r0,$imm */
1034{
1035 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1036 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1037#define FLD(f) abuf->fields.sfmt_addi.f
1038 int UNUSED written = 0;
1039 IADDR UNUSED pc = abuf->addr;
1040 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1041
1042 {
1043 SI opval = MULSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm))));
1044 CPU (h_gr[FLD (f_r1)]) = opval;
1045 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1046 }
1047
1048#undef FLD
1049}
1050 NEXT (vpc);
1051
1052 CASE (sem, INSN_NOR) : /* nor $r2,$r0,$r1 */
1053{
1054 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1055 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1056#define FLD(f) abuf->fields.sfmt_user.f
1057 int UNUSED written = 0;
1058 IADDR UNUSED pc = abuf->addr;
1059 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1060
1061 {
1062 SI opval = INVSI (ORSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)])));
1063 CPU (h_gr[FLD (f_r2)]) = opval;
1064 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1065 }
1066
1067#undef FLD
1068}
1069 NEXT (vpc);
1070
1071 CASE (sem, INSN_NORI) : /* nori $r1,$r0,$uimm */
1072{
1073 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1074 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1075#define FLD(f) abuf->fields.sfmt_andi.f
1076 int UNUSED written = 0;
1077 IADDR UNUSED pc = abuf->addr;
1078 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1079
1080 {
1081 SI opval = INVSI (ORSI (CPU (h_gr[FLD (f_r0)]), ZEXTSISI (FLD (f_uimm))));
1082 CPU (h_gr[FLD (f_r1)]) = opval;
1083 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1084 }
1085
1086#undef FLD
1087}
1088 NEXT (vpc);
1089
1090 CASE (sem, INSN_OR) : /* or $r2,$r0,$r1 */
1091{
1092 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1093 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1094#define FLD(f) abuf->fields.sfmt_user.f
1095 int UNUSED written = 0;
1096 IADDR UNUSED pc = abuf->addr;
1097 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1098
1099 {
1100 SI opval = ORSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));
1101 CPU (h_gr[FLD (f_r2)]) = opval;
1102 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1103 }
1104
1105#undef FLD
1106}
1107 NEXT (vpc);
1108
1109 CASE (sem, INSN_ORI) : /* ori $r1,$r0,$lo16 */
1110{
1111 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1112 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1113#define FLD(f) abuf->fields.sfmt_andi.f
1114 int UNUSED written = 0;
1115 IADDR UNUSED pc = abuf->addr;
1116 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1117
1118 {
1119 SI opval = ORSI (CPU (h_gr[FLD (f_r0)]), ZEXTSISI (FLD (f_uimm)));
1120 CPU (h_gr[FLD (f_r1)]) = opval;
1121 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1122 }
1123
1124#undef FLD
1125}
1126 NEXT (vpc);
1127
1128 CASE (sem, INSN_ORHII) : /* orhi $r1,$r0,$hi16 */
1129{
1130 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1131 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1132#define FLD(f) abuf->fields.sfmt_andi.f
1133 int UNUSED written = 0;
1134 IADDR UNUSED pc = abuf->addr;
1135 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1136
1137 {
1138 SI opval = ORSI (CPU (h_gr[FLD (f_r0)]), SLLSI (FLD (f_uimm), 16));
1139 CPU (h_gr[FLD (f_r1)]) = opval;
1140 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1141 }
1142
1143#undef FLD
1144}
1145 NEXT (vpc);
1146
1147 CASE (sem, INSN_RCSR) : /* rcsr $r2,$csr */
1148{
1149 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1150 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1151#define FLD(f) abuf->fields.sfmt_rcsr.f
1152 int UNUSED written = 0;
1153 IADDR UNUSED pc = abuf->addr;
1154 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1155
1156 {
1157 SI opval = CPU (h_csr[FLD (f_csr)]);
1158 CPU (h_gr[FLD (f_r2)]) = opval;
1159 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1160 }
1161
1162#undef FLD
1163}
1164 NEXT (vpc);
1165
1166 CASE (sem, INSN_SB) : /* sb ($r0+$imm),$r1 */
1167{
1168 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1169 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1170#define FLD(f) abuf->fields.sfmt_addi.f
1171 int UNUSED written = 0;
1172 IADDR UNUSED pc = abuf->addr;
1173 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1174
1175 {
1176 QI opval = CPU (h_gr[FLD (f_r1)]);
1177 SETMEMQI (current_cpu, pc, ADDSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm)))), opval);
1178 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
1179 }
1180
1181#undef FLD
1182}
1183 NEXT (vpc);
1184
1185 CASE (sem, INSN_SEXTB) : /* sextb $r2,$r0 */
1186{
1187 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1188 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1189#define FLD(f) abuf->fields.sfmt_user.f
1190 int UNUSED written = 0;
1191 IADDR UNUSED pc = abuf->addr;
1192 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1193
1194 {
1195 SI opval = EXTQISI (TRUNCSIQI (CPU (h_gr[FLD (f_r0)])));
1196 CPU (h_gr[FLD (f_r2)]) = opval;
1197 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1198 }
1199
1200#undef FLD
1201}
1202 NEXT (vpc);
1203
1204 CASE (sem, INSN_SEXTH) : /* sexth $r2,$r0 */
1205{
1206 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1207 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1208#define FLD(f) abuf->fields.sfmt_user.f
1209 int UNUSED written = 0;
1210 IADDR UNUSED pc = abuf->addr;
1211 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1212
1213 {
1214 SI opval = EXTHISI (TRUNCSIHI (CPU (h_gr[FLD (f_r0)])));
1215 CPU (h_gr[FLD (f_r2)]) = opval;
1216 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1217 }
1218
1219#undef FLD
1220}
1221 NEXT (vpc);
1222
1223 CASE (sem, INSN_SH) : /* sh ($r0+$imm),$r1 */
1224{
1225 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1226 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1227#define FLD(f) abuf->fields.sfmt_addi.f
1228 int UNUSED written = 0;
1229 IADDR UNUSED pc = abuf->addr;
1230 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1231
1232 {
1233 HI opval = CPU (h_gr[FLD (f_r1)]);
1234 SETMEMHI (current_cpu, pc, ADDSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm)))), opval);
1235 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
1236 }
1237
1238#undef FLD
1239}
1240 NEXT (vpc);
1241
1242 CASE (sem, INSN_SL) : /* sl $r2,$r0,$r1 */
1243{
1244 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1245 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1246#define FLD(f) abuf->fields.sfmt_user.f
1247 int UNUSED written = 0;
1248 IADDR UNUSED pc = abuf->addr;
1249 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1250
1251 {
1252 SI opval = SLLSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));
1253 CPU (h_gr[FLD (f_r2)]) = opval;
1254 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1255 }
1256
1257#undef FLD
1258}
1259 NEXT (vpc);
1260
1261 CASE (sem, INSN_SLI) : /* sli $r1,$r0,$imm */
1262{
1263 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1264 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1265#define FLD(f) abuf->fields.sfmt_addi.f
1266 int UNUSED written = 0;
1267 IADDR UNUSED pc = abuf->addr;
1268 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1269
1270 {
1271 SI opval = SLLSI (CPU (h_gr[FLD (f_r0)]), FLD (f_imm));
1272 CPU (h_gr[FLD (f_r1)]) = opval;
1273 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1274 }
1275
1276#undef FLD
1277}
1278 NEXT (vpc);
1279
1280 CASE (sem, INSN_SR) : /* sr $r2,$r0,$r1 */
1281{
1282 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1283 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1284#define FLD(f) abuf->fields.sfmt_user.f
1285 int UNUSED written = 0;
1286 IADDR UNUSED pc = abuf->addr;
1287 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1288
1289 {
1290 SI opval = SRASI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));
1291 CPU (h_gr[FLD (f_r2)]) = opval;
1292 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1293 }
1294
1295#undef FLD
1296}
1297 NEXT (vpc);
1298
1299 CASE (sem, INSN_SRI) : /* sri $r1,$r0,$imm */
1300{
1301 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1302 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1303#define FLD(f) abuf->fields.sfmt_addi.f
1304 int UNUSED written = 0;
1305 IADDR UNUSED pc = abuf->addr;
1306 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1307
1308 {
1309 SI opval = SRASI (CPU (h_gr[FLD (f_r0)]), FLD (f_imm));
1310 CPU (h_gr[FLD (f_r1)]) = opval;
1311 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1312 }
1313
1314#undef FLD
1315}
1316 NEXT (vpc);
1317
1318 CASE (sem, INSN_SRU) : /* sru $r2,$r0,$r1 */
1319{
1320 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1321 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1322#define FLD(f) abuf->fields.sfmt_user.f
1323 int UNUSED written = 0;
1324 IADDR UNUSED pc = abuf->addr;
1325 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1326
1327 {
1328 SI opval = SRLSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));
1329 CPU (h_gr[FLD (f_r2)]) = opval;
1330 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1331 }
1332
1333#undef FLD
1334}
1335 NEXT (vpc);
1336
1337 CASE (sem, INSN_SRUI) : /* srui $r1,$r0,$imm */
1338{
1339 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1340 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1341#define FLD(f) abuf->fields.sfmt_addi.f
1342 int UNUSED written = 0;
1343 IADDR UNUSED pc = abuf->addr;
1344 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1345
1346 {
1347 SI opval = SRLSI (CPU (h_gr[FLD (f_r0)]), FLD (f_imm));
1348 CPU (h_gr[FLD (f_r1)]) = opval;
1349 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1350 }
1351
1352#undef FLD
1353}
1354 NEXT (vpc);
1355
1356 CASE (sem, INSN_SUB) : /* sub $r2,$r0,$r1 */
1357{
1358 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1359 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1360#define FLD(f) abuf->fields.sfmt_user.f
1361 int UNUSED written = 0;
1362 IADDR UNUSED pc = abuf->addr;
1363 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1364
1365 {
1366 SI opval = SUBSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));
1367 CPU (h_gr[FLD (f_r2)]) = opval;
1368 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1369 }
1370
1371#undef FLD
1372}
1373 NEXT (vpc);
1374
1375 CASE (sem, INSN_SW) : /* sw ($r0+$imm),$r1 */
1376{
1377 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1378 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1379#define FLD(f) abuf->fields.sfmt_addi.f
1380 int UNUSED written = 0;
1381 IADDR UNUSED pc = abuf->addr;
1382 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1383
1384 {
1385 SI opval = CPU (h_gr[FLD (f_r1)]);
1386 SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm)))), opval);
1387 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
1388 }
1389
1390#undef FLD
1391}
1392 NEXT (vpc);
1393
1394 CASE (sem, INSN_USER) : /* user $r2,$r0,$r1,$user */
1395{
1396 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1397 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1398#define FLD(f) abuf->fields.sfmt_user.f
1399 int UNUSED written = 0;
1400 IADDR UNUSED pc = abuf->addr;
1401 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1402
1403 {
1404 SI opval = lm32bf_user_insn (current_cpu, CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]), FLD (f_user));
1405 CPU (h_gr[FLD (f_r2)]) = opval;
1406 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1407 }
1408
1409#undef FLD
1410}
1411 NEXT (vpc);
1412
1413 CASE (sem, INSN_WCSR) : /* wcsr $csr,$r1 */
1414{
1415 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1416 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1417#define FLD(f) abuf->fields.sfmt_wcsr.f
1418 int UNUSED written = 0;
1419 IADDR UNUSED pc = abuf->addr;
1420 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1421
1422lm32bf_wcsr_insn (current_cpu, FLD (f_csr), CPU (h_gr[FLD (f_r1)]));
1423
1424#undef FLD
1425}
1426 NEXT (vpc);
1427
1428 CASE (sem, INSN_XOR) : /* xor $r2,$r0,$r1 */
1429{
1430 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1431 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1432#define FLD(f) abuf->fields.sfmt_user.f
1433 int UNUSED written = 0;
1434 IADDR UNUSED pc = abuf->addr;
1435 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1436
1437 {
1438 SI opval = XORSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));
1439 CPU (h_gr[FLD (f_r2)]) = opval;
1440 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1441 }
1442
1443#undef FLD
1444}
1445 NEXT (vpc);
1446
1447 CASE (sem, INSN_XORI) : /* xori $r1,$r0,$uimm */
1448{
1449 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1450 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1451#define FLD(f) abuf->fields.sfmt_andi.f
1452 int UNUSED written = 0;
1453 IADDR UNUSED pc = abuf->addr;
1454 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1455
1456 {
1457 SI opval = XORSI (CPU (h_gr[FLD (f_r0)]), ZEXTSISI (FLD (f_uimm)));
1458 CPU (h_gr[FLD (f_r1)]) = opval;
1459 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1460 }
1461
1462#undef FLD
1463}
1464 NEXT (vpc);
1465
1466 CASE (sem, INSN_XNOR) : /* xnor $r2,$r0,$r1 */
1467{
1468 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1469 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1470#define FLD(f) abuf->fields.sfmt_user.f
1471 int UNUSED written = 0;
1472 IADDR UNUSED pc = abuf->addr;
1473 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1474
1475 {
1476 SI opval = INVSI (XORSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)])));
1477 CPU (h_gr[FLD (f_r2)]) = opval;
1478 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1479 }
1480
1481#undef FLD
1482}
1483 NEXT (vpc);
1484
1485 CASE (sem, INSN_XNORI) : /* xnori $r1,$r0,$uimm */
1486{
1487 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1488 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1489#define FLD(f) abuf->fields.sfmt_andi.f
1490 int UNUSED written = 0;
1491 IADDR UNUSED pc = abuf->addr;
1492 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1493
1494 {
1495 SI opval = INVSI (XORSI (CPU (h_gr[FLD (f_r0)]), ZEXTSISI (FLD (f_uimm))));
1496 CPU (h_gr[FLD (f_r1)]) = opval;
1497 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1498 }
1499
1500#undef FLD
1501}
1502 NEXT (vpc);
1503
1504 CASE (sem, INSN_BREAK) : /* break */
1505{
1506 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1507 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1508#define FLD(f) abuf->fields.fmt_empty.f
1509 int UNUSED written = 0;
1510 IADDR UNUSED pc = abuf->addr;
1511 SEM_BRANCH_INIT
1512 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1513
1514 {
1515 USI opval = lm32bf_break_insn (current_cpu, pc);
1516 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
1517 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
1518 }
1519
1520 SEM_BRANCH_FINI (vpc);
1521#undef FLD
1522}
1523 NEXT (vpc);
1524
1525 CASE (sem, INSN_SCALL) : /* scall */
1526{
1527 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1528 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1529#define FLD(f) abuf->fields.fmt_empty.f
1530 int UNUSED written = 0;
1531 IADDR UNUSED pc = abuf->addr;
1532 SEM_BRANCH_INIT
1533 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1534
1535 {
1536 USI opval = lm32bf_scall_insn (current_cpu, pc);
1537 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
1538 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
1539 }
1540
1541 SEM_BRANCH_FINI (vpc);
1542#undef FLD
1543}
1544 NEXT (vpc);
1545
1546
1547 }
1548 ENDSWITCH (sem) /* End of semantic switch. */
1549
1550 /* At this point `vpc' contains the next insn to execute. */
1551}
1552
1553#undef DEFINE_SWITCH
1554#endif /* DEFINE_SWITCH */
GDB Binutils - Deliverables
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