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2009-10-16 H.J. Lu <hongjiu.lu@intel.com>
[deliverable/binutils-gdb.git] / sim / lm32 / sem.c
CommitLineData
c28c63d8
JB		 1/* Simulator instruction semantics for lm32bf.
2
3THIS FILE IS MACHINE GENERATED WITH CGEN.
4
5Copyright 1996-2005 Free Software Foundation, Inc.
6
7This file is part of the GNU simulators.
8
9This program is free software; you can redistribute it and/or modify
10it under the terms of the GNU General Public License as published by
11the Free Software Foundation; either version 2, or (at your option)
12any later version.
13
14This program is distributed in the hope that it will be useful,
15but WITHOUT ANY WARRANTY; without even the implied warranty of
16MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17GNU General Public License for more details.
18
19You should have received a copy of the GNU General Public License along
20with this program; if not, write to the Free Software Foundation, Inc.,
2151 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
22
23*/
24
25#define WANT_CPU lm32bf
26#define WANT_CPU_LM32BF
27
28#include "sim-main.h"
29#include "cgen-mem.h"
30#include "cgen-ops.h"
31
32#undef GET_ATTR
33#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
34#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr)
35#else
36#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_/**/attr)
37#endif
38
39/* This is used so that we can compile two copies of the semantic code,
40 one with full feature support and one without that runs fast(er).
41 FAST_P, when desired, is defined on the command line, -DFAST_P=1. */
42#if FAST_P
43#define SEM_FN_NAME(cpu,fn) XCONCAT3 (cpu,_semf_,fn)
44#undef TRACE_RESULT
45#define TRACE_RESULT(cpu, abuf, name, type, val)
46#else
47#define SEM_FN_NAME(cpu,fn) XCONCAT3 (cpu,_sem_,fn)
48#endif
49
50/* x-invalid: --invalid-- */
51
52static SEM_PC
53SEM_FN_NAME (lm32bf,x_invalid) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
54{
55#define FLD(f) abuf->fields.fmt_empty.f
56 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
57 int UNUSED written = 0;
58 IADDR UNUSED pc = abuf->addr;
59 SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
60
61 {
62 /* Update the recorded pc in the cpu state struct.
63 Only necessary for WITH_SCACHE case, but to avoid the
64 conditional compilation .... */
65 SET_H_PC (pc);
66 /* Virtual insns have zero size. Overwrite vpc with address of next insn
67 using the default-insn-bitsize spec. When executing insns in parallel
68 we may want to queue the fault and continue execution. */
69 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
70 vpc = sim_engine_invalid_insn (current_cpu, pc, vpc);
71 }
72
73 return vpc;
74#undef FLD
75}
76
77/* x-after: --after-- */
78
79static SEM_PC
80SEM_FN_NAME (lm32bf,x_after) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
81{
82#define FLD(f) abuf->fields.fmt_empty.f
83 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
84 int UNUSED written = 0;
85 IADDR UNUSED pc = abuf->addr;
86 SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
87
88 {
89#if WITH_SCACHE_PBB_LM32BF
90 lm32bf_pbb_after (current_cpu, sem_arg);
91#endif
92 }
93
94 return vpc;
95#undef FLD
96}
97
98/* x-before: --before-- */
99
100static SEM_PC
101SEM_FN_NAME (lm32bf,x_before) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
102{
103#define FLD(f) abuf->fields.fmt_empty.f
104 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
105 int UNUSED written = 0;
106 IADDR UNUSED pc = abuf->addr;
107 SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
108
109 {
110#if WITH_SCACHE_PBB_LM32BF
111 lm32bf_pbb_before (current_cpu, sem_arg);
112#endif
113 }
114
115 return vpc;
116#undef FLD
117}
118
119/* x-cti-chain: --cti-chain-- */
120
121static SEM_PC
122SEM_FN_NAME (lm32bf,x_cti_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
123{
124#define FLD(f) abuf->fields.fmt_empty.f
125 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
126 int UNUSED written = 0;
127 IADDR UNUSED pc = abuf->addr;
128 SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
129
130 {
131#if WITH_SCACHE_PBB_LM32BF
132#ifdef DEFINE_SWITCH
133 vpc = lm32bf_pbb_cti_chain (current_cpu, sem_arg,
134 pbb_br_type, pbb_br_npc);
135 BREAK (sem);
136#else
137 /* FIXME: Allow provision of explicit ifmt spec in insn spec. */
138 vpc = lm32bf_pbb_cti_chain (current_cpu, sem_arg,
139 CPU_PBB_BR_TYPE (current_cpu),
140 CPU_PBB_BR_NPC (current_cpu));
141#endif
142#endif
143 }
144
145 return vpc;
146#undef FLD
147}
148
149/* x-chain: --chain-- */
150
151static SEM_PC
152SEM_FN_NAME (lm32bf,x_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
153{
154#define FLD(f) abuf->fields.fmt_empty.f
155 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
156 int UNUSED written = 0;
157 IADDR UNUSED pc = abuf->addr;
158 SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
159
160 {
161#if WITH_SCACHE_PBB_LM32BF
162 vpc = lm32bf_pbb_chain (current_cpu, sem_arg);
163#ifdef DEFINE_SWITCH
164 BREAK (sem);
165#endif
166#endif
167 }
168
169 return vpc;
170#undef FLD
171}
172
173/* x-begin: --begin-- */
174
175static SEM_PC
176SEM_FN_NAME (lm32bf,x_begin) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
177{
178#define FLD(f) abuf->fields.fmt_empty.f
179 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
180 int UNUSED written = 0;
181 IADDR UNUSED pc = abuf->addr;
182 SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
183
184 {
185#if WITH_SCACHE_PBB_LM32BF
186#if defined DEFINE_SWITCH || defined FAST_P
187 /* In the switch case FAST_P is a constant, allowing several optimizations
188 in any called inline functions. */
189 vpc = lm32bf_pbb_begin (current_cpu, FAST_P);
190#else
191#if 0 /* cgen engine can't handle dynamic fast/full switching yet. */
192 vpc = lm32bf_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu)));
193#else
194 vpc = lm32bf_pbb_begin (current_cpu, 0);
195#endif
196#endif
197#endif
198 }
199
200 return vpc;
201#undef FLD
202}
203
204/* add: add $r2,$r0,$r1 */
205
206static SEM_PC
207SEM_FN_NAME (lm32bf,add) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
208{
209#define FLD(f) abuf->fields.sfmt_user.f
210 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
211 int UNUSED written = 0;
212 IADDR UNUSED pc = abuf->addr;
213 SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
214
215 {
216 SI opval = ADDSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));
217 CPU (h_gr[FLD (f_r2)]) = opval;
218 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
219 }
220
221 return vpc;
222#undef FLD
223}
224
225/* addi: addi $r1,$r0,$imm */
226
227static SEM_PC
228SEM_FN_NAME (lm32bf,addi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
229{
230#define FLD(f) abuf->fields.sfmt_addi.f
231 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
232 int UNUSED written = 0;
233 IADDR UNUSED pc = abuf->addr;
234 SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
235
236 {
237 SI opval = ADDSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm))));
238 CPU (h_gr[FLD (f_r1)]) = opval;
239 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
240 }
241
242 return vpc;
243#undef FLD
244}
245
246/* and: and $r2,$r0,$r1 */
247
248static SEM_PC
249SEM_FN_NAME (lm32bf,and) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
250{
251#define FLD(f) abuf->fields.sfmt_user.f
252 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
253 int UNUSED written = 0;
254 IADDR UNUSED pc = abuf->addr;
255 SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
256
257 {
258 SI opval = ANDSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));
259 CPU (h_gr[FLD (f_r2)]) = opval;
260 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
261 }
262
263 return vpc;
264#undef FLD
265}
266
267/* andi: andi $r1,$r0,$uimm */
268
269static SEM_PC
270SEM_FN_NAME (lm32bf,andi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
271{
272#define FLD(f) abuf->fields.sfmt_andi.f
273 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
274 int UNUSED written = 0;
275 IADDR UNUSED pc = abuf->addr;
276 SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
277
278 {
279 SI opval = ANDSI (CPU (h_gr[FLD (f_r0)]), ZEXTSISI (FLD (f_uimm)));
280 CPU (h_gr[FLD (f_r1)]) = opval;
281 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
282 }
283
284 return vpc;
285#undef FLD
286}
287
288/* andhii: andhi $r1,$r0,$hi16 */
289
290static SEM_PC
291SEM_FN_NAME (lm32bf,andhii) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
292{
293#define FLD(f) abuf->fields.sfmt_andi.f
294 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
295 int UNUSED written = 0;
296 IADDR UNUSED pc = abuf->addr;
297 SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
298
299 {
300 SI opval = ANDSI (CPU (h_gr[FLD (f_r0)]), SLLSI (FLD (f_uimm), 16));
301 CPU (h_gr[FLD (f_r1)]) = opval;
302 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
303 }
304
305 return vpc;
306#undef FLD
307}
308
309/* b: b $r0 */
310
311static SEM_PC
312SEM_FN_NAME (lm32bf,b) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
313{
314#define FLD(f) abuf->fields.sfmt_be.f
315 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
316 int UNUSED written = 0;
317 IADDR UNUSED pc = abuf->addr;
318 SEM_BRANCH_INIT
319 SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
320
321 {
322 USI opval = lm32bf_b_insn (current_cpu, CPU (h_gr[FLD (f_r0)]), FLD (f_r0));
323 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
324 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
325 }
326
327 SEM_BRANCH_FINI (vpc);
328 return vpc;
329#undef FLD
330}
331
332/* bi: bi $call */
333
334static SEM_PC
335SEM_FN_NAME (lm32bf,bi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
336{
337#define FLD(f) abuf->fields.sfmt_bi.f
338 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
339 int UNUSED written = 0;
340 IADDR UNUSED pc = abuf->addr;
341 SEM_BRANCH_INIT
342 SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
343
344 {
345 USI opval = EXTSISI (FLD (i_call));
346 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
347 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
348 }
349
350 SEM_BRANCH_FINI (vpc);
351 return vpc;
352#undef FLD
353}
354
355/* be: be $r0,$r1,$branch */
356
357static SEM_PC
358SEM_FN_NAME (lm32bf,be) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
359{
360#define FLD(f) abuf->fields.sfmt_be.f
361 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
362 int UNUSED written = 0;
363 IADDR UNUSED pc = abuf->addr;
364 SEM_BRANCH_INIT
365 SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
366
367if (EQSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]))) {
368 {
369 USI opval = FLD (i_branch);
370 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
371 written |= (1 << 3);
372 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
373 }
374}
375
376 abuf->written = written;
377 SEM_BRANCH_FINI (vpc);
378 return vpc;
379#undef FLD
380}
381
382/* bg: bg $r0,$r1,$branch */
383
384static SEM_PC
385SEM_FN_NAME (lm32bf,bg) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
386{
387#define FLD(f) abuf->fields.sfmt_be.f
388 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
389 int UNUSED written = 0;
390 IADDR UNUSED pc = abuf->addr;
391 SEM_BRANCH_INIT
392 SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
393
394if (GTSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]))) {
395 {
396 USI opval = FLD (i_branch);
397 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
398 written |= (1 << 3);
399 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
400 }
401}
402
403 abuf->written = written;
404 SEM_BRANCH_FINI (vpc);
405 return vpc;
406#undef FLD
407}
408
409/* bge: bge $r0,$r1,$branch */
410
411static SEM_PC
412SEM_FN_NAME (lm32bf,bge) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
413{
414#define FLD(f) abuf->fields.sfmt_be.f
415 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
416 int UNUSED written = 0;
417 IADDR UNUSED pc = abuf->addr;
418 SEM_BRANCH_INIT
419 SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
420
421if (GESI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]))) {
422 {
423 USI opval = FLD (i_branch);
424 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
425 written |= (1 << 3);
426 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
427 }
428}
429
430 abuf->written = written;
431 SEM_BRANCH_FINI (vpc);
432 return vpc;
433#undef FLD
434}
435
436/* bgeu: bgeu $r0,$r1,$branch */
437
438static SEM_PC
439SEM_FN_NAME (lm32bf,bgeu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
440{
441#define FLD(f) abuf->fields.sfmt_be.f
442 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
443 int UNUSED written = 0;
444 IADDR UNUSED pc = abuf->addr;
445 SEM_BRANCH_INIT
446 SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
447
448if (GEUSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]))) {
449 {
450 USI opval = FLD (i_branch);
451 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
452 written |= (1 << 3);
453 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
454 }
455}
456
457 abuf->written = written;
458 SEM_BRANCH_FINI (vpc);
459 return vpc;
460#undef FLD
461}
462
463/* bgu: bgu $r0,$r1,$branch */
464
465static SEM_PC
466SEM_FN_NAME (lm32bf,bgu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
467{
468#define FLD(f) abuf->fields.sfmt_be.f
469 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
470 int UNUSED written = 0;
471 IADDR UNUSED pc = abuf->addr;
472 SEM_BRANCH_INIT
473 SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
474
475if (GTUSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]))) {
476 {
477 USI opval = FLD (i_branch);
478 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
479 written |= (1 << 3);
480 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
481 }
482}
483
484 abuf->written = written;
485 SEM_BRANCH_FINI (vpc);
486 return vpc;
487#undef FLD
488}
489
490/* bne: bne $r0,$r1,$branch */
491
492static SEM_PC
493SEM_FN_NAME (lm32bf,bne) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
494{
495#define FLD(f) abuf->fields.sfmt_be.f
496 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
497 int UNUSED written = 0;
498 IADDR UNUSED pc = abuf->addr;
499 SEM_BRANCH_INIT
500 SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
501
502if (NESI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]))) {
503 {
504 USI opval = FLD (i_branch);
505 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
506 written |= (1 << 3);
507 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
508 }
509}
510
511 abuf->written = written;
512 SEM_BRANCH_FINI (vpc);
513 return vpc;
514#undef FLD
515}
516
517/* call: call $r0 */
518
519static SEM_PC
520SEM_FN_NAME (lm32bf,call) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
521{
522#define FLD(f) abuf->fields.sfmt_be.f
523 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
524 int UNUSED written = 0;
525 IADDR UNUSED pc = abuf->addr;
526 SEM_BRANCH_INIT
527 SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
528
529{
530 {
531 SI opval = ADDSI (pc, 4);
532 CPU (h_gr[((UINT) 29)]) = opval;
533 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
534 }
535 {
536 USI opval = CPU (h_gr[FLD (f_r0)]);
537 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
538 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
539 }
540}
541
542 SEM_BRANCH_FINI (vpc);
543 return vpc;
544#undef FLD
545}
546
547/* calli: calli $call */
548
549static SEM_PC
550SEM_FN_NAME (lm32bf,calli) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
551{
552#define FLD(f) abuf->fields.sfmt_bi.f
553 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
554 int UNUSED written = 0;
555 IADDR UNUSED pc = abuf->addr;
556 SEM_BRANCH_INIT
557 SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
558
559{
560 {
561 SI opval = ADDSI (pc, 4);
562 CPU (h_gr[((UINT) 29)]) = opval;
563 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
564 }
565 {
566 USI opval = EXTSISI (FLD (i_call));
567 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
568 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
569 }
570}
571
572 SEM_BRANCH_FINI (vpc);
573 return vpc;
574#undef FLD
575}
576
577/* cmpe: cmpe $r2,$r0,$r1 */
578
579static SEM_PC
580SEM_FN_NAME (lm32bf,cmpe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
581{
582#define FLD(f) abuf->fields.sfmt_user.f
583 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
584 int UNUSED written = 0;
585 IADDR UNUSED pc = abuf->addr;
586 SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
587
588 {
589 SI opval = EQSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));
590 CPU (h_gr[FLD (f_r2)]) = opval;
591 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
592 }
593
594 return vpc;
595#undef FLD
596}
597
598/* cmpei: cmpei $r1,$r0,$imm */
599
600static SEM_PC
601SEM_FN_NAME (lm32bf,cmpei) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
602{
603#define FLD(f) abuf->fields.sfmt_addi.f
604 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
605 int UNUSED written = 0;
606 IADDR UNUSED pc = abuf->addr;
607 SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
608
609 {
610 SI opval = EQSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm))));
611 CPU (h_gr[FLD (f_r1)]) = opval;
612 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
613 }
614
615 return vpc;
616#undef FLD
617}
618
619/* cmpg: cmpg $r2,$r0,$r1 */
620
621static SEM_PC
622SEM_FN_NAME (lm32bf,cmpg) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
623{
624#define FLD(f) abuf->fields.sfmt_user.f
625 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
626 int UNUSED written = 0;
627 IADDR UNUSED pc = abuf->addr;
628 SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
629
630 {
631 SI opval = GTSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));
632 CPU (h_gr[FLD (f_r2)]) = opval;
633 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
634 }
635
636 return vpc;
637#undef FLD
638}
639
640/* cmpgi: cmpgi $r1,$r0,$imm */
641
642static SEM_PC
643SEM_FN_NAME (lm32bf,cmpgi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
644{
645#define FLD(f) abuf->fields.sfmt_addi.f
646 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
647 int UNUSED written = 0;
648 IADDR UNUSED pc = abuf->addr;
649 SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
650
651 {
652 SI opval = GTSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm))));
653 CPU (h_gr[FLD (f_r1)]) = opval;
654 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
655 }
656
657 return vpc;
658#undef FLD
659}
660
661/* cmpge: cmpge $r2,$r0,$r1 */
662
663static SEM_PC
664SEM_FN_NAME (lm32bf,cmpge) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
665{
666#define FLD(f) abuf->fields.sfmt_user.f
667 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
668 int UNUSED written = 0;
669 IADDR UNUSED pc = abuf->addr;
670 SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
671
672 {
673 SI opval = GESI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));
674 CPU (h_gr[FLD (f_r2)]) = opval;
675 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
676 }
677
678 return vpc;
679#undef FLD
680}
681
682/* cmpgei: cmpgei $r1,$r0,$imm */
683
684static SEM_PC
685SEM_FN_NAME (lm32bf,cmpgei) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
686{
687#define FLD(f) abuf->fields.sfmt_addi.f
688 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
689 int UNUSED written = 0;
690 IADDR UNUSED pc = abuf->addr;
691 SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
692
693 {
694 SI opval = GESI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm))));
695 CPU (h_gr[FLD (f_r1)]) = opval;
696 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
697 }
698
699 return vpc;
700#undef FLD
701}
702
703/* cmpgeu: cmpgeu $r2,$r0,$r1 */
704
705static SEM_PC
706SEM_FN_NAME (lm32bf,cmpgeu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
707{
708#define FLD(f) abuf->fields.sfmt_user.f
709 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
710 int UNUSED written = 0;
711 IADDR UNUSED pc = abuf->addr;
712 SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
713
714 {
715 SI opval = GEUSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));
716 CPU (h_gr[FLD (f_r2)]) = opval;
717 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
718 }
719
720 return vpc;
721#undef FLD
722}
723
724/* cmpgeui: cmpgeui $r1,$r0,$uimm */
725
726static SEM_PC
727SEM_FN_NAME (lm32bf,cmpgeui) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
728{
729#define FLD(f) abuf->fields.sfmt_andi.f
730 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
731 int UNUSED written = 0;
732 IADDR UNUSED pc = abuf->addr;
733 SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
734
735 {
736 SI opval = GEUSI (CPU (h_gr[FLD (f_r0)]), ZEXTSISI (FLD (f_uimm)));
737 CPU (h_gr[FLD (f_r1)]) = opval;
738 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
739 }
740
741 return vpc;
742#undef FLD
743}
744
745/* cmpgu: cmpgu $r2,$r0,$r1 */
746
747static SEM_PC
748SEM_FN_NAME (lm32bf,cmpgu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
749{
750#define FLD(f) abuf->fields.sfmt_user.f
751 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
752 int UNUSED written = 0;
753 IADDR UNUSED pc = abuf->addr;
754 SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
755
756 {
757 SI opval = GTUSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));
758 CPU (h_gr[FLD (f_r2)]) = opval;
759 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
760 }
761
762 return vpc;
763#undef FLD
764}
765
766/* cmpgui: cmpgui $r1,$r0,$uimm */
767
768static SEM_PC
769SEM_FN_NAME (lm32bf,cmpgui) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
770{
771#define FLD(f) abuf->fields.sfmt_andi.f
772 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
773 int UNUSED written = 0;
774 IADDR UNUSED pc = abuf->addr;
775 SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
776
777 {
778 SI opval = GTUSI (CPU (h_gr[FLD (f_r0)]), ZEXTSISI (FLD (f_uimm)));
779 CPU (h_gr[FLD (f_r1)]) = opval;
780 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
781 }
782
783 return vpc;
784#undef FLD
785}
786
787/* cmpne: cmpne $r2,$r0,$r1 */
788
789static SEM_PC
790SEM_FN_NAME (lm32bf,cmpne) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
791{
792#define FLD(f) abuf->fields.sfmt_user.f
793 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
794 int UNUSED written = 0;
795 IADDR UNUSED pc = abuf->addr;
796 SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
797
798 {
799 SI opval = NESI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));
800 CPU (h_gr[FLD (f_r2)]) = opval;
801 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
802 }
803
804 return vpc;
805#undef FLD
806}
807
808/* cmpnei: cmpnei $r1,$r0,$imm */
809
810static SEM_PC
811SEM_FN_NAME (lm32bf,cmpnei) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
812{
813#define FLD(f) abuf->fields.sfmt_addi.f
814 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
815 int UNUSED written = 0;
816 IADDR UNUSED pc = abuf->addr;
817 SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
818
819 {
820 SI opval = NESI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm))));
821 CPU (h_gr[FLD (f_r1)]) = opval;
822 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
823 }
824
825 return vpc;
826#undef FLD
827}
828
829/* divu: divu $r2,$r0,$r1 */
830
831static SEM_PC
832SEM_FN_NAME (lm32bf,divu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
833{
834#define FLD(f) abuf->fields.sfmt_user.f
835 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
836 int UNUSED written = 0;
837 IADDR UNUSED pc = abuf->addr;
838 SEM_BRANCH_INIT
839 SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
840
841 {
842 USI opval = lm32bf_divu_insn (current_cpu, pc, FLD (f_r0), FLD (f_r1), FLD (f_r2));
843 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
844 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
845 }
846
847 SEM_BRANCH_FINI (vpc);
848 return vpc;
849#undef FLD
850}
851
852/* lb: lb $r1,($r0+$imm) */
853
854static SEM_PC
855SEM_FN_NAME (lm32bf,lb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
856{
857#define FLD(f) abuf->fields.sfmt_addi.f
858 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
859 int UNUSED written = 0;
860 IADDR UNUSED pc = abuf->addr;
861 SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
862
863 {
864 SI opval = EXTQISI (GETMEMQI (current_cpu, pc, ADDSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm))))));
865 CPU (h_gr[FLD (f_r1)]) = opval;
866 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
867 }
868
869 return vpc;
870#undef FLD
871}
872
873/* lbu: lbu $r1,($r0+$imm) */
874
875static SEM_PC
876SEM_FN_NAME (lm32bf,lbu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
877{
878#define FLD(f) abuf->fields.sfmt_addi.f
879 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
880 int UNUSED written = 0;
881 IADDR UNUSED pc = abuf->addr;
882 SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
883
884 {
885 SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, ADDSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm))))));
886 CPU (h_gr[FLD (f_r1)]) = opval;
887 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
888 }
889
890 return vpc;
891#undef FLD
892}
893
894/* lh: lh $r1,($r0+$imm) */
895
896static SEM_PC
897SEM_FN_NAME (lm32bf,lh) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
898{
899#define FLD(f) abuf->fields.sfmt_addi.f
900 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
901 int UNUSED written = 0;
902 IADDR UNUSED pc = abuf->addr;
903 SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
904
905 {
906 SI opval = EXTHISI (GETMEMHI (current_cpu, pc, ADDSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm))))));
907 CPU (h_gr[FLD (f_r1)]) = opval;
908 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
909 }
910
911 return vpc;
912#undef FLD
913}
914
915/* lhu: lhu $r1,($r0+$imm) */
916
917static SEM_PC
918SEM_FN_NAME (lm32bf,lhu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
919{
920#define FLD(f) abuf->fields.sfmt_addi.f
921 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
922 int UNUSED written = 0;
923 IADDR UNUSED pc = abuf->addr;
924 SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
925
926 {
927 SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, ADDSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm))))));
928 CPU (h_gr[FLD (f_r1)]) = opval;
929 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
930 }
931
932 return vpc;
933#undef FLD
934}
935
936/* lw: lw $r1,($r0+$imm) */
937
938static SEM_PC
939SEM_FN_NAME (lm32bf,lw) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
940{
941#define FLD(f) abuf->fields.sfmt_addi.f
942 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
943 int UNUSED written = 0;
944 IADDR UNUSED pc = abuf->addr;
945 SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
946
947 {
948 SI opval = GETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm)))));
949 CPU (h_gr[FLD (f_r1)]) = opval;
950 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
951 }
952
953 return vpc;
954#undef FLD
955}
956
957/* modu: modu $r2,$r0,$r1 */
958
959static SEM_PC
960SEM_FN_NAME (lm32bf,modu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
961{
962#define FLD(f) abuf->fields.sfmt_user.f
963 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
964 int UNUSED written = 0;
965 IADDR UNUSED pc = abuf->addr;
966 SEM_BRANCH_INIT
967 SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
968
969 {
970 USI opval = lm32bf_modu_insn (current_cpu, pc, FLD (f_r0), FLD (f_r1), FLD (f_r2));
971 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
972 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
973 }
974
975 SEM_BRANCH_FINI (vpc);
976 return vpc;
977#undef FLD
978}
979
980/* mul: mul $r2,$r0,$r1 */
981
982static SEM_PC
983SEM_FN_NAME (lm32bf,mul) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
984{
985#define FLD(f) abuf->fields.sfmt_user.f
986 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
987 int UNUSED written = 0;
988 IADDR UNUSED pc = abuf->addr;
989 SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
990
991 {
992 SI opval = MULSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));
993 CPU (h_gr[FLD (f_r2)]) = opval;
994 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
995 }
996
997 return vpc;
998#undef FLD
999}
1000
1001/* muli: muli $r1,$r0,$imm */
1002
1003static SEM_PC
1004SEM_FN_NAME (lm32bf,muli) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
1005{
1006#define FLD(f) abuf->fields.sfmt_addi.f
1007 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1008 int UNUSED written = 0;
1009 IADDR UNUSED pc = abuf->addr;
1010 SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1011
1012 {
1013 SI opval = MULSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm))));
1014 CPU (h_gr[FLD (f_r1)]) = opval;
1015 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1016 }
1017
1018 return vpc;
1019#undef FLD
1020}
1021
1022/* nor: nor $r2,$r0,$r1 */
1023
1024static SEM_PC
1025SEM_FN_NAME (lm32bf,nor) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
1026{
1027#define FLD(f) abuf->fields.sfmt_user.f
1028 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1029 int UNUSED written = 0;
1030 IADDR UNUSED pc = abuf->addr;
1031 SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1032
1033 {
1034 SI opval = INVSI (ORSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)])));
1035 CPU (h_gr[FLD (f_r2)]) = opval;
1036 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1037 }
1038
1039 return vpc;
1040#undef FLD
1041}
1042
1043/* nori: nori $r1,$r0,$uimm */
1044
1045static SEM_PC
1046SEM_FN_NAME (lm32bf,nori) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
1047{
1048#define FLD(f) abuf->fields.sfmt_andi.f
1049 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1050 int UNUSED written = 0;
1051 IADDR UNUSED pc = abuf->addr;
1052 SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1053
1054 {
1055 SI opval = INVSI (ORSI (CPU (h_gr[FLD (f_r0)]), ZEXTSISI (FLD (f_uimm))));
1056 CPU (h_gr[FLD (f_r1)]) = opval;
1057 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1058 }
1059
1060 return vpc;
1061#undef FLD
1062}
1063
1064/* or: or $r2,$r0,$r1 */
1065
1066static SEM_PC
1067SEM_FN_NAME (lm32bf,or) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
1068{
1069#define FLD(f) abuf->fields.sfmt_user.f
1070 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1071 int UNUSED written = 0;
1072 IADDR UNUSED pc = abuf->addr;
1073 SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1074
1075 {
1076 SI opval = ORSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));
1077 CPU (h_gr[FLD (f_r2)]) = opval;
1078 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1079 }
1080
1081 return vpc;
1082#undef FLD
1083}
1084
1085/* ori: ori $r1,$r0,$lo16 */
1086
1087static SEM_PC
1088SEM_FN_NAME (lm32bf,ori) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
1089{
1090#define FLD(f) abuf->fields.sfmt_andi.f
1091 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1092 int UNUSED written = 0;
1093 IADDR UNUSED pc = abuf->addr;
1094 SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1095
1096 {
1097 SI opval = ORSI (CPU (h_gr[FLD (f_r0)]), ZEXTSISI (FLD (f_uimm)));
1098 CPU (h_gr[FLD (f_r1)]) = opval;
1099 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1100 }
1101
1102 return vpc;
1103#undef FLD
1104}
1105
1106/* orhii: orhi $r1,$r0,$hi16 */
1107
1108static SEM_PC
1109SEM_FN_NAME (lm32bf,orhii) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
1110{
1111#define FLD(f) abuf->fields.sfmt_andi.f
1112 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1113 int UNUSED written = 0;
1114 IADDR UNUSED pc = abuf->addr;
1115 SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1116
1117 {
1118 SI opval = ORSI (CPU (h_gr[FLD (f_r0)]), SLLSI (FLD (f_uimm), 16));
1119 CPU (h_gr[FLD (f_r1)]) = opval;
1120 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1121 }
1122
1123 return vpc;
1124#undef FLD
1125}
1126
1127/* rcsr: rcsr $r2,$csr */
1128
1129static SEM_PC
1130SEM_FN_NAME (lm32bf,rcsr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
1131{
1132#define FLD(f) abuf->fields.sfmt_rcsr.f
1133 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1134 int UNUSED written = 0;
1135 IADDR UNUSED pc = abuf->addr;
1136 SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1137
1138 {
1139 SI opval = CPU (h_csr[FLD (f_csr)]);
1140 CPU (h_gr[FLD (f_r2)]) = opval;
1141 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1142 }
1143
1144 return vpc;
1145#undef FLD
1146}
1147
1148/* sb: sb ($r0+$imm),$r1 */
1149
1150static SEM_PC
1151SEM_FN_NAME (lm32bf,sb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
1152{
1153#define FLD(f) abuf->fields.sfmt_addi.f
1154 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1155 int UNUSED written = 0;
1156 IADDR UNUSED pc = abuf->addr;
1157 SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1158
1159 {
1160 QI opval = CPU (h_gr[FLD (f_r1)]);
1161 SETMEMQI (current_cpu, pc, ADDSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm)))), opval);
1162 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
1163 }
1164
1165 return vpc;
1166#undef FLD
1167}
1168
1169/* sextb: sextb $r2,$r0 */
1170
1171static SEM_PC
1172SEM_FN_NAME (lm32bf,sextb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
1173{
1174#define FLD(f) abuf->fields.sfmt_user.f
1175 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1176 int UNUSED written = 0;
1177 IADDR UNUSED pc = abuf->addr;
1178 SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1179
1180 {
1181 SI opval = EXTQISI (TRUNCSIQI (CPU (h_gr[FLD (f_r0)])));
1182 CPU (h_gr[FLD (f_r2)]) = opval;
1183 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1184 }
1185
1186 return vpc;
1187#undef FLD
1188}
1189
1190/* sexth: sexth $r2,$r0 */
1191
1192static SEM_PC
1193SEM_FN_NAME (lm32bf,sexth) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
1194{
1195#define FLD(f) abuf->fields.sfmt_user.f
1196 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1197 int UNUSED written = 0;
1198 IADDR UNUSED pc = abuf->addr;
1199 SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1200
1201 {
1202 SI opval = EXTHISI (TRUNCSIHI (CPU (h_gr[FLD (f_r0)])));
1203 CPU (h_gr[FLD (f_r2)]) = opval;
1204 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1205 }
1206
1207 return vpc;
1208#undef FLD
1209}
1210
1211/* sh: sh ($r0+$imm),$r1 */
1212
1213static SEM_PC
1214SEM_FN_NAME (lm32bf,sh) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
1215{
1216#define FLD(f) abuf->fields.sfmt_addi.f
1217 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1218 int UNUSED written = 0;
1219 IADDR UNUSED pc = abuf->addr;
1220 SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1221
1222 {
1223 HI opval = CPU (h_gr[FLD (f_r1)]);
1224 SETMEMHI (current_cpu, pc, ADDSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm)))), opval);
1225 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
1226 }
1227
1228 return vpc;
1229#undef FLD
1230}
1231
1232/* sl: sl $r2,$r0,$r1 */
1233
1234static SEM_PC
1235SEM_FN_NAME (lm32bf,sl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
1236{
1237#define FLD(f) abuf->fields.sfmt_user.f
1238 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1239 int UNUSED written = 0;
1240 IADDR UNUSED pc = abuf->addr;
1241 SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1242
1243 {
1244 SI opval = SLLSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));
1245 CPU (h_gr[FLD (f_r2)]) = opval;
1246 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1247 }
1248
1249 return vpc;
1250#undef FLD
1251}
1252
1253/* sli: sli $r1,$r0,$imm */
1254
1255static SEM_PC
1256SEM_FN_NAME (lm32bf,sli) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
1257{
1258#define FLD(f) abuf->fields.sfmt_addi.f
1259 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1260 int UNUSED written = 0;
1261 IADDR UNUSED pc = abuf->addr;
1262 SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1263
1264 {
1265 SI opval = SLLSI (CPU (h_gr[FLD (f_r0)]), FLD (f_imm));
1266 CPU (h_gr[FLD (f_r1)]) = opval;
1267 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1268 }
1269
1270 return vpc;
1271#undef FLD
1272}
1273
1274/* sr: sr $r2,$r0,$r1 */
1275
1276static SEM_PC
1277SEM_FN_NAME (lm32bf,sr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
1278{
1279#define FLD(f) abuf->fields.sfmt_user.f
1280 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1281 int UNUSED written = 0;
1282 IADDR UNUSED pc = abuf->addr;
1283 SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1284
1285 {
1286 SI opval = SRASI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));
1287 CPU (h_gr[FLD (f_r2)]) = opval;
1288 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1289 }
1290
1291 return vpc;
1292#undef FLD
1293}
1294
1295/* sri: sri $r1,$r0,$imm */
1296
1297static SEM_PC
1298SEM_FN_NAME (lm32bf,sri) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
1299{
1300#define FLD(f) abuf->fields.sfmt_addi.f
1301 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1302 int UNUSED written = 0;
1303 IADDR UNUSED pc = abuf->addr;
1304 SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1305
1306 {
1307 SI opval = SRASI (CPU (h_gr[FLD (f_r0)]), FLD (f_imm));
1308 CPU (h_gr[FLD (f_r1)]) = opval;
1309 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1310 }
1311
1312 return vpc;
1313#undef FLD
1314}
1315
1316/* sru: sru $r2,$r0,$r1 */
1317
1318static SEM_PC
1319SEM_FN_NAME (lm32bf,sru) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
1320{
1321#define FLD(f) abuf->fields.sfmt_user.f
1322 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1323 int UNUSED written = 0;
1324 IADDR UNUSED pc = abuf->addr;
1325 SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1326
1327 {
1328 SI opval = SRLSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));
1329 CPU (h_gr[FLD (f_r2)]) = opval;
1330 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1331 }
1332
1333 return vpc;
1334#undef FLD
1335}
1336
1337/* srui: srui $r1,$r0,$imm */
1338
1339static SEM_PC
1340SEM_FN_NAME (lm32bf,srui) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
1341{
1342#define FLD(f) abuf->fields.sfmt_addi.f
1343 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1344 int UNUSED written = 0;
1345 IADDR UNUSED pc = abuf->addr;
1346 SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1347
1348 {
1349 SI opval = SRLSI (CPU (h_gr[FLD (f_r0)]), FLD (f_imm));
1350 CPU (h_gr[FLD (f_r1)]) = opval;
1351 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1352 }
1353
1354 return vpc;
1355#undef FLD
1356}
1357
1358/* sub: sub $r2,$r0,$r1 */
1359
1360static SEM_PC
1361SEM_FN_NAME (lm32bf,sub) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
1362{
1363#define FLD(f) abuf->fields.sfmt_user.f
1364 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1365 int UNUSED written = 0;
1366 IADDR UNUSED pc = abuf->addr;
1367 SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1368
1369 {
1370 SI opval = SUBSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));
1371 CPU (h_gr[FLD (f_r2)]) = opval;
1372 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1373 }
1374
1375 return vpc;
1376#undef FLD
1377}
1378
1379/* sw: sw ($r0+$imm),$r1 */
1380
1381static SEM_PC
1382SEM_FN_NAME (lm32bf,sw) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
1383{
1384#define FLD(f) abuf->fields.sfmt_addi.f
1385 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1386 int UNUSED written = 0;
1387 IADDR UNUSED pc = abuf->addr;
1388 SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1389
1390 {
1391 SI opval = CPU (h_gr[FLD (f_r1)]);
1392 SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm)))), opval);
1393 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
1394 }
1395
1396 return vpc;
1397#undef FLD
1398}
1399
1400/* user: user $r2,$r0,$r1,$user */
1401
1402static SEM_PC
1403SEM_FN_NAME (lm32bf,user) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
1404{
1405#define FLD(f) abuf->fields.sfmt_user.f
1406 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1407 int UNUSED written = 0;
1408 IADDR UNUSED pc = abuf->addr;
1409 SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1410
1411 {
1412 SI opval = lm32bf_user_insn (current_cpu, CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]), FLD (f_user));
1413 CPU (h_gr[FLD (f_r2)]) = opval;
1414 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1415 }
1416
1417 return vpc;
1418#undef FLD
1419}
1420
1421/* wcsr: wcsr $csr,$r1 */
1422
1423static SEM_PC
1424SEM_FN_NAME (lm32bf,wcsr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
1425{
1426#define FLD(f) abuf->fields.sfmt_wcsr.f
1427 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1428 int UNUSED written = 0;
1429 IADDR UNUSED pc = abuf->addr;
1430 SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1431
1432lm32bf_wcsr_insn (current_cpu, FLD (f_csr), CPU (h_gr[FLD (f_r1)]));
1433
1434 return vpc;
1435#undef FLD
1436}
1437
1438/* xor: xor $r2,$r0,$r1 */
1439
1440static SEM_PC
1441SEM_FN_NAME (lm32bf,xor) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
1442{
1443#define FLD(f) abuf->fields.sfmt_user.f
1444 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1445 int UNUSED written = 0;
1446 IADDR UNUSED pc = abuf->addr;
1447 SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1448
1449 {
1450 SI opval = XORSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));
1451 CPU (h_gr[FLD (f_r2)]) = opval;
1452 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1453 }
1454
1455 return vpc;
1456#undef FLD
1457}
1458
1459/* xori: xori $r1,$r0,$uimm */
1460
1461static SEM_PC
1462SEM_FN_NAME (lm32bf,xori) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
1463{
1464#define FLD(f) abuf->fields.sfmt_andi.f
1465 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1466 int UNUSED written = 0;
1467 IADDR UNUSED pc = abuf->addr;
1468 SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1469
1470 {
1471 SI opval = XORSI (CPU (h_gr[FLD (f_r0)]), ZEXTSISI (FLD (f_uimm)));
1472 CPU (h_gr[FLD (f_r1)]) = opval;
1473 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1474 }
1475
1476 return vpc;
1477#undef FLD
1478}
1479
1480/* xnor: xnor $r2,$r0,$r1 */
1481
1482static SEM_PC
1483SEM_FN_NAME (lm32bf,xnor) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
1484{
1485#define FLD(f) abuf->fields.sfmt_user.f
1486 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1487 int UNUSED written = 0;
1488 IADDR UNUSED pc = abuf->addr;
1489 SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1490
1491 {
1492 SI opval = INVSI (XORSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)])));
1493 CPU (h_gr[FLD (f_r2)]) = opval;
1494 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1495 }
1496
1497 return vpc;
1498#undef FLD
1499}
1500
1501/* xnori: xnori $r1,$r0,$uimm */
1502
1503static SEM_PC
1504SEM_FN_NAME (lm32bf,xnori) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
1505{
1506#define FLD(f) abuf->fields.sfmt_andi.f
1507 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1508 int UNUSED written = 0;
1509 IADDR UNUSED pc = abuf->addr;
1510 SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1511
1512 {
1513 SI opval = INVSI (XORSI (CPU (h_gr[FLD (f_r0)]), ZEXTSISI (FLD (f_uimm))));
1514 CPU (h_gr[FLD (f_r1)]) = opval;
1515 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1516 }
1517
1518 return vpc;
1519#undef FLD
1520}
1521
1522/* break: break */
1523
1524static SEM_PC
1525SEM_FN_NAME (lm32bf,break) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
1526{
1527#define FLD(f) abuf->fields.fmt_empty.f
1528 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1529 int UNUSED written = 0;
1530 IADDR UNUSED pc = abuf->addr;
1531 SEM_BRANCH_INIT
1532 SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1533
1534 {
1535 USI opval = lm32bf_break_insn (current_cpu, pc);
1536 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
1537 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
1538 }
1539
1540 SEM_BRANCH_FINI (vpc);
1541 return vpc;
1542#undef FLD
1543}
1544
1545/* scall: scall */
1546
1547static SEM_PC
1548SEM_FN_NAME (lm32bf,scall) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
1549{
1550#define FLD(f) abuf->fields.fmt_empty.f
1551 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1552 int UNUSED written = 0;
1553 IADDR UNUSED pc = abuf->addr;
1554 SEM_BRANCH_INIT
1555 SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1556
1557 {
1558 USI opval = lm32bf_scall_insn (current_cpu, pc);
1559 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
1560 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
1561 }
1562
1563 SEM_BRANCH_FINI (vpc);
1564 return vpc;
1565#undef FLD
1566}
1567
1568/* Table of all semantic fns. */
1569
1570static const struct sem_fn_desc sem_fns[] = {
1571 { LM32BF_INSN_X_INVALID, SEM_FN_NAME (lm32bf,x_invalid) },
1572 { LM32BF_INSN_X_AFTER, SEM_FN_NAME (lm32bf,x_after) },
1573 { LM32BF_INSN_X_BEFORE, SEM_FN_NAME (lm32bf,x_before) },
1574 { LM32BF_INSN_X_CTI_CHAIN, SEM_FN_NAME (lm32bf,x_cti_chain) },
1575 { LM32BF_INSN_X_CHAIN, SEM_FN_NAME (lm32bf,x_chain) },
1576 { LM32BF_INSN_X_BEGIN, SEM_FN_NAME (lm32bf,x_begin) },
1577 { LM32BF_INSN_ADD, SEM_FN_NAME (lm32bf,add) },
1578 { LM32BF_INSN_ADDI, SEM_FN_NAME (lm32bf,addi) },
1579 { LM32BF_INSN_AND, SEM_FN_NAME (lm32bf,and) },
1580 { LM32BF_INSN_ANDI, SEM_FN_NAME (lm32bf,andi) },
1581 { LM32BF_INSN_ANDHII, SEM_FN_NAME (lm32bf,andhii) },
1582 { LM32BF_INSN_B, SEM_FN_NAME (lm32bf,b) },
1583 { LM32BF_INSN_BI, SEM_FN_NAME (lm32bf,bi) },
1584 { LM32BF_INSN_BE, SEM_FN_NAME (lm32bf,be) },
1585 { LM32BF_INSN_BG, SEM_FN_NAME (lm32bf,bg) },
1586 { LM32BF_INSN_BGE, SEM_FN_NAME (lm32bf,bge) },
1587 { LM32BF_INSN_BGEU, SEM_FN_NAME (lm32bf,bgeu) },
1588 { LM32BF_INSN_BGU, SEM_FN_NAME (lm32bf,bgu) },
1589 { LM32BF_INSN_BNE, SEM_FN_NAME (lm32bf,bne) },
1590 { LM32BF_INSN_CALL, SEM_FN_NAME (lm32bf,call) },
1591 { LM32BF_INSN_CALLI, SEM_FN_NAME (lm32bf,calli) },
1592 { LM32BF_INSN_CMPE, SEM_FN_NAME (lm32bf,cmpe) },
1593 { LM32BF_INSN_CMPEI, SEM_FN_NAME (lm32bf,cmpei) },
1594 { LM32BF_INSN_CMPG, SEM_FN_NAME (lm32bf,cmpg) },
1595 { LM32BF_INSN_CMPGI, SEM_FN_NAME (lm32bf,cmpgi) },
1596 { LM32BF_INSN_CMPGE, SEM_FN_NAME (lm32bf,cmpge) },
1597 { LM32BF_INSN_CMPGEI, SEM_FN_NAME (lm32bf,cmpgei) },
1598 { LM32BF_INSN_CMPGEU, SEM_FN_NAME (lm32bf,cmpgeu) },
1599 { LM32BF_INSN_CMPGEUI, SEM_FN_NAME (lm32bf,cmpgeui) },
1600 { LM32BF_INSN_CMPGU, SEM_FN_NAME (lm32bf,cmpgu) },
1601 { LM32BF_INSN_CMPGUI, SEM_FN_NAME (lm32bf,cmpgui) },
1602 { LM32BF_INSN_CMPNE, SEM_FN_NAME (lm32bf,cmpne) },
1603 { LM32BF_INSN_CMPNEI, SEM_FN_NAME (lm32bf,cmpnei) },
1604 { LM32BF_INSN_DIVU, SEM_FN_NAME (lm32bf,divu) },
1605 { LM32BF_INSN_LB, SEM_FN_NAME (lm32bf,lb) },
1606 { LM32BF_INSN_LBU, SEM_FN_NAME (lm32bf,lbu) },
1607 { LM32BF_INSN_LH, SEM_FN_NAME (lm32bf,lh) },
1608 { LM32BF_INSN_LHU, SEM_FN_NAME (lm32bf,lhu) },
1609 { LM32BF_INSN_LW, SEM_FN_NAME (lm32bf,lw) },
1610 { LM32BF_INSN_MODU, SEM_FN_NAME (lm32bf,modu) },
1611 { LM32BF_INSN_MUL, SEM_FN_NAME (lm32bf,mul) },
1612 { LM32BF_INSN_MULI, SEM_FN_NAME (lm32bf,muli) },
1613 { LM32BF_INSN_NOR, SEM_FN_NAME (lm32bf,nor) },
1614 { LM32BF_INSN_NORI, SEM_FN_NAME (lm32bf,nori) },
1615 { LM32BF_INSN_OR, SEM_FN_NAME (lm32bf,or) },
1616 { LM32BF_INSN_ORI, SEM_FN_NAME (lm32bf,ori) },
1617 { LM32BF_INSN_ORHII, SEM_FN_NAME (lm32bf,orhii) },
1618 { LM32BF_INSN_RCSR, SEM_FN_NAME (lm32bf,rcsr) },
1619 { LM32BF_INSN_SB, SEM_FN_NAME (lm32bf,sb) },
1620 { LM32BF_INSN_SEXTB, SEM_FN_NAME (lm32bf,sextb) },
1621 { LM32BF_INSN_SEXTH, SEM_FN_NAME (lm32bf,sexth) },
1622 { LM32BF_INSN_SH, SEM_FN_NAME (lm32bf,sh) },
1623 { LM32BF_INSN_SL, SEM_FN_NAME (lm32bf,sl) },
1624 { LM32BF_INSN_SLI, SEM_FN_NAME (lm32bf,sli) },
1625 { LM32BF_INSN_SR, SEM_FN_NAME (lm32bf,sr) },
1626 { LM32BF_INSN_SRI, SEM_FN_NAME (lm32bf,sri) },
1627 { LM32BF_INSN_SRU, SEM_FN_NAME (lm32bf,sru) },
1628 { LM32BF_INSN_SRUI, SEM_FN_NAME (lm32bf,srui) },
1629 { LM32BF_INSN_SUB, SEM_FN_NAME (lm32bf,sub) },
1630 { LM32BF_INSN_SW, SEM_FN_NAME (lm32bf,sw) },
1631 { LM32BF_INSN_USER, SEM_FN_NAME (lm32bf,user) },
1632 { LM32BF_INSN_WCSR, SEM_FN_NAME (lm32bf,wcsr) },
1633 { LM32BF_INSN_XOR, SEM_FN_NAME (lm32bf,xor) },
1634 { LM32BF_INSN_XORI, SEM_FN_NAME (lm32bf,xori) },
1635 { LM32BF_INSN_XNOR, SEM_FN_NAME (lm32bf,xnor) },
1636 { LM32BF_INSN_XNORI, SEM_FN_NAME (lm32bf,xnori) },
1637 { LM32BF_INSN_BREAK, SEM_FN_NAME (lm32bf,break) },
1638 { LM32BF_INSN_SCALL, SEM_FN_NAME (lm32bf,scall) },
1639 { 0, 0 }
1640};
1641
1642/* Add the semantic fns to IDESC_TABLE. */
1643
1644void
1645SEM_FN_NAME (lm32bf,init_idesc_table) (SIM_CPU *current_cpu)
1646{
1647 IDESC *idesc_table = CPU_IDESC (current_cpu);
1648 const struct sem_fn_desc *sf;
1649 int mach_num = MACH_NUM (CPU_MACH (current_cpu));
1650
1651 for (sf = &sem_fns[0]; sf->fn != 0; ++sf)
1652 {
1653 const CGEN_INSN *insn = idesc_table[sf->index].idata;
1654 int valid_p = (CGEN_INSN_VIRTUAL_P (insn)
1655 || CGEN_INSN_MACH_HAS_P (insn, mach_num));
1656#if FAST_P
1657 if (valid_p)
1658 idesc_table[sf->index].sem_fast = sf->fn;
1659 else
1660 idesc_table[sf->index].sem_fast = SEM_FN_NAME (lm32bf,x_invalid);
1661#else
1662 if (valid_p)
1663 idesc_table[sf->index].sem_full = sf->fn;
1664 else
1665 idesc_table[sf->index].sem_full = SEM_FN_NAME (lm32bf,x_invalid);
1666#endif
1667 }
1668}
1669
GDB Binutils - Deliverables
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