Commit | Line | Data |
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d45a4bef JB |
1 | /* gdb.c --- sim interface to GDB. |
2 | ||
61baf725 | 3 | Copyright (C) 2005-2017 Free Software Foundation, Inc. |
d45a4bef JB |
4 | Contributed by Red Hat, Inc. |
5 | ||
6 | This file is part of the GNU simulators. | |
7 | ||
4744ac1b JB |
8 | This program is free software; you can redistribute it and/or modify |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 3 of the License, or | |
11 | (at your option) any later version. | |
d45a4bef | 12 | |
4744ac1b JB |
13 | This program is distributed in the hope that it will be useful, |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
d45a4bef JB |
17 | |
18 | You should have received a copy of the GNU General Public License | |
4744ac1b | 19 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
d45a4bef | 20 | |
a6ff997c | 21 | #include "config.h" |
d45a4bef JB |
22 | #include <stdio.h> |
23 | #include <assert.h> | |
24 | #include <signal.h> | |
269e9c18 | 25 | #include <stdlib.h> |
d45a4bef JB |
26 | #include <string.h> |
27 | #include <ctype.h> | |
28 | ||
29 | #include "ansidecl.h" | |
30 | #include "gdb/callback.h" | |
31 | #include "gdb/remote-sim.h" | |
32 | #include "gdb/signals.h" | |
33 | #include "gdb/sim-m32c.h" | |
34 | ||
35 | #include "cpu.h" | |
36 | #include "mem.h" | |
37 | #include "load.h" | |
38 | #include "syscalls.h" | |
7cc70e53 DD |
39 | #ifdef TIMER_A |
40 | #include "timer_a.h" | |
41 | #endif | |
d45a4bef JB |
42 | |
43 | /* I don't want to wrap up all the minisim's data structures in an | |
44 | object and pass that around. That'd be a big change, and neither | |
45 | GDB nor run needs that ability. | |
46 | ||
47 | So we just have one instance, that lives in global variables, and | |
48 | each time we open it, we re-initialize it. */ | |
49 | struct sim_state | |
50 | { | |
51 | const char *message; | |
52 | }; | |
53 | ||
54 | static struct sim_state the_minisim = { | |
55 | "This is the sole m32c minisim instance. See libsim.a's global variables." | |
56 | }; | |
57 | ||
58 | static int open; | |
59 | ||
60 | SIM_DESC | |
61 | sim_open (SIM_OPEN_KIND kind, | |
62 | struct host_callback_struct *callback, | |
2e3d4f4d | 63 | struct bfd *abfd, char * const *argv) |
d45a4bef | 64 | { |
3877a145 | 65 | setbuf (stdout, 0); |
d45a4bef JB |
66 | if (open) |
67 | fprintf (stderr, "m32c minisim: re-opened sim\n"); | |
68 | ||
69 | /* The 'run' interface doesn't use this function, so we don't care | |
70 | about KIND; it's always SIM_OPEN_DEBUG. */ | |
71 | if (kind != SIM_OPEN_DEBUG) | |
72 | fprintf (stderr, "m32c minisim: sim_open KIND != SIM_OPEN_DEBUG: %d\n", | |
73 | kind); | |
74 | ||
75 | if (abfd) | |
76 | m32c_set_mach (bfd_get_mach (abfd)); | |
77 | ||
78 | /* We can use ABFD, if non-NULL to select the appropriate | |
79 | architecture. But we only support the r8c right now. */ | |
80 | ||
81 | set_callbacks (callback); | |
82 | ||
83 | /* We don't expect any command-line arguments. */ | |
84 | ||
85 | init_mem (); | |
86 | init_regs (); | |
87 | ||
88 | open = 1; | |
89 | return &the_minisim; | |
90 | } | |
91 | ||
92 | static void | |
93 | check_desc (SIM_DESC sd) | |
94 | { | |
95 | if (sd != &the_minisim) | |
96 | fprintf (stderr, "m32c minisim: desc != &the_minisim\n"); | |
97 | } | |
98 | ||
99 | void | |
100 | sim_close (SIM_DESC sd, int quitting) | |
101 | { | |
102 | check_desc (sd); | |
103 | ||
104 | /* Not much to do. At least free up our memory. */ | |
105 | init_mem (); | |
106 | ||
107 | open = 0; | |
108 | } | |
109 | ||
110 | static bfd * | |
111 | open_objfile (const char *filename) | |
112 | { | |
113 | bfd *prog = bfd_openr (filename, 0); | |
114 | ||
115 | if (!prog) | |
116 | { | |
117 | fprintf (stderr, "Can't read %s\n", filename); | |
118 | return 0; | |
119 | } | |
120 | ||
121 | if (!bfd_check_format (prog, bfd_object)) | |
122 | { | |
123 | fprintf (stderr, "%s not a m32c program\n", filename); | |
124 | return 0; | |
125 | } | |
126 | ||
127 | return prog; | |
128 | } | |
129 | ||
130 | ||
131 | SIM_RC | |
b2b255bd | 132 | sim_load (SIM_DESC sd, const char *prog, struct bfd * abfd, int from_tty) |
d45a4bef JB |
133 | { |
134 | check_desc (sd); | |
135 | ||
136 | if (!abfd) | |
137 | abfd = open_objfile (prog); | |
138 | if (!abfd) | |
139 | return SIM_RC_FAIL; | |
140 | ||
141 | m32c_load (abfd); | |
142 | ||
143 | return SIM_RC_OK; | |
144 | } | |
145 | ||
146 | SIM_RC | |
2e3d4f4d MF |
147 | sim_create_inferior (SIM_DESC sd, struct bfd * abfd, |
148 | char * const *argv, char * const *env) | |
d45a4bef JB |
149 | { |
150 | check_desc (sd); | |
151 | ||
152 | if (abfd) | |
153 | m32c_load (abfd); | |
154 | ||
155 | return SIM_RC_OK; | |
156 | } | |
157 | ||
158 | int | |
159 | sim_read (SIM_DESC sd, SIM_ADDR mem, unsigned char *buf, int length) | |
160 | { | |
161 | check_desc (sd); | |
162 | ||
163 | if (mem == 0) | |
164 | return 0; | |
165 | ||
166 | mem_get_blk ((int) mem, buf, length); | |
167 | ||
168 | return length; | |
169 | } | |
170 | ||
171 | int | |
5558e7e6 | 172 | sim_write (SIM_DESC sd, SIM_ADDR mem, const unsigned char *buf, int length) |
d45a4bef JB |
173 | { |
174 | check_desc (sd); | |
175 | ||
176 | mem_put_blk ((int) mem, buf, length); | |
177 | ||
178 | return length; | |
179 | } | |
180 | ||
181 | ||
182 | /* Read the LENGTH bytes at BUF as an little-endian value. */ | |
183 | static DI | |
184 | get_le (unsigned char *buf, int length) | |
185 | { | |
186 | DI acc = 0; | |
187 | while (--length >= 0) | |
188 | acc = (acc << 8) + buf[length]; | |
189 | ||
190 | return acc; | |
191 | } | |
192 | ||
193 | /* Store VAL as a little-endian value in the LENGTH bytes at BUF. */ | |
194 | static void | |
195 | put_le (unsigned char *buf, int length, DI val) | |
196 | { | |
197 | int i; | |
198 | ||
199 | for (i = 0; i < length; i++) | |
200 | { | |
201 | buf[i] = val & 0xff; | |
202 | val >>= 8; | |
203 | } | |
204 | } | |
205 | ||
206 | static int | |
207 | check_regno (enum m32c_sim_reg regno) | |
208 | { | |
209 | return 0 <= regno && regno < m32c_sim_reg_num_regs; | |
210 | } | |
211 | ||
212 | static size_t | |
213 | mask_size (int addr_mask) | |
214 | { | |
215 | switch (addr_mask) | |
216 | { | |
217 | case 0xffff: | |
218 | return 2; | |
219 | case 0xfffff: | |
220 | case 0xffffff: | |
221 | return 3; | |
222 | default: | |
223 | fprintf (stderr, | |
224 | "m32c minisim: addr_mask_size: unexpected mask 0x%x\n", | |
225 | addr_mask); | |
226 | return sizeof (addr_mask); | |
227 | } | |
228 | } | |
229 | ||
230 | static size_t | |
231 | reg_size (enum m32c_sim_reg regno) | |
232 | { | |
233 | switch (regno) | |
234 | { | |
235 | case m32c_sim_reg_r0_bank0: | |
236 | case m32c_sim_reg_r1_bank0: | |
237 | case m32c_sim_reg_r2_bank0: | |
238 | case m32c_sim_reg_r3_bank0: | |
239 | case m32c_sim_reg_r0_bank1: | |
240 | case m32c_sim_reg_r1_bank1: | |
241 | case m32c_sim_reg_r2_bank1: | |
242 | case m32c_sim_reg_r3_bank1: | |
243 | case m32c_sim_reg_flg: | |
244 | case m32c_sim_reg_svf: | |
245 | return 2; | |
246 | ||
247 | case m32c_sim_reg_a0_bank0: | |
248 | case m32c_sim_reg_a1_bank0: | |
249 | case m32c_sim_reg_fb_bank0: | |
250 | case m32c_sim_reg_sb_bank0: | |
251 | case m32c_sim_reg_a0_bank1: | |
252 | case m32c_sim_reg_a1_bank1: | |
253 | case m32c_sim_reg_fb_bank1: | |
254 | case m32c_sim_reg_sb_bank1: | |
255 | case m32c_sim_reg_usp: | |
256 | case m32c_sim_reg_isp: | |
257 | return mask_size (addr_mask); | |
258 | ||
259 | case m32c_sim_reg_pc: | |
260 | case m32c_sim_reg_intb: | |
261 | case m32c_sim_reg_svp: | |
262 | case m32c_sim_reg_vct: | |
263 | return mask_size (membus_mask); | |
264 | ||
265 | case m32c_sim_reg_dmd0: | |
266 | case m32c_sim_reg_dmd1: | |
267 | return 1; | |
268 | ||
269 | case m32c_sim_reg_dct0: | |
270 | case m32c_sim_reg_dct1: | |
271 | case m32c_sim_reg_drc0: | |
272 | case m32c_sim_reg_drc1: | |
273 | return 2; | |
274 | ||
275 | case m32c_sim_reg_dma0: | |
276 | case m32c_sim_reg_dma1: | |
277 | case m32c_sim_reg_dsa0: | |
278 | case m32c_sim_reg_dsa1: | |
279 | case m32c_sim_reg_dra0: | |
280 | case m32c_sim_reg_dra1: | |
281 | return 3; | |
282 | ||
283 | default: | |
284 | fprintf (stderr, "m32c minisim: unrecognized register number: %d\n", | |
285 | regno); | |
286 | return -1; | |
287 | } | |
288 | } | |
289 | ||
290 | int | |
291 | sim_fetch_register (SIM_DESC sd, int regno, unsigned char *buf, int length) | |
292 | { | |
293 | size_t size; | |
294 | ||
295 | check_desc (sd); | |
296 | ||
297 | if (!check_regno (regno)) | |
298 | return 0; | |
299 | ||
300 | size = reg_size (regno); | |
301 | if (length == size) | |
302 | { | |
303 | DI val; | |
304 | ||
305 | switch (regno) | |
306 | { | |
307 | case m32c_sim_reg_r0_bank0: | |
308 | val = regs.r[0].r_r0; | |
309 | break; | |
310 | case m32c_sim_reg_r1_bank0: | |
311 | val = regs.r[0].r_r1; | |
312 | break; | |
313 | case m32c_sim_reg_r2_bank0: | |
314 | val = regs.r[0].r_r2; | |
315 | break; | |
316 | case m32c_sim_reg_r3_bank0: | |
317 | val = regs.r[0].r_r3; | |
318 | break; | |
319 | case m32c_sim_reg_a0_bank0: | |
320 | val = regs.r[0].r_a0; | |
321 | break; | |
322 | case m32c_sim_reg_a1_bank0: | |
323 | val = regs.r[0].r_a1; | |
324 | break; | |
325 | case m32c_sim_reg_fb_bank0: | |
326 | val = regs.r[0].r_fb; | |
327 | break; | |
328 | case m32c_sim_reg_sb_bank0: | |
329 | val = regs.r[0].r_sb; | |
330 | break; | |
331 | case m32c_sim_reg_r0_bank1: | |
332 | val = regs.r[1].r_r0; | |
333 | break; | |
334 | case m32c_sim_reg_r1_bank1: | |
335 | val = regs.r[1].r_r1; | |
336 | break; | |
337 | case m32c_sim_reg_r2_bank1: | |
338 | val = regs.r[1].r_r2; | |
339 | break; | |
340 | case m32c_sim_reg_r3_bank1: | |
341 | val = regs.r[1].r_r3; | |
342 | break; | |
343 | case m32c_sim_reg_a0_bank1: | |
344 | val = regs.r[1].r_a0; | |
345 | break; | |
346 | case m32c_sim_reg_a1_bank1: | |
347 | val = regs.r[1].r_a1; | |
348 | break; | |
349 | case m32c_sim_reg_fb_bank1: | |
350 | val = regs.r[1].r_fb; | |
351 | break; | |
352 | case m32c_sim_reg_sb_bank1: | |
353 | val = regs.r[1].r_sb; | |
354 | break; | |
355 | ||
356 | case m32c_sim_reg_usp: | |
357 | val = regs.r_usp; | |
358 | break; | |
359 | case m32c_sim_reg_isp: | |
360 | val = regs.r_isp; | |
361 | break; | |
362 | case m32c_sim_reg_pc: | |
363 | val = regs.r_pc; | |
364 | break; | |
365 | case m32c_sim_reg_intb: | |
366 | val = regs.r_intbl * 65536 + regs.r_intbl; | |
367 | break; | |
368 | case m32c_sim_reg_flg: | |
369 | val = regs.r_flags; | |
370 | break; | |
371 | ||
372 | /* These registers aren't implemented by the minisim. */ | |
373 | case m32c_sim_reg_svf: | |
374 | case m32c_sim_reg_svp: | |
375 | case m32c_sim_reg_vct: | |
376 | case m32c_sim_reg_dmd0: | |
377 | case m32c_sim_reg_dmd1: | |
378 | case m32c_sim_reg_dct0: | |
379 | case m32c_sim_reg_dct1: | |
380 | case m32c_sim_reg_drc0: | |
381 | case m32c_sim_reg_drc1: | |
382 | case m32c_sim_reg_dma0: | |
383 | case m32c_sim_reg_dma1: | |
384 | case m32c_sim_reg_dsa0: | |
385 | case m32c_sim_reg_dsa1: | |
386 | case m32c_sim_reg_dra0: | |
387 | case m32c_sim_reg_dra1: | |
388 | return 0; | |
389 | ||
390 | default: | |
391 | fprintf (stderr, "m32c minisim: unrecognized register number: %d\n", | |
392 | regno); | |
393 | return -1; | |
394 | } | |
395 | ||
396 | put_le (buf, length, val); | |
397 | } | |
398 | ||
399 | return size; | |
400 | } | |
401 | ||
402 | int | |
403 | sim_store_register (SIM_DESC sd, int regno, unsigned char *buf, int length) | |
404 | { | |
405 | size_t size; | |
406 | ||
407 | check_desc (sd); | |
408 | ||
409 | if (!check_regno (regno)) | |
dae477fe | 410 | return -1; |
d45a4bef JB |
411 | |
412 | size = reg_size (regno); | |
413 | ||
414 | if (length == size) | |
415 | { | |
416 | DI val = get_le (buf, length); | |
417 | ||
418 | switch (regno) | |
419 | { | |
420 | case m32c_sim_reg_r0_bank0: | |
421 | regs.r[0].r_r0 = val & 0xffff; | |
422 | break; | |
423 | case m32c_sim_reg_r1_bank0: | |
424 | regs.r[0].r_r1 = val & 0xffff; | |
425 | break; | |
426 | case m32c_sim_reg_r2_bank0: | |
427 | regs.r[0].r_r2 = val & 0xffff; | |
428 | break; | |
429 | case m32c_sim_reg_r3_bank0: | |
430 | regs.r[0].r_r3 = val & 0xffff; | |
431 | break; | |
432 | case m32c_sim_reg_a0_bank0: | |
433 | regs.r[0].r_a0 = val & addr_mask; | |
434 | break; | |
435 | case m32c_sim_reg_a1_bank0: | |
436 | regs.r[0].r_a1 = val & addr_mask; | |
437 | break; | |
438 | case m32c_sim_reg_fb_bank0: | |
439 | regs.r[0].r_fb = val & addr_mask; | |
440 | break; | |
441 | case m32c_sim_reg_sb_bank0: | |
442 | regs.r[0].r_sb = val & addr_mask; | |
443 | break; | |
444 | case m32c_sim_reg_r0_bank1: | |
445 | regs.r[1].r_r0 = val & 0xffff; | |
446 | break; | |
447 | case m32c_sim_reg_r1_bank1: | |
448 | regs.r[1].r_r1 = val & 0xffff; | |
449 | break; | |
450 | case m32c_sim_reg_r2_bank1: | |
451 | regs.r[1].r_r2 = val & 0xffff; | |
452 | break; | |
453 | case m32c_sim_reg_r3_bank1: | |
454 | regs.r[1].r_r3 = val & 0xffff; | |
455 | break; | |
456 | case m32c_sim_reg_a0_bank1: | |
457 | regs.r[1].r_a0 = val & addr_mask; | |
458 | break; | |
459 | case m32c_sim_reg_a1_bank1: | |
460 | regs.r[1].r_a1 = val & addr_mask; | |
461 | break; | |
462 | case m32c_sim_reg_fb_bank1: | |
463 | regs.r[1].r_fb = val & addr_mask; | |
464 | break; | |
465 | case m32c_sim_reg_sb_bank1: | |
466 | regs.r[1].r_sb = val & addr_mask; | |
467 | break; | |
468 | ||
469 | case m32c_sim_reg_usp: | |
470 | regs.r_usp = val & addr_mask; | |
471 | break; | |
472 | case m32c_sim_reg_isp: | |
473 | regs.r_isp = val & addr_mask; | |
474 | break; | |
475 | case m32c_sim_reg_pc: | |
476 | regs.r_pc = val & membus_mask; | |
477 | break; | |
478 | case m32c_sim_reg_intb: | |
479 | regs.r_intbl = (val & membus_mask) & 0xffff; | |
480 | regs.r_intbh = (val & membus_mask) >> 16; | |
481 | break; | |
482 | case m32c_sim_reg_flg: | |
483 | regs.r_flags = val & 0xffff; | |
484 | break; | |
485 | ||
486 | /* These registers aren't implemented by the minisim. */ | |
487 | case m32c_sim_reg_svf: | |
488 | case m32c_sim_reg_svp: | |
489 | case m32c_sim_reg_vct: | |
490 | case m32c_sim_reg_dmd0: | |
491 | case m32c_sim_reg_dmd1: | |
492 | case m32c_sim_reg_dct0: | |
493 | case m32c_sim_reg_dct1: | |
494 | case m32c_sim_reg_drc0: | |
495 | case m32c_sim_reg_drc1: | |
496 | case m32c_sim_reg_dma0: | |
497 | case m32c_sim_reg_dma1: | |
498 | case m32c_sim_reg_dsa0: | |
499 | case m32c_sim_reg_dsa1: | |
500 | case m32c_sim_reg_dra0: | |
501 | case m32c_sim_reg_dra1: | |
502 | return 0; | |
503 | ||
504 | default: | |
505 | fprintf (stderr, "m32c minisim: unrecognized register number: %d\n", | |
506 | regno); | |
dae477fe | 507 | return 0; |
d45a4bef JB |
508 | } |
509 | } | |
510 | ||
511 | return size; | |
512 | } | |
513 | ||
d45a4bef JB |
514 | static volatile int stop; |
515 | static enum sim_stop reason; | |
269e9c18 | 516 | static int siggnal; |
d45a4bef JB |
517 | |
518 | ||
519 | /* Given a signal number used by the M32C bsp (that is, newlib), | |
bba258ad | 520 | return a target signal number used by GDB. */ |
269e9c18 | 521 | static int |
bba258ad | 522 | m32c_signal_to_target (int m32c) |
d45a4bef JB |
523 | { |
524 | switch (m32c) | |
525 | { | |
526 | case 4: | |
a493e3e2 | 527 | return GDB_SIGNAL_ILL; |
d45a4bef JB |
528 | |
529 | case 5: | |
a493e3e2 | 530 | return GDB_SIGNAL_TRAP; |
d45a4bef JB |
531 | |
532 | case 10: | |
a493e3e2 | 533 | return GDB_SIGNAL_BUS; |
d45a4bef JB |
534 | |
535 | case 11: | |
a493e3e2 | 536 | return GDB_SIGNAL_SEGV; |
d45a4bef JB |
537 | |
538 | case 24: | |
a493e3e2 | 539 | return GDB_SIGNAL_XCPU; |
d45a4bef JB |
540 | |
541 | case 2: | |
a493e3e2 | 542 | return GDB_SIGNAL_INT; |
d45a4bef JB |
543 | |
544 | case 8: | |
a493e3e2 | 545 | return GDB_SIGNAL_FPE; |
d45a4bef JB |
546 | |
547 | case 6: | |
a493e3e2 | 548 | return GDB_SIGNAL_ABRT; |
d45a4bef JB |
549 | } |
550 | ||
551 | return 0; | |
552 | } | |
553 | ||
554 | ||
555 | /* Take a step return code RC and set up the variables consulted by | |
556 | sim_stop_reason appropriately. */ | |
269e9c18 | 557 | static void |
d45a4bef JB |
558 | handle_step (int rc) |
559 | { | |
560 | if (M32C_STEPPED (rc) || M32C_HIT_BREAK (rc)) | |
561 | { | |
562 | reason = sim_stopped; | |
a493e3e2 | 563 | siggnal = GDB_SIGNAL_TRAP; |
d45a4bef JB |
564 | } |
565 | else if (M32C_STOPPED (rc)) | |
566 | { | |
567 | reason = sim_stopped; | |
bba258ad | 568 | siggnal = m32c_signal_to_target (M32C_STOP_SIG (rc)); |
d45a4bef JB |
569 | } |
570 | else | |
571 | { | |
572 | assert (M32C_EXITED (rc)); | |
573 | reason = sim_exited; | |
574 | siggnal = M32C_EXIT_STATUS (rc); | |
575 | } | |
576 | } | |
577 | ||
578 | ||
579 | void | |
580 | sim_resume (SIM_DESC sd, int step, int sig_to_deliver) | |
581 | { | |
582 | check_desc (sd); | |
583 | ||
584 | if (sig_to_deliver != 0) | |
585 | { | |
586 | fprintf (stderr, | |
587 | "Warning: the m32c minisim does not implement " | |
588 | "signal delivery yet.\n" "Resuming with no signal.\n"); | |
589 | } | |
590 | ||
591 | if (step) | |
3877a145 DD |
592 | { |
593 | handle_step (decode_opcode ()); | |
594 | #ifdef TIMER_A | |
595 | update_timer_a (); | |
596 | #endif | |
597 | } | |
d45a4bef JB |
598 | else |
599 | { | |
600 | /* We don't clear 'stop' here, because then we would miss | |
601 | interrupts that arrived on the way here. Instead, we clear | |
602 | the flag in sim_stop_reason, after GDB has disabled the | |
603 | interrupt signal handler. */ | |
604 | for (;;) | |
605 | { | |
269e9c18 MF |
606 | int rc; |
607 | ||
d45a4bef JB |
608 | if (stop) |
609 | { | |
610 | stop = 0; | |
611 | reason = sim_stopped; | |
a493e3e2 | 612 | siggnal = GDB_SIGNAL_INT; |
d45a4bef JB |
613 | break; |
614 | } | |
615 | ||
269e9c18 | 616 | rc = decode_opcode (); |
3877a145 DD |
617 | #ifdef TIMER_A |
618 | update_timer_a (); | |
619 | #endif | |
d45a4bef JB |
620 | |
621 | if (!M32C_STEPPED (rc)) | |
622 | { | |
623 | handle_step (rc); | |
624 | break; | |
625 | } | |
626 | } | |
627 | } | |
3877a145 | 628 | m32c_sim_restore_console (); |
d45a4bef JB |
629 | } |
630 | ||
631 | int | |
632 | sim_stop (SIM_DESC sd) | |
633 | { | |
634 | stop = 1; | |
635 | ||
636 | return 1; | |
637 | } | |
638 | ||
639 | void | |
640 | sim_stop_reason (SIM_DESC sd, enum sim_stop *reason_p, int *sigrc_p) | |
641 | { | |
642 | check_desc (sd); | |
643 | ||
644 | *reason_p = reason; | |
645 | *sigrc_p = siggnal; | |
646 | } | |
647 | ||
648 | void | |
60d847df | 649 | sim_do_command (SIM_DESC sd, const char *cmd) |
d45a4bef | 650 | { |
60d847df MF |
651 | const char *args; |
652 | char *p = strdup (cmd); | |
d45a4bef | 653 | |
60d847df | 654 | check_desc (sd); |
d45a4bef JB |
655 | |
656 | /* Skip leading whitespace. */ | |
657 | while (isspace (*p)) | |
658 | p++; | |
659 | ||
660 | /* Find the extent of the command word. */ | |
661 | for (p = cmd; *p; p++) | |
662 | if (isspace (*p)) | |
663 | break; | |
664 | ||
665 | /* Null-terminate the command word, and record the start of any | |
666 | further arguments. */ | |
d45a4bef JB |
667 | if (*p) |
668 | { | |
669 | *p = '\0'; | |
670 | args = p + 1; | |
671 | while (isspace (*args)) | |
672 | args++; | |
673 | } | |
674 | else | |
675 | args = p; | |
676 | ||
677 | if (strcmp (cmd, "trace") == 0) | |
678 | { | |
679 | if (strcmp (args, "on") == 0) | |
680 | trace = 1; | |
681 | else if (strcmp (args, "off") == 0) | |
682 | trace = 0; | |
683 | else | |
684 | printf ("The 'sim trace' command expects 'on' or 'off' " | |
685 | "as an argument.\n"); | |
686 | } | |
687 | else if (strcmp (cmd, "verbose") == 0) | |
688 | { | |
689 | if (strcmp (args, "on") == 0) | |
690 | verbose = 1; | |
691 | else if (strcmp (args, "off") == 0) | |
692 | verbose = 0; | |
693 | else | |
694 | printf ("The 'sim verbose' command expects 'on' or 'off'" | |
695 | " as an argument.\n"); | |
696 | } | |
697 | else | |
698 | printf ("The 'sim' command expects either 'trace' or 'verbose'" | |
699 | " as a subcommand.\n"); | |
60d847df MF |
700 | |
701 | free (p); | |
d45a4bef | 702 | } |
af9f7da7 MF |
703 | |
704 | char ** | |
3cb2ab1a | 705 | sim_complete_command (SIM_DESC sd, const char *text, const char *word) |
af9f7da7 MF |
706 | { |
707 | return NULL; | |
708 | } | |
32f25203 NC |
709 | |
710 | void | |
711 | sim_info (SIM_DESC sd, int verbose) | |
712 | { | |
713 | printf ("The m32c minisim doesn't collect any statistics.\n"); | |
714 | } |