[deliverable/binutils-gdb.git] / sim / m32r / Makefile.in

# Makefile template for Configure for the m32r simulator
# Copyright (C) 1996, 1997, 1998, 1999, 2000, 2003 Free Software Foundation, Inc.
# Contributed by Cygnus Support.
#
# This file is part of GDB, the GNU debugger.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License along
# with this program; if not, write to the Free Software Foundation, Inc.,
# 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.

## COMMON_PRE_CONFIG_FRAG

M32R_OBJS = m32r.o cpu.o decode.o sem.o model.o mloop.o
M32RX_OBJS = m32rx.o cpux.o decodex.o modelx.o mloopx.o
M32R2_OBJS = m32r2.o cpu2.o decode2.o model2.o mloop2.o

CONFIG_DEVICES = dv-sockser.o
CONFIG_DEVICES =

SIM_OBJS = \
	$(SIM_NEW_COMMON_OBJS) \
	sim-cpu.o \
	sim-hload.o \
	sim-hrw.o \
	sim-model.o \
	sim-reg.o \
	cgen-utils.o cgen-trace.o cgen-scache.o \
	cgen-run.o sim-reason.o sim-engine.o sim-stop.o \
	sim-if.o arch.o \
	$(M32R_OBJS) \
	$(M32RX_OBJS) \
	$(M32R2_OBJS) \
	traps.o devices.o \
	$(CONFIG_DEVICES)

# Extra headers included by sim-main.h.
SIM_EXTRA_DEPS = \
	$(CGEN_INCLUDE_DEPS) \
	arch.h cpuall.h m32r-sim.h $(srcdir)/../../opcodes/m32r-desc.h

SIM_EXTRA_CFLAGS =

SIM_RUN_OBJS = nrun.o
SIM_EXTRA_CLEAN = m32r-clean

# This selects the m32r newlib/libgloss syscall definitions.
NL_TARGET = -DNL_TARGET_m32r

## COMMON_POST_CONFIG_FRAG

arch = m32r

sim-if.o: sim-if.c $(SIM_MAIN_DEPS) $(srcdir)/../common/sim-core.h

arch.o: arch.c $(SIM_MAIN_DEPS)

traps.o: traps.c targ-vals.h $(SIM_MAIN_DEPS)
devices.o: devices.c $(SIM_MAIN_DEPS)

# M32R objs

M32RBF_INCLUDE_DEPS = \
	$(CGEN_MAIN_CPU_DEPS) \
	cpu.h decode.h eng.h

m32r.o: m32r.c $(M32RBF_INCLUDE_DEPS)

# FIXME: Use of `mono' is wip.
mloop.c eng.h: stamp-mloop
stamp-mloop: $(srcdir)/../common/genmloop.sh mloop.in Makefile
	$(SHELL) $(srccom)/genmloop.sh \
		-mono -fast -pbb -switch sem-switch.c \
		-cpu m32rbf -infile $(srcdir)/mloop.in
	$(SHELL) $(srcroot)/move-if-change eng.hin eng.h
	$(SHELL) $(srcroot)/move-if-change mloop.cin mloop.c
	touch stamp-mloop
mloop.o: mloop.c sem-switch.c $(M32RBF_INCLUDE_DEPS)

cpu.o: cpu.c $(M32RBF_INCLUDE_DEPS)
decode.o: decode.c $(M32RBF_INCLUDE_DEPS)
sem.o: sem.c $(M32RBF_INCLUDE_DEPS)
model.o: model.c $(M32RBF_INCLUDE_DEPS)

# M32RX objs

M32RXF_INCLUDE_DEPS = \
	$(CGEN_MAIN_CPU_DEPS) \
	cpux.h decodex.h engx.h

m32rx.o: m32rx.c $(M32RXF_INCLUDE_DEPS)

# FIXME: Use of `mono' is wip.
mloopx.c engx.h: stamp-xmloop
stamp-xmloop: $(srcdir)/../common/genmloop.sh mloopx.in Makefile
	$(SHELL) $(srccom)/genmloop.sh \
		-mono -no-fast -pbb -parallel-write -switch semx-switch.c \
		-cpu m32rxf -infile $(srcdir)/mloopx.in
	$(SHELL) $(srcroot)/move-if-change eng.hin engx.h
	$(SHELL) $(srcroot)/move-if-change mloop.cin mloopx.c
	touch stamp-xmloop
mloopx.o: mloopx.c semx-switch.c $(M32RXF_INCLUDE_DEPS)

cpux.o: cpux.c $(M32RXF_INCLUDE_DEPS)
decodex.o: decodex.c $(M32RXF_INCLUDE_DEPS)
semx.o: semx.c $(M32RXF_INCLUDE_DEPS)
modelx.o: modelx.c $(M32RXF_INCLUDE_DEPS)

# M32R2 objs

M32R2F_INCLUDE_DEPS = \
	$(CGEN_MAIN_CPU_DEPS) \
	cpu2.h decode2.h eng2.h

m32r2.o: m32r2.c $(M32R2F_INCLUDE_DEPS)

# FIXME: Use of `mono' is wip.
mloop2.c eng2.h: stamp-2mloop
stamp-2mloop: $(srcdir)/../common/genmloop.sh mloop2.in Makefile
	$(SHELL) $(srccom)/genmloop.sh \
		-mono -no-fast -pbb -parallel-write -switch sem2-switch.c \
		-cpu m32r2f -infile $(srcdir)/mloop2.in
	$(SHELL) $(srcroot)/move-if-change eng.hin eng2.h
	$(SHELL) $(srcroot)/move-if-change mloop.cin mloop2.c
	touch stamp-2mloop

mloop2.o:  mloop2.c sem2-switch.c $(M32R2F_INCLUDE_DEPS)
cpu2.o:    cpu2.c    $(M32R2F_INCLUDE_DEPS)
decode2.o: decode2.c $(M32R2F_INCLUDE_DEPS)
sem2.o:    sem2.c    $(M32R2F_INCLUDE_DEPS)
model2.o:  model2.c  $(M32R2F_INCLUDE_DEPS)

m32r-clean:
	rm -f mloop.c eng.h stamp-mloop
	rm -f mloopx.c engx.h stamp-xmloop
	rm -f mloop2.c eng2.h stamp-2mloop
	rm -f stamp-arch stamp-cpu stamp-xcpu stamp-2cpu
	rm -f tmp-*

# cgen support, enable with --enable-cgen-maint
CGEN_MAINT = ; @true
# The following line is commented in or out depending upon --enable-cgen-maint.
@CGEN_MAINT@CGEN_MAINT =

stamp-arch: $(CGEN_READ_SCM) $(CGEN_ARCH_SCM) $(CGEN_CPU_DIR)/m32r.cpu
	$(MAKE) cgen-arch $(CGEN_FLAGS_TO_PASS) mach=all \
	  archfile=$(CGEN_CPU_DIR)/m32r.cpu \
	  FLAGS="with-scache with-profile=fn"
	touch stamp-arch
arch.h arch.c cpuall.h: $(CGEN_MAINT) stamp-arch

stamp-cpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(CGEN_CPU_DIR)/m32r.cpu
	$(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \
	  cpu=m32rbf mach=m32r SUFFIX= \
	  archfile=$(CGEN_CPU_DIR)/m32r.cpu \
	  FLAGS="with-scache with-profile=fn" \
	  EXTRAFILES="$(CGEN_CPU_SEM) $(CGEN_CPU_SEMSW)"
	touch stamp-cpu
cpu.h sem.c sem-switch.c model.c decode.c decode.h: $(CGEN_MAINT) stamp-cpu

stamp-xcpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(CGEN_CPU_DIR)/m32r.cpu
	$(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \
	  cpu=m32rxf mach=m32rx SUFFIX=x \
	  archfile=$(CGEN_CPU_DIR)/m32r.cpu \
	  FLAGS="with-scache with-profile=fn" \
	  EXTRAFILES="$(CGEN_CPU_SEMSW)"
	touch stamp-xcpu
cpux.h semx-switch.c modelx.c decodex.c decodex.h: $(CGEN_MAINT) stamp-xcpu

stamp-2cpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(CGEN_CPU_DIR)/m32r.cpu
	$(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \
	  cpu=m32r2f mach=m32r2 SUFFIX=2 \
	  archfile=$(CGEN_CPU_DIR)/m32r.cpu \
	  FLAGS="with-scache with-profile=fn" \
	  EXTRAFILES="$(CGEN_CPU_SEMSW)"
	touch stamp-2cpu
cpu2.h sem2-switch.c model2.c decode2.c decode2.h: $(CGEN_MAINT) stamp-2cpu
Commit	Line	Data
c906108c	1	# Makefile template for Configure for the m32r simulator
16b47b25	2	# Copyright (C) 1996, 1997, 1998, 1999, 2000, 2003 Free Software Foundation, Inc.
c906108c SS	3	# Contributed by Cygnus Support.
	4	#
	5	# This file is part of GDB, the GNU debugger.
	6	#
	7	# This program is free software; you can redistribute it and/or modify
	8	# it under the terms of the GNU General Public License as published by
	9	# the Free Software Foundation; either version 2 of the License, or
	10	# (at your option) any later version.
	11	#
	12	# This program is distributed in the hope that it will be useful,
	13	# but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	# GNU General Public License for more details.
	16	#
	17	# You should have received a copy of the GNU General Public License along
	18	# with this program; if not, write to the Free Software Foundation, Inc.,
	19	# 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
	20
	21	## COMMON_PRE_CONFIG_FRAG
	22
	23	M32R_OBJS = m32r.o cpu.o decode.o sem.o model.o mloop.o
2df3850c	24	M32RX_OBJS = m32rx.o cpux.o decodex.o modelx.o mloopx.o
16b47b25	25	M32R2_OBJS = m32r2.o cpu2.o decode2.o model2.o mloop2.o
c906108c SS	26
	27	CONFIG_DEVICES = dv-sockser.o
	28	CONFIG_DEVICES =
	29
	30	SIM_OBJS = \
	31	$(SIM_NEW_COMMON_OBJS) \
	32	sim-cpu.o \
	33	sim-hload.o \
	34	sim-hrw.o \
	35	sim-model.o \
	36	sim-reg.o \
	37	cgen-utils.o cgen-trace.o cgen-scache.o \
	38	cgen-run.o sim-reason.o sim-engine.o sim-stop.o \
	39	sim-if.o arch.o \
	40	$(M32R_OBJS) \
2df3850c	41	$(M32RX_OBJS) \
16b47b25	42	$(M32R2_OBJS) \
c906108c SS	43	traps.o devices.o \
	44	$(CONFIG_DEVICES)
	45
	46	# Extra headers included by sim-main.h.
	47	SIM_EXTRA_DEPS = \
	48	$(CGEN_INCLUDE_DEPS) \
	49	arch.h cpuall.h m32r-sim.h $(srcdir)/../../opcodes/m32r-desc.h
	50
	51	SIM_EXTRA_CFLAGS =
	52
	53	SIM_RUN_OBJS = nrun.o
	54	SIM_EXTRA_CLEAN = m32r-clean
	55
	56	# This selects the m32r newlib/libgloss syscall definitions.
	57	NL_TARGET = -DNL_TARGET_m32r
	58
	59	## COMMON_POST_CONFIG_FRAG
	60
	61	arch = m32r
	62
	63	sim-if.o: sim-if.c $(SIM_MAIN_DEPS) $(srcdir)/../common/sim-core.h
	64
	65	arch.o: arch.c $(SIM_MAIN_DEPS)
	66
	67	traps.o: traps.c targ-vals.h $(SIM_MAIN_DEPS)
	68	devices.o: devices.c $(SIM_MAIN_DEPS)
	69
	70	# M32R objs
	71
	72	M32RBF_INCLUDE_DEPS = \
	73	$(CGEN_MAIN_CPU_DEPS) \
	74	cpu.h decode.h eng.h
	75
	76	m32r.o: m32r.c $(M32RBF_INCLUDE_DEPS)
	77
	78	# FIXME: Use of `mono' is wip.
	79	mloop.c eng.h: stamp-mloop
	80	stamp-mloop: $(srcdir)/../common/genmloop.sh mloop.in Makefile
	81	$(SHELL) $(srccom)/genmloop.sh \
	82	-mono -fast -pbb -switch sem-switch.c \
	83	-cpu m32rbf -infile $(srcdir)/mloop.in
	84	$(SHELL) $(srcroot)/move-if-change eng.hin eng.h
	85	$(SHELL) $(srcroot)/move-if-change mloop.cin mloop.c
	86	touch stamp-mloop
	87	mloop.o: mloop.c sem-switch.c $(M32RBF_INCLUDE_DEPS)
	88
	89	cpu.o: cpu.c $(M32RBF_INCLUDE_DEPS)
	90	decode.o: decode.c $(M32RBF_INCLUDE_DEPS)
	91	sem.o: sem.c $(M32RBF_INCLUDE_DEPS)
	92	model.o: model.c $(M32RBF_INCLUDE_DEPS)
	93
2df3850c JM	94	# M32RX objs
	95
	96	M32RXF_INCLUDE_DEPS = \
	97	$(CGEN_MAIN_CPU_DEPS) \
	98	cpux.h decodex.h engx.h
	99
	100	m32rx.o: m32rx.c $(M32RXF_INCLUDE_DEPS)
	101
	102	# FIXME: Use of `mono' is wip.
	103	mloopx.c engx.h: stamp-xmloop
	104	stamp-xmloop: $(srcdir)/../common/genmloop.sh mloopx.in Makefile
	105	$(SHELL) $(srccom)/genmloop.sh \
	106	-mono -no-fast -pbb -parallel-write -switch semx-switch.c \
	107	-cpu m32rxf -infile $(srcdir)/mloopx.in
	108	$(SHELL) $(srcroot)/move-if-change eng.hin engx.h
	109	$(SHELL) $(srcroot)/move-if-change mloop.cin mloopx.c
	110	touch stamp-xmloop
	111	mloopx.o: mloopx.c semx-switch.c $(M32RXF_INCLUDE_DEPS)
	112
	113	cpux.o: cpux.c $(M32RXF_INCLUDE_DEPS)
	114	decodex.o: decodex.c $(M32RXF_INCLUDE_DEPS)
	115	semx.o: semx.c $(M32RXF_INCLUDE_DEPS)
	116	modelx.o: modelx.c $(M32RXF_INCLUDE_DEPS)
c906108c	117
16b47b25 NC	118	# M32R2 objs
	119
	120	M32R2F_INCLUDE_DEPS = \
	121	$(CGEN_MAIN_CPU_DEPS) \
	122	cpu2.h decode2.h eng2.h
	123
	124	m32r2.o: m32r2.c $(M32R2F_INCLUDE_DEPS)
	125
	126	# FIXME: Use of `mono' is wip.
	127	mloop2.c eng2.h: stamp-2mloop
	128	stamp-2mloop: $(srcdir)/../common/genmloop.sh mloop2.in Makefile
	129	$(SHELL) $(srccom)/genmloop.sh \
	130	-mono -no-fast -pbb -parallel-write -switch sem2-switch.c \
	131	-cpu m32r2f -infile $(srcdir)/mloop2.in
	132	$(SHELL) $(srcroot)/move-if-change eng.hin eng2.h
	133	$(SHELL) $(srcroot)/move-if-change mloop.cin mloop2.c
	134	touch stamp-2mloop
	135
	136	mloop2.o: mloop2.c sem2-switch.c $(M32R2F_INCLUDE_DEPS)
	137	cpu2.o: cpu2.c $(M32R2F_INCLUDE_DEPS)
	138	decode2.o: decode2.c $(M32R2F_INCLUDE_DEPS)
	139	sem2.o: sem2.c $(M32R2F_INCLUDE_DEPS)
	140	model2.o: model2.c $(M32R2F_INCLUDE_DEPS)
	141
c906108c SS	142	m32r-clean:
c906108c SS	143	rm -f mloop.c eng.h stamp-mloop
2df3850c	144	rm -f mloopx.c engx.h stamp-xmloop
16b47b25 NC	145	rm -f mloop2.c eng2.h stamp-2mloop
16b47b25 NC	146	rm -f stamp-arch stamp-cpu stamp-xcpu stamp-2cpu
c906108c SS	147	rm -f tmp-*
c906108c SS	148
604259a0 FCE	149	# cgen support, enable with --enable-cgen-maint
	150	CGEN_MAINT = ; @true
	151	# The following line is commented in or out depending upon --enable-cgen-maint.
	152	@CGEN_MAINT@CGEN_MAINT =
	153
e3e473da	154	stamp-arch: $(CGEN_READ_SCM) $(CGEN_ARCH_SCM) $(CGEN_CPU_DIR)/m32r.cpu
604259a0	155	$(MAKE) cgen-arch $(CGEN_FLAGS_TO_PASS) mach=all \
a6fc1778	156	archfile=$(CGEN_CPU_DIR)/m32r.cpu \
604259a0 FCE	157	FLAGS="with-scache with-profile=fn"
	158	touch stamp-arch
	159	arch.h arch.c cpuall.h: $(CGEN_MAINT) stamp-arch
604259a0	160
e3e473da	161	stamp-cpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(CGEN_CPU_DIR)/m32r.cpu
604259a0 FCE	162	$(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \
604259a0 FCE	163	cpu=m32rbf mach=m32r SUFFIX= \
a6fc1778	164	archfile=$(CGEN_CPU_DIR)/m32r.cpu \
604259a0 FCE	165	FLAGS="with-scache with-profile=fn" \
	166	EXTRAFILES="$(CGEN_CPU_SEM) $(CGEN_CPU_SEMSW)"
	167	touch stamp-cpu
	168	cpu.h sem.c sem-switch.c model.c decode.c decode.h: $(CGEN_MAINT) stamp-cpu
604259a0	169
e3e473da	170	stamp-xcpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(CGEN_CPU_DIR)/m32r.cpu
604259a0	171	$(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \
a6fc1778 DB	172	cpu=m32rxf mach=m32rx SUFFIX=x \
	173	archfile=$(CGEN_CPU_DIR)/m32r.cpu \
	174	FLAGS="with-scache with-profile=fn" \
	175	EXTRAFILES="$(CGEN_CPU_SEMSW)"
604259a0 FCE	176	touch stamp-xcpu
604259a0 FCE	177	cpux.h semx-switch.c modelx.c decodex.c decodex.h: $(CGEN_MAINT) stamp-xcpu
16b47b25 NC	178
	179	stamp-2cpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(CGEN_CPU_DIR)/m32r.cpu
	180	$(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \
	181	cpu=m32r2f mach=m32r2 SUFFIX=2 \
	182	archfile=$(CGEN_CPU_DIR)/m32r.cpu \
	183	FLAGS="with-scache with-profile=fn" \
	184	EXTRAFILES="$(CGEN_CPU_SEMSW)"
	185	touch stamp-2cpu
	186	cpu2.h sem2-switch.c model2.c decode2.c decode2.h: $(CGEN_MAINT) stamp-2cpu