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c906108c SS |
1 | /* CPU family header for m32rbf. |
2 | ||
3 | THIS FILE IS MACHINE GENERATED WITH CGEN. | |
4 | ||
55552082 | 5 | Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc. |
c906108c SS |
6 | |
7 | This file is part of the GNU Simulators. | |
8 | ||
9 | This program is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 2, or (at your option) | |
12 | any later version. | |
13 | ||
14 | This program is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License along | |
20 | with this program; if not, write to the Free Software Foundation, Inc., | |
21 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
22 | ||
23 | */ | |
24 | ||
25 | #ifndef CPU_M32RBF_H | |
26 | #define CPU_M32RBF_H | |
27 | ||
28 | /* Maximum number of instructions that are fetched at a time. | |
29 | This is for LIW type instructions sets (e.g. m32r). */ | |
30 | #define MAX_LIW_INSNS 2 | |
31 | ||
32 | /* Maximum number of instructions that can be executed in parallel. */ | |
33 | #define MAX_PARALLEL_INSNS 1 | |
34 | ||
35 | /* CPU state information. */ | |
36 | typedef struct { | |
37 | /* Hardware elements. */ | |
38 | struct { | |
39 | /* program counter */ | |
40 | USI h_pc; | |
41 | #define GET_H_PC() CPU (h_pc) | |
42 | #define SET_H_PC(x) (CPU (h_pc) = (x)) | |
43 | /* general registers */ | |
44 | SI h_gr[16]; | |
45 | #define GET_H_GR(a1) CPU (h_gr)[a1] | |
46 | #define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x)) | |
47 | /* control registers */ | |
48 | USI h_cr[16]; | |
7a292a7a SS |
49 | #define GET_H_CR(index) m32rbf_h_cr_get_handler (current_cpu, index) |
50 | #define SET_H_CR(index, x) \ | |
51 | do { \ | |
52 | m32rbf_h_cr_set_handler (current_cpu, (index), (x));\ | |
de8f5985 | 53 | ;} while (0) |
c906108c SS |
54 | /* accumulator */ |
55 | DI h_accum; | |
7a292a7a SS |
56 | #define GET_H_ACCUM() m32rbf_h_accum_get_handler (current_cpu) |
57 | #define SET_H_ACCUM(x) \ | |
58 | do { \ | |
59 | m32rbf_h_accum_set_handler (current_cpu, (x));\ | |
de8f5985 | 60 | ;} while (0) |
c906108c SS |
61 | /* condition bit */ |
62 | BI h_cond; | |
63 | #define GET_H_COND() CPU (h_cond) | |
64 | #define SET_H_COND(x) (CPU (h_cond) = (x)) | |
65 | /* psw part of psw */ | |
66 | UQI h_psw; | |
7a292a7a SS |
67 | #define GET_H_PSW() m32rbf_h_psw_get_handler (current_cpu) |
68 | #define SET_H_PSW(x) \ | |
69 | do { \ | |
70 | m32rbf_h_psw_set_handler (current_cpu, (x));\ | |
de8f5985 | 71 | ;} while (0) |
c906108c SS |
72 | /* backup psw */ |
73 | UQI h_bpsw; | |
74 | #define GET_H_BPSW() CPU (h_bpsw) | |
75 | #define SET_H_BPSW(x) (CPU (h_bpsw) = (x)) | |
76 | /* backup bpsw */ | |
77 | UQI h_bbpsw; | |
78 | #define GET_H_BBPSW() CPU (h_bbpsw) | |
79 | #define SET_H_BBPSW(x) (CPU (h_bbpsw) = (x)) | |
80 | /* lock */ | |
81 | BI h_lock; | |
82 | #define GET_H_LOCK() CPU (h_lock) | |
83 | #define SET_H_LOCK(x) (CPU (h_lock) = (x)) | |
84 | } hardware; | |
85 | #define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware) | |
86 | } M32RBF_CPU_DATA; | |
87 | ||
88 | /* Cover fns for register access. */ | |
89 | USI m32rbf_h_pc_get (SIM_CPU *); | |
90 | void m32rbf_h_pc_set (SIM_CPU *, USI); | |
91 | SI m32rbf_h_gr_get (SIM_CPU *, UINT); | |
92 | void m32rbf_h_gr_set (SIM_CPU *, UINT, SI); | |
93 | USI m32rbf_h_cr_get (SIM_CPU *, UINT); | |
94 | void m32rbf_h_cr_set (SIM_CPU *, UINT, USI); | |
95 | DI m32rbf_h_accum_get (SIM_CPU *); | |
96 | void m32rbf_h_accum_set (SIM_CPU *, DI); | |
c906108c SS |
97 | BI m32rbf_h_cond_get (SIM_CPU *); |
98 | void m32rbf_h_cond_set (SIM_CPU *, BI); | |
99 | UQI m32rbf_h_psw_get (SIM_CPU *); | |
100 | void m32rbf_h_psw_set (SIM_CPU *, UQI); | |
101 | UQI m32rbf_h_bpsw_get (SIM_CPU *); | |
102 | void m32rbf_h_bpsw_set (SIM_CPU *, UQI); | |
103 | UQI m32rbf_h_bbpsw_get (SIM_CPU *); | |
104 | void m32rbf_h_bbpsw_set (SIM_CPU *, UQI); | |
105 | BI m32rbf_h_lock_get (SIM_CPU *); | |
106 | void m32rbf_h_lock_set (SIM_CPU *, BI); | |
107 | ||
108 | /* These must be hand-written. */ | |
109 | extern CPUREG_FETCH_FN m32rbf_fetch_register; | |
110 | extern CPUREG_STORE_FN m32rbf_store_register; | |
111 | ||
112 | typedef struct { | |
113 | UINT h_gr; | |
114 | } MODEL_M32R_D_DATA; | |
115 | ||
116 | typedef struct { | |
117 | int empty; | |
118 | } MODEL_TEST_DATA; | |
119 | ||
96baa820 JM |
120 | /* Instruction argument buffer. */ |
121 | ||
c906108c | 122 | union sem_fields { |
96baa820 JM |
123 | struct { /* no operands */ |
124 | int empty; | |
125 | } fmt_empty; | |
126 | struct { /* */ | |
127 | UINT f_uimm4; | |
128 | } sfmt_trap; | |
129 | struct { /* */ | |
130 | IADDR i_disp24; | |
131 | unsigned char out_h_gr_14; | |
132 | } sfmt_bl24; | |
133 | struct { /* */ | |
134 | IADDR i_disp8; | |
135 | unsigned char out_h_gr_14; | |
136 | } sfmt_bl8; | |
137 | struct { /* */ | |
138 | SI* i_dr; | |
139 | UINT f_hi16; | |
96baa820 | 140 | UINT f_r1; |
96baa820 | 141 | unsigned char out_dr; |
de8f5985 | 142 | } sfmt_seth; |
96baa820 JM |
143 | struct { /* */ |
144 | ADDR i_uimm24; | |
145 | SI* i_dr; | |
de8f5985 | 146 | UINT f_r1; |
96baa820 JM |
147 | unsigned char out_dr; |
148 | } sfmt_ld24; | |
149 | struct { /* */ | |
150 | SI* i_sr; | |
de8f5985 | 151 | UINT f_r2; |
96baa820 JM |
152 | unsigned char in_sr; |
153 | unsigned char out_h_gr_14; | |
154 | } sfmt_jl; | |
155 | struct { /* */ | |
156 | SI* i_dr; | |
de8f5985 | 157 | UINT f_r1; |
96baa820 JM |
158 | UINT f_uimm5; |
159 | unsigned char in_dr; | |
160 | unsigned char out_dr; | |
161 | } sfmt_slli; | |
162 | struct { /* */ | |
163 | SI* i_dr; | |
164 | INT f_simm8; | |
de8f5985 | 165 | UINT f_r1; |
96baa820 JM |
166 | unsigned char in_dr; |
167 | unsigned char out_dr; | |
168 | } sfmt_addi; | |
169 | struct { /* */ | |
170 | SI* i_src1; | |
171 | SI* i_src2; | |
de8f5985 DB |
172 | UINT f_r1; |
173 | UINT f_r2; | |
96baa820 JM |
174 | unsigned char in_src1; |
175 | unsigned char in_src2; | |
176 | unsigned char out_src2; | |
177 | } sfmt_st_plus; | |
178 | struct { /* */ | |
179 | SI* i_src1; | |
180 | SI* i_src2; | |
181 | INT f_simm16; | |
de8f5985 DB |
182 | UINT f_r1; |
183 | UINT f_r2; | |
96baa820 JM |
184 | unsigned char in_src1; |
185 | unsigned char in_src2; | |
186 | } sfmt_st_d; | |
187 | struct { /* */ | |
188 | SI* i_dr; | |
189 | SI* i_sr; | |
de8f5985 DB |
190 | UINT f_r1; |
191 | UINT f_r2; | |
96baa820 JM |
192 | unsigned char in_sr; |
193 | unsigned char out_dr; | |
194 | unsigned char out_sr; | |
195 | } sfmt_ld_plus; | |
196 | struct { /* */ | |
197 | IADDR i_disp16; | |
198 | SI* i_src1; | |
199 | SI* i_src2; | |
de8f5985 DB |
200 | UINT f_r1; |
201 | UINT f_r2; | |
96baa820 JM |
202 | unsigned char in_src1; |
203 | unsigned char in_src2; | |
204 | } sfmt_beq; | |
205 | struct { /* */ | |
206 | SI* i_dr; | |
207 | SI* i_sr; | |
de8f5985 DB |
208 | UINT f_r1; |
209 | UINT f_r2; | |
96baa820 JM |
210 | UINT f_uimm16; |
211 | unsigned char in_sr; | |
212 | unsigned char out_dr; | |
213 | } sfmt_and3; | |
214 | struct { /* */ | |
215 | SI* i_dr; | |
216 | SI* i_sr; | |
217 | INT f_simm16; | |
de8f5985 DB |
218 | UINT f_r1; |
219 | UINT f_r2; | |
96baa820 JM |
220 | unsigned char in_sr; |
221 | unsigned char out_dr; | |
222 | } sfmt_add3; | |
223 | struct { /* */ | |
224 | SI* i_dr; | |
225 | SI* i_sr; | |
de8f5985 DB |
226 | UINT f_r1; |
227 | UINT f_r2; | |
96baa820 JM |
228 | unsigned char in_dr; |
229 | unsigned char in_sr; | |
230 | unsigned char out_dr; | |
231 | } sfmt_add; | |
c906108c SS |
232 | #if WITH_SCACHE_PBB |
233 | /* Writeback handler. */ | |
234 | struct { | |
235 | /* Pointer to argbuf entry for insn whose results need writing back. */ | |
236 | const struct argbuf *abuf; | |
237 | } write; | |
238 | /* x-before handler */ | |
239 | struct { | |
240 | /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/ | |
241 | int first_p; | |
242 | } before; | |
243 | /* x-after handler */ | |
244 | struct { | |
245 | int empty; | |
246 | } after; | |
247 | /* This entry is used to terminate each pbb. */ | |
248 | struct { | |
249 | /* Number of insns in pbb. */ | |
250 | int insn_count; | |
251 | /* Next pbb to execute. */ | |
252 | SCACHE *next; | |
96baa820 | 253 | SCACHE *branch_target; |
c906108c SS |
254 | } chain; |
255 | #endif | |
256 | }; | |
257 | ||
258 | /* The ARGBUF struct. */ | |
259 | struct argbuf { | |
260 | /* These are the baseclass definitions. */ | |
261 | IADDR addr; | |
262 | const IDESC *idesc; | |
263 | char trace_p; | |
264 | char profile_p; | |
96baa820 JM |
265 | /* ??? Temporary hack for skip insns. */ |
266 | char skip_count; | |
267 | char unused; | |
c906108c SS |
268 | /* cpu specific data follows */ |
269 | union sem semantic; | |
270 | int written; | |
271 | union sem_fields fields; | |
272 | }; | |
273 | ||
274 | /* A cached insn. | |
275 | ||
276 | ??? SCACHE used to contain more than just argbuf. We could delete the | |
277 | type entirely and always just use ARGBUF, but for future concerns and as | |
278 | a level of abstraction it is left in. */ | |
279 | ||
280 | struct scache { | |
281 | struct argbuf argbuf; | |
282 | }; | |
283 | ||
284 | /* Macros to simplify extraction, reading and semantic code. | |
285 | These define and assign the local vars that contain the insn's fields. */ | |
286 | ||
287 | #define EXTRACT_IFMT_EMPTY_VARS \ | |
c906108c SS |
288 | unsigned int length; |
289 | #define EXTRACT_IFMT_EMPTY_CODE \ | |
290 | length = 0; \ | |
291 | ||
292 | #define EXTRACT_IFMT_ADD_VARS \ | |
c906108c SS |
293 | UINT f_op1; \ |
294 | UINT f_r1; \ | |
295 | UINT f_op2; \ | |
296 | UINT f_r2; \ | |
297 | unsigned int length; | |
298 | #define EXTRACT_IFMT_ADD_CODE \ | |
299 | length = 2; \ | |
96baa820 JM |
300 | f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \ |
301 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \ | |
302 | f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \ | |
303 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \ | |
c906108c SS |
304 | |
305 | #define EXTRACT_IFMT_ADD3_VARS \ | |
c906108c SS |
306 | UINT f_op1; \ |
307 | UINT f_r1; \ | |
308 | UINT f_op2; \ | |
309 | UINT f_r2; \ | |
310 | INT f_simm16; \ | |
311 | unsigned int length; | |
312 | #define EXTRACT_IFMT_ADD3_CODE \ | |
313 | length = 4; \ | |
96baa820 JM |
314 | f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \ |
315 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \ | |
316 | f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \ | |
317 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ | |
318 | f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \ | |
c906108c SS |
319 | |
320 | #define EXTRACT_IFMT_AND3_VARS \ | |
c906108c SS |
321 | UINT f_op1; \ |
322 | UINT f_r1; \ | |
323 | UINT f_op2; \ | |
324 | UINT f_r2; \ | |
325 | UINT f_uimm16; \ | |
326 | unsigned int length; | |
327 | #define EXTRACT_IFMT_AND3_CODE \ | |
328 | length = 4; \ | |
96baa820 JM |
329 | f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \ |
330 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \ | |
331 | f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \ | |
332 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ | |
333 | f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \ | |
c906108c SS |
334 | |
335 | #define EXTRACT_IFMT_OR3_VARS \ | |
c906108c SS |
336 | UINT f_op1; \ |
337 | UINT f_r1; \ | |
338 | UINT f_op2; \ | |
339 | UINT f_r2; \ | |
340 | UINT f_uimm16; \ | |
341 | unsigned int length; | |
342 | #define EXTRACT_IFMT_OR3_CODE \ | |
343 | length = 4; \ | |
96baa820 JM |
344 | f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \ |
345 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \ | |
346 | f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \ | |
347 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ | |
348 | f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \ | |
c906108c SS |
349 | |
350 | #define EXTRACT_IFMT_ADDI_VARS \ | |
c906108c SS |
351 | UINT f_op1; \ |
352 | UINT f_r1; \ | |
353 | INT f_simm8; \ | |
354 | unsigned int length; | |
355 | #define EXTRACT_IFMT_ADDI_CODE \ | |
356 | length = 2; \ | |
96baa820 JM |
357 | f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \ |
358 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \ | |
359 | f_simm8 = EXTRACT_MSB0_INT (insn, 16, 8, 8); \ | |
c906108c SS |
360 | |
361 | #define EXTRACT_IFMT_ADDV3_VARS \ | |
c906108c SS |
362 | UINT f_op1; \ |
363 | UINT f_r1; \ | |
364 | UINT f_op2; \ | |
365 | UINT f_r2; \ | |
366 | INT f_simm16; \ | |
367 | unsigned int length; | |
368 | #define EXTRACT_IFMT_ADDV3_CODE \ | |
369 | length = 4; \ | |
96baa820 JM |
370 | f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \ |
371 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \ | |
372 | f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \ | |
373 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ | |
374 | f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \ | |
c906108c SS |
375 | |
376 | #define EXTRACT_IFMT_BC8_VARS \ | |
c906108c SS |
377 | UINT f_op1; \ |
378 | UINT f_r1; \ | |
379 | SI f_disp8; \ | |
380 | unsigned int length; | |
381 | #define EXTRACT_IFMT_BC8_CODE \ | |
382 | length = 2; \ | |
96baa820 JM |
383 | f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \ |
384 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \ | |
385 | f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \ | |
c906108c SS |
386 | |
387 | #define EXTRACT_IFMT_BC24_VARS \ | |
c906108c SS |
388 | UINT f_op1; \ |
389 | UINT f_r1; \ | |
390 | SI f_disp24; \ | |
391 | unsigned int length; | |
392 | #define EXTRACT_IFMT_BC24_CODE \ | |
393 | length = 4; \ | |
96baa820 JM |
394 | f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \ |
395 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \ | |
396 | f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc)); \ | |
c906108c SS |
397 | |
398 | #define EXTRACT_IFMT_BEQ_VARS \ | |
c906108c SS |
399 | UINT f_op1; \ |
400 | UINT f_r1; \ | |
401 | UINT f_op2; \ | |
402 | UINT f_r2; \ | |
403 | SI f_disp16; \ | |
404 | unsigned int length; | |
405 | #define EXTRACT_IFMT_BEQ_CODE \ | |
406 | length = 4; \ | |
96baa820 JM |
407 | f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \ |
408 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \ | |
409 | f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \ | |
410 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ | |
411 | f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc)); \ | |
c906108c SS |
412 | |
413 | #define EXTRACT_IFMT_BEQZ_VARS \ | |
c906108c SS |
414 | UINT f_op1; \ |
415 | UINT f_r1; \ | |
416 | UINT f_op2; \ | |
417 | UINT f_r2; \ | |
418 | SI f_disp16; \ | |
419 | unsigned int length; | |
420 | #define EXTRACT_IFMT_BEQZ_CODE \ | |
421 | length = 4; \ | |
96baa820 JM |
422 | f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \ |
423 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \ | |
424 | f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \ | |
425 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ | |
426 | f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc)); \ | |
c906108c SS |
427 | |
428 | #define EXTRACT_IFMT_CMP_VARS \ | |
c906108c SS |
429 | UINT f_op1; \ |
430 | UINT f_r1; \ | |
431 | UINT f_op2; \ | |
432 | UINT f_r2; \ | |
433 | unsigned int length; | |
434 | #define EXTRACT_IFMT_CMP_CODE \ | |
435 | length = 2; \ | |
96baa820 JM |
436 | f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \ |
437 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \ | |
438 | f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \ | |
439 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \ | |
c906108c SS |
440 | |
441 | #define EXTRACT_IFMT_CMPI_VARS \ | |
c906108c SS |
442 | UINT f_op1; \ |
443 | UINT f_r1; \ | |
444 | UINT f_op2; \ | |
445 | UINT f_r2; \ | |
446 | INT f_simm16; \ | |
447 | unsigned int length; | |
448 | #define EXTRACT_IFMT_CMPI_CODE \ | |
449 | length = 4; \ | |
96baa820 JM |
450 | f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \ |
451 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \ | |
452 | f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \ | |
453 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ | |
454 | f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \ | |
c906108c SS |
455 | |
456 | #define EXTRACT_IFMT_DIV_VARS \ | |
c906108c SS |
457 | UINT f_op1; \ |
458 | UINT f_r1; \ | |
459 | UINT f_op2; \ | |
460 | UINT f_r2; \ | |
461 | INT f_simm16; \ | |
462 | unsigned int length; | |
463 | #define EXTRACT_IFMT_DIV_CODE \ | |
464 | length = 4; \ | |
96baa820 JM |
465 | f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \ |
466 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \ | |
467 | f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \ | |
468 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ | |
469 | f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \ | |
c906108c SS |
470 | |
471 | #define EXTRACT_IFMT_JL_VARS \ | |
c906108c SS |
472 | UINT f_op1; \ |
473 | UINT f_r1; \ | |
474 | UINT f_op2; \ | |
475 | UINT f_r2; \ | |
476 | unsigned int length; | |
477 | #define EXTRACT_IFMT_JL_CODE \ | |
478 | length = 2; \ | |
96baa820 JM |
479 | f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \ |
480 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \ | |
481 | f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \ | |
482 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \ | |
c906108c SS |
483 | |
484 | #define EXTRACT_IFMT_LD24_VARS \ | |
c906108c SS |
485 | UINT f_op1; \ |
486 | UINT f_r1; \ | |
487 | UINT f_uimm24; \ | |
488 | unsigned int length; | |
489 | #define EXTRACT_IFMT_LD24_CODE \ | |
490 | length = 4; \ | |
96baa820 JM |
491 | f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \ |
492 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \ | |
493 | f_uimm24 = EXTRACT_MSB0_UINT (insn, 32, 8, 24); \ | |
c906108c SS |
494 | |
495 | #define EXTRACT_IFMT_LDI16_VARS \ | |
c906108c SS |
496 | UINT f_op1; \ |
497 | UINT f_r1; \ | |
498 | UINT f_op2; \ | |
499 | UINT f_r2; \ | |
500 | INT f_simm16; \ | |
501 | unsigned int length; | |
502 | #define EXTRACT_IFMT_LDI16_CODE \ | |
503 | length = 4; \ | |
96baa820 JM |
504 | f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \ |
505 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \ | |
506 | f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \ | |
507 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ | |
508 | f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \ | |
c906108c SS |
509 | |
510 | #define EXTRACT_IFMT_MVFACHI_VARS \ | |
c906108c SS |
511 | UINT f_op1; \ |
512 | UINT f_r1; \ | |
513 | UINT f_op2; \ | |
514 | UINT f_r2; \ | |
515 | unsigned int length; | |
516 | #define EXTRACT_IFMT_MVFACHI_CODE \ | |
517 | length = 2; \ | |
96baa820 JM |
518 | f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \ |
519 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \ | |
520 | f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \ | |
521 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \ | |
c906108c SS |
522 | |
523 | #define EXTRACT_IFMT_MVFC_VARS \ | |
c906108c SS |
524 | UINT f_op1; \ |
525 | UINT f_r1; \ | |
526 | UINT f_op2; \ | |
527 | UINT f_r2; \ | |
528 | unsigned int length; | |
529 | #define EXTRACT_IFMT_MVFC_CODE \ | |
530 | length = 2; \ | |
96baa820 JM |
531 | f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \ |
532 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \ | |
533 | f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \ | |
534 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \ | |
c906108c SS |
535 | |
536 | #define EXTRACT_IFMT_MVTACHI_VARS \ | |
c906108c SS |
537 | UINT f_op1; \ |
538 | UINT f_r1; \ | |
539 | UINT f_op2; \ | |
540 | UINT f_r2; \ | |
541 | unsigned int length; | |
542 | #define EXTRACT_IFMT_MVTACHI_CODE \ | |
543 | length = 2; \ | |
96baa820 JM |
544 | f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \ |
545 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \ | |
546 | f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \ | |
547 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \ | |
c906108c SS |
548 | |
549 | #define EXTRACT_IFMT_MVTC_VARS \ | |
c906108c SS |
550 | UINT f_op1; \ |
551 | UINT f_r1; \ | |
552 | UINT f_op2; \ | |
553 | UINT f_r2; \ | |
554 | unsigned int length; | |
555 | #define EXTRACT_IFMT_MVTC_CODE \ | |
556 | length = 2; \ | |
96baa820 JM |
557 | f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \ |
558 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \ | |
559 | f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \ | |
560 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \ | |
c906108c SS |
561 | |
562 | #define EXTRACT_IFMT_NOP_VARS \ | |
c906108c SS |
563 | UINT f_op1; \ |
564 | UINT f_r1; \ | |
565 | UINT f_op2; \ | |
566 | UINT f_r2; \ | |
567 | unsigned int length; | |
568 | #define EXTRACT_IFMT_NOP_CODE \ | |
569 | length = 2; \ | |
96baa820 JM |
570 | f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \ |
571 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \ | |
572 | f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \ | |
573 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \ | |
c906108c SS |
574 | |
575 | #define EXTRACT_IFMT_SETH_VARS \ | |
c906108c SS |
576 | UINT f_op1; \ |
577 | UINT f_r1; \ | |
578 | UINT f_op2; \ | |
579 | UINT f_r2; \ | |
580 | UINT f_hi16; \ | |
581 | unsigned int length; | |
582 | #define EXTRACT_IFMT_SETH_CODE \ | |
583 | length = 4; \ | |
96baa820 JM |
584 | f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \ |
585 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \ | |
586 | f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \ | |
587 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ | |
588 | f_hi16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \ | |
c906108c SS |
589 | |
590 | #define EXTRACT_IFMT_SLLI_VARS \ | |
c906108c SS |
591 | UINT f_op1; \ |
592 | UINT f_r1; \ | |
593 | UINT f_shift_op2; \ | |
594 | UINT f_uimm5; \ | |
595 | unsigned int length; | |
596 | #define EXTRACT_IFMT_SLLI_CODE \ | |
597 | length = 2; \ | |
96baa820 JM |
598 | f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \ |
599 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \ | |
600 | f_shift_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 3); \ | |
601 | f_uimm5 = EXTRACT_MSB0_UINT (insn, 16, 11, 5); \ | |
c906108c SS |
602 | |
603 | #define EXTRACT_IFMT_ST_D_VARS \ | |
c906108c SS |
604 | UINT f_op1; \ |
605 | UINT f_r1; \ | |
606 | UINT f_op2; \ | |
607 | UINT f_r2; \ | |
608 | INT f_simm16; \ | |
609 | unsigned int length; | |
610 | #define EXTRACT_IFMT_ST_D_CODE \ | |
611 | length = 4; \ | |
96baa820 JM |
612 | f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \ |
613 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \ | |
614 | f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \ | |
615 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ | |
616 | f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \ | |
c906108c SS |
617 | |
618 | #define EXTRACT_IFMT_TRAP_VARS \ | |
c906108c SS |
619 | UINT f_op1; \ |
620 | UINT f_r1; \ | |
621 | UINT f_op2; \ | |
622 | UINT f_uimm4; \ | |
623 | unsigned int length; | |
624 | #define EXTRACT_IFMT_TRAP_CODE \ | |
625 | length = 2; \ | |
96baa820 JM |
626 | f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \ |
627 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \ | |
628 | f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \ | |
629 | f_uimm4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \ | |
c906108c SS |
630 | |
631 | /* Collection of various things for the trace handler to use. */ | |
632 | ||
633 | typedef struct trace_record { | |
634 | IADDR pc; | |
635 | /* FIXME:wip */ | |
636 | } TRACE_RECORD; | |
637 | ||
638 | #endif /* CPU_M32RBF_H */ |