Commit | Line | Data |
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c906108c SS |
1 | /* CPU family header for m32rbf. |
2 | ||
3 | THIS FILE IS MACHINE GENERATED WITH CGEN. | |
4 | ||
e2882c85 | 5 | Copyright 1996-2018 Free Software Foundation, Inc. |
c906108c | 6 | |
378af1d6 | 7 | This file is part of the GNU simulators. |
c906108c | 8 | |
e9c60591 DE |
9 | This file is free software; you can redistribute it and/or modify |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 3, or (at your option) | |
12 | any later version. | |
c906108c | 13 | |
e9c60591 DE |
14 | It is distributed in the hope that it will be useful, but WITHOUT |
15 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
16 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
17 | License for more details. | |
c906108c | 18 | |
e9c60591 | 19 | You should have received a copy of the GNU General Public License along |
51b318de | 20 | with this program; if not, see <http://www.gnu.org/licenses/>. |
c906108c SS |
21 | |
22 | */ | |
23 | ||
24 | #ifndef CPU_M32RBF_H | |
25 | #define CPU_M32RBF_H | |
26 | ||
27 | /* Maximum number of instructions that are fetched at a time. | |
28 | This is for LIW type instructions sets (e.g. m32r). */ | |
29 | #define MAX_LIW_INSNS 2 | |
30 | ||
31 | /* Maximum number of instructions that can be executed in parallel. */ | |
32 | #define MAX_PARALLEL_INSNS 1 | |
33 | ||
197fa1aa DE |
34 | /* The size of an "int" needed to hold an instruction word. |
35 | This is usually 32 bits, but some architectures needs 64 bits. */ | |
36 | typedef CGEN_INSN_INT CGEN_INSN_WORD; | |
37 | ||
38 | #include "cgen-engine.h" | |
39 | ||
c906108c SS |
40 | /* CPU state information. */ |
41 | typedef struct { | |
42 | /* Hardware elements. */ | |
43 | struct { | |
44 | /* program counter */ | |
45 | USI h_pc; | |
46 | #define GET_H_PC() CPU (h_pc) | |
47 | #define SET_H_PC(x) (CPU (h_pc) = (x)) | |
48 | /* general registers */ | |
49 | SI h_gr[16]; | |
50 | #define GET_H_GR(a1) CPU (h_gr)[a1] | |
51 | #define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x)) | |
52 | /* control registers */ | |
53 | USI h_cr[16]; | |
7a292a7a SS |
54 | #define GET_H_CR(index) m32rbf_h_cr_get_handler (current_cpu, index) |
55 | #define SET_H_CR(index, x) \ | |
56 | do { \ | |
57 | m32rbf_h_cr_set_handler (current_cpu, (index), (x));\ | |
de8f5985 | 58 | ;} while (0) |
c906108c SS |
59 | /* accumulator */ |
60 | DI h_accum; | |
7a292a7a SS |
61 | #define GET_H_ACCUM() m32rbf_h_accum_get_handler (current_cpu) |
62 | #define SET_H_ACCUM(x) \ | |
63 | do { \ | |
64 | m32rbf_h_accum_set_handler (current_cpu, (x));\ | |
de8f5985 | 65 | ;} while (0) |
c906108c SS |
66 | /* condition bit */ |
67 | BI h_cond; | |
68 | #define GET_H_COND() CPU (h_cond) | |
69 | #define SET_H_COND(x) (CPU (h_cond) = (x)) | |
70 | /* psw part of psw */ | |
71 | UQI h_psw; | |
7a292a7a SS |
72 | #define GET_H_PSW() m32rbf_h_psw_get_handler (current_cpu) |
73 | #define SET_H_PSW(x) \ | |
74 | do { \ | |
75 | m32rbf_h_psw_set_handler (current_cpu, (x));\ | |
de8f5985 | 76 | ;} while (0) |
c906108c SS |
77 | /* backup psw */ |
78 | UQI h_bpsw; | |
79 | #define GET_H_BPSW() CPU (h_bpsw) | |
80 | #define SET_H_BPSW(x) (CPU (h_bpsw) = (x)) | |
81 | /* backup bpsw */ | |
82 | UQI h_bbpsw; | |
83 | #define GET_H_BBPSW() CPU (h_bbpsw) | |
84 | #define SET_H_BBPSW(x) (CPU (h_bbpsw) = (x)) | |
85 | /* lock */ | |
86 | BI h_lock; | |
87 | #define GET_H_LOCK() CPU (h_lock) | |
88 | #define SET_H_LOCK(x) (CPU (h_lock) = (x)) | |
89 | } hardware; | |
90 | #define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware) | |
91 | } M32RBF_CPU_DATA; | |
92 | ||
93 | /* Cover fns for register access. */ | |
94 | USI m32rbf_h_pc_get (SIM_CPU *); | |
95 | void m32rbf_h_pc_set (SIM_CPU *, USI); | |
96 | SI m32rbf_h_gr_get (SIM_CPU *, UINT); | |
97 | void m32rbf_h_gr_set (SIM_CPU *, UINT, SI); | |
98 | USI m32rbf_h_cr_get (SIM_CPU *, UINT); | |
99 | void m32rbf_h_cr_set (SIM_CPU *, UINT, USI); | |
100 | DI m32rbf_h_accum_get (SIM_CPU *); | |
101 | void m32rbf_h_accum_set (SIM_CPU *, DI); | |
c906108c SS |
102 | BI m32rbf_h_cond_get (SIM_CPU *); |
103 | void m32rbf_h_cond_set (SIM_CPU *, BI); | |
104 | UQI m32rbf_h_psw_get (SIM_CPU *); | |
105 | void m32rbf_h_psw_set (SIM_CPU *, UQI); | |
106 | UQI m32rbf_h_bpsw_get (SIM_CPU *); | |
107 | void m32rbf_h_bpsw_set (SIM_CPU *, UQI); | |
108 | UQI m32rbf_h_bbpsw_get (SIM_CPU *); | |
109 | void m32rbf_h_bbpsw_set (SIM_CPU *, UQI); | |
110 | BI m32rbf_h_lock_get (SIM_CPU *); | |
111 | void m32rbf_h_lock_set (SIM_CPU *, BI); | |
112 | ||
113 | /* These must be hand-written. */ | |
114 | extern CPUREG_FETCH_FN m32rbf_fetch_register; | |
115 | extern CPUREG_STORE_FN m32rbf_store_register; | |
116 | ||
117 | typedef struct { | |
118 | UINT h_gr; | |
119 | } MODEL_M32R_D_DATA; | |
120 | ||
121 | typedef struct { | |
122 | int empty; | |
123 | } MODEL_TEST_DATA; | |
124 | ||
96baa820 JM |
125 | /* Instruction argument buffer. */ |
126 | ||
c906108c | 127 | union sem_fields { |
96baa820 JM |
128 | struct { /* no operands */ |
129 | int empty; | |
2310652a | 130 | } sfmt_empty; |
16b47b25 NC |
131 | struct { /* */ |
132 | UINT f_uimm8; | |
133 | } sfmt_clrpsw; | |
96baa820 JM |
134 | struct { /* */ |
135 | UINT f_uimm4; | |
136 | } sfmt_trap; | |
137 | struct { /* */ | |
138 | IADDR i_disp24; | |
378af1d6 | 139 | unsigned char out_h_gr_SI_14; |
96baa820 JM |
140 | } sfmt_bl24; |
141 | struct { /* */ | |
142 | IADDR i_disp8; | |
378af1d6 | 143 | unsigned char out_h_gr_SI_14; |
96baa820 JM |
144 | } sfmt_bl8; |
145 | struct { /* */ | |
146 | SI* i_dr; | |
147 | UINT f_hi16; | |
96baa820 | 148 | UINT f_r1; |
96baa820 | 149 | unsigned char out_dr; |
de8f5985 | 150 | } sfmt_seth; |
96baa820 JM |
151 | struct { /* */ |
152 | ADDR i_uimm24; | |
153 | SI* i_dr; | |
de8f5985 | 154 | UINT f_r1; |
96baa820 JM |
155 | unsigned char out_dr; |
156 | } sfmt_ld24; | |
157 | struct { /* */ | |
158 | SI* i_sr; | |
de8f5985 | 159 | UINT f_r2; |
96baa820 | 160 | unsigned char in_sr; |
378af1d6 | 161 | unsigned char out_h_gr_SI_14; |
96baa820 | 162 | } sfmt_jl; |
16b47b25 NC |
163 | struct { /* */ |
164 | SI* i_sr; | |
165 | INT f_simm16; | |
166 | UINT f_r2; | |
167 | UINT f_uimm3; | |
168 | unsigned char in_sr; | |
169 | } sfmt_bset; | |
96baa820 JM |
170 | struct { /* */ |
171 | SI* i_dr; | |
de8f5985 | 172 | UINT f_r1; |
96baa820 JM |
173 | UINT f_uimm5; |
174 | unsigned char in_dr; | |
175 | unsigned char out_dr; | |
176 | } sfmt_slli; | |
177 | struct { /* */ | |
178 | SI* i_dr; | |
179 | INT f_simm8; | |
de8f5985 | 180 | UINT f_r1; |
96baa820 JM |
181 | unsigned char in_dr; |
182 | unsigned char out_dr; | |
183 | } sfmt_addi; | |
184 | struct { /* */ | |
185 | SI* i_src1; | |
186 | SI* i_src2; | |
de8f5985 DB |
187 | UINT f_r1; |
188 | UINT f_r2; | |
96baa820 JM |
189 | unsigned char in_src1; |
190 | unsigned char in_src2; | |
191 | unsigned char out_src2; | |
192 | } sfmt_st_plus; | |
193 | struct { /* */ | |
194 | SI* i_src1; | |
195 | SI* i_src2; | |
196 | INT f_simm16; | |
de8f5985 DB |
197 | UINT f_r1; |
198 | UINT f_r2; | |
96baa820 JM |
199 | unsigned char in_src1; |
200 | unsigned char in_src2; | |
201 | } sfmt_st_d; | |
202 | struct { /* */ | |
203 | SI* i_dr; | |
204 | SI* i_sr; | |
de8f5985 DB |
205 | UINT f_r1; |
206 | UINT f_r2; | |
96baa820 JM |
207 | unsigned char in_sr; |
208 | unsigned char out_dr; | |
209 | unsigned char out_sr; | |
210 | } sfmt_ld_plus; | |
211 | struct { /* */ | |
212 | IADDR i_disp16; | |
213 | SI* i_src1; | |
214 | SI* i_src2; | |
de8f5985 DB |
215 | UINT f_r1; |
216 | UINT f_r2; | |
96baa820 JM |
217 | unsigned char in_src1; |
218 | unsigned char in_src2; | |
219 | } sfmt_beq; | |
220 | struct { /* */ | |
221 | SI* i_dr; | |
222 | SI* i_sr; | |
de8f5985 DB |
223 | UINT f_r1; |
224 | UINT f_r2; | |
96baa820 JM |
225 | UINT f_uimm16; |
226 | unsigned char in_sr; | |
227 | unsigned char out_dr; | |
228 | } sfmt_and3; | |
229 | struct { /* */ | |
230 | SI* i_dr; | |
231 | SI* i_sr; | |
232 | INT f_simm16; | |
de8f5985 DB |
233 | UINT f_r1; |
234 | UINT f_r2; | |
96baa820 JM |
235 | unsigned char in_sr; |
236 | unsigned char out_dr; | |
237 | } sfmt_add3; | |
238 | struct { /* */ | |
239 | SI* i_dr; | |
240 | SI* i_sr; | |
de8f5985 DB |
241 | UINT f_r1; |
242 | UINT f_r2; | |
96baa820 JM |
243 | unsigned char in_dr; |
244 | unsigned char in_sr; | |
245 | unsigned char out_dr; | |
246 | } sfmt_add; | |
c906108c SS |
247 | #if WITH_SCACHE_PBB |
248 | /* Writeback handler. */ | |
249 | struct { | |
250 | /* Pointer to argbuf entry for insn whose results need writing back. */ | |
251 | const struct argbuf *abuf; | |
252 | } write; | |
253 | /* x-before handler */ | |
254 | struct { | |
255 | /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/ | |
256 | int first_p; | |
257 | } before; | |
258 | /* x-after handler */ | |
259 | struct { | |
260 | int empty; | |
261 | } after; | |
262 | /* This entry is used to terminate each pbb. */ | |
263 | struct { | |
264 | /* Number of insns in pbb. */ | |
265 | int insn_count; | |
266 | /* Next pbb to execute. */ | |
267 | SCACHE *next; | |
96baa820 | 268 | SCACHE *branch_target; |
c906108c SS |
269 | } chain; |
270 | #endif | |
271 | }; | |
272 | ||
273 | /* The ARGBUF struct. */ | |
274 | struct argbuf { | |
275 | /* These are the baseclass definitions. */ | |
276 | IADDR addr; | |
277 | const IDESC *idesc; | |
278 | char trace_p; | |
279 | char profile_p; | |
96baa820 JM |
280 | /* ??? Temporary hack for skip insns. */ |
281 | char skip_count; | |
282 | char unused; | |
c906108c SS |
283 | /* cpu specific data follows */ |
284 | union sem semantic; | |
285 | int written; | |
286 | union sem_fields fields; | |
287 | }; | |
288 | ||
289 | /* A cached insn. | |
290 | ||
291 | ??? SCACHE used to contain more than just argbuf. We could delete the | |
292 | type entirely and always just use ARGBUF, but for future concerns and as | |
293 | a level of abstraction it is left in. */ | |
294 | ||
295 | struct scache { | |
296 | struct argbuf argbuf; | |
297 | }; | |
298 | ||
299 | /* Macros to simplify extraction, reading and semantic code. | |
300 | These define and assign the local vars that contain the insn's fields. */ | |
301 | ||
302 | #define EXTRACT_IFMT_EMPTY_VARS \ | |
c906108c SS |
303 | unsigned int length; |
304 | #define EXTRACT_IFMT_EMPTY_CODE \ | |
305 | length = 0; \ | |
306 | ||
307 | #define EXTRACT_IFMT_ADD_VARS \ | |
c906108c SS |
308 | UINT f_op1; \ |
309 | UINT f_r1; \ | |
310 | UINT f_op2; \ | |
311 | UINT f_r2; \ | |
312 | unsigned int length; | |
313 | #define EXTRACT_IFMT_ADD_CODE \ | |
314 | length = 2; \ | |
96baa820 JM |
315 | f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \ |
316 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \ | |
317 | f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \ | |
318 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \ | |
c906108c SS |
319 | |
320 | #define EXTRACT_IFMT_ADD3_VARS \ | |
c906108c SS |
321 | UINT f_op1; \ |
322 | UINT f_r1; \ | |
323 | UINT f_op2; \ | |
324 | UINT f_r2; \ | |
325 | INT f_simm16; \ | |
326 | unsigned int length; | |
327 | #define EXTRACT_IFMT_ADD3_CODE \ | |
328 | length = 4; \ | |
96baa820 JM |
329 | f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \ |
330 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \ | |
331 | f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \ | |
332 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ | |
62836bf4 | 333 | f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \ |
c906108c SS |
334 | |
335 | #define EXTRACT_IFMT_AND3_VARS \ | |
c906108c SS |
336 | UINT f_op1; \ |
337 | UINT f_r1; \ | |
338 | UINT f_op2; \ | |
339 | UINT f_r2; \ | |
340 | UINT f_uimm16; \ | |
341 | unsigned int length; | |
342 | #define EXTRACT_IFMT_AND3_CODE \ | |
343 | length = 4; \ | |
96baa820 JM |
344 | f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \ |
345 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \ | |
346 | f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \ | |
347 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ | |
348 | f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \ | |
c906108c SS |
349 | |
350 | #define EXTRACT_IFMT_OR3_VARS \ | |
c906108c SS |
351 | UINT f_op1; \ |
352 | UINT f_r1; \ | |
353 | UINT f_op2; \ | |
354 | UINT f_r2; \ | |
355 | UINT f_uimm16; \ | |
356 | unsigned int length; | |
357 | #define EXTRACT_IFMT_OR3_CODE \ | |
358 | length = 4; \ | |
96baa820 JM |
359 | f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \ |
360 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \ | |
361 | f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \ | |
362 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ | |
363 | f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \ | |
c906108c SS |
364 | |
365 | #define EXTRACT_IFMT_ADDI_VARS \ | |
c906108c SS |
366 | UINT f_op1; \ |
367 | UINT f_r1; \ | |
368 | INT f_simm8; \ | |
369 | unsigned int length; | |
370 | #define EXTRACT_IFMT_ADDI_CODE \ | |
371 | length = 2; \ | |
96baa820 JM |
372 | f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \ |
373 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \ | |
62836bf4 | 374 | f_simm8 = EXTRACT_MSB0_SINT (insn, 16, 8, 8); \ |
c906108c SS |
375 | |
376 | #define EXTRACT_IFMT_ADDV3_VARS \ | |
c906108c SS |
377 | UINT f_op1; \ |
378 | UINT f_r1; \ | |
379 | UINT f_op2; \ | |
380 | UINT f_r2; \ | |
381 | INT f_simm16; \ | |
382 | unsigned int length; | |
383 | #define EXTRACT_IFMT_ADDV3_CODE \ | |
384 | length = 4; \ | |
96baa820 JM |
385 | f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \ |
386 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \ | |
387 | f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \ | |
388 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ | |
62836bf4 | 389 | f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \ |
c906108c SS |
390 | |
391 | #define EXTRACT_IFMT_BC8_VARS \ | |
c906108c SS |
392 | UINT f_op1; \ |
393 | UINT f_r1; \ | |
394 | SI f_disp8; \ | |
395 | unsigned int length; | |
396 | #define EXTRACT_IFMT_BC8_CODE \ | |
397 | length = 2; \ | |
96baa820 JM |
398 | f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \ |
399 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \ | |
62836bf4 | 400 | f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \ |
c906108c SS |
401 | |
402 | #define EXTRACT_IFMT_BC24_VARS \ | |
c906108c SS |
403 | UINT f_op1; \ |
404 | UINT f_r1; \ | |
405 | SI f_disp24; \ | |
406 | unsigned int length; | |
407 | #define EXTRACT_IFMT_BC24_CODE \ | |
408 | length = 4; \ | |
96baa820 JM |
409 | f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \ |
410 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \ | |
62836bf4 | 411 | f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) << (2))) + (pc)); \ |
c906108c SS |
412 | |
413 | #define EXTRACT_IFMT_BEQ_VARS \ | |
c906108c SS |
414 | UINT f_op1; \ |
415 | UINT f_r1; \ | |
416 | UINT f_op2; \ | |
417 | UINT f_r2; \ | |
418 | SI f_disp16; \ | |
419 | unsigned int length; | |
420 | #define EXTRACT_IFMT_BEQ_CODE \ | |
421 | length = 4; \ | |
96baa820 JM |
422 | f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \ |
423 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \ | |
424 | f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \ | |
425 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ | |
62836bf4 | 426 | f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) << (2))) + (pc)); \ |
c906108c SS |
427 | |
428 | #define EXTRACT_IFMT_BEQZ_VARS \ | |
c906108c SS |
429 | UINT f_op1; \ |
430 | UINT f_r1; \ | |
431 | UINT f_op2; \ | |
432 | UINT f_r2; \ | |
433 | SI f_disp16; \ | |
434 | unsigned int length; | |
435 | #define EXTRACT_IFMT_BEQZ_CODE \ | |
436 | length = 4; \ | |
96baa820 JM |
437 | f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \ |
438 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \ | |
439 | f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \ | |
440 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ | |
62836bf4 | 441 | f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) << (2))) + (pc)); \ |
c906108c SS |
442 | |
443 | #define EXTRACT_IFMT_CMP_VARS \ | |
c906108c SS |
444 | UINT f_op1; \ |
445 | UINT f_r1; \ | |
446 | UINT f_op2; \ | |
447 | UINT f_r2; \ | |
448 | unsigned int length; | |
449 | #define EXTRACT_IFMT_CMP_CODE \ | |
450 | length = 2; \ | |
96baa820 JM |
451 | f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \ |
452 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \ | |
453 | f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \ | |
454 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \ | |
c906108c SS |
455 | |
456 | #define EXTRACT_IFMT_CMPI_VARS \ | |
c906108c SS |
457 | UINT f_op1; \ |
458 | UINT f_r1; \ | |
459 | UINT f_op2; \ | |
460 | UINT f_r2; \ | |
461 | INT f_simm16; \ | |
462 | unsigned int length; | |
463 | #define EXTRACT_IFMT_CMPI_CODE \ | |
464 | length = 4; \ | |
96baa820 JM |
465 | f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \ |
466 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \ | |
467 | f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \ | |
468 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ | |
62836bf4 | 469 | f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \ |
c906108c SS |
470 | |
471 | #define EXTRACT_IFMT_DIV_VARS \ | |
c906108c SS |
472 | UINT f_op1; \ |
473 | UINT f_r1; \ | |
474 | UINT f_op2; \ | |
475 | UINT f_r2; \ | |
476 | INT f_simm16; \ | |
477 | unsigned int length; | |
478 | #define EXTRACT_IFMT_DIV_CODE \ | |
479 | length = 4; \ | |
96baa820 JM |
480 | f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \ |
481 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \ | |
482 | f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \ | |
483 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ | |
62836bf4 | 484 | f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \ |
c906108c SS |
485 | |
486 | #define EXTRACT_IFMT_JL_VARS \ | |
c906108c SS |
487 | UINT f_op1; \ |
488 | UINT f_r1; \ | |
489 | UINT f_op2; \ | |
490 | UINT f_r2; \ | |
491 | unsigned int length; | |
492 | #define EXTRACT_IFMT_JL_CODE \ | |
493 | length = 2; \ | |
96baa820 JM |
494 | f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \ |
495 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \ | |
496 | f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \ | |
497 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \ | |
c906108c SS |
498 | |
499 | #define EXTRACT_IFMT_LD24_VARS \ | |
c906108c SS |
500 | UINT f_op1; \ |
501 | UINT f_r1; \ | |
502 | UINT f_uimm24; \ | |
503 | unsigned int length; | |
504 | #define EXTRACT_IFMT_LD24_CODE \ | |
505 | length = 4; \ | |
96baa820 JM |
506 | f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \ |
507 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \ | |
508 | f_uimm24 = EXTRACT_MSB0_UINT (insn, 32, 8, 24); \ | |
c906108c SS |
509 | |
510 | #define EXTRACT_IFMT_LDI16_VARS \ | |
c906108c SS |
511 | UINT f_op1; \ |
512 | UINT f_r1; \ | |
513 | UINT f_op2; \ | |
514 | UINT f_r2; \ | |
515 | INT f_simm16; \ | |
516 | unsigned int length; | |
517 | #define EXTRACT_IFMT_LDI16_CODE \ | |
518 | length = 4; \ | |
96baa820 JM |
519 | f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \ |
520 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \ | |
521 | f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \ | |
522 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ | |
62836bf4 | 523 | f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \ |
c906108c SS |
524 | |
525 | #define EXTRACT_IFMT_MVFACHI_VARS \ | |
c906108c SS |
526 | UINT f_op1; \ |
527 | UINT f_r1; \ | |
528 | UINT f_op2; \ | |
529 | UINT f_r2; \ | |
530 | unsigned int length; | |
531 | #define EXTRACT_IFMT_MVFACHI_CODE \ | |
532 | length = 2; \ | |
96baa820 JM |
533 | f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \ |
534 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \ | |
535 | f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \ | |
536 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \ | |
c906108c SS |
537 | |
538 | #define EXTRACT_IFMT_MVFC_VARS \ | |
c906108c SS |
539 | UINT f_op1; \ |
540 | UINT f_r1; \ | |
541 | UINT f_op2; \ | |
542 | UINT f_r2; \ | |
543 | unsigned int length; | |
544 | #define EXTRACT_IFMT_MVFC_CODE \ | |
545 | length = 2; \ | |
96baa820 JM |
546 | f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \ |
547 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \ | |
548 | f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \ | |
549 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \ | |
c906108c SS |
550 | |
551 | #define EXTRACT_IFMT_MVTACHI_VARS \ | |
c906108c SS |
552 | UINT f_op1; \ |
553 | UINT f_r1; \ | |
554 | UINT f_op2; \ | |
555 | UINT f_r2; \ | |
556 | unsigned int length; | |
557 | #define EXTRACT_IFMT_MVTACHI_CODE \ | |
558 | length = 2; \ | |
96baa820 JM |
559 | f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \ |
560 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \ | |
561 | f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \ | |
562 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \ | |
c906108c SS |
563 | |
564 | #define EXTRACT_IFMT_MVTC_VARS \ | |
c906108c SS |
565 | UINT f_op1; \ |
566 | UINT f_r1; \ | |
567 | UINT f_op2; \ | |
568 | UINT f_r2; \ | |
569 | unsigned int length; | |
570 | #define EXTRACT_IFMT_MVTC_CODE \ | |
571 | length = 2; \ | |
96baa820 JM |
572 | f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \ |
573 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \ | |
574 | f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \ | |
575 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \ | |
c906108c SS |
576 | |
577 | #define EXTRACT_IFMT_NOP_VARS \ | |
c906108c SS |
578 | UINT f_op1; \ |
579 | UINT f_r1; \ | |
580 | UINT f_op2; \ | |
581 | UINT f_r2; \ | |
582 | unsigned int length; | |
583 | #define EXTRACT_IFMT_NOP_CODE \ | |
584 | length = 2; \ | |
96baa820 JM |
585 | f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \ |
586 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \ | |
587 | f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \ | |
588 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \ | |
c906108c SS |
589 | |
590 | #define EXTRACT_IFMT_SETH_VARS \ | |
c906108c SS |
591 | UINT f_op1; \ |
592 | UINT f_r1; \ | |
593 | UINT f_op2; \ | |
594 | UINT f_r2; \ | |
595 | UINT f_hi16; \ | |
596 | unsigned int length; | |
597 | #define EXTRACT_IFMT_SETH_CODE \ | |
598 | length = 4; \ | |
96baa820 JM |
599 | f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \ |
600 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \ | |
601 | f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \ | |
602 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ | |
603 | f_hi16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \ | |
c906108c SS |
604 | |
605 | #define EXTRACT_IFMT_SLLI_VARS \ | |
c906108c SS |
606 | UINT f_op1; \ |
607 | UINT f_r1; \ | |
608 | UINT f_shift_op2; \ | |
609 | UINT f_uimm5; \ | |
610 | unsigned int length; | |
611 | #define EXTRACT_IFMT_SLLI_CODE \ | |
612 | length = 2; \ | |
96baa820 JM |
613 | f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \ |
614 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \ | |
615 | f_shift_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 3); \ | |
616 | f_uimm5 = EXTRACT_MSB0_UINT (insn, 16, 11, 5); \ | |
c906108c SS |
617 | |
618 | #define EXTRACT_IFMT_ST_D_VARS \ | |
c906108c SS |
619 | UINT f_op1; \ |
620 | UINT f_r1; \ | |
621 | UINT f_op2; \ | |
622 | UINT f_r2; \ | |
623 | INT f_simm16; \ | |
624 | unsigned int length; | |
625 | #define EXTRACT_IFMT_ST_D_CODE \ | |
626 | length = 4; \ | |
96baa820 JM |
627 | f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \ |
628 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \ | |
629 | f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \ | |
630 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ | |
62836bf4 | 631 | f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \ |
c906108c SS |
632 | |
633 | #define EXTRACT_IFMT_TRAP_VARS \ | |
c906108c SS |
634 | UINT f_op1; \ |
635 | UINT f_r1; \ | |
636 | UINT f_op2; \ | |
637 | UINT f_uimm4; \ | |
638 | unsigned int length; | |
639 | #define EXTRACT_IFMT_TRAP_CODE \ | |
640 | length = 2; \ | |
96baa820 JM |
641 | f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \ |
642 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \ | |
643 | f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \ | |
644 | f_uimm4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \ | |
c906108c | 645 | |
16b47b25 NC |
646 | #define EXTRACT_IFMT_CLRPSW_VARS \ |
647 | UINT f_op1; \ | |
648 | UINT f_r1; \ | |
649 | UINT f_uimm8; \ | |
650 | unsigned int length; | |
651 | #define EXTRACT_IFMT_CLRPSW_CODE \ | |
652 | length = 2; \ | |
653 | f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \ | |
654 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \ | |
655 | f_uimm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \ | |
656 | ||
657 | #define EXTRACT_IFMT_BSET_VARS \ | |
658 | UINT f_op1; \ | |
659 | UINT f_bit4; \ | |
660 | UINT f_uimm3; \ | |
661 | UINT f_op2; \ | |
662 | UINT f_r2; \ | |
663 | INT f_simm16; \ | |
664 | unsigned int length; | |
665 | #define EXTRACT_IFMT_BSET_CODE \ | |
666 | length = 4; \ | |
667 | f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \ | |
668 | f_bit4 = EXTRACT_MSB0_UINT (insn, 32, 4, 1); \ | |
669 | f_uimm3 = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \ | |
670 | f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \ | |
671 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ | |
62836bf4 | 672 | f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \ |
16b47b25 NC |
673 | |
674 | #define EXTRACT_IFMT_BTST_VARS \ | |
675 | UINT f_op1; \ | |
676 | UINT f_bit4; \ | |
677 | UINT f_uimm3; \ | |
678 | UINT f_op2; \ | |
679 | UINT f_r2; \ | |
680 | unsigned int length; | |
681 | #define EXTRACT_IFMT_BTST_CODE \ | |
682 | length = 2; \ | |
683 | f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \ | |
684 | f_bit4 = EXTRACT_MSB0_UINT (insn, 16, 4, 1); \ | |
685 | f_uimm3 = EXTRACT_MSB0_UINT (insn, 16, 5, 3); \ | |
686 | f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \ | |
687 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \ | |
688 | ||
c906108c SS |
689 | /* Collection of various things for the trace handler to use. */ |
690 | ||
691 | typedef struct trace_record { | |
692 | IADDR pc; | |
693 | /* FIXME:wip */ | |
694 | } TRACE_RECORD; | |
695 | ||
696 | #endif /* CPU_M32RBF_H */ |