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2008-12-15 Paul Pluzhnikov <ppluzhnikov@google.com>
[deliverable/binutils-gdb.git] / sim / m32r / cpu.h
CommitLineData
c906108c
SS		 1/* CPU family header for m32rbf.
2
3THIS FILE IS MACHINE GENERATED WITH CGEN.
4
16b47b25 5Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
c906108c 6
378af1d6 7This file is part of the GNU simulators.
c906108c
SS		 8
9This program is free software; you can redistribute it and/or modify
10it under the terms of the GNU General Public License as published by
4744ac1b
JB		 11the Free Software Foundation; either version 3 of the License, or
12(at your option) any later version.
c906108c
SS		 13
14This program is distributed in the hope that it will be useful,
15but WITHOUT ANY WARRANTY; without even the implied warranty of
16MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17GNU General Public License for more details.
18
4744ac1b
JB		 19You should have received a copy of the GNU General Public License
20along with this program. If not, see <http://www.gnu.org/licenses/>.
c906108c
SS		 21
22*/
23
24#ifndef CPU_M32RBF_H
25#define CPU_M32RBF_H
26
27/* Maximum number of instructions that are fetched at a time.
28 This is for LIW type instructions sets (e.g. m32r). */
29#define MAX_LIW_INSNS 2
30
31/* Maximum number of instructions that can be executed in parallel. */
32#define MAX_PARALLEL_INSNS 1
33
34/* CPU state information. */
35typedef struct {
36 /* Hardware elements. */
37 struct {
38 /* program counter */
39 USI h_pc;
40#define GET_H_PC() CPU (h_pc)
41#define SET_H_PC(x) (CPU (h_pc) = (x))
42 /* general registers */
43 SI h_gr[16];
44#define GET_H_GR(a1) CPU (h_gr)[a1]
45#define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
46 /* control registers */
47 USI h_cr[16];
7a292a7a
SS		 48#define GET_H_CR(index) m32rbf_h_cr_get_handler (current_cpu, index)
49#define SET_H_CR(index, x) \
50do { \
51m32rbf_h_cr_set_handler (current_cpu, (index), (x));\
de8f5985 52;} while (0)
c906108c
SS		 53 /* accumulator */
54 DI h_accum;
7a292a7a
SS		 55#define GET_H_ACCUM() m32rbf_h_accum_get_handler (current_cpu)
56#define SET_H_ACCUM(x) \
57do { \
58m32rbf_h_accum_set_handler (current_cpu, (x));\
de8f5985 59;} while (0)
c906108c
SS		 60 /* condition bit */
61 BI h_cond;
62#define GET_H_COND() CPU (h_cond)
63#define SET_H_COND(x) (CPU (h_cond) = (x))
64 /* psw part of psw */
65 UQI h_psw;
7a292a7a
SS		 66#define GET_H_PSW() m32rbf_h_psw_get_handler (current_cpu)
67#define SET_H_PSW(x) \
68do { \
69m32rbf_h_psw_set_handler (current_cpu, (x));\
de8f5985 70;} while (0)
c906108c
SS		 71 /* backup psw */
72 UQI h_bpsw;
73#define GET_H_BPSW() CPU (h_bpsw)
74#define SET_H_BPSW(x) (CPU (h_bpsw) = (x))
75 /* backup bpsw */
76 UQI h_bbpsw;
77#define GET_H_BBPSW() CPU (h_bbpsw)
78#define SET_H_BBPSW(x) (CPU (h_bbpsw) = (x))
79 /* lock */
80 BI h_lock;
81#define GET_H_LOCK() CPU (h_lock)
82#define SET_H_LOCK(x) (CPU (h_lock) = (x))
83 } hardware;
84#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
85} M32RBF_CPU_DATA;
86
87/* Cover fns for register access. */
88USI m32rbf_h_pc_get (SIM_CPU *);
89void m32rbf_h_pc_set (SIM_CPU *, USI);
90SI m32rbf_h_gr_get (SIM_CPU *, UINT);
91void m32rbf_h_gr_set (SIM_CPU *, UINT, SI);
92USI m32rbf_h_cr_get (SIM_CPU *, UINT);
93void m32rbf_h_cr_set (SIM_CPU *, UINT, USI);
94DI m32rbf_h_accum_get (SIM_CPU *);
95void m32rbf_h_accum_set (SIM_CPU *, DI);
c906108c
SS		 96BI m32rbf_h_cond_get (SIM_CPU *);
97void m32rbf_h_cond_set (SIM_CPU *, BI);
98UQI m32rbf_h_psw_get (SIM_CPU *);
99void m32rbf_h_psw_set (SIM_CPU *, UQI);
100UQI m32rbf_h_bpsw_get (SIM_CPU *);
101void m32rbf_h_bpsw_set (SIM_CPU *, UQI);
102UQI m32rbf_h_bbpsw_get (SIM_CPU *);
103void m32rbf_h_bbpsw_set (SIM_CPU *, UQI);
104BI m32rbf_h_lock_get (SIM_CPU *);
105void m32rbf_h_lock_set (SIM_CPU *, BI);
106
107/* These must be hand-written. */
108extern CPUREG_FETCH_FN m32rbf_fetch_register;
109extern CPUREG_STORE_FN m32rbf_store_register;
110
111typedef struct {
112 UINT h_gr;
113} MODEL_M32R_D_DATA;
114
115typedef struct {
116 int empty;
117} MODEL_TEST_DATA;
118
96baa820
JM		 119/* Instruction argument buffer. */
120
c906108c 121union sem_fields {
96baa820
JM		 122 struct { /* no operands */
123 int empty;
124 } fmt_empty;
16b47b25
NC		 125 struct { /* */
126 UINT f_uimm8;
127 } sfmt_clrpsw;
96baa820
JM		 128 struct { /* */
129 UINT f_uimm4;
130 } sfmt_trap;
131 struct { /* */
132 IADDR i_disp24;
378af1d6 133 unsigned char out_h_gr_SI_14;
96baa820
JM		 134 } sfmt_bl24;
135 struct { /* */
136 IADDR i_disp8;
378af1d6 137 unsigned char out_h_gr_SI_14;
96baa820
JM		 138 } sfmt_bl8;
139 struct { /* */
140 SI* i_dr;
141 UINT f_hi16;
96baa820 142 UINT f_r1;
96baa820 143 unsigned char out_dr;
de8f5985 144 } sfmt_seth;
96baa820
JM		 145 struct { /* */
146 ADDR i_uimm24;
147 SI* i_dr;
de8f5985 148 UINT f_r1;
96baa820
JM		 149 unsigned char out_dr;
150 } sfmt_ld24;
151 struct { /* */
152 SI* i_sr;
de8f5985 153 UINT f_r2;
96baa820 154 unsigned char in_sr;
378af1d6 155 unsigned char out_h_gr_SI_14;
96baa820 156 } sfmt_jl;
16b47b25
NC		 157 struct { /* */
158 SI* i_sr;
159 INT f_simm16;
160 UINT f_r2;
161 UINT f_uimm3;
162 unsigned char in_sr;
163 } sfmt_bset;
96baa820
JM		 164 struct { /* */
165 SI* i_dr;
de8f5985 166 UINT f_r1;
96baa820
JM		 167 UINT f_uimm5;
168 unsigned char in_dr;
169 unsigned char out_dr;
170 } sfmt_slli;
171 struct { /* */
172 SI* i_dr;
173 INT f_simm8;
de8f5985 174 UINT f_r1;
96baa820
JM		 175 unsigned char in_dr;
176 unsigned char out_dr;
177 } sfmt_addi;
178 struct { /* */
179 SI* i_src1;
180 SI* i_src2;
de8f5985
DB		 181 UINT f_r1;
182 UINT f_r2;
96baa820
JM		 183 unsigned char in_src1;
184 unsigned char in_src2;
185 unsigned char out_src2;
186 } sfmt_st_plus;
187 struct { /* */
188 SI* i_src1;
189 SI* i_src2;
190 INT f_simm16;
de8f5985
DB		 191 UINT f_r1;
192 UINT f_r2;
96baa820
JM		 193 unsigned char in_src1;
194 unsigned char in_src2;
195 } sfmt_st_d;
196 struct { /* */
197 SI* i_dr;
198 SI* i_sr;
de8f5985
DB		 199 UINT f_r1;
200 UINT f_r2;
96baa820
JM		 201 unsigned char in_sr;
202 unsigned char out_dr;
203 unsigned char out_sr;
204 } sfmt_ld_plus;
205 struct { /* */
206 IADDR i_disp16;
207 SI* i_src1;
208 SI* i_src2;
de8f5985
DB		 209 UINT f_r1;
210 UINT f_r2;
96baa820
JM		 211 unsigned char in_src1;
212 unsigned char in_src2;
213 } sfmt_beq;
214 struct { /* */
215 SI* i_dr;
216 SI* i_sr;
de8f5985
DB		 217 UINT f_r1;
218 UINT f_r2;
96baa820
JM		 219 UINT f_uimm16;
220 unsigned char in_sr;
221 unsigned char out_dr;
222 } sfmt_and3;
223 struct { /* */
224 SI* i_dr;
225 SI* i_sr;
226 INT f_simm16;
de8f5985
DB		 227 UINT f_r1;
228 UINT f_r2;
96baa820
JM		 229 unsigned char in_sr;
230 unsigned char out_dr;
231 } sfmt_add3;
232 struct { /* */
233 SI* i_dr;
234 SI* i_sr;
de8f5985
DB		 235 UINT f_r1;
236 UINT f_r2;
96baa820
JM		 237 unsigned char in_dr;
238 unsigned char in_sr;
239 unsigned char out_dr;
240 } sfmt_add;
c906108c
SS		 241#if WITH_SCACHE_PBB
242 /* Writeback handler. */
243 struct {
244 /* Pointer to argbuf entry for insn whose results need writing back. */
245 const struct argbuf *abuf;
246 } write;
247 /* x-before handler */
248 struct {
249 /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
250 int first_p;
251 } before;
252 /* x-after handler */
253 struct {
254 int empty;
255 } after;
256 /* This entry is used to terminate each pbb. */
257 struct {
258 /* Number of insns in pbb. */
259 int insn_count;
260 /* Next pbb to execute. */
261 SCACHE *next;
96baa820 262 SCACHE *branch_target;
c906108c
SS		 263 } chain;
264#endif
265};
266
267/* The ARGBUF struct. */
268struct argbuf {
269 /* These are the baseclass definitions. */
270 IADDR addr;
271 const IDESC *idesc;
272 char trace_p;
273 char profile_p;
96baa820
JM		 274 /* ??? Temporary hack for skip insns. */
275 char skip_count;
276 char unused;
c906108c
SS		 277 /* cpu specific data follows */
278 union sem semantic;
279 int written;
280 union sem_fields fields;
281};
282
283/* A cached insn.
284
285 ??? SCACHE used to contain more than just argbuf. We could delete the
286 type entirely and always just use ARGBUF, but for future concerns and as
287 a level of abstraction it is left in. */
288
289struct scache {
290 struct argbuf argbuf;
291};
292
293/* Macros to simplify extraction, reading and semantic code.
294 These define and assign the local vars that contain the insn's fields. */
295
296#define EXTRACT_IFMT_EMPTY_VARS \
c906108c
SS		 297 unsigned int length;
298#define EXTRACT_IFMT_EMPTY_CODE \
299 length = 0; \
300
301#define EXTRACT_IFMT_ADD_VARS \
c906108c
SS		 302 UINT f_op1; \
303 UINT f_r1; \
304 UINT f_op2; \
305 UINT f_r2; \
306 unsigned int length;
307#define EXTRACT_IFMT_ADD_CODE \
308 length = 2; \
96baa820
JM		 309 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
310 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
311 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
312 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
c906108c
SS		 313
314#define EXTRACT_IFMT_ADD3_VARS \
c906108c
SS		 315 UINT f_op1; \
316 UINT f_r1; \
317 UINT f_op2; \
318 UINT f_r2; \
319 INT f_simm16; \
320 unsigned int length;
321#define EXTRACT_IFMT_ADD3_CODE \
322 length = 4; \
96baa820
JM		 323 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
324 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
325 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
326 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
327 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
c906108c
SS		 328
329#define EXTRACT_IFMT_AND3_VARS \
c906108c
SS		 330 UINT f_op1; \
331 UINT f_r1; \
332 UINT f_op2; \
333 UINT f_r2; \
334 UINT f_uimm16; \
335 unsigned int length;
336#define EXTRACT_IFMT_AND3_CODE \
337 length = 4; \
96baa820
JM		 338 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
339 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
340 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
341 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
342 f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
c906108c
SS		 343
344#define EXTRACT_IFMT_OR3_VARS \
c906108c
SS		 345 UINT f_op1; \
346 UINT f_r1; \
347 UINT f_op2; \
348 UINT f_r2; \
349 UINT f_uimm16; \
350 unsigned int length;
351#define EXTRACT_IFMT_OR3_CODE \
352 length = 4; \
96baa820
JM		 353 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
354 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
355 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
356 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
357 f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
c906108c
SS		 358
359#define EXTRACT_IFMT_ADDI_VARS \
c906108c
SS		 360 UINT f_op1; \
361 UINT f_r1; \
362 INT f_simm8; \
363 unsigned int length;
364#define EXTRACT_IFMT_ADDI_CODE \
365 length = 2; \
96baa820
JM		 366 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
367 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
368 f_simm8 = EXTRACT_MSB0_INT (insn, 16, 8, 8); \
c906108c
SS		 369
370#define EXTRACT_IFMT_ADDV3_VARS \
c906108c
SS		 371 UINT f_op1; \
372 UINT f_r1; \
373 UINT f_op2; \
374 UINT f_r2; \
375 INT f_simm16; \
376 unsigned int length;
377#define EXTRACT_IFMT_ADDV3_CODE \
378 length = 4; \
96baa820
JM		 379 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
380 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
381 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
382 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
383 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
c906108c
SS		 384
385#define EXTRACT_IFMT_BC8_VARS \
c906108c
SS		 386 UINT f_op1; \
387 UINT f_r1; \
388 SI f_disp8; \
389 unsigned int length;
390#define EXTRACT_IFMT_BC8_CODE \
391 length = 2; \
96baa820
JM		 392 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
393 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
394 f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
c906108c
SS		 395
396#define EXTRACT_IFMT_BC24_VARS \
c906108c
SS		 397 UINT f_op1; \
398 UINT f_r1; \
399 SI f_disp24; \
400 unsigned int length;
401#define EXTRACT_IFMT_BC24_CODE \
402 length = 4; \
96baa820
JM		 403 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
404 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
405 f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc)); \
c906108c
SS		 406
407#define EXTRACT_IFMT_BEQ_VARS \
c906108c
SS		 408 UINT f_op1; \
409 UINT f_r1; \
410 UINT f_op2; \
411 UINT f_r2; \
412 SI f_disp16; \
413 unsigned int length;
414#define EXTRACT_IFMT_BEQ_CODE \
415 length = 4; \
96baa820
JM		 416 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
417 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
418 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
419 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
420 f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
c906108c
SS		 421
422#define EXTRACT_IFMT_BEQZ_VARS \
c906108c
SS		 423 UINT f_op1; \
424 UINT f_r1; \
425 UINT f_op2; \
426 UINT f_r2; \
427 SI f_disp16; \
428 unsigned int length;
429#define EXTRACT_IFMT_BEQZ_CODE \
430 length = 4; \
96baa820
JM		 431 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
432 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
433 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
434 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
435 f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
c906108c
SS		 436
437#define EXTRACT_IFMT_CMP_VARS \
c906108c
SS		 438 UINT f_op1; \
439 UINT f_r1; \
440 UINT f_op2; \
441 UINT f_r2; \
442 unsigned int length;
443#define EXTRACT_IFMT_CMP_CODE \
444 length = 2; \
96baa820
JM		 445 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
446 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
447 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
448 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
c906108c
SS		 449
450#define EXTRACT_IFMT_CMPI_VARS \
c906108c
SS		 451 UINT f_op1; \
452 UINT f_r1; \
453 UINT f_op2; \
454 UINT f_r2; \
455 INT f_simm16; \
456 unsigned int length;
457#define EXTRACT_IFMT_CMPI_CODE \
458 length = 4; \
96baa820
JM		 459 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
460 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
461 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
462 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
463 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
c906108c
SS		 464
465#define EXTRACT_IFMT_DIV_VARS \
c906108c
SS		 466 UINT f_op1; \
467 UINT f_r1; \
468 UINT f_op2; \
469 UINT f_r2; \
470 INT f_simm16; \
471 unsigned int length;
472#define EXTRACT_IFMT_DIV_CODE \
473 length = 4; \
96baa820
JM		 474 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
475 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
476 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
477 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
478 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
c906108c
SS		 479
480#define EXTRACT_IFMT_JL_VARS \
c906108c
SS		 481 UINT f_op1; \
482 UINT f_r1; \
483 UINT f_op2; \
484 UINT f_r2; \
485 unsigned int length;
486#define EXTRACT_IFMT_JL_CODE \
487 length = 2; \
96baa820
JM		 488 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
489 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
490 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
491 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
c906108c
SS		 492
493#define EXTRACT_IFMT_LD24_VARS \
c906108c
SS		 494 UINT f_op1; \
495 UINT f_r1; \
496 UINT f_uimm24; \
497 unsigned int length;
498#define EXTRACT_IFMT_LD24_CODE \
499 length = 4; \
96baa820
JM		 500 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
501 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
502 f_uimm24 = EXTRACT_MSB0_UINT (insn, 32, 8, 24); \
c906108c
SS		 503
504#define EXTRACT_IFMT_LDI16_VARS \
c906108c
SS		 505 UINT f_op1; \
506 UINT f_r1; \
507 UINT f_op2; \
508 UINT f_r2; \
509 INT f_simm16; \
510 unsigned int length;
511#define EXTRACT_IFMT_LDI16_CODE \
512 length = 4; \
96baa820
JM		 513 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
514 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
515 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
516 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
517 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
c906108c
SS		 518
519#define EXTRACT_IFMT_MVFACHI_VARS \
c906108c
SS		 520 UINT f_op1; \
521 UINT f_r1; \
522 UINT f_op2; \
523 UINT f_r2; \
524 unsigned int length;
525#define EXTRACT_IFMT_MVFACHI_CODE \
526 length = 2; \
96baa820
JM		 527 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
528 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
529 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
530 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
c906108c
SS		 531
532#define EXTRACT_IFMT_MVFC_VARS \
c906108c
SS		 533 UINT f_op1; \
534 UINT f_r1; \
535 UINT f_op2; \
536 UINT f_r2; \
537 unsigned int length;
538#define EXTRACT_IFMT_MVFC_CODE \
539 length = 2; \
96baa820
JM		 540 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
541 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
542 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
543 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
c906108c
SS		 544
545#define EXTRACT_IFMT_MVTACHI_VARS \
c906108c
SS		 546 UINT f_op1; \
547 UINT f_r1; \
548 UINT f_op2; \
549 UINT f_r2; \
550 unsigned int length;
551#define EXTRACT_IFMT_MVTACHI_CODE \
552 length = 2; \
96baa820
JM		 553 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
554 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
555 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
556 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
c906108c
SS		 557
558#define EXTRACT_IFMT_MVTC_VARS \
c906108c
SS		 559 UINT f_op1; \
560 UINT f_r1; \
561 UINT f_op2; \
562 UINT f_r2; \
563 unsigned int length;
564#define EXTRACT_IFMT_MVTC_CODE \
565 length = 2; \
96baa820
JM		 566 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
567 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
568 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
569 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
c906108c
SS		 570
571#define EXTRACT_IFMT_NOP_VARS \
c906108c
SS		 572 UINT f_op1; \
573 UINT f_r1; \
574 UINT f_op2; \
575 UINT f_r2; \
576 unsigned int length;
577#define EXTRACT_IFMT_NOP_CODE \
578 length = 2; \
96baa820
JM		 579 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
580 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
581 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
582 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
c906108c
SS		 583
584#define EXTRACT_IFMT_SETH_VARS \
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SS		 585 UINT f_op1; \
586 UINT f_r1; \
587 UINT f_op2; \
588 UINT f_r2; \
589 UINT f_hi16; \
590 unsigned int length;
591#define EXTRACT_IFMT_SETH_CODE \
592 length = 4; \
96baa820
JM		 593 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
594 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
595 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
596 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
597 f_hi16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
c906108c
SS		 598
599#define EXTRACT_IFMT_SLLI_VARS \
c906108c
SS		 600 UINT f_op1; \
601 UINT f_r1; \
602 UINT f_shift_op2; \
603 UINT f_uimm5; \
604 unsigned int length;
605#define EXTRACT_IFMT_SLLI_CODE \
606 length = 2; \
96baa820
JM		 607 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
608 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
609 f_shift_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 3); \
610 f_uimm5 = EXTRACT_MSB0_UINT (insn, 16, 11, 5); \
c906108c
SS		 611
612#define EXTRACT_IFMT_ST_D_VARS \
c906108c
SS		 613 UINT f_op1; \
614 UINT f_r1; \
615 UINT f_op2; \
616 UINT f_r2; \
617 INT f_simm16; \
618 unsigned int length;
619#define EXTRACT_IFMT_ST_D_CODE \
620 length = 4; \
96baa820
JM		 621 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
622 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
623 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
624 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
625 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
c906108c
SS		 626
627#define EXTRACT_IFMT_TRAP_VARS \
c906108c
SS		 628 UINT f_op1; \
629 UINT f_r1; \
630 UINT f_op2; \
631 UINT f_uimm4; \
632 unsigned int length;
633#define EXTRACT_IFMT_TRAP_CODE \
634 length = 2; \
96baa820
JM		 635 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
636 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
637 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
638 f_uimm4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
c906108c 639
16b47b25
NC		 640#define EXTRACT_IFMT_CLRPSW_VARS \
641 UINT f_op1; \
642 UINT f_r1; \
643 UINT f_uimm8; \
644 unsigned int length;
645#define EXTRACT_IFMT_CLRPSW_CODE \
646 length = 2; \
647 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
648 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
649 f_uimm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \
650
651#define EXTRACT_IFMT_BSET_VARS \
652 UINT f_op1; \
653 UINT f_bit4; \
654 UINT f_uimm3; \
655 UINT f_op2; \
656 UINT f_r2; \
657 INT f_simm16; \
658 unsigned int length;
659#define EXTRACT_IFMT_BSET_CODE \
660 length = 4; \
661 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
662 f_bit4 = EXTRACT_MSB0_UINT (insn, 32, 4, 1); \
663 f_uimm3 = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
664 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
665 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
666 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
667
668#define EXTRACT_IFMT_BTST_VARS \
669 UINT f_op1; \
670 UINT f_bit4; \
671 UINT f_uimm3; \
672 UINT f_op2; \
673 UINT f_r2; \
674 unsigned int length;
675#define EXTRACT_IFMT_BTST_CODE \
676 length = 2; \
677 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
678 f_bit4 = EXTRACT_MSB0_UINT (insn, 16, 4, 1); \
679 f_uimm3 = EXTRACT_MSB0_UINT (insn, 16, 5, 3); \
680 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
681 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
682
c906108c
SS		 683/* Collection of various things for the trace handler to use. */
684
685typedef struct trace_record {
686 IADDR pc;
687 /* FIXME:wip */
688} TRACE_RECORD;
689
690#endif /* CPU_M32RBF_H */
GDB Binutils - Deliverables
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