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* Makefile.in (M32R_OBJS): Add cpu.o.
[deliverable/binutils-gdb.git] / sim / m32r / cpux.h
CommitLineData
8e420152
DE		 1/* CPU family header for m32rx.
2
b8a9943d
DE		 3This file is machine generated with CGEN.
4
8e420152
DE		 5Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
6
7This file is part of the GNU Simulators.
8
9This program is free software; you can redistribute it and/or modify
10it under the terms of the GNU General Public License as published by
11the Free Software Foundation; either version 2, or (at your option)
12any later version.
13
14This program is distributed in the hope that it will be useful,
15but WITHOUT ANY WARRANTY; without even the implied warranty of
16MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17GNU General Public License for more details.
18
19You should have received a copy of the GNU General Public License along
20with this program; if not, write to the Free Software Foundation, Inc.,
2159 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22
23*/
24
25#ifndef CPU_M32RX_H
26#define CPU_M32RX_H
27
28/* Maximum number of instructions that are fetched at a time.
29 This is for LIW type instructions sets (e.g. m32r). */
30#define MAX_LIW_INSNS 2
31
32/* Maximum number of instructions that can be executed in parallel. */
33#define MAX_PARALLEL_INSNS 2
34
35/* CPU state information. */
36typedef struct {
37 /* Hardware elements. */
38 struct {
39 /* program counter */
40 USI h_pc;
41#define GET_H_PC() CPU (h_pc)
42#define SET_H_PC(x) (CPU (h_pc) = (x))
43 /* general registers */
44 SI h_gr[16];
45#define GET_H_GR(a1) CPU (h_gr)[a1]
46#define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
47 /* control registers */
48 SI h_cr[7];
49#define GET_H_CR(a1) CPU (h_cr)[a1]
50#define SET_H_CR(a1, x) (CPU (h_cr)[a1] = (x))
51 /* accumulator */
52 DI h_accum;
53#define GET_H_ACCUM() CPU (h_accum)
54#define SET_H_ACCUM(x) (CPU (h_accum) = (x))
b8a9943d 55/* start-sanitize-m32rx */
8e420152
DE		 56 /* accumulators */
57 DI h_accums[2];
b8a9943d 58/* end-sanitize-m32rx */
8e420152
DE		 59#define GET_H_ACCUMS(a1) CPU (h_accums)[a1]
60#define SET_H_ACCUMS(a1, x) (CPU (h_accums)[a1] = (x))
b8a9943d 61/* start-sanitize-m32rx */
8e420152
DE		 62 /* abort flag */
63 UBI h_abort;
b8a9943d 64/* end-sanitize-m32rx */
8e420152
DE		 65#define GET_H_ABORT() CPU (h_abort)
66#define SET_H_ABORT(x) (CPU (h_abort) = (x))
67 /* condition bit */
68 UBI h_cond;
69#define GET_H_COND() CPU (h_cond)
70#define SET_H_COND(x) (CPU (h_cond) = (x))
71 /* sm */
72 UBI h_sm;
73#define GET_H_SM() CPU (h_sm)
74#define SET_H_SM(x) (CPU (h_sm) = (x))
75 /* bsm */
76 UBI h_bsm;
77#define GET_H_BSM() CPU (h_bsm)
78#define SET_H_BSM(x) (CPU (h_bsm) = (x))
79 /* ie */
80 UBI h_ie;
81#define GET_H_IE() CPU (h_ie)
82#define SET_H_IE(x) (CPU (h_ie) = (x))
83 /* bie */
84 UBI h_bie;
85#define GET_H_BIE() CPU (h_bie)
86#define SET_H_BIE(x) (CPU (h_bie) = (x))
87 /* bcond */
88 UBI h_bcond;
89#define GET_H_BCOND() CPU (h_bcond)
90#define SET_H_BCOND(x) (CPU (h_bcond) = (x))
91 /* bpc */
92 SI h_bpc;
93#define GET_H_BPC() CPU (h_bpc)
94#define SET_H_BPC(x) (CPU (h_bpc) = (x))
95 } hardware;
96#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
97 /* CPU profiling state information. */
98 struct {
99 /* general registers */
100 unsigned long h_gr;
101 } profile;
102#define CPU_CGEN_PROFILE(cpu) (& (cpu)->cpu_data.profile)
103} M32RX_CPU_DATA;
104
b8a9943d 105extern DECODE *m32rx_decode (SIM_CPU *, PCADDR, insn_t);
8e420152
DE		 106
107/* The ARGBUF struct. */
108struct argbuf {
109 /* These are the baseclass definitions. */
110 unsigned int length;
111 PCADDR addr;
112 const struct cgen_insn *opcode;
b8a9943d
DE		 113#if ! defined (SCACHE_P)
114 insn_t insn;
115#endif
8e420152
DE		 116 /* cpu specific data follows */
117 union {
118 struct { /* e.g. add $dr,$sr */
119 UINT f_r1;
120 UINT f_r2;
121 } fmt_0_add;
122 struct { /* e.g. add3 $dr,$sr,#$slo16 */
123 UINT f_r1;
124 UINT f_r2;
125 HI f_simm16;
126 } fmt_1_add3;
127 struct { /* e.g. and3 $dr,$sr,#$uimm16 */
128 UINT f_r1;
129 UINT f_r2;
130 USI f_uimm16;
131 } fmt_2_and3;
132 struct { /* e.g. or3 $dr,$sr,#$ulo16 */
133 UINT f_r1;
134 UINT f_r2;
135 UHI f_uimm16;
136 } fmt_3_or3;
137 struct { /* e.g. addi $dr,#$simm8 */
138 UINT f_r1;
139 SI f_simm8;
140 } fmt_4_addi;
141 struct { /* e.g. addv3 $dr,$sr,#$simm16 */
142 UINT f_r1;
143 UINT f_r2;
144 SI f_simm16;
145 } fmt_5_addv3;
146 struct { /* e.g. addx $dr,$sr */
147 UINT f_r1;
148 UINT f_r2;
149 } fmt_6_addx;
150 struct { /* e.g. bc $disp8 */
151 IADDR f_disp8;
152 } fmt_7_bc8;
153 struct { /* e.g. bc $disp24 */
154 IADDR f_disp24;
155 } fmt_8_bc24;
156 struct { /* e.g. beq $src1,$src2,$disp16 */
157 UINT f_r1;
158 UINT f_r2;
159 IADDR f_disp16;
160 } fmt_9_beq;
161 struct { /* e.g. beqz $src2,$disp16 */
162 UINT f_r2;
163 IADDR f_disp16;
164 } fmt_10_beqz;
165 struct { /* e.g. bl $disp8 */
166 IADDR f_disp8;
167 } fmt_11_bl8;
168 struct { /* e.g. bl $disp24 */
169 IADDR f_disp24;
170 } fmt_12_bl24;
171 struct { /* e.g. bcl $disp8 */
172 IADDR f_disp8;
173 } fmt_13_bcl8;
174 struct { /* e.g. bcl $disp24 */
175 IADDR f_disp24;
176 } fmt_14_bcl24;
177 struct { /* e.g. bra $disp8 */
178 IADDR f_disp8;
179 } fmt_15_bra8;
180 struct { /* e.g. bra $disp24 */
181 IADDR f_disp24;
182 } fmt_16_bra24;
183 struct { /* e.g. cmp $src1,$src2 */
184 UINT f_r1;
185 UINT f_r2;
186 } fmt_17_cmp;
187 struct { /* e.g. cmpi $src2,#$simm16 */
188 UINT f_r2;
189 SI f_simm16;
190 } fmt_18_cmpi;
191 struct { /* e.g. cmpui $src2,#$uimm16 */
192 UINT f_r2;
193 USI f_uimm16;
194 } fmt_19_cmpui;
195 struct { /* e.g. cmpz $src2 */
196 UINT f_r2;
197 } fmt_20_cmpz;
198 struct { /* e.g. div $dr,$sr */
199 UINT f_r1;
200 UINT f_r2;
201 } fmt_21_div;
202 struct { /* e.g. jc $sr */
203 UINT f_r2;
204 } fmt_22_jc;
205 struct { /* e.g. jl $sr */
206 UINT f_r2;
207 } fmt_23_jl;
208 struct { /* e.g. jmp $sr */
209 UINT f_r2;
210 } fmt_24_jmp;
211 struct { /* e.g. ld $dr,@$sr */
212 UINT f_r1;
213 UINT f_r2;
214 } fmt_25_ld;
215 struct { /* e.g. ld $dr,@($slo16,$sr) */
216 UINT f_r1;
217 UINT f_r2;
218 HI f_simm16;
219 } fmt_26_ld_d;
220 struct { /* e.g. ldb $dr,@$sr */
221 UINT f_r1;
222 UINT f_r2;
223 } fmt_27_ldb;
224 struct { /* e.g. ldb $dr,@($slo16,$sr) */
225 UINT f_r1;
226 UINT f_r2;
227 HI f_simm16;
228 } fmt_28_ldb_d;
229 struct { /* e.g. ldh $dr,@$sr */
230 UINT f_r1;
231 UINT f_r2;
232 } fmt_29_ldh;
233 struct { /* e.g. ldh $dr,@($slo16,$sr) */
234 UINT f_r1;
235 UINT f_r2;
236 HI f_simm16;
237 } fmt_30_ldh_d;
238 struct { /* e.g. ld24 $dr,#$uimm24 */
239 UINT f_r1;
240 ADDR f_uimm24;
241 } fmt_31_ld24;
242 struct { /* e.g. ldi $dr,#$simm8 */
243 UINT f_r1;
244 SI f_simm8;
245 } fmt_32_ldi8;
246 struct { /* e.g. ldi $dr,$slo16 */
247 UINT f_r1;
248 HI f_simm16;
249 } fmt_33_ldi16;
8e420152
DE		 250 struct { /* e.g. machi $src1,$src2,$acc */
251 UINT f_r1;
252 UINT f_acc;
253 UINT f_r2;
b8a9943d 254 } fmt_34_machi_a;
8e420152
DE		 255 struct { /* e.g. mulhi $src1,$src2,$acc */
256 UINT f_r1;
257 UINT f_acc;
258 UINT f_r2;
b8a9943d 259 } fmt_35_mulhi_a;
8e420152
DE		 260 struct { /* e.g. mv $dr,$sr */
261 UINT f_r1;
262 UINT f_r2;
b8a9943d 263 } fmt_36_mv;
8e420152
DE		 264 struct { /* e.g. mvfachi $dr,$accs */
265 UINT f_r1;
266 UINT f_accs;
b8a9943d 267 } fmt_37_mvfachi_a;
8e420152
DE		 268 struct { /* e.g. mvfc $dr,$scr */
269 UINT f_r1;
270 UINT f_r2;
b8a9943d 271 } fmt_38_mvfc;
8e420152
DE		 272 struct { /* e.g. mvtachi $src1,$accs */
273 UINT f_r1;
274 UINT f_accs;
b8a9943d 275 } fmt_39_mvtachi_a;
8e420152
DE		 276 struct { /* e.g. mvtc $sr,$dcr */
277 UINT f_r1;
278 UINT f_r2;
b8a9943d 279 } fmt_40_mvtc;
8e420152
DE		 280 struct { /* e.g. nop */
281 int empty;
b8a9943d 282 } fmt_41_nop;
e0bd6e18
DE		 283 struct { /* e.g. rac $accd */
284 UINT f_accd;
285 } fmt_42_rac_d;
286 struct { /* e.g. rac $accd,$accs */
287 UINT f_accd;
8e420152 288 UINT f_accs;
e0bd6e18
DE		 289 } fmt_43_rac_ds;
290 struct { /* e.g. rac $accd,$accs,#$imm1 */
291 UINT f_accd;
292 UINT f_accs;
293 USI f_imm1;
294 } fmt_44_rac_dsi;
b8a9943d
DE		 295 struct { /* e.g. rte */
296 int empty;
e0bd6e18 297 } fmt_45_rte;
b8a9943d 298 struct { /* e.g. seth $dr,#$hi16 */
8e420152
DE		 299 UINT f_r1;
300 UHI f_hi16;
e0bd6e18 301 } fmt_46_seth;
8e420152
DE		 302 struct { /* e.g. slli $dr,#$uimm5 */
303 UINT f_r1;
304 USI f_uimm5;
e0bd6e18 305 } fmt_47_slli;
8e420152
DE		 306 struct { /* e.g. st $src1,@($slo16,$src2) */
307 UINT f_r1;
308 UINT f_r2;
309 HI f_simm16;
e0bd6e18 310 } fmt_48_st_d;
8e420152
DE		 311 struct { /* e.g. trap #$uimm4 */
312 USI f_uimm4;
e0bd6e18 313 } fmt_49_trap;
8e420152
DE		 314 struct { /* e.g. satb $dr,$src2 */
315 UINT f_r1;
316 UINT f_r2;
e0bd6e18 317 } fmt_50_satb;
b8a9943d
DE		 318 struct { /* e.g. sat $dr,$src2 */
319 UINT f_r1;
8e420152 320 UINT f_r2;
e0bd6e18 321 } fmt_51_sat;
8e420152
DE		 322 struct { /* e.g. sadd */
323 int empty;
e0bd6e18 324 } fmt_52_sadd;
8e420152
DE		 325 struct { /* e.g. macwu1 $src1,$src2 */
326 UINT f_r1;
327 UINT f_r2;
e0bd6e18 328 } fmt_53_macwu1;
b8a9943d
DE		 329 struct { /* e.g. msblo $src1,$src2 */
330 UINT f_r1;
331 UINT f_r2;
e0bd6e18 332 } fmt_54_msblo;
8e420152
DE		 333 struct { /* e.g. sc */
334 int empty;
e0bd6e18 335 } fmt_55_sc;
8e420152
DE		 336 } fields;
337#if 1 || WITH_PROFILE_MODEL_P /*FIXME:wip*/
338 unsigned long h_gr_get;
339 unsigned long h_gr_set;
340#endif
341};
342
343/* A cached insn.
344 This is also used in the non-scache case. In this situation we assume
345 the cache size is 1, and do a few things a little differently. */
346
347struct scache {
348 IADDR next;
349 union {
350#if ! WITH_SEM_SWITCH_FULL
351 SEMANTIC_FN *sem_fn;
352#endif
353#if ! WITH_SEM_SWITCH_FAST
354#if WITH_SCACHE
355 SEMANTIC_CACHE_FN *sem_fast_fn;
356#else
357 SEMANTIC_FN *sem_fast_fn;
358#endif
359#endif
360#if WITH_SEM_SWITCH_FULL || WITH_SEM_SWITCH_FAST
361#ifdef __GNUC__
362 void *sem_case;
363#else
364 int sem_case;
365#endif
366#endif
367 } semantic;
368 struct argbuf argbuf;
369};
370
371/* Macros to simplify extraction, reading and semantic code.
372 These define and assign the local vars that contain the insn's fields. */
373
374#define EXTRACT_FMT_0_ADD_VARS \
375 /* Instruction fields. */ \
376 UINT f_op1; \
377 UINT f_r1; \
378 UINT f_op2; \
379 UINT f_r2; \
380 unsigned int length;
381#define EXTRACT_FMT_0_ADD_CODE \
382 length = 2; \
383 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
384 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
385 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
386 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
387
388#define EXTRACT_FMT_1_ADD3_VARS \
389 /* Instruction fields. */ \
390 UINT f_op1; \
391 UINT f_r1; \
392 UINT f_op2; \
393 UINT f_r2; \
394 int f_simm16; \
395 unsigned int length;
396#define EXTRACT_FMT_1_ADD3_CODE \
397 length = 4; \
398 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
399 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
400 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
401 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
402 f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
403
404#define EXTRACT_FMT_2_AND3_VARS \
405 /* Instruction fields. */ \
406 UINT f_op1; \
407 UINT f_r1; \
408 UINT f_op2; \
409 UINT f_r2; \
410 UINT f_uimm16; \
411 unsigned int length;
412#define EXTRACT_FMT_2_AND3_CODE \
413 length = 4; \
414 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
415 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
416 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
417 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
418 f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
419
420#define EXTRACT_FMT_3_OR3_VARS \
421 /* Instruction fields. */ \
422 UINT f_op1; \
423 UINT f_r1; \
424 UINT f_op2; \
425 UINT f_r2; \
426 UINT f_uimm16; \
427 unsigned int length;
428#define EXTRACT_FMT_3_OR3_CODE \
429 length = 4; \
430 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
431 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
432 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
433 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
434 f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
435
436#define EXTRACT_FMT_4_ADDI_VARS \
437 /* Instruction fields. */ \
438 UINT f_op1; \
439 UINT f_r1; \
440 int f_simm8; \
441 unsigned int length;
442#define EXTRACT_FMT_4_ADDI_CODE \
443 length = 2; \
444 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
445 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
446 f_simm8 = EXTRACT_SIGNED (insn, 16, 8, 8); \
447
448#define EXTRACT_FMT_5_ADDV3_VARS \
449 /* Instruction fields. */ \
450 UINT f_op1; \
451 UINT f_r1; \
452 UINT f_op2; \
453 UINT f_r2; \
454 int f_simm16; \
455 unsigned int length;
456#define EXTRACT_FMT_5_ADDV3_CODE \
457 length = 4; \
458 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
459 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
460 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
461 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
462 f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
463
464#define EXTRACT_FMT_6_ADDX_VARS \
465 /* Instruction fields. */ \
466 UINT f_op1; \
467 UINT f_r1; \
468 UINT f_op2; \
469 UINT f_r2; \
470 unsigned int length;
471#define EXTRACT_FMT_6_ADDX_CODE \
472 length = 2; \
473 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
474 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
475 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
476 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
477
478#define EXTRACT_FMT_7_BC8_VARS \
479 /* Instruction fields. */ \
480 UINT f_op1; \
481 UINT f_r1; \
482 int f_disp8; \
483 unsigned int length;
484#define EXTRACT_FMT_7_BC8_CODE \
485 length = 2; \
486 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
487 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
488 f_disp8 = EXTRACT_SIGNED (insn, 16, 8, 8) << 2; \
489
490#define EXTRACT_FMT_8_BC24_VARS \
491 /* Instruction fields. */ \
492 UINT f_op1; \
493 UINT f_r1; \
494 int f_disp24; \
495 unsigned int length;
496#define EXTRACT_FMT_8_BC24_CODE \
497 length = 4; \
498 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
499 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
500 f_disp24 = EXTRACT_SIGNED (insn, 32, 8, 24) << 2; \
501
502#define EXTRACT_FMT_9_BEQ_VARS \
503 /* Instruction fields. */ \
504 UINT f_op1; \
505 UINT f_r1; \
506 UINT f_op2; \
507 UINT f_r2; \
508 int f_disp16; \
509 unsigned int length;
510#define EXTRACT_FMT_9_BEQ_CODE \
511 length = 4; \
512 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
513 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
514 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
515 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
516 f_disp16 = EXTRACT_SIGNED (insn, 32, 16, 16) << 2; \
517
518#define EXTRACT_FMT_10_BEQZ_VARS \
519 /* Instruction fields. */ \
520 UINT f_op1; \
521 UINT f_r1; \
522 UINT f_op2; \
523 UINT f_r2; \
524 int f_disp16; \
525 unsigned int length;
526#define EXTRACT_FMT_10_BEQZ_CODE \
527 length = 4; \
528 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
529 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
530 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
531 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
532 f_disp16 = EXTRACT_SIGNED (insn, 32, 16, 16) << 2; \
533
534#define EXTRACT_FMT_11_BL8_VARS \
535 /* Instruction fields. */ \
536 UINT f_op1; \
537 UINT f_r1; \
538 int f_disp8; \
539 unsigned int length;
540#define EXTRACT_FMT_11_BL8_CODE \
541 length = 2; \
542 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
543 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
544 f_disp8 = EXTRACT_SIGNED (insn, 16, 8, 8) << 2; \
545
546#define EXTRACT_FMT_12_BL24_VARS \
547 /* Instruction fields. */ \
548 UINT f_op1; \
549 UINT f_r1; \
550 int f_disp24; \
551 unsigned int length;
552#define EXTRACT_FMT_12_BL24_CODE \
553 length = 4; \
554 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
555 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
556 f_disp24 = EXTRACT_SIGNED (insn, 32, 8, 24) << 2; \
557
558#define EXTRACT_FMT_13_BCL8_VARS \
559 /* Instruction fields. */ \
560 UINT f_op1; \
561 UINT f_r1; \
562 int f_disp8; \
563 unsigned int length;
564#define EXTRACT_FMT_13_BCL8_CODE \
565 length = 2; \
566 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
567 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
568 f_disp8 = EXTRACT_SIGNED (insn, 16, 8, 8) << 2; \
569
570#define EXTRACT_FMT_14_BCL24_VARS \
571 /* Instruction fields. */ \
572 UINT f_op1; \
573 UINT f_r1; \
574 int f_disp24; \
575 unsigned int length;
576#define EXTRACT_FMT_14_BCL24_CODE \
577 length = 4; \
578 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
579 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
580 f_disp24 = EXTRACT_SIGNED (insn, 32, 8, 24) << 2; \
581
582#define EXTRACT_FMT_15_BRA8_VARS \
583 /* Instruction fields. */ \
584 UINT f_op1; \
585 UINT f_r1; \
586 int f_disp8; \
587 unsigned int length;
588#define EXTRACT_FMT_15_BRA8_CODE \
589 length = 2; \
590 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
591 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
592 f_disp8 = EXTRACT_SIGNED (insn, 16, 8, 8) << 2; \
593
594#define EXTRACT_FMT_16_BRA24_VARS \
595 /* Instruction fields. */ \
596 UINT f_op1; \
597 UINT f_r1; \
598 int f_disp24; \
599 unsigned int length;
600#define EXTRACT_FMT_16_BRA24_CODE \
601 length = 4; \
602 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
603 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
604 f_disp24 = EXTRACT_SIGNED (insn, 32, 8, 24) << 2; \
605
606#define EXTRACT_FMT_17_CMP_VARS \
607 /* Instruction fields. */ \
608 UINT f_op1; \
609 UINT f_r1; \
610 UINT f_op2; \
611 UINT f_r2; \
612 unsigned int length;
613#define EXTRACT_FMT_17_CMP_CODE \
614 length = 2; \
615 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
616 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
617 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
618 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
619
620#define EXTRACT_FMT_18_CMPI_VARS \
621 /* Instruction fields. */ \
622 UINT f_op1; \
623 UINT f_r1; \
624 UINT f_op2; \
625 UINT f_r2; \
626 int f_simm16; \
627 unsigned int length;
628#define EXTRACT_FMT_18_CMPI_CODE \
629 length = 4; \
630 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
631 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
632 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
633 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
634 f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
635
636#define EXTRACT_FMT_19_CMPUI_VARS \
637 /* Instruction fields. */ \
638 UINT f_op1; \
639 UINT f_r1; \
640 UINT f_op2; \
641 UINT f_r2; \
642 UINT f_uimm16; \
643 unsigned int length;
644#define EXTRACT_FMT_19_CMPUI_CODE \
645 length = 4; \
646 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
647 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
648 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
649 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
650 f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
651
652#define EXTRACT_FMT_20_CMPZ_VARS \
653 /* Instruction fields. */ \
654 UINT f_op1; \
655 UINT f_r1; \
656 UINT f_op2; \
657 UINT f_r2; \
658 unsigned int length;
659#define EXTRACT_FMT_20_CMPZ_CODE \
660 length = 2; \
661 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
662 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
663 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
664 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
665
666#define EXTRACT_FMT_21_DIV_VARS \
667 /* Instruction fields. */ \
668 UINT f_op1; \
669 UINT f_r1; \
670 UINT f_op2; \
671 UINT f_r2; \
672 int f_simm16; \
673 unsigned int length;
674#define EXTRACT_FMT_21_DIV_CODE \
675 length = 4; \
676 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
677 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
678 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
679 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
680 f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
681
682#define EXTRACT_FMT_22_JC_VARS \
683 /* Instruction fields. */ \
684 UINT f_op1; \
685 UINT f_r1; \
686 UINT f_op2; \
687 UINT f_r2; \
688 unsigned int length;
689#define EXTRACT_FMT_22_JC_CODE \
690 length = 2; \
691 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
692 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
693 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
694 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
695
696#define EXTRACT_FMT_23_JL_VARS \
697 /* Instruction fields. */ \
698 UINT f_op1; \
699 UINT f_r1; \
700 UINT f_op2; \
701 UINT f_r2; \
702 unsigned int length;
703#define EXTRACT_FMT_23_JL_CODE \
704 length = 2; \
705 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
706 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
707 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
708 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
709
710#define EXTRACT_FMT_24_JMP_VARS \
711 /* Instruction fields. */ \
712 UINT f_op1; \
713 UINT f_r1; \
714 UINT f_op2; \
715 UINT f_r2; \
716 unsigned int length;
717#define EXTRACT_FMT_24_JMP_CODE \
718 length = 2; \
719 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
720 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
721 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
722 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
723
724#define EXTRACT_FMT_25_LD_VARS \
725 /* Instruction fields. */ \
726 UINT f_op1; \
727 UINT f_r1; \
728 UINT f_op2; \
729 UINT f_r2; \
730 unsigned int length;
731#define EXTRACT_FMT_25_LD_CODE \
732 length = 2; \
733 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
734 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
735 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
736 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
737
738#define EXTRACT_FMT_26_LD_D_VARS \
739 /* Instruction fields. */ \
740 UINT f_op1; \
741 UINT f_r1; \
742 UINT f_op2; \
743 UINT f_r2; \
744 int f_simm16; \
745 unsigned int length;
746#define EXTRACT_FMT_26_LD_D_CODE \
747 length = 4; \
748 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
749 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
750 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
751 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
752 f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
753
754#define EXTRACT_FMT_27_LDB_VARS \
755 /* Instruction fields. */ \
756 UINT f_op1; \
757 UINT f_r1; \
758 UINT f_op2; \
759 UINT f_r2; \
760 unsigned int length;
761#define EXTRACT_FMT_27_LDB_CODE \
762 length = 2; \
763 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
764 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
765 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
766 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
767
768#define EXTRACT_FMT_28_LDB_D_VARS \
769 /* Instruction fields. */ \
770 UINT f_op1; \
771 UINT f_r1; \
772 UINT f_op2; \
773 UINT f_r2; \
774 int f_simm16; \
775 unsigned int length;
776#define EXTRACT_FMT_28_LDB_D_CODE \
777 length = 4; \
778 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
779 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
780 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
781 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
782 f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
783
784#define EXTRACT_FMT_29_LDH_VARS \
785 /* Instruction fields. */ \
786 UINT f_op1; \
787 UINT f_r1; \
788 UINT f_op2; \
789 UINT f_r2; \
790 unsigned int length;
791#define EXTRACT_FMT_29_LDH_CODE \
792 length = 2; \
793 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
794 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
795 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
796 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
797
798#define EXTRACT_FMT_30_LDH_D_VARS \
799 /* Instruction fields. */ \
800 UINT f_op1; \
801 UINT f_r1; \
802 UINT f_op2; \
803 UINT f_r2; \
804 int f_simm16; \
805 unsigned int length;
806#define EXTRACT_FMT_30_LDH_D_CODE \
807 length = 4; \
808 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
809 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
810 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
811 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
812 f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
813
814#define EXTRACT_FMT_31_LD24_VARS \
815 /* Instruction fields. */ \
816 UINT f_op1; \
817 UINT f_r1; \
818 UINT f_uimm24; \
819 unsigned int length;
820#define EXTRACT_FMT_31_LD24_CODE \
821 length = 4; \
822 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
823 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
824 f_uimm24 = EXTRACT_UNSIGNED (insn, 32, 8, 24); \
825
826#define EXTRACT_FMT_32_LDI8_VARS \
827 /* Instruction fields. */ \
828 UINT f_op1; \
829 UINT f_r1; \
830 int f_simm8; \
831 unsigned int length;
832#define EXTRACT_FMT_32_LDI8_CODE \
833 length = 2; \
834 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
835 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
836 f_simm8 = EXTRACT_SIGNED (insn, 16, 8, 8); \
837
838#define EXTRACT_FMT_33_LDI16_VARS \
839 /* Instruction fields. */ \
840 UINT f_op1; \
841 UINT f_r1; \
842 UINT f_op2; \
843 UINT f_r2; \
844 int f_simm16; \
845 unsigned int length;
846#define EXTRACT_FMT_33_LDI16_CODE \
847 length = 4; \
848 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
849 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
850 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
851 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
852 f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
853
b8a9943d 854#define EXTRACT_FMT_34_MACHI_A_VARS \
8e420152
DE		 855 /* Instruction fields. */ \
856 UINT f_op1; \
857 UINT f_r1; \
858 UINT f_acc; \
859 UINT f_op23; \
860 UINT f_r2; \
861 unsigned int length;
b8a9943d 862#define EXTRACT_FMT_34_MACHI_A_CODE \
8e420152
DE		 863 length = 2; \
864 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
865 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
866 f_acc = EXTRACT_UNSIGNED (insn, 16, 8, 1); \
867 f_op23 = EXTRACT_UNSIGNED (insn, 16, 9, 3); \
868 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
869
b8a9943d 870#define EXTRACT_FMT_35_MULHI_A_VARS \
8e420152
DE		 871 /* Instruction fields. */ \
872 UINT f_op1; \
873 UINT f_r1; \
874 UINT f_acc; \
875 UINT f_op23; \
876 UINT f_r2; \
877 unsigned int length;
b8a9943d 878#define EXTRACT_FMT_35_MULHI_A_CODE \
8e420152
DE		 879 length = 2; \
880 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
881 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
882 f_acc = EXTRACT_UNSIGNED (insn, 16, 8, 1); \
883 f_op23 = EXTRACT_UNSIGNED (insn, 16, 9, 3); \
884 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
885
b8a9943d 886#define EXTRACT_FMT_36_MV_VARS \
8e420152
DE		 887 /* Instruction fields. */ \
888 UINT f_op1; \
889 UINT f_r1; \
890 UINT f_op2; \
891 UINT f_r2; \
892 unsigned int length;
b8a9943d 893#define EXTRACT_FMT_36_MV_CODE \
8e420152
DE		 894 length = 2; \
895 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
896 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
897 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
898 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
899
b8a9943d 900#define EXTRACT_FMT_37_MVFACHI_A_VARS \
8e420152
DE		 901 /* Instruction fields. */ \
902 UINT f_op1; \
903 UINT f_r1; \
904 UINT f_op2; \
905 UINT f_accs; \
906 UINT f_op3; \
907 unsigned int length;
b8a9943d 908#define EXTRACT_FMT_37_MVFACHI_A_CODE \
8e420152
DE		 909 length = 2; \
910 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
911 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
912 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
913 f_accs = EXTRACT_UNSIGNED (insn, 16, 12, 2); \
914 f_op3 = EXTRACT_UNSIGNED (insn, 16, 14, 2); \
915
b8a9943d 916#define EXTRACT_FMT_38_MVFC_VARS \
8e420152
DE		 917 /* Instruction fields. */ \
918 UINT f_op1; \
919 UINT f_r1; \
920 UINT f_op2; \
921 UINT f_r2; \
922 unsigned int length;
b8a9943d 923#define EXTRACT_FMT_38_MVFC_CODE \
8e420152
DE		 924 length = 2; \
925 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
926 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
927 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
928 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
929
b8a9943d 930#define EXTRACT_FMT_39_MVTACHI_A_VARS \
8e420152
DE		 931 /* Instruction fields. */ \
932 UINT f_op1; \
933 UINT f_r1; \
934 UINT f_op2; \
935 UINT f_accs; \
936 UINT f_op3; \
937 unsigned int length;
b8a9943d 938#define EXTRACT_FMT_39_MVTACHI_A_CODE \
8e420152
DE		 939 length = 2; \
940 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
941 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
942 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
943 f_accs = EXTRACT_UNSIGNED (insn, 16, 12, 2); \
944 f_op3 = EXTRACT_UNSIGNED (insn, 16, 14, 2); \
945
b8a9943d 946#define EXTRACT_FMT_40_MVTC_VARS \
8e420152
DE		 947 /* Instruction fields. */ \
948 UINT f_op1; \
949 UINT f_r1; \
950 UINT f_op2; \
951 UINT f_r2; \
952 unsigned int length;
b8a9943d 953#define EXTRACT_FMT_40_MVTC_CODE \
8e420152
DE		 954 length = 2; \
955 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
956 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
957 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
958 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
959
b8a9943d 960#define EXTRACT_FMT_41_NOP_VARS \
8e420152
DE		 961 /* Instruction fields. */ \
962 UINT f_op1; \
963 UINT f_r1; \
964 UINT f_op2; \
965 UINT f_r2; \
966 unsigned int length;
b8a9943d 967#define EXTRACT_FMT_41_NOP_CODE \
8e420152
DE		 968 length = 2; \
969 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
970 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
971 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
972 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
973
e0bd6e18 974#define EXTRACT_FMT_42_RAC_D_VARS \
8e420152
DE		 975 /* Instruction fields. */ \
976 UINT f_op1; \
e0bd6e18
DE		 977 UINT f_accd; \
978 UINT f_bits67; \
8e420152 979 UINT f_op2; \
b8a9943d 980 UINT f_accs; \
e0bd6e18
DE		 981 UINT f_bit14; \
982 UINT f_imm1; \
8e420152 983 unsigned int length;
e0bd6e18 984#define EXTRACT_FMT_42_RAC_D_CODE \
8e420152
DE		 985 length = 2; \
986 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
e0bd6e18
DE		 987 f_accd = EXTRACT_UNSIGNED (insn, 16, 4, 2); \
988 f_bits67 = EXTRACT_UNSIGNED (insn, 16, 6, 2); \
8e420152 989 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
b8a9943d 990 f_accs = EXTRACT_UNSIGNED (insn, 16, 12, 2); \
e0bd6e18
DE		 991 f_bit14 = EXTRACT_UNSIGNED (insn, 16, 14, 1); \
992 f_imm1 = EXTRACT_UNSIGNED (insn, 16, 15, 1); \
8e420152 993
e0bd6e18
DE		 994#define EXTRACT_FMT_43_RAC_DS_VARS \
995 /* Instruction fields. */ \
996 UINT f_op1; \
997 UINT f_accd; \
998 UINT f_bits67; \
999 UINT f_op2; \
1000 UINT f_accs; \
1001 UINT f_bit14; \
1002 UINT f_imm1; \
1003 unsigned int length;
1004#define EXTRACT_FMT_43_RAC_DS_CODE \
1005 length = 2; \
1006 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1007 f_accd = EXTRACT_UNSIGNED (insn, 16, 4, 2); \
1008 f_bits67 = EXTRACT_UNSIGNED (insn, 16, 6, 2); \
1009 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1010 f_accs = EXTRACT_UNSIGNED (insn, 16, 12, 2); \
1011 f_bit14 = EXTRACT_UNSIGNED (insn, 16, 14, 1); \
1012 f_imm1 = EXTRACT_UNSIGNED (insn, 16, 15, 1); \
1013
1014#define EXTRACT_FMT_44_RAC_DSI_VARS \
1015 /* Instruction fields. */ \
1016 UINT f_op1; \
1017 UINT f_accd; \
1018 UINT f_bits67; \
1019 UINT f_op2; \
1020 UINT f_accs; \
1021 UINT f_bit14; \
1022 UINT f_imm1; \
1023 unsigned int length;
1024#define EXTRACT_FMT_44_RAC_DSI_CODE \
1025 length = 2; \
1026 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1027 f_accd = EXTRACT_UNSIGNED (insn, 16, 4, 2); \
1028 f_bits67 = EXTRACT_UNSIGNED (insn, 16, 6, 2); \
1029 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1030 f_accs = EXTRACT_UNSIGNED (insn, 16, 12, 2); \
1031 f_bit14 = EXTRACT_UNSIGNED (insn, 16, 14, 1); \
1032 f_imm1 = EXTRACT_UNSIGNED (insn, 16, 15, 1); \
1033
1034#define EXTRACT_FMT_45_RTE_VARS \
8e420152
DE		 1035 /* Instruction fields. */ \
1036 UINT f_op1; \
1037 UINT f_r1; \
1038 UINT f_op2; \
b8a9943d 1039 UINT f_r2; \
8e420152 1040 unsigned int length;
e0bd6e18 1041#define EXTRACT_FMT_45_RTE_CODE \
8e420152
DE		 1042 length = 2; \
1043 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1044 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1045 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
b8a9943d 1046 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
8e420152 1047
e0bd6e18 1048#define EXTRACT_FMT_46_SETH_VARS \
8e420152
DE		 1049 /* Instruction fields. */ \
1050 UINT f_op1; \
1051 UINT f_r1; \
1052 UINT f_op2; \
1053 UINT f_r2; \
1054 UINT f_hi16; \
1055 unsigned int length;
e0bd6e18 1056#define EXTRACT_FMT_46_SETH_CODE \
8e420152
DE		 1057 length = 4; \
1058 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
1059 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
1060 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
1061 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
1062 f_hi16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
1063
e0bd6e18 1064#define EXTRACT_FMT_47_SLLI_VARS \
8e420152
DE		 1065 /* Instruction fields. */ \
1066 UINT f_op1; \
1067 UINT f_r1; \
1068 UINT f_shift_op2; \
1069 UINT f_uimm5; \
1070 unsigned int length;
e0bd6e18 1071#define EXTRACT_FMT_47_SLLI_CODE \
8e420152
DE		 1072 length = 2; \
1073 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1074 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1075 f_shift_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 3); \
1076 f_uimm5 = EXTRACT_UNSIGNED (insn, 16, 11, 5); \
1077
e0bd6e18 1078#define EXTRACT_FMT_48_ST_D_VARS \
8e420152
DE		 1079 /* Instruction fields. */ \
1080 UINT f_op1; \
1081 UINT f_r1; \
1082 UINT f_op2; \
1083 UINT f_r2; \
1084 int f_simm16; \
1085 unsigned int length;
e0bd6e18 1086#define EXTRACT_FMT_48_ST_D_CODE \
8e420152
DE		 1087 length = 4; \
1088 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
1089 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
1090 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
1091 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
1092 f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
1093
e0bd6e18 1094#define EXTRACT_FMT_49_TRAP_VARS \
8e420152
DE		 1095 /* Instruction fields. */ \
1096 UINT f_op1; \
1097 UINT f_r1; \
1098 UINT f_op2; \
1099 UINT f_uimm4; \
1100 unsigned int length;
e0bd6e18 1101#define EXTRACT_FMT_49_TRAP_CODE \
8e420152
DE		 1102 length = 2; \
1103 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1104 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1105 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1106 f_uimm4 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1107
e0bd6e18 1108#define EXTRACT_FMT_50_SATB_VARS \
b8a9943d
DE		 1109 /* Instruction fields. */ \
1110 UINT f_op1; \
1111 UINT f_r1; \
1112 UINT f_op2; \
1113 UINT f_r2; \
1114 UINT f_uimm16; \
1115 unsigned int length;
e0bd6e18 1116#define EXTRACT_FMT_50_SATB_CODE \
b8a9943d
DE		 1117 length = 4; \
1118 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
1119 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
1120 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
1121 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
1122 f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
1123
e0bd6e18 1124#define EXTRACT_FMT_51_SAT_VARS \
8e420152
DE		 1125 /* Instruction fields. */ \
1126 UINT f_op1; \
1127 UINT f_r1; \
1128 UINT f_op2; \
1129 UINT f_r2; \
1130 UINT f_uimm16; \
1131 unsigned int length;
e0bd6e18 1132#define EXTRACT_FMT_51_SAT_CODE \
8e420152
DE		 1133 length = 4; \
1134 f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
1135 f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
1136 f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
1137 f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
1138 f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
1139
e0bd6e18 1140#define EXTRACT_FMT_52_SADD_VARS \
8e420152
DE		 1141 /* Instruction fields. */ \
1142 UINT f_op1; \
1143 UINT f_r1; \
1144 UINT f_op2; \
1145 UINT f_r2; \
1146 unsigned int length;
e0bd6e18 1147#define EXTRACT_FMT_52_SADD_CODE \
8e420152
DE		 1148 length = 2; \
1149 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1150 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1151 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1152 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1153
e0bd6e18 1154#define EXTRACT_FMT_53_MACWU1_VARS \
8e420152
DE		 1155 /* Instruction fields. */ \
1156 UINT f_op1; \
1157 UINT f_r1; \
1158 UINT f_op2; \
1159 UINT f_r2; \
1160 unsigned int length;
e0bd6e18 1161#define EXTRACT_FMT_53_MACWU1_CODE \
8e420152
DE		 1162 length = 2; \
1163 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1164 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1165 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1166 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1167
e0bd6e18 1168#define EXTRACT_FMT_54_MSBLO_VARS \
8e420152
DE		 1169 /* Instruction fields. */ \
1170 UINT f_op1; \
1171 UINT f_r1; \
1172 UINT f_op2; \
1173 UINT f_r2; \
1174 unsigned int length;
e0bd6e18 1175#define EXTRACT_FMT_54_MSBLO_CODE \
8e420152
DE		 1176 length = 2; \
1177 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1178 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1179 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1180 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1181
e0bd6e18 1182#define EXTRACT_FMT_55_SC_VARS \
8e420152
DE		 1183 /* Instruction fields. */ \
1184 UINT f_op1; \
1185 UINT f_r1; \
1186 UINT f_op2; \
1187 UINT f_r2; \
1188 unsigned int length;
e0bd6e18 1189#define EXTRACT_FMT_55_SC_CODE \
8e420152
DE		 1190 length = 2; \
1191 f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1192 f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1193 f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1194 f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1195
1196/* Fetched input values of an instruction. */
1197
e0bd6e18 1198struct parexec {
8e420152
DE		 1199 union {
1200 struct { /* e.g. add $dr,$sr */
1201 SI dr;
1202 SI sr;
1203 } fmt_0_add;
1204 struct { /* e.g. add3 $dr,$sr,#$slo16 */
1205 HI slo16;
1206 SI sr;
1207 } fmt_1_add3;
1208 struct { /* e.g. and3 $dr,$sr,#$uimm16 */
1209 SI sr;
1210 USI uimm16;
1211 } fmt_2_and3;
1212 struct { /* e.g. or3 $dr,$sr,#$ulo16 */
1213 SI sr;
1214 UHI ulo16;
1215 } fmt_3_or3;
1216 struct { /* e.g. addi $dr,#$simm8 */
1217 SI dr;
1218 SI simm8;
1219 } fmt_4_addi;
1220 struct { /* e.g. addv3 $dr,$sr,#$simm16 */
1221 SI simm16;
1222 SI sr;
1223 } fmt_5_addv3;
1224 struct { /* e.g. addx $dr,$sr */
1225 UBI condbit;
1226 SI dr;
1227 SI sr;
1228 } fmt_6_addx;
1229 struct { /* e.g. bc $disp8 */
1230 UBI condbit;
1231 IADDR disp8;
1232 } fmt_7_bc8;
1233 struct { /* e.g. bc $disp24 */
1234 UBI condbit;
1235 IADDR disp24;
1236 } fmt_8_bc24;
1237 struct { /* e.g. beq $src1,$src2,$disp16 */
1238 IADDR disp16;
1239 SI src1;
1240 SI src2;
1241 } fmt_9_beq;
1242 struct { /* e.g. beqz $src2,$disp16 */
1243 IADDR disp16;
1244 SI src2;
1245 } fmt_10_beqz;
1246 struct { /* e.g. bl $disp8 */
1247 IADDR disp8;
1248 USI pc;
1249 } fmt_11_bl8;
1250 struct { /* e.g. bl $disp24 */
1251 IADDR disp24;
1252 USI pc;
1253 } fmt_12_bl24;
1254 struct { /* e.g. bcl $disp8 */
1255 UBI condbit;
1256 IADDR disp8;
1257 USI pc;
1258 } fmt_13_bcl8;
1259 struct { /* e.g. bcl $disp24 */
1260 UBI condbit;
1261 IADDR disp24;
1262 USI pc;
1263 } fmt_14_bcl24;
1264 struct { /* e.g. bra $disp8 */
1265 IADDR disp8;
1266 } fmt_15_bra8;
1267 struct { /* e.g. bra $disp24 */
1268 IADDR disp24;
1269 } fmt_16_bra24;
1270 struct { /* e.g. cmp $src1,$src2 */
1271 SI src1;
1272 SI src2;
1273 } fmt_17_cmp;
1274 struct { /* e.g. cmpi $src2,#$simm16 */
1275 SI simm16;
1276 SI src2;
1277 } fmt_18_cmpi;
1278 struct { /* e.g. cmpui $src2,#$uimm16 */
1279 SI src2;
1280 USI uimm16;
1281 } fmt_19_cmpui;
1282 struct { /* e.g. cmpz $src2 */
1283 SI src2;
1284 } fmt_20_cmpz;
1285 struct { /* e.g. div $dr,$sr */
1286 SI dr;
1287 SI sr;
1288 } fmt_21_div;
1289 struct { /* e.g. jc $sr */
1290 UBI condbit;
1291 SI sr;
1292 } fmt_22_jc;
1293 struct { /* e.g. jl $sr */
1294 USI pc;
1295 SI sr;
1296 } fmt_23_jl;
1297 struct { /* e.g. jmp $sr */
1298 SI sr;
1299 } fmt_24_jmp;
1300 struct { /* e.g. ld $dr,@$sr */
b8a9943d 1301 UQI h_memory_sr;
8e420152
DE		 1302 SI sr;
1303 } fmt_25_ld;
1304 struct { /* e.g. ld $dr,@($slo16,$sr) */
b8a9943d 1305 UQI h_memory_add_WI_sr_slo16;
8e420152
DE		 1306 HI slo16;
1307 SI sr;
1308 } fmt_26_ld_d;
1309 struct { /* e.g. ldb $dr,@$sr */
b8a9943d 1310 UQI h_memory_sr;
8e420152
DE		 1311 SI sr;
1312 } fmt_27_ldb;
1313 struct { /* e.g. ldb $dr,@($slo16,$sr) */
b8a9943d 1314 UQI h_memory_add_WI_sr_slo16;
8e420152
DE		 1315 HI slo16;
1316 SI sr;
1317 } fmt_28_ldb_d;
1318 struct { /* e.g. ldh $dr,@$sr */
b8a9943d 1319 UQI h_memory_sr;
8e420152
DE		 1320 SI sr;
1321 } fmt_29_ldh;
1322 struct { /* e.g. ldh $dr,@($slo16,$sr) */
b8a9943d 1323 UQI h_memory_add_WI_sr_slo16;
8e420152
DE		 1324 HI slo16;
1325 SI sr;
1326 } fmt_30_ldh_d;
1327 struct { /* e.g. ld24 $dr,#$uimm24 */
1328 ADDR uimm24;
1329 } fmt_31_ld24;
1330 struct { /* e.g. ldi $dr,#$simm8 */
1331 SI simm8;
1332 } fmt_32_ldi8;
1333 struct { /* e.g. ldi $dr,$slo16 */
1334 HI slo16;
1335 } fmt_33_ldi16;
8e420152
DE		 1336 struct { /* e.g. machi $src1,$src2,$acc */
1337 DI acc;
1338 SI src1;
1339 SI src2;
b8a9943d 1340 } fmt_34_machi_a;
8e420152
DE		 1341 struct { /* e.g. mulhi $src1,$src2,$acc */
1342 SI src1;
1343 SI src2;
b8a9943d 1344 } fmt_35_mulhi_a;
8e420152
DE		 1345 struct { /* e.g. mv $dr,$sr */
1346 SI sr;
b8a9943d 1347 } fmt_36_mv;
8e420152
DE		 1348 struct { /* e.g. mvfachi $dr,$accs */
1349 DI accs;
b8a9943d 1350 } fmt_37_mvfachi_a;
8e420152
DE		 1351 struct { /* e.g. mvfc $dr,$scr */
1352 SI scr;
b8a9943d 1353 } fmt_38_mvfc;
8e420152
DE		 1354 struct { /* e.g. mvtachi $src1,$accs */
1355 DI accs;
1356 SI src1;
b8a9943d 1357 } fmt_39_mvtachi_a;
8e420152
DE		 1358 struct { /* e.g. mvtc $sr,$dcr */
1359 SI sr;
b8a9943d 1360 } fmt_40_mvtc;
8e420152
DE		 1361 struct { /* e.g. nop */
1362 int empty;
b8a9943d 1363 } fmt_41_nop;
e0bd6e18
DE		 1364 struct { /* e.g. rac $accd */
1365 DI accum;
1366 } fmt_42_rac_d;
1367 struct { /* e.g. rac $accd,$accs */
1368 DI accs;
1369 } fmt_43_rac_ds;
1370 struct { /* e.g. rac $accd,$accs,#$imm1 */
8e420152 1371 DI accs;
e0bd6e18
DE		 1372 USI imm1;
1373 } fmt_44_rac_dsi;
b8a9943d
DE		 1374 struct { /* e.g. rte */
1375 UBI h_bcond_0;
1376 UBI h_bie_0;
1377 SI h_bpc_0;
1378 UBI h_bsm_0;
e0bd6e18 1379 } fmt_45_rte;
b8a9943d 1380 struct { /* e.g. seth $dr,#$hi16 */
8e420152 1381 UHI hi16;
e0bd6e18 1382 } fmt_46_seth;
8e420152
DE		 1383 struct { /* e.g. slli $dr,#$uimm5 */
1384 SI dr;
1385 USI uimm5;
e0bd6e18 1386 } fmt_47_slli;
8e420152
DE		 1387 struct { /* e.g. st $src1,@($slo16,$src2) */
1388 HI slo16;
1389 SI src1;
1390 SI src2;
e0bd6e18 1391 } fmt_48_st_d;
8e420152
DE		 1392 struct { /* e.g. trap #$uimm4 */
1393 USI uimm4;
e0bd6e18 1394 } fmt_49_trap;
8e420152 1395 struct { /* e.g. satb $dr,$src2 */
b8a9943d 1396 SI src2;
e0bd6e18 1397 } fmt_50_satb;
b8a9943d
DE		 1398 struct { /* e.g. sat $dr,$src2 */
1399 UBI condbit;
1400 SI src2;
e0bd6e18 1401 } fmt_51_sat;
8e420152 1402 struct { /* e.g. sadd */
b8a9943d
DE		 1403 DI h_accums_0;
1404 DI h_accums_1;
e0bd6e18 1405 } fmt_52_sadd;
8e420152 1406 struct { /* e.g. macwu1 $src1,$src2 */
b8a9943d
DE		 1407 DI h_accums_1;
1408 SI src1;
1409 SI src2;
e0bd6e18 1410 } fmt_53_macwu1;
b8a9943d
DE		 1411 struct { /* e.g. msblo $src1,$src2 */
1412 DI accum;
8e420152
DE		 1413 SI src1;
1414 SI src2;
e0bd6e18 1415 } fmt_54_msblo;
8e420152
DE		 1416 struct { /* e.g. sc */
1417 UBI condbit;
e0bd6e18 1418 } fmt_55_sc;
8e420152
DE		 1419 } operands;
1420};
1421
1422#endif /* CPU_M32RX_H */
GDB Binutils - Deliverables
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