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[deliverable/binutils-gdb.git] / sim / m32r / cpux.h
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2df3850c
JM		 1/* CPU family header for m32rxf.
2
3THIS FILE IS MACHINE GENERATED WITH CGEN.
4
16b47b25 5Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
2df3850c 6
378af1d6 7This file is part of the GNU simulators.
2df3850c
JM		 8
9This program is free software; you can redistribute it and/or modify
10it under the terms of the GNU General Public License as published by
4744ac1b
JB		 11the Free Software Foundation; either version 3 of the License, or
12(at your option) any later version.
2df3850c
JM		 13
14This program is distributed in the hope that it will be useful,
15but WITHOUT ANY WARRANTY; without even the implied warranty of
16MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17GNU General Public License for more details.
18
4744ac1b
JB		 19You should have received a copy of the GNU General Public License
20along with this program. If not, see <http://www.gnu.org/licenses/>.
2df3850c
JM		 21
22*/
23
24#ifndef CPU_M32RXF_H
25#define CPU_M32RXF_H
26
27/* Maximum number of instructions that are fetched at a time.
28 This is for LIW type instructions sets (e.g. m32r). */
29#define MAX_LIW_INSNS 2
30
31/* Maximum number of instructions that can be executed in parallel. */
32#define MAX_PARALLEL_INSNS 2
33
34/* CPU state information. */
35typedef struct {
36 /* Hardware elements. */
37 struct {
38 /* program counter */
39 USI h_pc;
40#define GET_H_PC() CPU (h_pc)
41#define SET_H_PC(x) (CPU (h_pc) = (x))
42 /* general registers */
43 SI h_gr[16];
44#define GET_H_GR(a1) CPU (h_gr)[a1]
45#define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
46 /* control registers */
47 USI h_cr[16];
48#define GET_H_CR(index) m32rxf_h_cr_get_handler (current_cpu, index)
49#define SET_H_CR(index, x) \
50do { \
51m32rxf_h_cr_set_handler (current_cpu, (index), (x));\
de8f5985 52;} while (0)
2df3850c
JM		 53 /* accumulator */
54 DI h_accum;
55#define GET_H_ACCUM() m32rxf_h_accum_get_handler (current_cpu)
56#define SET_H_ACCUM(x) \
57do { \
58m32rxf_h_accum_set_handler (current_cpu, (x));\
de8f5985 59;} while (0)
2df3850c
JM		 60 /* accumulators */
61 DI h_accums[2];
62#define GET_H_ACCUMS(index) m32rxf_h_accums_get_handler (current_cpu, index)
63#define SET_H_ACCUMS(index, x) \
64do { \
65m32rxf_h_accums_set_handler (current_cpu, (index), (x));\
de8f5985 66;} while (0)
2df3850c
JM		 67 /* condition bit */
68 BI h_cond;
69#define GET_H_COND() CPU (h_cond)
70#define SET_H_COND(x) (CPU (h_cond) = (x))
71 /* psw part of psw */
72 UQI h_psw;
73#define GET_H_PSW() m32rxf_h_psw_get_handler (current_cpu)
74#define SET_H_PSW(x) \
75do { \
76m32rxf_h_psw_set_handler (current_cpu, (x));\
de8f5985 77;} while (0)
2df3850c
JM		 78 /* backup psw */
79 UQI h_bpsw;
80#define GET_H_BPSW() CPU (h_bpsw)
81#define SET_H_BPSW(x) (CPU (h_bpsw) = (x))
82 /* backup bpsw */
83 UQI h_bbpsw;
84#define GET_H_BBPSW() CPU (h_bbpsw)
85#define SET_H_BBPSW(x) (CPU (h_bbpsw) = (x))
86 /* lock */
87 BI h_lock;
88#define GET_H_LOCK() CPU (h_lock)
89#define SET_H_LOCK(x) (CPU (h_lock) = (x))
90 } hardware;
91#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
92} M32RXF_CPU_DATA;
93
94/* Cover fns for register access. */
95USI m32rxf_h_pc_get (SIM_CPU *);
96void m32rxf_h_pc_set (SIM_CPU *, USI);
97SI m32rxf_h_gr_get (SIM_CPU *, UINT);
98void m32rxf_h_gr_set (SIM_CPU *, UINT, SI);
99USI m32rxf_h_cr_get (SIM_CPU *, UINT);
100void m32rxf_h_cr_set (SIM_CPU *, UINT, USI);
101DI m32rxf_h_accum_get (SIM_CPU *);
102void m32rxf_h_accum_set (SIM_CPU *, DI);
103DI m32rxf_h_accums_get (SIM_CPU *, UINT);
104void m32rxf_h_accums_set (SIM_CPU *, UINT, DI);
105BI m32rxf_h_cond_get (SIM_CPU *);
106void m32rxf_h_cond_set (SIM_CPU *, BI);
107UQI m32rxf_h_psw_get (SIM_CPU *);
108void m32rxf_h_psw_set (SIM_CPU *, UQI);
109UQI m32rxf_h_bpsw_get (SIM_CPU *);
110void m32rxf_h_bpsw_set (SIM_CPU *, UQI);
111UQI m32rxf_h_bbpsw_get (SIM_CPU *);
112void m32rxf_h_bbpsw_set (SIM_CPU *, UQI);
113BI m32rxf_h_lock_get (SIM_CPU *);
114void m32rxf_h_lock_set (SIM_CPU *, BI);
115
116/* These must be hand-written. */
117extern CPUREG_FETCH_FN m32rxf_fetch_register;
118extern CPUREG_STORE_FN m32rxf_store_register;
119
120typedef struct {
121 int empty;
122} MODEL_M32RX_DATA;
123
124/* Instruction argument buffer. */
125
126union sem_fields {
127 struct { /* no operands */
128 int empty;
129 } fmt_empty;
16b47b25
NC		 130 struct { /* */
131 UINT f_uimm8;
132 } sfmt_clrpsw;
2df3850c
JM		 133 struct { /* */
134 UINT f_uimm4;
135 } sfmt_trap;
136 struct { /* */
137 IADDR i_disp24;
378af1d6 138 unsigned char out_h_gr_SI_14;
2df3850c
JM		 139 } sfmt_bl24;
140 struct { /* */
141 IADDR i_disp8;
378af1d6 142 unsigned char out_h_gr_SI_14;
2df3850c 143 } sfmt_bl8;
2df3850c
JM		 144 struct { /* */
145 SI f_imm1;
146 UINT f_accd;
147 UINT f_accs;
148 } sfmt_rac_dsi;
149 struct { /* */
de8f5985
DB		 150 SI* i_dr;
151 UINT f_hi16;
2df3850c 152 UINT f_r1;
de8f5985
DB		 153 unsigned char out_dr;
154 } sfmt_seth;
2df3850c
JM		 155 struct { /* */
156 SI* i_src1;
157 UINT f_accs;
de8f5985 158 UINT f_r1;
2df3850c
JM		 159 unsigned char in_src1;
160 } sfmt_mvtachi_a;
2df3850c
JM		 161 struct { /* */
162 SI* i_dr;
163 UINT f_accs;
de8f5985 164 UINT f_r1;
2df3850c
JM		 165 unsigned char out_dr;
166 } sfmt_mvfachi_a;
167 struct { /* */
168 ADDR i_uimm24;
169 SI* i_dr;
de8f5985 170 UINT f_r1;
2df3850c
JM		 171 unsigned char out_dr;
172 } sfmt_ld24;
173 struct { /* */
174 SI* i_sr;
de8f5985 175 UINT f_r2;
2df3850c 176 unsigned char in_sr;
378af1d6 177 unsigned char out_h_gr_SI_14;
2df3850c 178 } sfmt_jl;
16b47b25
NC		 179 struct { /* */
180 SI* i_sr;
181 INT f_simm16;
182 UINT f_r2;
183 UINT f_uimm3;
184 unsigned char in_sr;
185 } sfmt_bset;
2df3850c
JM		 186 struct { /* */
187 SI* i_dr;
de8f5985 188 UINT f_r1;
2df3850c
JM		 189 UINT f_uimm5;
190 unsigned char in_dr;
191 unsigned char out_dr;
192 } sfmt_slli;
193 struct { /* */
194 SI* i_dr;
195 INT f_simm8;
de8f5985 196 UINT f_r1;
2df3850c
JM		 197 unsigned char in_dr;
198 unsigned char out_dr;
199 } sfmt_addi;
200 struct { /* */
201 SI* i_src1;
202 SI* i_src2;
de8f5985
DB		 203 UINT f_r1;
204 UINT f_r2;
2df3850c
JM		 205 unsigned char in_src1;
206 unsigned char in_src2;
207 unsigned char out_src2;
208 } sfmt_st_plus;
209 struct { /* */
210 SI* i_src1;
211 SI* i_src2;
212 INT f_simm16;
de8f5985
DB		 213 UINT f_r1;
214 UINT f_r2;
2df3850c
JM		 215 unsigned char in_src1;
216 unsigned char in_src2;
217 } sfmt_st_d;
218 struct { /* */
219 SI* i_src1;
220 SI* i_src2;
221 UINT f_acc;
de8f5985
DB		 222 UINT f_r1;
223 UINT f_r2;
2df3850c
JM		 224 unsigned char in_src1;
225 unsigned char in_src2;
226 } sfmt_machi_a;
227 struct { /* */
228 SI* i_dr;
229 SI* i_sr;
de8f5985
DB		 230 UINT f_r1;
231 UINT f_r2;
2df3850c
JM		 232 unsigned char in_sr;
233 unsigned char out_dr;
234 unsigned char out_sr;
235 } sfmt_ld_plus;
236 struct { /* */
237 IADDR i_disp16;
238 SI* i_src1;
239 SI* i_src2;
de8f5985
DB		 240 UINT f_r1;
241 UINT f_r2;
2df3850c
JM		 242 unsigned char in_src1;
243 unsigned char in_src2;
244 } sfmt_beq;
245 struct { /* */
246 SI* i_dr;
247 SI* i_sr;
de8f5985
DB		 248 UINT f_r1;
249 UINT f_r2;
2df3850c
JM		 250 UINT f_uimm16;
251 unsigned char in_sr;
252 unsigned char out_dr;
253 } sfmt_and3;
254 struct { /* */
255 SI* i_dr;
256 SI* i_sr;
257 INT f_simm16;
de8f5985
DB		 258 UINT f_r1;
259 UINT f_r2;
2df3850c
JM		 260 unsigned char in_sr;
261 unsigned char out_dr;
262 } sfmt_add3;
263 struct { /* */
264 SI* i_dr;
265 SI* i_sr;
de8f5985
DB		 266 UINT f_r1;
267 UINT f_r2;
2df3850c
JM		 268 unsigned char in_dr;
269 unsigned char in_sr;
270 unsigned char out_dr;
271 } sfmt_add;
272#if WITH_SCACHE_PBB
273 /* Writeback handler. */
274 struct {
275 /* Pointer to argbuf entry for insn whose results need writing back. */
276 const struct argbuf *abuf;
277 } write;
278 /* x-before handler */
279 struct {
280 /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
281 int first_p;
282 } before;
283 /* x-after handler */
284 struct {
285 int empty;
286 } after;
287 /* This entry is used to terminate each pbb. */
288 struct {
289 /* Number of insns in pbb. */
290 int insn_count;
291 /* Next pbb to execute. */
292 SCACHE *next;
293 SCACHE *branch_target;
294 } chain;
295#endif
296};
297
298/* The ARGBUF struct. */
299struct argbuf {
300 /* These are the baseclass definitions. */
301 IADDR addr;
302 const IDESC *idesc;
303 char trace_p;
304 char profile_p;
305 /* ??? Temporary hack for skip insns. */
306 char skip_count;
307 char unused;
308 /* cpu specific data follows */
309 union sem semantic;
310 int written;
311 union sem_fields fields;
312};
313
314/* A cached insn.
315
316 ??? SCACHE used to contain more than just argbuf. We could delete the
317 type entirely and always just use ARGBUF, but for future concerns and as
318 a level of abstraction it is left in. */
319
320struct scache {
321 struct argbuf argbuf;
322};
323
324/* Macros to simplify extraction, reading and semantic code.
325 These define and assign the local vars that contain the insn's fields. */
326
327#define EXTRACT_IFMT_EMPTY_VARS \
328 unsigned int length;
329#define EXTRACT_IFMT_EMPTY_CODE \
330 length = 0; \
331
332#define EXTRACT_IFMT_ADD_VARS \
333 UINT f_op1; \
334 UINT f_r1; \
335 UINT f_op2; \
336 UINT f_r2; \
337 unsigned int length;
338#define EXTRACT_IFMT_ADD_CODE \
339 length = 2; \
340 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
341 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
342 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
343 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
344
345#define EXTRACT_IFMT_ADD3_VARS \
346 UINT f_op1; \
347 UINT f_r1; \
348 UINT f_op2; \
349 UINT f_r2; \
350 INT f_simm16; \
351 unsigned int length;
352#define EXTRACT_IFMT_ADD3_CODE \
353 length = 4; \
354 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
355 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
356 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
357 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
358 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
359
360#define EXTRACT_IFMT_AND3_VARS \
361 UINT f_op1; \
362 UINT f_r1; \
363 UINT f_op2; \
364 UINT f_r2; \
365 UINT f_uimm16; \
366 unsigned int length;
367#define EXTRACT_IFMT_AND3_CODE \
368 length = 4; \
369 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
370 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
371 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
372 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
373 f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
374
375#define EXTRACT_IFMT_OR3_VARS \
376 UINT f_op1; \
377 UINT f_r1; \
378 UINT f_op2; \
379 UINT f_r2; \
380 UINT f_uimm16; \
381 unsigned int length;
382#define EXTRACT_IFMT_OR3_CODE \
383 length = 4; \
384 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
385 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
386 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
387 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
388 f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
389
390#define EXTRACT_IFMT_ADDI_VARS \
391 UINT f_op1; \
392 UINT f_r1; \
393 INT f_simm8; \
394 unsigned int length;
395#define EXTRACT_IFMT_ADDI_CODE \
396 length = 2; \
397 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
398 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
399 f_simm8 = EXTRACT_MSB0_INT (insn, 16, 8, 8); \
400
401#define EXTRACT_IFMT_ADDV3_VARS \
402 UINT f_op1; \
403 UINT f_r1; \
404 UINT f_op2; \
405 UINT f_r2; \
406 INT f_simm16; \
407 unsigned int length;
408#define EXTRACT_IFMT_ADDV3_CODE \
409 length = 4; \
410 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
411 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
412 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
413 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
414 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
415
416#define EXTRACT_IFMT_BC8_VARS \
417 UINT f_op1; \
418 UINT f_r1; \
419 SI f_disp8; \
420 unsigned int length;
421#define EXTRACT_IFMT_BC8_CODE \
422 length = 2; \
423 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
424 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
425 f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
426
427#define EXTRACT_IFMT_BC24_VARS \
428 UINT f_op1; \
429 UINT f_r1; \
430 SI f_disp24; \
431 unsigned int length;
432#define EXTRACT_IFMT_BC24_CODE \
433 length = 4; \
434 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
435 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
436 f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc)); \
437
438#define EXTRACT_IFMT_BEQ_VARS \
439 UINT f_op1; \
440 UINT f_r1; \
441 UINT f_op2; \
442 UINT f_r2; \
443 SI f_disp16; \
444 unsigned int length;
445#define EXTRACT_IFMT_BEQ_CODE \
446 length = 4; \
447 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
448 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
449 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
450 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
451 f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
452
453#define EXTRACT_IFMT_BEQZ_VARS \
454 UINT f_op1; \
455 UINT f_r1; \
456 UINT f_op2; \
457 UINT f_r2; \
458 SI f_disp16; \
459 unsigned int length;
460#define EXTRACT_IFMT_BEQZ_CODE \
461 length = 4; \
462 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
463 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
464 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
465 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
466 f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
467
468#define EXTRACT_IFMT_CMP_VARS \
469 UINT f_op1; \
470 UINT f_r1; \
471 UINT f_op2; \
472 UINT f_r2; \
473 unsigned int length;
474#define EXTRACT_IFMT_CMP_CODE \
475 length = 2; \
476 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
477 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
478 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
479 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
480
481#define EXTRACT_IFMT_CMPI_VARS \
482 UINT f_op1; \
483 UINT f_r1; \
484 UINT f_op2; \
485 UINT f_r2; \
486 INT f_simm16; \
487 unsigned int length;
488#define EXTRACT_IFMT_CMPI_CODE \
489 length = 4; \
490 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
491 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
492 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
493 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
494 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
495
496#define EXTRACT_IFMT_CMPZ_VARS \
497 UINT f_op1; \
498 UINT f_r1; \
499 UINT f_op2; \
500 UINT f_r2; \
501 unsigned int length;
502#define EXTRACT_IFMT_CMPZ_CODE \
503 length = 2; \
504 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
505 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
506 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
507 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
508
509#define EXTRACT_IFMT_DIV_VARS \
510 UINT f_op1; \
511 UINT f_r1; \
512 UINT f_op2; \
513 UINT f_r2; \
514 INT f_simm16; \
515 unsigned int length;
516#define EXTRACT_IFMT_DIV_CODE \
517 length = 4; \
518 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
519 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
520 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
521 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
522 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
523
524#define EXTRACT_IFMT_JC_VARS \
525 UINT f_op1; \
526 UINT f_r1; \
527 UINT f_op2; \
528 UINT f_r2; \
529 unsigned int length;
530#define EXTRACT_IFMT_JC_CODE \
531 length = 2; \
532 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
533 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
534 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
535 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
536
537#define EXTRACT_IFMT_LD24_VARS \
538 UINT f_op1; \
539 UINT f_r1; \
540 UINT f_uimm24; \
541 unsigned int length;
542#define EXTRACT_IFMT_LD24_CODE \
543 length = 4; \
544 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
545 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
546 f_uimm24 = EXTRACT_MSB0_UINT (insn, 32, 8, 24); \
547
548#define EXTRACT_IFMT_LDI16_VARS \
549 UINT f_op1; \
550 UINT f_r1; \
551 UINT f_op2; \
552 UINT f_r2; \
553 INT f_simm16; \
554 unsigned int length;
555#define EXTRACT_IFMT_LDI16_CODE \
556 length = 4; \
557 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
558 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
559 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
560 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
561 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
562
563#define EXTRACT_IFMT_MACHI_A_VARS \
564 UINT f_op1; \
565 UINT f_r1; \
566 UINT f_acc; \
567 UINT f_op23; \
568 UINT f_r2; \
569 unsigned int length;
570#define EXTRACT_IFMT_MACHI_A_CODE \
571 length = 2; \
572 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
573 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
574 f_acc = EXTRACT_MSB0_UINT (insn, 16, 8, 1); \
575 f_op23 = EXTRACT_MSB0_UINT (insn, 16, 9, 3); \
576 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
577
578#define EXTRACT_IFMT_MVFACHI_A_VARS \
579 UINT f_op1; \
580 UINT f_r1; \
581 UINT f_op2; \
582 UINT f_accs; \
583 UINT f_op3; \
584 unsigned int length;
585#define EXTRACT_IFMT_MVFACHI_A_CODE \
586 length = 2; \
587 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
588 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
589 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
590 f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); \
591 f_op3 = EXTRACT_MSB0_UINT (insn, 16, 14, 2); \
592
593#define EXTRACT_IFMT_MVFC_VARS \
594 UINT f_op1; \
595 UINT f_r1; \
596 UINT f_op2; \
597 UINT f_r2; \
598 unsigned int length;
599#define EXTRACT_IFMT_MVFC_CODE \
600 length = 2; \
601 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
602 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
603 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
604 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
605
606#define EXTRACT_IFMT_MVTACHI_A_VARS \
607 UINT f_op1; \
608 UINT f_r1; \
609 UINT f_op2; \
610 UINT f_accs; \
611 UINT f_op3; \
612 unsigned int length;
613#define EXTRACT_IFMT_MVTACHI_A_CODE \
614 length = 2; \
615 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
616 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
617 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
618 f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); \
619 f_op3 = EXTRACT_MSB0_UINT (insn, 16, 14, 2); \
620
621#define EXTRACT_IFMT_MVTC_VARS \
622 UINT f_op1; \
623 UINT f_r1; \
624 UINT f_op2; \
625 UINT f_r2; \
626 unsigned int length;
627#define EXTRACT_IFMT_MVTC_CODE \
628 length = 2; \
629 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
630 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
631 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
632 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
633
634#define EXTRACT_IFMT_NOP_VARS \
635 UINT f_op1; \
636 UINT f_r1; \
637 UINT f_op2; \
638 UINT f_r2; \
639 unsigned int length;
640#define EXTRACT_IFMT_NOP_CODE \
641 length = 2; \
642 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
643 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
644 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
645 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
646
647#define EXTRACT_IFMT_RAC_DSI_VARS \
648 UINT f_op1; \
649 UINT f_accd; \
650 UINT f_bits67; \
651 UINT f_op2; \
652 UINT f_accs; \
653 UINT f_bit14; \
654 SI f_imm1; \
655 unsigned int length;
656#define EXTRACT_IFMT_RAC_DSI_CODE \
657 length = 2; \
658 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
659 f_accd = EXTRACT_MSB0_UINT (insn, 16, 4, 2); \
660 f_bits67 = EXTRACT_MSB0_UINT (insn, 16, 6, 2); \
661 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
662 f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); \
663 f_bit14 = EXTRACT_MSB0_UINT (insn, 16, 14, 1); \
664 f_imm1 = ((EXTRACT_MSB0_UINT (insn, 16, 15, 1)) + (1)); \
665
666#define EXTRACT_IFMT_SETH_VARS \
667 UINT f_op1; \
668 UINT f_r1; \
669 UINT f_op2; \
670 UINT f_r2; \
671 UINT f_hi16; \
672 unsigned int length;
673#define EXTRACT_IFMT_SETH_CODE \
674 length = 4; \
675 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
676 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
677 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
678 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
679 f_hi16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
680
681#define EXTRACT_IFMT_SLLI_VARS \
682 UINT f_op1; \
683 UINT f_r1; \
684 UINT f_shift_op2; \
685 UINT f_uimm5; \
686 unsigned int length;
687#define EXTRACT_IFMT_SLLI_CODE \
688 length = 2; \
689 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
690 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
691 f_shift_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 3); \
692 f_uimm5 = EXTRACT_MSB0_UINT (insn, 16, 11, 5); \
693
694#define EXTRACT_IFMT_ST_D_VARS \
695 UINT f_op1; \
696 UINT f_r1; \
697 UINT f_op2; \
698 UINT f_r2; \
699 INT f_simm16; \
700 unsigned int length;
701#define EXTRACT_IFMT_ST_D_CODE \
702 length = 4; \
703 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
704 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
705 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
706 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
707 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
708
709#define EXTRACT_IFMT_TRAP_VARS \
710 UINT f_op1; \
711 UINT f_r1; \
712 UINT f_op2; \
713 UINT f_uimm4; \
714 unsigned int length;
715#define EXTRACT_IFMT_TRAP_CODE \
716 length = 2; \
717 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
718 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
719 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
720 f_uimm4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
721
722#define EXTRACT_IFMT_SATB_VARS \
723 UINT f_op1; \
724 UINT f_r1; \
725 UINT f_op2; \
726 UINT f_r2; \
727 UINT f_uimm16; \
728 unsigned int length;
729#define EXTRACT_IFMT_SATB_CODE \
730 length = 4; \
731 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
732 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
733 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
734 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
735 f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
736
16b47b25
NC		 737#define EXTRACT_IFMT_CLRPSW_VARS \
738 UINT f_op1; \
739 UINT f_r1; \
740 UINT f_uimm8; \
741 unsigned int length;
742#define EXTRACT_IFMT_CLRPSW_CODE \
743 length = 2; \
744 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
745 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
746 f_uimm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \
747
748#define EXTRACT_IFMT_BSET_VARS \
749 UINT f_op1; \
750 UINT f_bit4; \
751 UINT f_uimm3; \
752 UINT f_op2; \
753 UINT f_r2; \
754 INT f_simm16; \
755 unsigned int length;
756#define EXTRACT_IFMT_BSET_CODE \
757 length = 4; \
758 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
759 f_bit4 = EXTRACT_MSB0_UINT (insn, 32, 4, 1); \
760 f_uimm3 = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
761 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
762 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
763 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
764
765#define EXTRACT_IFMT_BTST_VARS \
766 UINT f_op1; \
767 UINT f_bit4; \
768 UINT f_uimm3; \
769 UINT f_op2; \
770 UINT f_r2; \
771 unsigned int length;
772#define EXTRACT_IFMT_BTST_CODE \
773 length = 2; \
774 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
775 f_bit4 = EXTRACT_MSB0_UINT (insn, 16, 4, 1); \
776 f_uimm3 = EXTRACT_MSB0_UINT (insn, 16, 5, 3); \
777 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
778 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
779
2df3850c
JM		 780/* Queued output values of an instruction. */
781
782struct parexec {
783 union {
784 struct { /* empty sformat for unspecified field list */
785 int empty;
786 } sfmt_empty;
787 struct { /* e.g. add $dr,$sr */
788 SI dr;
789 } sfmt_add;
790 struct { /* e.g. add3 $dr,$sr,$hash$slo16 */
791 SI dr;
792 } sfmt_add3;
793 struct { /* e.g. and3 $dr,$sr,$uimm16 */
794 SI dr;
795 } sfmt_and3;
796 struct { /* e.g. or3 $dr,$sr,$hash$ulo16 */
797 SI dr;
798 } sfmt_or3;
799 struct { /* e.g. addi $dr,$simm8 */
800 SI dr;
801 } sfmt_addi;
802 struct { /* e.g. addv $dr,$sr */
803 BI condbit;
804 SI dr;
805 } sfmt_addv;
806 struct { /* e.g. addv3 $dr,$sr,$simm16 */
807 BI condbit;
808 SI dr;
809 } sfmt_addv3;
810 struct { /* e.g. addx $dr,$sr */
811 BI condbit;
812 SI dr;
813 } sfmt_addx;
814 struct { /* e.g. bc.s $disp8 */
815 USI pc;
816 } sfmt_bc8;
817 struct { /* e.g. bc.l $disp24 */
818 USI pc;
819 } sfmt_bc24;
820 struct { /* e.g. beq $src1,$src2,$disp16 */
821 USI pc;
822 } sfmt_beq;
823 struct { /* e.g. beqz $src2,$disp16 */
824 USI pc;
825 } sfmt_beqz;
826 struct { /* e.g. bl.s $disp8 */
378af1d6 827 SI h_gr_SI_14;
2df3850c
JM		 828 USI pc;
829 } sfmt_bl8;
830 struct { /* e.g. bl.l $disp24 */
378af1d6 831 SI h_gr_SI_14;
2df3850c
JM		 832 USI pc;
833 } sfmt_bl24;
834 struct { /* e.g. bcl.s $disp8 */
378af1d6 835 SI h_gr_SI_14;
2df3850c
JM		 836 USI pc;
837 } sfmt_bcl8;
838 struct { /* e.g. bcl.l $disp24 */
378af1d6 839 SI h_gr_SI_14;
2df3850c
JM		 840 USI pc;
841 } sfmt_bcl24;
842 struct { /* e.g. bra.s $disp8 */
843 USI pc;
844 } sfmt_bra8;
845 struct { /* e.g. bra.l $disp24 */
846 USI pc;
847 } sfmt_bra24;
848 struct { /* e.g. cmp $src1,$src2 */
849 BI condbit;
850 } sfmt_cmp;
851 struct { /* e.g. cmpi $src2,$simm16 */
852 BI condbit;
853 } sfmt_cmpi;
854 struct { /* e.g. cmpz $src2 */
855 BI condbit;
856 } sfmt_cmpz;
857 struct { /* e.g. div $dr,$sr */
858 SI dr;
859 } sfmt_div;
860 struct { /* e.g. jc $sr */
861 USI pc;
862 } sfmt_jc;
863 struct { /* e.g. jl $sr */
378af1d6 864 SI h_gr_SI_14;
2df3850c
JM		 865 USI pc;
866 } sfmt_jl;
867 struct { /* e.g. jmp $sr */
868 USI pc;
869 } sfmt_jmp;
870 struct { /* e.g. ld $dr,@$sr */
871 SI dr;
872 } sfmt_ld;
873 struct { /* e.g. ld $dr,@($slo16,$sr) */
874 SI dr;
875 } sfmt_ld_d;
378af1d6
DB		 876 struct { /* e.g. ldb $dr,@$sr */
877 SI dr;
878 } sfmt_ldb;
879 struct { /* e.g. ldb $dr,@($slo16,$sr) */
880 SI dr;
881 } sfmt_ldb_d;
882 struct { /* e.g. ldh $dr,@$sr */
883 SI dr;
884 } sfmt_ldh;
885 struct { /* e.g. ldh $dr,@($slo16,$sr) */
886 SI dr;
887 } sfmt_ldh_d;
2df3850c
JM		 888 struct { /* e.g. ld $dr,@$sr+ */
889 SI dr;
890 SI sr;
891 } sfmt_ld_plus;
892 struct { /* e.g. ld24 $dr,$uimm24 */
893 SI dr;
894 } sfmt_ld24;
895 struct { /* e.g. ldi8 $dr,$simm8 */
896 SI dr;
897 } sfmt_ldi8;
898 struct { /* e.g. ldi16 $dr,$hash$slo16 */
899 SI dr;
900 } sfmt_ldi16;
901 struct { /* e.g. lock $dr,@$sr */
902 SI dr;
378af1d6 903 BI h_lock_BI;
2df3850c
JM		 904 } sfmt_lock;
905 struct { /* e.g. machi $src1,$src2,$acc */
906 DI acc;
907 } sfmt_machi_a;
908 struct { /* e.g. mulhi $src1,$src2,$acc */
909 DI acc;
910 } sfmt_mulhi_a;
911 struct { /* e.g. mv $dr,$sr */
912 SI dr;
913 } sfmt_mv;
914 struct { /* e.g. mvfachi $dr,$accs */
915 SI dr;
916 } sfmt_mvfachi_a;
917 struct { /* e.g. mvfc $dr,$scr */
918 SI dr;
919 } sfmt_mvfc;
920 struct { /* e.g. mvtachi $src1,$accs */
921 DI accs;
922 } sfmt_mvtachi_a;
923 struct { /* e.g. mvtc $sr,$dcr */
924 USI dcr;
925 } sfmt_mvtc;
926 struct { /* e.g. nop */
927 int empty;
928 } sfmt_nop;
929 struct { /* e.g. rac $accd,$accs,$imm1 */
930 DI accd;
931 } sfmt_rac_dsi;
932 struct { /* e.g. rte */
378af1d6
DB		 933 UQI h_bpsw_UQI;
934 USI h_cr_USI_6;
935 UQI h_psw_UQI;
2df3850c
JM		 936 USI pc;
937 } sfmt_rte;
938 struct { /* e.g. seth $dr,$hash$hi16 */
939 SI dr;
940 } sfmt_seth;
941 struct { /* e.g. sll3 $dr,$sr,$simm16 */
942 SI dr;
943 } sfmt_sll3;
944 struct { /* e.g. slli $dr,$uimm5 */
945 SI dr;
946 } sfmt_slli;
947 struct { /* e.g. st $src1,@$src2 */
378af1d6
DB		 948 SI h_memory_SI_src2;
949 USI h_memory_SI_src2_idx;
2df3850c
JM		 950 } sfmt_st;
951 struct { /* e.g. st $src1,@($slo16,$src2) */
378af1d6
DB		 952 SI h_memory_SI_add__DFLT_src2_slo16;
953 USI h_memory_SI_add__DFLT_src2_slo16_idx;
2df3850c
JM		 954 } sfmt_st_d;
955 struct { /* e.g. stb $src1,@$src2 */
378af1d6
DB		 956 QI h_memory_QI_src2;
957 USI h_memory_QI_src2_idx;
2df3850c
JM		 958 } sfmt_stb;
959 struct { /* e.g. stb $src1,@($slo16,$src2) */
378af1d6
DB		 960 QI h_memory_QI_add__DFLT_src2_slo16;
961 USI h_memory_QI_add__DFLT_src2_slo16_idx;
2df3850c
JM		 962 } sfmt_stb_d;
963 struct { /* e.g. sth $src1,@$src2 */
378af1d6
DB		 964 HI h_memory_HI_src2;
965 USI h_memory_HI_src2_idx;
2df3850c
JM		 966 } sfmt_sth;
967 struct { /* e.g. sth $src1,@($slo16,$src2) */
378af1d6
DB		 968 HI h_memory_HI_add__DFLT_src2_slo16;
969 USI h_memory_HI_add__DFLT_src2_slo16_idx;
2df3850c
JM		 970 } sfmt_sth_d;
971 struct { /* e.g. st $src1,@+$src2 */
378af1d6
DB		 972 SI h_memory_SI_new_src2;
973 USI h_memory_SI_new_src2_idx;
2df3850c
JM		 974 SI src2;
975 } sfmt_st_plus;
16b47b25
NC		 976 struct { /* e.g. sth $src1,@$src2+ */
977 HI h_memory_HI_new_src2;
978 USI h_memory_HI_new_src2_idx;
979 SI src2;
980 } sfmt_sth_plus;
981 struct { /* e.g. stb $src1,@$src2+ */
982 QI h_memory_QI_new_src2;
983 USI h_memory_QI_new_src2_idx;
984 SI src2;
985 } sfmt_stb_plus;
2df3850c 986 struct { /* e.g. trap $uimm4 */
378af1d6
DB		 987 UQI h_bbpsw_UQI;
988 UQI h_bpsw_UQI;
989 USI h_cr_USI_14;
990 USI h_cr_USI_6;
991 UQI h_psw_UQI;
2df3850c
JM		 992 SI pc;
993 } sfmt_trap;
994 struct { /* e.g. unlock $src1,@$src2 */
378af1d6
DB		 995 BI h_lock_BI;
996 SI h_memory_SI_src2;
997 USI h_memory_SI_src2_idx;
2df3850c
JM		 998 } sfmt_unlock;
999 struct { /* e.g. satb $dr,$sr */
1000 SI dr;
1001 } sfmt_satb;
1002 struct { /* e.g. sat $dr,$sr */
1003 SI dr;
1004 } sfmt_sat;
1005 struct { /* e.g. sadd */
378af1d6 1006 DI h_accums_DI_0;
2df3850c
JM		 1007 } sfmt_sadd;
1008 struct { /* e.g. macwu1 $src1,$src2 */
378af1d6 1009 DI h_accums_DI_1;
2df3850c
JM		 1010 } sfmt_macwu1;
1011 struct { /* e.g. msblo $src1,$src2 */
1012 DI accum;
1013 } sfmt_msblo;
1014 struct { /* e.g. mulwu1 $src1,$src2 */
378af1d6 1015 DI h_accums_DI_1;
2df3850c
JM		 1016 } sfmt_mulwu1;
1017 struct { /* e.g. sc */
1018 int empty;
1019 } sfmt_sc;
16b47b25
NC		 1020 struct { /* e.g. clrpsw $uimm8 */
1021 USI h_cr_USI_0;
1022 } sfmt_clrpsw;
1023 struct { /* e.g. setpsw $uimm8 */
1024 USI h_cr_USI_0;
1025 } sfmt_setpsw;
1026 struct { /* e.g. bset $uimm3,@($slo16,$sr) */
1027 QI h_memory_QI_add__DFLT_sr_slo16;
1028 USI h_memory_QI_add__DFLT_sr_slo16_idx;
1029 } sfmt_bset;
1030 struct { /* e.g. btst $uimm3,$sr */
1031 BI condbit;
1032 } sfmt_btst;
2df3850c
JM		 1033 } operands;
1034 /* For conditionally written operands, bitmask of which ones were. */
1035 int written;
1036};
1037
1038/* Collection of various things for the trace handler to use. */
1039
1040typedef struct trace_record {
1041 IADDR pc;
1042 /* FIXME:wip */
1043} TRACE_RECORD;
1044
1045#endif /* CPU_M32RXF_H */
GDB Binutils - Deliverables
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