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* arch.c: Regenerate.
[deliverable/binutils-gdb.git] / sim / m32r / cpux.h
CommitLineData
2df3850c
JM		 1/* CPU family header for m32rxf.
2
3THIS FILE IS MACHINE GENERATED WITH CGEN.
4
e9c60591 5Copyright 1996-2009 Free Software Foundation, Inc.
2df3850c 6
378af1d6 7This file is part of the GNU simulators.
2df3850c 8
e9c60591
DE		 9 This file is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
12 any later version.
2df3850c 13
e9c60591
DE		 14 It is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
2df3850c 18
e9c60591
DE		 19 You should have received a copy of the GNU General Public License along
20 with this program; if not, write to the Free Software Foundation, Inc.,
21 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
2df3850c
JM		 22
23*/
24
25#ifndef CPU_M32RXF_H
26#define CPU_M32RXF_H
27
28/* Maximum number of instructions that are fetched at a time.
29 This is for LIW type instructions sets (e.g. m32r). */
30#define MAX_LIW_INSNS 2
31
32/* Maximum number of instructions that can be executed in parallel. */
33#define MAX_PARALLEL_INSNS 2
34
35/* CPU state information. */
36typedef struct {
37 /* Hardware elements. */
38 struct {
39 /* program counter */
40 USI h_pc;
41#define GET_H_PC() CPU (h_pc)
42#define SET_H_PC(x) (CPU (h_pc) = (x))
43 /* general registers */
44 SI h_gr[16];
45#define GET_H_GR(a1) CPU (h_gr)[a1]
46#define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
47 /* control registers */
48 USI h_cr[16];
49#define GET_H_CR(index) m32rxf_h_cr_get_handler (current_cpu, index)
50#define SET_H_CR(index, x) \
51do { \
52m32rxf_h_cr_set_handler (current_cpu, (index), (x));\
de8f5985 53;} while (0)
2df3850c
JM		 54 /* accumulator */
55 DI h_accum;
56#define GET_H_ACCUM() m32rxf_h_accum_get_handler (current_cpu)
57#define SET_H_ACCUM(x) \
58do { \
59m32rxf_h_accum_set_handler (current_cpu, (x));\
de8f5985 60;} while (0)
2df3850c
JM		 61 /* accumulators */
62 DI h_accums[2];
63#define GET_H_ACCUMS(index) m32rxf_h_accums_get_handler (current_cpu, index)
64#define SET_H_ACCUMS(index, x) \
65do { \
66m32rxf_h_accums_set_handler (current_cpu, (index), (x));\
de8f5985 67;} while (0)
2df3850c
JM		 68 /* condition bit */
69 BI h_cond;
70#define GET_H_COND() CPU (h_cond)
71#define SET_H_COND(x) (CPU (h_cond) = (x))
72 /* psw part of psw */
73 UQI h_psw;
74#define GET_H_PSW() m32rxf_h_psw_get_handler (current_cpu)
75#define SET_H_PSW(x) \
76do { \
77m32rxf_h_psw_set_handler (current_cpu, (x));\
de8f5985 78;} while (0)
2df3850c
JM		 79 /* backup psw */
80 UQI h_bpsw;
81#define GET_H_BPSW() CPU (h_bpsw)
82#define SET_H_BPSW(x) (CPU (h_bpsw) = (x))
83 /* backup bpsw */
84 UQI h_bbpsw;
85#define GET_H_BBPSW() CPU (h_bbpsw)
86#define SET_H_BBPSW(x) (CPU (h_bbpsw) = (x))
87 /* lock */
88 BI h_lock;
89#define GET_H_LOCK() CPU (h_lock)
90#define SET_H_LOCK(x) (CPU (h_lock) = (x))
91 } hardware;
92#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
93} M32RXF_CPU_DATA;
94
95/* Cover fns for register access. */
96USI m32rxf_h_pc_get (SIM_CPU *);
97void m32rxf_h_pc_set (SIM_CPU *, USI);
98SI m32rxf_h_gr_get (SIM_CPU *, UINT);
99void m32rxf_h_gr_set (SIM_CPU *, UINT, SI);
100USI m32rxf_h_cr_get (SIM_CPU *, UINT);
101void m32rxf_h_cr_set (SIM_CPU *, UINT, USI);
102DI m32rxf_h_accum_get (SIM_CPU *);
103void m32rxf_h_accum_set (SIM_CPU *, DI);
104DI m32rxf_h_accums_get (SIM_CPU *, UINT);
105void m32rxf_h_accums_set (SIM_CPU *, UINT, DI);
106BI m32rxf_h_cond_get (SIM_CPU *);
107void m32rxf_h_cond_set (SIM_CPU *, BI);
108UQI m32rxf_h_psw_get (SIM_CPU *);
109void m32rxf_h_psw_set (SIM_CPU *, UQI);
110UQI m32rxf_h_bpsw_get (SIM_CPU *);
111void m32rxf_h_bpsw_set (SIM_CPU *, UQI);
112UQI m32rxf_h_bbpsw_get (SIM_CPU *);
113void m32rxf_h_bbpsw_set (SIM_CPU *, UQI);
114BI m32rxf_h_lock_get (SIM_CPU *);
115void m32rxf_h_lock_set (SIM_CPU *, BI);
116
117/* These must be hand-written. */
118extern CPUREG_FETCH_FN m32rxf_fetch_register;
119extern CPUREG_STORE_FN m32rxf_store_register;
120
121typedef struct {
122 int empty;
123} MODEL_M32RX_DATA;
124
125/* Instruction argument buffer. */
126
127union sem_fields {
128 struct { /* no operands */
129 int empty;
130 } fmt_empty;
16b47b25
NC		 131 struct { /* */
132 UINT f_uimm8;
133 } sfmt_clrpsw;
2df3850c
JM		 134 struct { /* */
135 UINT f_uimm4;
136 } sfmt_trap;
137 struct { /* */
138 IADDR i_disp24;
378af1d6 139 unsigned char out_h_gr_SI_14;
2df3850c
JM		 140 } sfmt_bl24;
141 struct { /* */
142 IADDR i_disp8;
378af1d6 143 unsigned char out_h_gr_SI_14;
2df3850c 144 } sfmt_bl8;
2df3850c
JM		 145 struct { /* */
146 SI f_imm1;
147 UINT f_accd;
148 UINT f_accs;
149 } sfmt_rac_dsi;
150 struct { /* */
de8f5985
DB		 151 SI* i_dr;
152 UINT f_hi16;
2df3850c 153 UINT f_r1;
de8f5985
DB		 154 unsigned char out_dr;
155 } sfmt_seth;
2df3850c
JM		 156 struct { /* */
157 SI* i_src1;
158 UINT f_accs;
de8f5985 159 UINT f_r1;
2df3850c
JM		 160 unsigned char in_src1;
161 } sfmt_mvtachi_a;
2df3850c
JM		 162 struct { /* */
163 SI* i_dr;
164 UINT f_accs;
de8f5985 165 UINT f_r1;
2df3850c
JM		 166 unsigned char out_dr;
167 } sfmt_mvfachi_a;
168 struct { /* */
169 ADDR i_uimm24;
170 SI* i_dr;
de8f5985 171 UINT f_r1;
2df3850c
JM		 172 unsigned char out_dr;
173 } sfmt_ld24;
174 struct { /* */
175 SI* i_sr;
de8f5985 176 UINT f_r2;
2df3850c 177 unsigned char in_sr;
378af1d6 178 unsigned char out_h_gr_SI_14;
2df3850c 179 } sfmt_jl;
16b47b25
NC		 180 struct { /* */
181 SI* i_sr;
182 INT f_simm16;
183 UINT f_r2;
184 UINT f_uimm3;
185 unsigned char in_sr;
186 } sfmt_bset;
2df3850c
JM		 187 struct { /* */
188 SI* i_dr;
de8f5985 189 UINT f_r1;
2df3850c
JM		 190 UINT f_uimm5;
191 unsigned char in_dr;
192 unsigned char out_dr;
193 } sfmt_slli;
194 struct { /* */
195 SI* i_dr;
196 INT f_simm8;
de8f5985 197 UINT f_r1;
2df3850c
JM		 198 unsigned char in_dr;
199 unsigned char out_dr;
200 } sfmt_addi;
201 struct { /* */
202 SI* i_src1;
203 SI* i_src2;
de8f5985
DB		 204 UINT f_r1;
205 UINT f_r2;
2df3850c
JM		 206 unsigned char in_src1;
207 unsigned char in_src2;
208 unsigned char out_src2;
209 } sfmt_st_plus;
210 struct { /* */
211 SI* i_src1;
212 SI* i_src2;
213 INT f_simm16;
de8f5985
DB		 214 UINT f_r1;
215 UINT f_r2;
2df3850c
JM		 216 unsigned char in_src1;
217 unsigned char in_src2;
218 } sfmt_st_d;
219 struct { /* */
220 SI* i_src1;
221 SI* i_src2;
222 UINT f_acc;
de8f5985
DB		 223 UINT f_r1;
224 UINT f_r2;
2df3850c
JM		 225 unsigned char in_src1;
226 unsigned char in_src2;
227 } sfmt_machi_a;
228 struct { /* */
229 SI* i_dr;
230 SI* i_sr;
de8f5985
DB		 231 UINT f_r1;
232 UINT f_r2;
2df3850c
JM		 233 unsigned char in_sr;
234 unsigned char out_dr;
235 unsigned char out_sr;
236 } sfmt_ld_plus;
237 struct { /* */
238 IADDR i_disp16;
239 SI* i_src1;
240 SI* i_src2;
de8f5985
DB		 241 UINT f_r1;
242 UINT f_r2;
2df3850c
JM		 243 unsigned char in_src1;
244 unsigned char in_src2;
245 } sfmt_beq;
246 struct { /* */
247 SI* i_dr;
248 SI* i_sr;
de8f5985
DB		 249 UINT f_r1;
250 UINT f_r2;
2df3850c
JM		 251 UINT f_uimm16;
252 unsigned char in_sr;
253 unsigned char out_dr;
254 } sfmt_and3;
255 struct { /* */
256 SI* i_dr;
257 SI* i_sr;
258 INT f_simm16;
de8f5985
DB		 259 UINT f_r1;
260 UINT f_r2;
2df3850c
JM		 261 unsigned char in_sr;
262 unsigned char out_dr;
263 } sfmt_add3;
264 struct { /* */
265 SI* i_dr;
266 SI* i_sr;
de8f5985
DB		 267 UINT f_r1;
268 UINT f_r2;
2df3850c
JM		 269 unsigned char in_dr;
270 unsigned char in_sr;
271 unsigned char out_dr;
272 } sfmt_add;
273#if WITH_SCACHE_PBB
274 /* Writeback handler. */
275 struct {
276 /* Pointer to argbuf entry for insn whose results need writing back. */
277 const struct argbuf *abuf;
278 } write;
279 /* x-before handler */
280 struct {
281 /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
282 int first_p;
283 } before;
284 /* x-after handler */
285 struct {
286 int empty;
287 } after;
288 /* This entry is used to terminate each pbb. */
289 struct {
290 /* Number of insns in pbb. */
291 int insn_count;
292 /* Next pbb to execute. */
293 SCACHE *next;
294 SCACHE *branch_target;
295 } chain;
296#endif
297};
298
299/* The ARGBUF struct. */
300struct argbuf {
301 /* These are the baseclass definitions. */
302 IADDR addr;
303 const IDESC *idesc;
304 char trace_p;
305 char profile_p;
306 /* ??? Temporary hack for skip insns. */
307 char skip_count;
308 char unused;
309 /* cpu specific data follows */
310 union sem semantic;
311 int written;
312 union sem_fields fields;
313};
314
315/* A cached insn.
316
317 ??? SCACHE used to contain more than just argbuf. We could delete the
318 type entirely and always just use ARGBUF, but for future concerns and as
319 a level of abstraction it is left in. */
320
321struct scache {
322 struct argbuf argbuf;
323};
324
325/* Macros to simplify extraction, reading and semantic code.
326 These define and assign the local vars that contain the insn's fields. */
327
328#define EXTRACT_IFMT_EMPTY_VARS \
329 unsigned int length;
330#define EXTRACT_IFMT_EMPTY_CODE \
331 length = 0; \
332
333#define EXTRACT_IFMT_ADD_VARS \
334 UINT f_op1; \
335 UINT f_r1; \
336 UINT f_op2; \
337 UINT f_r2; \
338 unsigned int length;
339#define EXTRACT_IFMT_ADD_CODE \
340 length = 2; \
341 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
342 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
343 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
344 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
345
346#define EXTRACT_IFMT_ADD3_VARS \
347 UINT f_op1; \
348 UINT f_r1; \
349 UINT f_op2; \
350 UINT f_r2; \
351 INT f_simm16; \
352 unsigned int length;
353#define EXTRACT_IFMT_ADD3_CODE \
354 length = 4; \
355 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
356 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
357 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
358 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
359 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
360
361#define EXTRACT_IFMT_AND3_VARS \
362 UINT f_op1; \
363 UINT f_r1; \
364 UINT f_op2; \
365 UINT f_r2; \
366 UINT f_uimm16; \
367 unsigned int length;
368#define EXTRACT_IFMT_AND3_CODE \
369 length = 4; \
370 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
371 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
372 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
373 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
374 f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
375
376#define EXTRACT_IFMT_OR3_VARS \
377 UINT f_op1; \
378 UINT f_r1; \
379 UINT f_op2; \
380 UINT f_r2; \
381 UINT f_uimm16; \
382 unsigned int length;
383#define EXTRACT_IFMT_OR3_CODE \
384 length = 4; \
385 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
386 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
387 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
388 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
389 f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
390
391#define EXTRACT_IFMT_ADDI_VARS \
392 UINT f_op1; \
393 UINT f_r1; \
394 INT f_simm8; \
395 unsigned int length;
396#define EXTRACT_IFMT_ADDI_CODE \
397 length = 2; \
398 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
399 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
400 f_simm8 = EXTRACT_MSB0_INT (insn, 16, 8, 8); \
401
402#define EXTRACT_IFMT_ADDV3_VARS \
403 UINT f_op1; \
404 UINT f_r1; \
405 UINT f_op2; \
406 UINT f_r2; \
407 INT f_simm16; \
408 unsigned int length;
409#define EXTRACT_IFMT_ADDV3_CODE \
410 length = 4; \
411 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
412 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
413 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
414 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
415 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
416
417#define EXTRACT_IFMT_BC8_VARS \
418 UINT f_op1; \
419 UINT f_r1; \
420 SI f_disp8; \
421 unsigned int length;
422#define EXTRACT_IFMT_BC8_CODE \
423 length = 2; \
424 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
425 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
426 f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
427
428#define EXTRACT_IFMT_BC24_VARS \
429 UINT f_op1; \
430 UINT f_r1; \
431 SI f_disp24; \
432 unsigned int length;
433#define EXTRACT_IFMT_BC24_CODE \
434 length = 4; \
435 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
436 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
437 f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc)); \
438
439#define EXTRACT_IFMT_BEQ_VARS \
440 UINT f_op1; \
441 UINT f_r1; \
442 UINT f_op2; \
443 UINT f_r2; \
444 SI f_disp16; \
445 unsigned int length;
446#define EXTRACT_IFMT_BEQ_CODE \
447 length = 4; \
448 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
449 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
450 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
451 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
452 f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
453
454#define EXTRACT_IFMT_BEQZ_VARS \
455 UINT f_op1; \
456 UINT f_r1; \
457 UINT f_op2; \
458 UINT f_r2; \
459 SI f_disp16; \
460 unsigned int length;
461#define EXTRACT_IFMT_BEQZ_CODE \
462 length = 4; \
463 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
464 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
465 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
466 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
467 f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
468
469#define EXTRACT_IFMT_CMP_VARS \
470 UINT f_op1; \
471 UINT f_r1; \
472 UINT f_op2; \
473 UINT f_r2; \
474 unsigned int length;
475#define EXTRACT_IFMT_CMP_CODE \
476 length = 2; \
477 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
478 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
479 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
480 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
481
482#define EXTRACT_IFMT_CMPI_VARS \
483 UINT f_op1; \
484 UINT f_r1; \
485 UINT f_op2; \
486 UINT f_r2; \
487 INT f_simm16; \
488 unsigned int length;
489#define EXTRACT_IFMT_CMPI_CODE \
490 length = 4; \
491 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
492 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
493 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
494 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
495 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
496
497#define EXTRACT_IFMT_CMPZ_VARS \
498 UINT f_op1; \
499 UINT f_r1; \
500 UINT f_op2; \
501 UINT f_r2; \
502 unsigned int length;
503#define EXTRACT_IFMT_CMPZ_CODE \
504 length = 2; \
505 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
506 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
507 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
508 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
509
510#define EXTRACT_IFMT_DIV_VARS \
511 UINT f_op1; \
512 UINT f_r1; \
513 UINT f_op2; \
514 UINT f_r2; \
515 INT f_simm16; \
516 unsigned int length;
517#define EXTRACT_IFMT_DIV_CODE \
518 length = 4; \
519 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
520 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
521 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
522 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
523 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
524
525#define EXTRACT_IFMT_JC_VARS \
526 UINT f_op1; \
527 UINT f_r1; \
528 UINT f_op2; \
529 UINT f_r2; \
530 unsigned int length;
531#define EXTRACT_IFMT_JC_CODE \
532 length = 2; \
533 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
534 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
535 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
536 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
537
538#define EXTRACT_IFMT_LD24_VARS \
539 UINT f_op1; \
540 UINT f_r1; \
541 UINT f_uimm24; \
542 unsigned int length;
543#define EXTRACT_IFMT_LD24_CODE \
544 length = 4; \
545 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
546 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
547 f_uimm24 = EXTRACT_MSB0_UINT (insn, 32, 8, 24); \
548
549#define EXTRACT_IFMT_LDI16_VARS \
550 UINT f_op1; \
551 UINT f_r1; \
552 UINT f_op2; \
553 UINT f_r2; \
554 INT f_simm16; \
555 unsigned int length;
556#define EXTRACT_IFMT_LDI16_CODE \
557 length = 4; \
558 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
559 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
560 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
561 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
562 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
563
564#define EXTRACT_IFMT_MACHI_A_VARS \
565 UINT f_op1; \
566 UINT f_r1; \
567 UINT f_acc; \
568 UINT f_op23; \
569 UINT f_r2; \
570 unsigned int length;
571#define EXTRACT_IFMT_MACHI_A_CODE \
572 length = 2; \
573 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
574 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
575 f_acc = EXTRACT_MSB0_UINT (insn, 16, 8, 1); \
576 f_op23 = EXTRACT_MSB0_UINT (insn, 16, 9, 3); \
577 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
578
579#define EXTRACT_IFMT_MVFACHI_A_VARS \
580 UINT f_op1; \
581 UINT f_r1; \
582 UINT f_op2; \
583 UINT f_accs; \
584 UINT f_op3; \
585 unsigned int length;
586#define EXTRACT_IFMT_MVFACHI_A_CODE \
587 length = 2; \
588 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
589 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
590 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
591 f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); \
592 f_op3 = EXTRACT_MSB0_UINT (insn, 16, 14, 2); \
593
594#define EXTRACT_IFMT_MVFC_VARS \
595 UINT f_op1; \
596 UINT f_r1; \
597 UINT f_op2; \
598 UINT f_r2; \
599 unsigned int length;
600#define EXTRACT_IFMT_MVFC_CODE \
601 length = 2; \
602 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
603 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
604 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
605 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
606
607#define EXTRACT_IFMT_MVTACHI_A_VARS \
608 UINT f_op1; \
609 UINT f_r1; \
610 UINT f_op2; \
611 UINT f_accs; \
612 UINT f_op3; \
613 unsigned int length;
614#define EXTRACT_IFMT_MVTACHI_A_CODE \
615 length = 2; \
616 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
617 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
618 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
619 f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); \
620 f_op3 = EXTRACT_MSB0_UINT (insn, 16, 14, 2); \
621
622#define EXTRACT_IFMT_MVTC_VARS \
623 UINT f_op1; \
624 UINT f_r1; \
625 UINT f_op2; \
626 UINT f_r2; \
627 unsigned int length;
628#define EXTRACT_IFMT_MVTC_CODE \
629 length = 2; \
630 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
631 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
632 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
633 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
634
635#define EXTRACT_IFMT_NOP_VARS \
636 UINT f_op1; \
637 UINT f_r1; \
638 UINT f_op2; \
639 UINT f_r2; \
640 unsigned int length;
641#define EXTRACT_IFMT_NOP_CODE \
642 length = 2; \
643 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
644 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
645 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
646 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
647
648#define EXTRACT_IFMT_RAC_DSI_VARS \
649 UINT f_op1; \
650 UINT f_accd; \
651 UINT f_bits67; \
652 UINT f_op2; \
653 UINT f_accs; \
654 UINT f_bit14; \
655 SI f_imm1; \
656 unsigned int length;
657#define EXTRACT_IFMT_RAC_DSI_CODE \
658 length = 2; \
659 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
660 f_accd = EXTRACT_MSB0_UINT (insn, 16, 4, 2); \
661 f_bits67 = EXTRACT_MSB0_UINT (insn, 16, 6, 2); \
662 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
663 f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); \
664 f_bit14 = EXTRACT_MSB0_UINT (insn, 16, 14, 1); \
665 f_imm1 = ((EXTRACT_MSB0_UINT (insn, 16, 15, 1)) + (1)); \
666
667#define EXTRACT_IFMT_SETH_VARS \
668 UINT f_op1; \
669 UINT f_r1; \
670 UINT f_op2; \
671 UINT f_r2; \
672 UINT f_hi16; \
673 unsigned int length;
674#define EXTRACT_IFMT_SETH_CODE \
675 length = 4; \
676 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
677 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
678 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
679 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
680 f_hi16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
681
682#define EXTRACT_IFMT_SLLI_VARS \
683 UINT f_op1; \
684 UINT f_r1; \
685 UINT f_shift_op2; \
686 UINT f_uimm5; \
687 unsigned int length;
688#define EXTRACT_IFMT_SLLI_CODE \
689 length = 2; \
690 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
691 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
692 f_shift_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 3); \
693 f_uimm5 = EXTRACT_MSB0_UINT (insn, 16, 11, 5); \
694
695#define EXTRACT_IFMT_ST_D_VARS \
696 UINT f_op1; \
697 UINT f_r1; \
698 UINT f_op2; \
699 UINT f_r2; \
700 INT f_simm16; \
701 unsigned int length;
702#define EXTRACT_IFMT_ST_D_CODE \
703 length = 4; \
704 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
705 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
706 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
707 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
708 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
709
710#define EXTRACT_IFMT_TRAP_VARS \
711 UINT f_op1; \
712 UINT f_r1; \
713 UINT f_op2; \
714 UINT f_uimm4; \
715 unsigned int length;
716#define EXTRACT_IFMT_TRAP_CODE \
717 length = 2; \
718 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
719 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
720 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
721 f_uimm4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
722
723#define EXTRACT_IFMT_SATB_VARS \
724 UINT f_op1; \
725 UINT f_r1; \
726 UINT f_op2; \
727 UINT f_r2; \
728 UINT f_uimm16; \
729 unsigned int length;
730#define EXTRACT_IFMT_SATB_CODE \
731 length = 4; \
732 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
733 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
734 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
735 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
736 f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
737
16b47b25
NC		 738#define EXTRACT_IFMT_CLRPSW_VARS \
739 UINT f_op1; \
740 UINT f_r1; \
741 UINT f_uimm8; \
742 unsigned int length;
743#define EXTRACT_IFMT_CLRPSW_CODE \
744 length = 2; \
745 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
746 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
747 f_uimm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \
748
749#define EXTRACT_IFMT_BSET_VARS \
750 UINT f_op1; \
751 UINT f_bit4; \
752 UINT f_uimm3; \
753 UINT f_op2; \
754 UINT f_r2; \
755 INT f_simm16; \
756 unsigned int length;
757#define EXTRACT_IFMT_BSET_CODE \
758 length = 4; \
759 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
760 f_bit4 = EXTRACT_MSB0_UINT (insn, 32, 4, 1); \
761 f_uimm3 = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
762 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
763 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
764 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
765
766#define EXTRACT_IFMT_BTST_VARS \
767 UINT f_op1; \
768 UINT f_bit4; \
769 UINT f_uimm3; \
770 UINT f_op2; \
771 UINT f_r2; \
772 unsigned int length;
773#define EXTRACT_IFMT_BTST_CODE \
774 length = 2; \
775 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
776 f_bit4 = EXTRACT_MSB0_UINT (insn, 16, 4, 1); \
777 f_uimm3 = EXTRACT_MSB0_UINT (insn, 16, 5, 3); \
778 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
779 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
780
2df3850c
JM		 781/* Queued output values of an instruction. */
782
783struct parexec {
784 union {
785 struct { /* empty sformat for unspecified field list */
786 int empty;
787 } sfmt_empty;
788 struct { /* e.g. add $dr,$sr */
789 SI dr;
790 } sfmt_add;
791 struct { /* e.g. add3 $dr,$sr,$hash$slo16 */
792 SI dr;
793 } sfmt_add3;
794 struct { /* e.g. and3 $dr,$sr,$uimm16 */
795 SI dr;
796 } sfmt_and3;
797 struct { /* e.g. or3 $dr,$sr,$hash$ulo16 */
798 SI dr;
799 } sfmt_or3;
800 struct { /* e.g. addi $dr,$simm8 */
801 SI dr;
802 } sfmt_addi;
803 struct { /* e.g. addv $dr,$sr */
804 BI condbit;
805 SI dr;
806 } sfmt_addv;
807 struct { /* e.g. addv3 $dr,$sr,$simm16 */
808 BI condbit;
809 SI dr;
810 } sfmt_addv3;
811 struct { /* e.g. addx $dr,$sr */
812 BI condbit;
813 SI dr;
814 } sfmt_addx;
815 struct { /* e.g. bc.s $disp8 */
816 USI pc;
817 } sfmt_bc8;
818 struct { /* e.g. bc.l $disp24 */
819 USI pc;
820 } sfmt_bc24;
821 struct { /* e.g. beq $src1,$src2,$disp16 */
822 USI pc;
823 } sfmt_beq;
824 struct { /* e.g. beqz $src2,$disp16 */
825 USI pc;
826 } sfmt_beqz;
827 struct { /* e.g. bl.s $disp8 */
378af1d6 828 SI h_gr_SI_14;
2df3850c
JM		 829 USI pc;
830 } sfmt_bl8;
831 struct { /* e.g. bl.l $disp24 */
378af1d6 832 SI h_gr_SI_14;
2df3850c
JM		 833 USI pc;
834 } sfmt_bl24;
835 struct { /* e.g. bcl.s $disp8 */
378af1d6 836 SI h_gr_SI_14;
2df3850c
JM		 837 USI pc;
838 } sfmt_bcl8;
839 struct { /* e.g. bcl.l $disp24 */
378af1d6 840 SI h_gr_SI_14;
2df3850c
JM		 841 USI pc;
842 } sfmt_bcl24;
843 struct { /* e.g. bra.s $disp8 */
844 USI pc;
845 } sfmt_bra8;
846 struct { /* e.g. bra.l $disp24 */
847 USI pc;
848 } sfmt_bra24;
849 struct { /* e.g. cmp $src1,$src2 */
850 BI condbit;
851 } sfmt_cmp;
852 struct { /* e.g. cmpi $src2,$simm16 */
853 BI condbit;
854 } sfmt_cmpi;
855 struct { /* e.g. cmpz $src2 */
856 BI condbit;
857 } sfmt_cmpz;
858 struct { /* e.g. div $dr,$sr */
859 SI dr;
860 } sfmt_div;
861 struct { /* e.g. jc $sr */
862 USI pc;
863 } sfmt_jc;
864 struct { /* e.g. jl $sr */
378af1d6 865 SI h_gr_SI_14;
2df3850c
JM		 866 USI pc;
867 } sfmt_jl;
868 struct { /* e.g. jmp $sr */
869 USI pc;
870 } sfmt_jmp;
871 struct { /* e.g. ld $dr,@$sr */
872 SI dr;
873 } sfmt_ld;
874 struct { /* e.g. ld $dr,@($slo16,$sr) */
875 SI dr;
876 } sfmt_ld_d;
378af1d6
DB		 877 struct { /* e.g. ldb $dr,@$sr */
878 SI dr;
879 } sfmt_ldb;
880 struct { /* e.g. ldb $dr,@($slo16,$sr) */
881 SI dr;
882 } sfmt_ldb_d;
883 struct { /* e.g. ldh $dr,@$sr */
884 SI dr;
885 } sfmt_ldh;
886 struct { /* e.g. ldh $dr,@($slo16,$sr) */
887 SI dr;
888 } sfmt_ldh_d;
2df3850c
JM		 889 struct { /* e.g. ld $dr,@$sr+ */
890 SI dr;
891 SI sr;
892 } sfmt_ld_plus;
893 struct { /* e.g. ld24 $dr,$uimm24 */
894 SI dr;
895 } sfmt_ld24;
896 struct { /* e.g. ldi8 $dr,$simm8 */
897 SI dr;
898 } sfmt_ldi8;
899 struct { /* e.g. ldi16 $dr,$hash$slo16 */
900 SI dr;
901 } sfmt_ldi16;
902 struct { /* e.g. lock $dr,@$sr */
903 SI dr;
378af1d6 904 BI h_lock_BI;
2df3850c
JM		 905 } sfmt_lock;
906 struct { /* e.g. machi $src1,$src2,$acc */
907 DI acc;
908 } sfmt_machi_a;
909 struct { /* e.g. mulhi $src1,$src2,$acc */
910 DI acc;
911 } sfmt_mulhi_a;
912 struct { /* e.g. mv $dr,$sr */
913 SI dr;
914 } sfmt_mv;
915 struct { /* e.g. mvfachi $dr,$accs */
916 SI dr;
917 } sfmt_mvfachi_a;
918 struct { /* e.g. mvfc $dr,$scr */
919 SI dr;
920 } sfmt_mvfc;
921 struct { /* e.g. mvtachi $src1,$accs */
922 DI accs;
923 } sfmt_mvtachi_a;
924 struct { /* e.g. mvtc $sr,$dcr */
925 USI dcr;
926 } sfmt_mvtc;
927 struct { /* e.g. nop */
928 int empty;
929 } sfmt_nop;
930 struct { /* e.g. rac $accd,$accs,$imm1 */
931 DI accd;
932 } sfmt_rac_dsi;
933 struct { /* e.g. rte */
378af1d6
DB		 934 UQI h_bpsw_UQI;
935 USI h_cr_USI_6;
936 UQI h_psw_UQI;
2df3850c
JM		 937 USI pc;
938 } sfmt_rte;
939 struct { /* e.g. seth $dr,$hash$hi16 */
940 SI dr;
941 } sfmt_seth;
942 struct { /* e.g. sll3 $dr,$sr,$simm16 */
943 SI dr;
944 } sfmt_sll3;
945 struct { /* e.g. slli $dr,$uimm5 */
946 SI dr;
947 } sfmt_slli;
948 struct { /* e.g. st $src1,@$src2 */
378af1d6
DB		 949 SI h_memory_SI_src2;
950 USI h_memory_SI_src2_idx;
2df3850c
JM		 951 } sfmt_st;
952 struct { /* e.g. st $src1,@($slo16,$src2) */
e9c60591
DE		 953 SI h_memory_SI_add__SI_src2_slo16;
954 USI h_memory_SI_add__SI_src2_slo16_idx;
2df3850c
JM		 955 } sfmt_st_d;
956 struct { /* e.g. stb $src1,@$src2 */
378af1d6
DB		 957 QI h_memory_QI_src2;
958 USI h_memory_QI_src2_idx;
2df3850c
JM		 959 } sfmt_stb;
960 struct { /* e.g. stb $src1,@($slo16,$src2) */
e9c60591
DE		 961 QI h_memory_QI_add__SI_src2_slo16;
962 USI h_memory_QI_add__SI_src2_slo16_idx;
2df3850c
JM		 963 } sfmt_stb_d;
964 struct { /* e.g. sth $src1,@$src2 */
378af1d6
DB		 965 HI h_memory_HI_src2;
966 USI h_memory_HI_src2_idx;
2df3850c
JM		 967 } sfmt_sth;
968 struct { /* e.g. sth $src1,@($slo16,$src2) */
e9c60591
DE		 969 HI h_memory_HI_add__SI_src2_slo16;
970 USI h_memory_HI_add__SI_src2_slo16_idx;
2df3850c
JM		 971 } sfmt_sth_d;
972 struct { /* e.g. st $src1,@+$src2 */
378af1d6
DB		 973 SI h_memory_SI_new_src2;
974 USI h_memory_SI_new_src2_idx;
2df3850c
JM		 975 SI src2;
976 } sfmt_st_plus;
16b47b25
NC		 977 struct { /* e.g. sth $src1,@$src2+ */
978 HI h_memory_HI_new_src2;
979 USI h_memory_HI_new_src2_idx;
980 SI src2;
981 } sfmt_sth_plus;
982 struct { /* e.g. stb $src1,@$src2+ */
983 QI h_memory_QI_new_src2;
984 USI h_memory_QI_new_src2_idx;
985 SI src2;
986 } sfmt_stb_plus;
2df3850c 987 struct { /* e.g. trap $uimm4 */
378af1d6
DB		 988 UQI h_bbpsw_UQI;
989 UQI h_bpsw_UQI;
990 USI h_cr_USI_14;
991 USI h_cr_USI_6;
992 UQI h_psw_UQI;
e9c60591 993 USI pc;
2df3850c
JM		 994 } sfmt_trap;
995 struct { /* e.g. unlock $src1,@$src2 */
378af1d6
DB		 996 BI h_lock_BI;
997 SI h_memory_SI_src2;
998 USI h_memory_SI_src2_idx;
2df3850c
JM		 999 } sfmt_unlock;
1000 struct { /* e.g. satb $dr,$sr */
1001 SI dr;
1002 } sfmt_satb;
1003 struct { /* e.g. sat $dr,$sr */
1004 SI dr;
1005 } sfmt_sat;
1006 struct { /* e.g. sadd */
378af1d6 1007 DI h_accums_DI_0;
2df3850c
JM		 1008 } sfmt_sadd;
1009 struct { /* e.g. macwu1 $src1,$src2 */
378af1d6 1010 DI h_accums_DI_1;
2df3850c
JM		 1011 } sfmt_macwu1;
1012 struct { /* e.g. msblo $src1,$src2 */
1013 DI accum;
1014 } sfmt_msblo;
1015 struct { /* e.g. mulwu1 $src1,$src2 */
378af1d6 1016 DI h_accums_DI_1;
2df3850c
JM		 1017 } sfmt_mulwu1;
1018 struct { /* e.g. sc */
1019 int empty;
1020 } sfmt_sc;
16b47b25
NC		 1021 struct { /* e.g. clrpsw $uimm8 */
1022 USI h_cr_USI_0;
1023 } sfmt_clrpsw;
1024 struct { /* e.g. setpsw $uimm8 */
1025 USI h_cr_USI_0;
1026 } sfmt_setpsw;
1027 struct { /* e.g. bset $uimm3,@($slo16,$sr) */
e9c60591
DE		 1028 QI h_memory_QI_add__SI_sr_slo16;
1029 USI h_memory_QI_add__SI_sr_slo16_idx;
16b47b25
NC		 1030 } sfmt_bset;
1031 struct { /* e.g. btst $uimm3,$sr */
1032 BI condbit;
1033 } sfmt_btst;
2df3850c
JM		 1034 } operands;
1035 /* For conditionally written operands, bitmask of which ones were. */
1036 int written;
1037};
1038
1039/* Collection of various things for the trace handler to use. */
1040
1041typedef struct trace_record {
1042 IADDR pc;
1043 /* FIXME:wip */
1044} TRACE_RECORD;
1045
1046#endif /* CPU_M32RXF_H */
GDB Binutils - Deliverables
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