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16b47b25 NC |
1 | /* Simulator instruction decoder for m32r2f. |
2 | ||
3 | THIS FILE IS MACHINE GENERATED WITH CGEN. | |
4 | ||
0f51e9bf | 5 | Copyright 1996-2010 Free Software Foundation, Inc. |
16b47b25 NC |
6 | |
7 | This file is part of the GNU simulators. | |
8 | ||
e9c60591 DE |
9 | This file is free software; you can redistribute it and/or modify |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 3, or (at your option) | |
12 | any later version. | |
16b47b25 | 13 | |
e9c60591 DE |
14 | It is distributed in the hope that it will be useful, but WITHOUT |
15 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
16 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
17 | License for more details. | |
16b47b25 | 18 | |
e9c60591 DE |
19 | You should have received a copy of the GNU General Public License along |
20 | with this program; if not, write to the Free Software Foundation, Inc., | |
21 | 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. | |
16b47b25 NC |
22 | |
23 | */ | |
24 | ||
25 | #define WANT_CPU m32r2f | |
26 | #define WANT_CPU_M32R2F | |
27 | ||
28 | #include "sim-main.h" | |
29 | #include "sim-assert.h" | |
30 | ||
31 | /* Insn can't be executed in parallel. | |
32 | Or is that "do NOt Pass to Air defense Radar"? :-) */ | |
33 | #define NOPAR (-1) | |
34 | ||
35 | /* The instruction descriptor array. | |
36 | This is computed at runtime. Space for it is not malloc'd to save a | |
37 | teensy bit of cpu in the decoder. Moving it to malloc space is trivial | |
38 | but won't be done until necessary (we don't currently support the runtime | |
39 | addition of instructions nor an SMP machine with different cpus). */ | |
40 | static IDESC m32r2f_insn_data[M32R2F_INSN__MAX]; | |
41 | ||
42 | /* Commas between elements are contained in the macros. | |
43 | Some of these are conditionally compiled out. */ | |
44 | ||
45 | static const struct insn_sem m32r2f_insn_sem[] = | |
46 | { | |
47 | { VIRTUAL_INSN_X_INVALID, M32R2F_INSN_X_INVALID, M32R2F_SFMT_EMPTY, NOPAR, NOPAR }, | |
48 | { VIRTUAL_INSN_X_AFTER, M32R2F_INSN_X_AFTER, M32R2F_SFMT_EMPTY, NOPAR, NOPAR }, | |
49 | { VIRTUAL_INSN_X_BEFORE, M32R2F_INSN_X_BEFORE, M32R2F_SFMT_EMPTY, NOPAR, NOPAR }, | |
50 | { VIRTUAL_INSN_X_CTI_CHAIN, M32R2F_INSN_X_CTI_CHAIN, M32R2F_SFMT_EMPTY, NOPAR, NOPAR }, | |
51 | { VIRTUAL_INSN_X_CHAIN, M32R2F_INSN_X_CHAIN, M32R2F_SFMT_EMPTY, NOPAR, NOPAR }, | |
52 | { VIRTUAL_INSN_X_BEGIN, M32R2F_INSN_X_BEGIN, M32R2F_SFMT_EMPTY, NOPAR, NOPAR }, | |
53 | { M32R_INSN_ADD, M32R2F_INSN_ADD, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_ADD, M32R2F_INSN_WRITE_ADD }, | |
54 | { M32R_INSN_ADD3, M32R2F_INSN_ADD3, M32R2F_SFMT_ADD3, NOPAR, NOPAR }, | |
55 | { M32R_INSN_AND, M32R2F_INSN_AND, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_AND, M32R2F_INSN_WRITE_AND }, | |
56 | { M32R_INSN_AND3, M32R2F_INSN_AND3, M32R2F_SFMT_AND3, NOPAR, NOPAR }, | |
57 | { M32R_INSN_OR, M32R2F_INSN_OR, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_OR, M32R2F_INSN_WRITE_OR }, | |
58 | { M32R_INSN_OR3, M32R2F_INSN_OR3, M32R2F_SFMT_OR3, NOPAR, NOPAR }, | |
59 | { M32R_INSN_XOR, M32R2F_INSN_XOR, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_XOR, M32R2F_INSN_WRITE_XOR }, | |
60 | { M32R_INSN_XOR3, M32R2F_INSN_XOR3, M32R2F_SFMT_AND3, NOPAR, NOPAR }, | |
61 | { M32R_INSN_ADDI, M32R2F_INSN_ADDI, M32R2F_SFMT_ADDI, M32R2F_INSN_PAR_ADDI, M32R2F_INSN_WRITE_ADDI }, | |
62 | { M32R_INSN_ADDV, M32R2F_INSN_ADDV, M32R2F_SFMT_ADDV, M32R2F_INSN_PAR_ADDV, M32R2F_INSN_WRITE_ADDV }, | |
63 | { M32R_INSN_ADDV3, M32R2F_INSN_ADDV3, M32R2F_SFMT_ADDV3, NOPAR, NOPAR }, | |
64 | { M32R_INSN_ADDX, M32R2F_INSN_ADDX, M32R2F_SFMT_ADDX, M32R2F_INSN_PAR_ADDX, M32R2F_INSN_WRITE_ADDX }, | |
65 | { M32R_INSN_BC8, M32R2F_INSN_BC8, M32R2F_SFMT_BC8, M32R2F_INSN_PAR_BC8, M32R2F_INSN_WRITE_BC8 }, | |
66 | { M32R_INSN_BC24, M32R2F_INSN_BC24, M32R2F_SFMT_BC24, NOPAR, NOPAR }, | |
67 | { M32R_INSN_BEQ, M32R2F_INSN_BEQ, M32R2F_SFMT_BEQ, NOPAR, NOPAR }, | |
68 | { M32R_INSN_BEQZ, M32R2F_INSN_BEQZ, M32R2F_SFMT_BEQZ, NOPAR, NOPAR }, | |
69 | { M32R_INSN_BGEZ, M32R2F_INSN_BGEZ, M32R2F_SFMT_BEQZ, NOPAR, NOPAR }, | |
70 | { M32R_INSN_BGTZ, M32R2F_INSN_BGTZ, M32R2F_SFMT_BEQZ, NOPAR, NOPAR }, | |
71 | { M32R_INSN_BLEZ, M32R2F_INSN_BLEZ, M32R2F_SFMT_BEQZ, NOPAR, NOPAR }, | |
72 | { M32R_INSN_BLTZ, M32R2F_INSN_BLTZ, M32R2F_SFMT_BEQZ, NOPAR, NOPAR }, | |
73 | { M32R_INSN_BNEZ, M32R2F_INSN_BNEZ, M32R2F_SFMT_BEQZ, NOPAR, NOPAR }, | |
74 | { M32R_INSN_BL8, M32R2F_INSN_BL8, M32R2F_SFMT_BL8, M32R2F_INSN_PAR_BL8, M32R2F_INSN_WRITE_BL8 }, | |
75 | { M32R_INSN_BL24, M32R2F_INSN_BL24, M32R2F_SFMT_BL24, NOPAR, NOPAR }, | |
76 | { M32R_INSN_BCL8, M32R2F_INSN_BCL8, M32R2F_SFMT_BCL8, M32R2F_INSN_PAR_BCL8, M32R2F_INSN_WRITE_BCL8 }, | |
77 | { M32R_INSN_BCL24, M32R2F_INSN_BCL24, M32R2F_SFMT_BCL24, NOPAR, NOPAR }, | |
78 | { M32R_INSN_BNC8, M32R2F_INSN_BNC8, M32R2F_SFMT_BC8, M32R2F_INSN_PAR_BNC8, M32R2F_INSN_WRITE_BNC8 }, | |
79 | { M32R_INSN_BNC24, M32R2F_INSN_BNC24, M32R2F_SFMT_BC24, NOPAR, NOPAR }, | |
80 | { M32R_INSN_BNE, M32R2F_INSN_BNE, M32R2F_SFMT_BEQ, NOPAR, NOPAR }, | |
81 | { M32R_INSN_BRA8, M32R2F_INSN_BRA8, M32R2F_SFMT_BRA8, M32R2F_INSN_PAR_BRA8, M32R2F_INSN_WRITE_BRA8 }, | |
82 | { M32R_INSN_BRA24, M32R2F_INSN_BRA24, M32R2F_SFMT_BRA24, NOPAR, NOPAR }, | |
83 | { M32R_INSN_BNCL8, M32R2F_INSN_BNCL8, M32R2F_SFMT_BCL8, M32R2F_INSN_PAR_BNCL8, M32R2F_INSN_WRITE_BNCL8 }, | |
84 | { M32R_INSN_BNCL24, M32R2F_INSN_BNCL24, M32R2F_SFMT_BCL24, NOPAR, NOPAR }, | |
85 | { M32R_INSN_CMP, M32R2F_INSN_CMP, M32R2F_SFMT_CMP, M32R2F_INSN_PAR_CMP, M32R2F_INSN_WRITE_CMP }, | |
86 | { M32R_INSN_CMPI, M32R2F_INSN_CMPI, M32R2F_SFMT_CMPI, NOPAR, NOPAR }, | |
87 | { M32R_INSN_CMPU, M32R2F_INSN_CMPU, M32R2F_SFMT_CMP, M32R2F_INSN_PAR_CMPU, M32R2F_INSN_WRITE_CMPU }, | |
88 | { M32R_INSN_CMPUI, M32R2F_INSN_CMPUI, M32R2F_SFMT_CMPI, NOPAR, NOPAR }, | |
89 | { M32R_INSN_CMPEQ, M32R2F_INSN_CMPEQ, M32R2F_SFMT_CMP, M32R2F_INSN_PAR_CMPEQ, M32R2F_INSN_WRITE_CMPEQ }, | |
90 | { M32R_INSN_CMPZ, M32R2F_INSN_CMPZ, M32R2F_SFMT_CMPZ, M32R2F_INSN_PAR_CMPZ, M32R2F_INSN_WRITE_CMPZ }, | |
91 | { M32R_INSN_DIV, M32R2F_INSN_DIV, M32R2F_SFMT_DIV, NOPAR, NOPAR }, | |
92 | { M32R_INSN_DIVU, M32R2F_INSN_DIVU, M32R2F_SFMT_DIV, NOPAR, NOPAR }, | |
93 | { M32R_INSN_REM, M32R2F_INSN_REM, M32R2F_SFMT_DIV, NOPAR, NOPAR }, | |
94 | { M32R_INSN_REMU, M32R2F_INSN_REMU, M32R2F_SFMT_DIV, NOPAR, NOPAR }, | |
95 | { M32R_INSN_REMH, M32R2F_INSN_REMH, M32R2F_SFMT_DIV, NOPAR, NOPAR }, | |
96 | { M32R_INSN_REMUH, M32R2F_INSN_REMUH, M32R2F_SFMT_DIV, NOPAR, NOPAR }, | |
97 | { M32R_INSN_REMB, M32R2F_INSN_REMB, M32R2F_SFMT_DIV, NOPAR, NOPAR }, | |
98 | { M32R_INSN_REMUB, M32R2F_INSN_REMUB, M32R2F_SFMT_DIV, NOPAR, NOPAR }, | |
99 | { M32R_INSN_DIVUH, M32R2F_INSN_DIVUH, M32R2F_SFMT_DIV, NOPAR, NOPAR }, | |
100 | { M32R_INSN_DIVB, M32R2F_INSN_DIVB, M32R2F_SFMT_DIV, NOPAR, NOPAR }, | |
101 | { M32R_INSN_DIVUB, M32R2F_INSN_DIVUB, M32R2F_SFMT_DIV, NOPAR, NOPAR }, | |
102 | { M32R_INSN_DIVH, M32R2F_INSN_DIVH, M32R2F_SFMT_DIV, NOPAR, NOPAR }, | |
103 | { M32R_INSN_JC, M32R2F_INSN_JC, M32R2F_SFMT_JC, M32R2F_INSN_PAR_JC, M32R2F_INSN_WRITE_JC }, | |
104 | { M32R_INSN_JNC, M32R2F_INSN_JNC, M32R2F_SFMT_JC, M32R2F_INSN_PAR_JNC, M32R2F_INSN_WRITE_JNC }, | |
105 | { M32R_INSN_JL, M32R2F_INSN_JL, M32R2F_SFMT_JL, M32R2F_INSN_PAR_JL, M32R2F_INSN_WRITE_JL }, | |
106 | { M32R_INSN_JMP, M32R2F_INSN_JMP, M32R2F_SFMT_JMP, M32R2F_INSN_PAR_JMP, M32R2F_INSN_WRITE_JMP }, | |
107 | { M32R_INSN_LD, M32R2F_INSN_LD, M32R2F_SFMT_LD, M32R2F_INSN_PAR_LD, M32R2F_INSN_WRITE_LD }, | |
108 | { M32R_INSN_LD_D, M32R2F_INSN_LD_D, M32R2F_SFMT_LD_D, NOPAR, NOPAR }, | |
109 | { M32R_INSN_LDB, M32R2F_INSN_LDB, M32R2F_SFMT_LDB, M32R2F_INSN_PAR_LDB, M32R2F_INSN_WRITE_LDB }, | |
110 | { M32R_INSN_LDB_D, M32R2F_INSN_LDB_D, M32R2F_SFMT_LDB_D, NOPAR, NOPAR }, | |
111 | { M32R_INSN_LDH, M32R2F_INSN_LDH, M32R2F_SFMT_LDH, M32R2F_INSN_PAR_LDH, M32R2F_INSN_WRITE_LDH }, | |
112 | { M32R_INSN_LDH_D, M32R2F_INSN_LDH_D, M32R2F_SFMT_LDH_D, NOPAR, NOPAR }, | |
113 | { M32R_INSN_LDUB, M32R2F_INSN_LDUB, M32R2F_SFMT_LDB, M32R2F_INSN_PAR_LDUB, M32R2F_INSN_WRITE_LDUB }, | |
114 | { M32R_INSN_LDUB_D, M32R2F_INSN_LDUB_D, M32R2F_SFMT_LDB_D, NOPAR, NOPAR }, | |
115 | { M32R_INSN_LDUH, M32R2F_INSN_LDUH, M32R2F_SFMT_LDH, M32R2F_INSN_PAR_LDUH, M32R2F_INSN_WRITE_LDUH }, | |
116 | { M32R_INSN_LDUH_D, M32R2F_INSN_LDUH_D, M32R2F_SFMT_LDH_D, NOPAR, NOPAR }, | |
117 | { M32R_INSN_LD_PLUS, M32R2F_INSN_LD_PLUS, M32R2F_SFMT_LD_PLUS, M32R2F_INSN_PAR_LD_PLUS, M32R2F_INSN_WRITE_LD_PLUS }, | |
118 | { M32R_INSN_LD24, M32R2F_INSN_LD24, M32R2F_SFMT_LD24, NOPAR, NOPAR }, | |
119 | { M32R_INSN_LDI8, M32R2F_INSN_LDI8, M32R2F_SFMT_LDI8, M32R2F_INSN_PAR_LDI8, M32R2F_INSN_WRITE_LDI8 }, | |
120 | { M32R_INSN_LDI16, M32R2F_INSN_LDI16, M32R2F_SFMT_LDI16, NOPAR, NOPAR }, | |
121 | { M32R_INSN_LOCK, M32R2F_INSN_LOCK, M32R2F_SFMT_LOCK, M32R2F_INSN_PAR_LOCK, M32R2F_INSN_WRITE_LOCK }, | |
122 | { M32R_INSN_MACHI_A, M32R2F_INSN_MACHI_A, M32R2F_SFMT_MACHI_A, M32R2F_INSN_PAR_MACHI_A, M32R2F_INSN_WRITE_MACHI_A }, | |
123 | { M32R_INSN_MACLO_A, M32R2F_INSN_MACLO_A, M32R2F_SFMT_MACHI_A, M32R2F_INSN_PAR_MACLO_A, M32R2F_INSN_WRITE_MACLO_A }, | |
124 | { M32R_INSN_MACWHI_A, M32R2F_INSN_MACWHI_A, M32R2F_SFMT_MACHI_A, M32R2F_INSN_PAR_MACWHI_A, M32R2F_INSN_WRITE_MACWHI_A }, | |
125 | { M32R_INSN_MACWLO_A, M32R2F_INSN_MACWLO_A, M32R2F_SFMT_MACHI_A, M32R2F_INSN_PAR_MACWLO_A, M32R2F_INSN_WRITE_MACWLO_A }, | |
126 | { M32R_INSN_MUL, M32R2F_INSN_MUL, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_MUL, M32R2F_INSN_WRITE_MUL }, | |
127 | { M32R_INSN_MULHI_A, M32R2F_INSN_MULHI_A, M32R2F_SFMT_MULHI_A, M32R2F_INSN_PAR_MULHI_A, M32R2F_INSN_WRITE_MULHI_A }, | |
128 | { M32R_INSN_MULLO_A, M32R2F_INSN_MULLO_A, M32R2F_SFMT_MULHI_A, M32R2F_INSN_PAR_MULLO_A, M32R2F_INSN_WRITE_MULLO_A }, | |
129 | { M32R_INSN_MULWHI_A, M32R2F_INSN_MULWHI_A, M32R2F_SFMT_MULHI_A, M32R2F_INSN_PAR_MULWHI_A, M32R2F_INSN_WRITE_MULWHI_A }, | |
130 | { M32R_INSN_MULWLO_A, M32R2F_INSN_MULWLO_A, M32R2F_SFMT_MULHI_A, M32R2F_INSN_PAR_MULWLO_A, M32R2F_INSN_WRITE_MULWLO_A }, | |
131 | { M32R_INSN_MV, M32R2F_INSN_MV, M32R2F_SFMT_MV, M32R2F_INSN_PAR_MV, M32R2F_INSN_WRITE_MV }, | |
132 | { M32R_INSN_MVFACHI_A, M32R2F_INSN_MVFACHI_A, M32R2F_SFMT_MVFACHI_A, M32R2F_INSN_PAR_MVFACHI_A, M32R2F_INSN_WRITE_MVFACHI_A }, | |
133 | { M32R_INSN_MVFACLO_A, M32R2F_INSN_MVFACLO_A, M32R2F_SFMT_MVFACHI_A, M32R2F_INSN_PAR_MVFACLO_A, M32R2F_INSN_WRITE_MVFACLO_A }, | |
134 | { M32R_INSN_MVFACMI_A, M32R2F_INSN_MVFACMI_A, M32R2F_SFMT_MVFACHI_A, M32R2F_INSN_PAR_MVFACMI_A, M32R2F_INSN_WRITE_MVFACMI_A }, | |
135 | { M32R_INSN_MVFC, M32R2F_INSN_MVFC, M32R2F_SFMT_MVFC, M32R2F_INSN_PAR_MVFC, M32R2F_INSN_WRITE_MVFC }, | |
136 | { M32R_INSN_MVTACHI_A, M32R2F_INSN_MVTACHI_A, M32R2F_SFMT_MVTACHI_A, M32R2F_INSN_PAR_MVTACHI_A, M32R2F_INSN_WRITE_MVTACHI_A }, | |
137 | { M32R_INSN_MVTACLO_A, M32R2F_INSN_MVTACLO_A, M32R2F_SFMT_MVTACHI_A, M32R2F_INSN_PAR_MVTACLO_A, M32R2F_INSN_WRITE_MVTACLO_A }, | |
138 | { M32R_INSN_MVTC, M32R2F_INSN_MVTC, M32R2F_SFMT_MVTC, M32R2F_INSN_PAR_MVTC, M32R2F_INSN_WRITE_MVTC }, | |
139 | { M32R_INSN_NEG, M32R2F_INSN_NEG, M32R2F_SFMT_MV, M32R2F_INSN_PAR_NEG, M32R2F_INSN_WRITE_NEG }, | |
140 | { M32R_INSN_NOP, M32R2F_INSN_NOP, M32R2F_SFMT_NOP, M32R2F_INSN_PAR_NOP, M32R2F_INSN_WRITE_NOP }, | |
141 | { M32R_INSN_NOT, M32R2F_INSN_NOT, M32R2F_SFMT_MV, M32R2F_INSN_PAR_NOT, M32R2F_INSN_WRITE_NOT }, | |
142 | { M32R_INSN_RAC_DSI, M32R2F_INSN_RAC_DSI, M32R2F_SFMT_RAC_DSI, M32R2F_INSN_PAR_RAC_DSI, M32R2F_INSN_WRITE_RAC_DSI }, | |
143 | { M32R_INSN_RACH_DSI, M32R2F_INSN_RACH_DSI, M32R2F_SFMT_RAC_DSI, M32R2F_INSN_PAR_RACH_DSI, M32R2F_INSN_WRITE_RACH_DSI }, | |
144 | { M32R_INSN_RTE, M32R2F_INSN_RTE, M32R2F_SFMT_RTE, M32R2F_INSN_PAR_RTE, M32R2F_INSN_WRITE_RTE }, | |
145 | { M32R_INSN_SETH, M32R2F_INSN_SETH, M32R2F_SFMT_SETH, NOPAR, NOPAR }, | |
146 | { M32R_INSN_SLL, M32R2F_INSN_SLL, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_SLL, M32R2F_INSN_WRITE_SLL }, | |
147 | { M32R_INSN_SLL3, M32R2F_INSN_SLL3, M32R2F_SFMT_SLL3, NOPAR, NOPAR }, | |
148 | { M32R_INSN_SLLI, M32R2F_INSN_SLLI, M32R2F_SFMT_SLLI, M32R2F_INSN_PAR_SLLI, M32R2F_INSN_WRITE_SLLI }, | |
149 | { M32R_INSN_SRA, M32R2F_INSN_SRA, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_SRA, M32R2F_INSN_WRITE_SRA }, | |
150 | { M32R_INSN_SRA3, M32R2F_INSN_SRA3, M32R2F_SFMT_SLL3, NOPAR, NOPAR }, | |
151 | { M32R_INSN_SRAI, M32R2F_INSN_SRAI, M32R2F_SFMT_SLLI, M32R2F_INSN_PAR_SRAI, M32R2F_INSN_WRITE_SRAI }, | |
152 | { M32R_INSN_SRL, M32R2F_INSN_SRL, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_SRL, M32R2F_INSN_WRITE_SRL }, | |
153 | { M32R_INSN_SRL3, M32R2F_INSN_SRL3, M32R2F_SFMT_SLL3, NOPAR, NOPAR }, | |
154 | { M32R_INSN_SRLI, M32R2F_INSN_SRLI, M32R2F_SFMT_SLLI, M32R2F_INSN_PAR_SRLI, M32R2F_INSN_WRITE_SRLI }, | |
155 | { M32R_INSN_ST, M32R2F_INSN_ST, M32R2F_SFMT_ST, M32R2F_INSN_PAR_ST, M32R2F_INSN_WRITE_ST }, | |
156 | { M32R_INSN_ST_D, M32R2F_INSN_ST_D, M32R2F_SFMT_ST_D, NOPAR, NOPAR }, | |
157 | { M32R_INSN_STB, M32R2F_INSN_STB, M32R2F_SFMT_STB, M32R2F_INSN_PAR_STB, M32R2F_INSN_WRITE_STB }, | |
158 | { M32R_INSN_STB_D, M32R2F_INSN_STB_D, M32R2F_SFMT_STB_D, NOPAR, NOPAR }, | |
159 | { M32R_INSN_STH, M32R2F_INSN_STH, M32R2F_SFMT_STH, M32R2F_INSN_PAR_STH, M32R2F_INSN_WRITE_STH }, | |
160 | { M32R_INSN_STH_D, M32R2F_INSN_STH_D, M32R2F_SFMT_STH_D, NOPAR, NOPAR }, | |
161 | { M32R_INSN_ST_PLUS, M32R2F_INSN_ST_PLUS, M32R2F_SFMT_ST_PLUS, M32R2F_INSN_PAR_ST_PLUS, M32R2F_INSN_WRITE_ST_PLUS }, | |
162 | { M32R_INSN_STH_PLUS, M32R2F_INSN_STH_PLUS, M32R2F_SFMT_STH_PLUS, M32R2F_INSN_PAR_STH_PLUS, M32R2F_INSN_WRITE_STH_PLUS }, | |
163 | { M32R_INSN_STB_PLUS, M32R2F_INSN_STB_PLUS, M32R2F_SFMT_STB_PLUS, M32R2F_INSN_PAR_STB_PLUS, M32R2F_INSN_WRITE_STB_PLUS }, | |
164 | { M32R_INSN_ST_MINUS, M32R2F_INSN_ST_MINUS, M32R2F_SFMT_ST_PLUS, M32R2F_INSN_PAR_ST_MINUS, M32R2F_INSN_WRITE_ST_MINUS }, | |
165 | { M32R_INSN_SUB, M32R2F_INSN_SUB, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_SUB, M32R2F_INSN_WRITE_SUB }, | |
166 | { M32R_INSN_SUBV, M32R2F_INSN_SUBV, M32R2F_SFMT_ADDV, M32R2F_INSN_PAR_SUBV, M32R2F_INSN_WRITE_SUBV }, | |
167 | { M32R_INSN_SUBX, M32R2F_INSN_SUBX, M32R2F_SFMT_ADDX, M32R2F_INSN_PAR_SUBX, M32R2F_INSN_WRITE_SUBX }, | |
168 | { M32R_INSN_TRAP, M32R2F_INSN_TRAP, M32R2F_SFMT_TRAP, M32R2F_INSN_PAR_TRAP, M32R2F_INSN_WRITE_TRAP }, | |
169 | { M32R_INSN_UNLOCK, M32R2F_INSN_UNLOCK, M32R2F_SFMT_UNLOCK, M32R2F_INSN_PAR_UNLOCK, M32R2F_INSN_WRITE_UNLOCK }, | |
170 | { M32R_INSN_SATB, M32R2F_INSN_SATB, M32R2F_SFMT_SATB, NOPAR, NOPAR }, | |
171 | { M32R_INSN_SATH, M32R2F_INSN_SATH, M32R2F_SFMT_SATB, NOPAR, NOPAR }, | |
172 | { M32R_INSN_SAT, M32R2F_INSN_SAT, M32R2F_SFMT_SAT, NOPAR, NOPAR }, | |
173 | { M32R_INSN_PCMPBZ, M32R2F_INSN_PCMPBZ, M32R2F_SFMT_CMPZ, M32R2F_INSN_PAR_PCMPBZ, M32R2F_INSN_WRITE_PCMPBZ }, | |
174 | { M32R_INSN_SADD, M32R2F_INSN_SADD, M32R2F_SFMT_SADD, M32R2F_INSN_PAR_SADD, M32R2F_INSN_WRITE_SADD }, | |
175 | { M32R_INSN_MACWU1, M32R2F_INSN_MACWU1, M32R2F_SFMT_MACWU1, M32R2F_INSN_PAR_MACWU1, M32R2F_INSN_WRITE_MACWU1 }, | |
176 | { M32R_INSN_MSBLO, M32R2F_INSN_MSBLO, M32R2F_SFMT_MSBLO, M32R2F_INSN_PAR_MSBLO, M32R2F_INSN_WRITE_MSBLO }, | |
177 | { M32R_INSN_MULWU1, M32R2F_INSN_MULWU1, M32R2F_SFMT_MULWU1, M32R2F_INSN_PAR_MULWU1, M32R2F_INSN_WRITE_MULWU1 }, | |
178 | { M32R_INSN_MACLH1, M32R2F_INSN_MACLH1, M32R2F_SFMT_MACWU1, M32R2F_INSN_PAR_MACLH1, M32R2F_INSN_WRITE_MACLH1 }, | |
179 | { M32R_INSN_SC, M32R2F_INSN_SC, M32R2F_SFMT_SC, M32R2F_INSN_PAR_SC, M32R2F_INSN_WRITE_SC }, | |
180 | { M32R_INSN_SNC, M32R2F_INSN_SNC, M32R2F_SFMT_SC, M32R2F_INSN_PAR_SNC, M32R2F_INSN_WRITE_SNC }, | |
181 | { M32R_INSN_CLRPSW, M32R2F_INSN_CLRPSW, M32R2F_SFMT_CLRPSW, M32R2F_INSN_PAR_CLRPSW, M32R2F_INSN_WRITE_CLRPSW }, | |
182 | { M32R_INSN_SETPSW, M32R2F_INSN_SETPSW, M32R2F_SFMT_SETPSW, M32R2F_INSN_PAR_SETPSW, M32R2F_INSN_WRITE_SETPSW }, | |
183 | { M32R_INSN_BSET, M32R2F_INSN_BSET, M32R2F_SFMT_BSET, NOPAR, NOPAR }, | |
184 | { M32R_INSN_BCLR, M32R2F_INSN_BCLR, M32R2F_SFMT_BSET, NOPAR, NOPAR }, | |
185 | { M32R_INSN_BTST, M32R2F_INSN_BTST, M32R2F_SFMT_BTST, M32R2F_INSN_PAR_BTST, M32R2F_INSN_WRITE_BTST }, | |
186 | }; | |
187 | ||
2310652a DE |
188 | static const struct insn_sem m32r2f_insn_sem_invalid = |
189 | { | |
16b47b25 NC |
190 | VIRTUAL_INSN_X_INVALID, M32R2F_INSN_X_INVALID, M32R2F_SFMT_EMPTY, NOPAR, NOPAR |
191 | }; | |
192 | ||
193 | /* Initialize an IDESC from the compile-time computable parts. */ | |
194 | ||
195 | static INLINE void | |
196 | init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t) | |
197 | { | |
198 | const CGEN_INSN *insn_table = CGEN_CPU_INSN_TABLE (CPU_CPU_DESC (cpu))->init_entries; | |
199 | ||
200 | id->num = t->index; | |
201 | id->sfmt = t->sfmt; | |
202 | if ((int) t->type <= 0) | |
203 | id->idata = & cgen_virtual_insn_table[- (int) t->type]; | |
204 | else | |
205 | id->idata = & insn_table[t->type]; | |
206 | id->attrs = CGEN_INSN_ATTRS (id->idata); | |
207 | /* Oh my god, a magic number. */ | |
208 | id->length = CGEN_INSN_BITSIZE (id->idata) / 8; | |
209 | ||
210 | #if WITH_PROFILE_MODEL_P | |
211 | id->timing = & MODEL_TIMING (CPU_MODEL (cpu)) [t->index]; | |
212 | { | |
213 | SIM_DESC sd = CPU_STATE (cpu); | |
214 | SIM_ASSERT (t->index == id->timing->num); | |
215 | } | |
216 | #endif | |
217 | ||
218 | /* Semantic pointers are initialized elsewhere. */ | |
219 | } | |
220 | ||
221 | /* Initialize the instruction descriptor table. */ | |
222 | ||
223 | void | |
224 | m32r2f_init_idesc_table (SIM_CPU *cpu) | |
225 | { | |
226 | IDESC *id,*tabend; | |
227 | const struct insn_sem *t,*tend; | |
228 | int tabsize = M32R2F_INSN__MAX; | |
229 | IDESC *table = m32r2f_insn_data; | |
230 | ||
231 | memset (table, 0, tabsize * sizeof (IDESC)); | |
232 | ||
233 | /* First set all entries to the `invalid insn'. */ | |
234 | t = & m32r2f_insn_sem_invalid; | |
235 | for (id = table, tabend = table + tabsize; id < tabend; ++id) | |
236 | init_idesc (cpu, id, t); | |
237 | ||
238 | /* Now fill in the values for the chosen cpu. */ | |
239 | for (t = m32r2f_insn_sem, tend = t + sizeof (m32r2f_insn_sem) / sizeof (*t); | |
240 | t != tend; ++t) | |
241 | { | |
242 | init_idesc (cpu, & table[t->index], t); | |
243 | if (t->par_index != NOPAR) | |
244 | { | |
245 | init_idesc (cpu, &table[t->par_index], t); | |
246 | table[t->index].par_idesc = &table[t->par_index]; | |
247 | } | |
248 | if (t->par_index != NOPAR) | |
249 | { | |
250 | init_idesc (cpu, &table[t->write_index], t); | |
251 | table[t->par_index].par_idesc = &table[t->write_index]; | |
252 | } | |
253 | } | |
254 | ||
255 | /* Link the IDESC table into the cpu. */ | |
256 | CPU_IDESC (cpu) = table; | |
257 | } | |
258 | ||
259 | /* Given an instruction, return a pointer to its IDESC entry. */ | |
260 | ||
261 | const IDESC * | |
262 | m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, | |
197fa1aa | 263 | CGEN_INSN_WORD base_insn, CGEN_INSN_WORD entire_insn, |
16b47b25 NC |
264 | ARGBUF *abuf) |
265 | { | |
266 | /* Result of decoder. */ | |
267 | M32R2F_INSN_TYPE itype; | |
268 | ||
269 | { | |
197fa1aa | 270 | CGEN_INSN_WORD insn = base_insn; |
16b47b25 NC |
271 | |
272 | { | |
273 | unsigned int val = (((insn >> 8) & (15 << 4)) | ((insn >> 4) & (15 << 0))); | |
274 | switch (val) | |
275 | { | |
276 | case 0 : itype = M32R2F_INSN_SUBV; goto extract_sfmt_addv; | |
277 | case 1 : itype = M32R2F_INSN_SUBX; goto extract_sfmt_addx; | |
278 | case 2 : itype = M32R2F_INSN_SUB; goto extract_sfmt_add; | |
279 | case 3 : itype = M32R2F_INSN_NEG; goto extract_sfmt_mv; | |
280 | case 4 : itype = M32R2F_INSN_CMP; goto extract_sfmt_cmp; | |
281 | case 5 : itype = M32R2F_INSN_CMPU; goto extract_sfmt_cmp; | |
282 | case 6 : itype = M32R2F_INSN_CMPEQ; goto extract_sfmt_cmp; | |
283 | case 7 : | |
284 | { | |
285 | unsigned int val = (((insn >> 8) & (3 << 0))); | |
286 | switch (val) | |
287 | { | |
e9c60591 DE |
288 | case 0 : |
289 | if ((entire_insn & 0xfff0) == 0x70) | |
290 | { itype = M32R2F_INSN_CMPZ; goto extract_sfmt_cmpz; } | |
291 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
292 | case 3 : | |
293 | if ((entire_insn & 0xfff0) == 0x370) | |
294 | { itype = M32R2F_INSN_PCMPBZ; goto extract_sfmt_cmpz; } | |
295 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
16b47b25 NC |
296 | default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; |
297 | } | |
298 | } | |
299 | case 8 : itype = M32R2F_INSN_ADDV; goto extract_sfmt_addv; | |
300 | case 9 : itype = M32R2F_INSN_ADDX; goto extract_sfmt_addx; | |
301 | case 10 : itype = M32R2F_INSN_ADD; goto extract_sfmt_add; | |
302 | case 11 : itype = M32R2F_INSN_NOT; goto extract_sfmt_mv; | |
303 | case 12 : itype = M32R2F_INSN_AND; goto extract_sfmt_add; | |
304 | case 13 : itype = M32R2F_INSN_XOR; goto extract_sfmt_add; | |
305 | case 14 : itype = M32R2F_INSN_OR; goto extract_sfmt_add; | |
e9c60591 DE |
306 | case 15 : |
307 | if ((entire_insn & 0xf8f0) == 0xf0) | |
308 | { itype = M32R2F_INSN_BTST; goto extract_sfmt_btst; } | |
309 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
16b47b25 NC |
310 | case 16 : itype = M32R2F_INSN_SRL; goto extract_sfmt_add; |
311 | case 18 : itype = M32R2F_INSN_SRA; goto extract_sfmt_add; | |
312 | case 20 : itype = M32R2F_INSN_SLL; goto extract_sfmt_add; | |
313 | case 22 : itype = M32R2F_INSN_MUL; goto extract_sfmt_add; | |
314 | case 24 : itype = M32R2F_INSN_MV; goto extract_sfmt_mv; | |
315 | case 25 : itype = M32R2F_INSN_MVFC; goto extract_sfmt_mvfc; | |
316 | case 26 : itype = M32R2F_INSN_MVTC; goto extract_sfmt_mvtc; | |
317 | case 28 : | |
318 | { | |
319 | unsigned int val = (((insn >> 8) & (3 << 0))); | |
320 | switch (val) | |
321 | { | |
e9c60591 DE |
322 | case 0 : |
323 | if ((entire_insn & 0xfff0) == 0x1cc0) | |
324 | { itype = M32R2F_INSN_JC; goto extract_sfmt_jc; } | |
325 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
326 | case 1 : | |
327 | if ((entire_insn & 0xfff0) == 0x1dc0) | |
328 | { itype = M32R2F_INSN_JNC; goto extract_sfmt_jc; } | |
329 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
330 | case 2 : | |
331 | if ((entire_insn & 0xfff0) == 0x1ec0) | |
332 | { itype = M32R2F_INSN_JL; goto extract_sfmt_jl; } | |
333 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
334 | case 3 : | |
335 | if ((entire_insn & 0xfff0) == 0x1fc0) | |
336 | { itype = M32R2F_INSN_JMP; goto extract_sfmt_jmp; } | |
337 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
16b47b25 NC |
338 | default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; |
339 | } | |
340 | } | |
e9c60591 DE |
341 | case 29 : |
342 | if ((entire_insn & 0xffff) == 0x10d6) | |
343 | { itype = M32R2F_INSN_RTE; goto extract_sfmt_rte; } | |
344 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
345 | case 31 : | |
346 | if ((entire_insn & 0xfff0) == 0x10f0) | |
347 | { itype = M32R2F_INSN_TRAP; goto extract_sfmt_trap; } | |
348 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
16b47b25 NC |
349 | case 32 : itype = M32R2F_INSN_STB; goto extract_sfmt_stb; |
350 | case 33 : itype = M32R2F_INSN_STB_PLUS; goto extract_sfmt_stb_plus; | |
351 | case 34 : itype = M32R2F_INSN_STH; goto extract_sfmt_sth; | |
352 | case 35 : itype = M32R2F_INSN_STH_PLUS; goto extract_sfmt_sth_plus; | |
353 | case 36 : itype = M32R2F_INSN_ST; goto extract_sfmt_st; | |
354 | case 37 : itype = M32R2F_INSN_UNLOCK; goto extract_sfmt_unlock; | |
355 | case 38 : itype = M32R2F_INSN_ST_PLUS; goto extract_sfmt_st_plus; | |
356 | case 39 : itype = M32R2F_INSN_ST_MINUS; goto extract_sfmt_st_plus; | |
357 | case 40 : itype = M32R2F_INSN_LDB; goto extract_sfmt_ldb; | |
358 | case 41 : itype = M32R2F_INSN_LDUB; goto extract_sfmt_ldb; | |
359 | case 42 : itype = M32R2F_INSN_LDH; goto extract_sfmt_ldh; | |
360 | case 43 : itype = M32R2F_INSN_LDUH; goto extract_sfmt_ldh; | |
361 | case 44 : itype = M32R2F_INSN_LD; goto extract_sfmt_ld; | |
362 | case 45 : itype = M32R2F_INSN_LOCK; goto extract_sfmt_lock; | |
363 | case 46 : itype = M32R2F_INSN_LD_PLUS; goto extract_sfmt_ld_plus; | |
364 | case 48 : /* fall through */ | |
365 | case 56 : itype = M32R2F_INSN_MULHI_A; goto extract_sfmt_mulhi_a; | |
366 | case 49 : /* fall through */ | |
367 | case 57 : itype = M32R2F_INSN_MULLO_A; goto extract_sfmt_mulhi_a; | |
368 | case 50 : /* fall through */ | |
369 | case 58 : itype = M32R2F_INSN_MULWHI_A; goto extract_sfmt_mulhi_a; | |
370 | case 51 : /* fall through */ | |
371 | case 59 : itype = M32R2F_INSN_MULWLO_A; goto extract_sfmt_mulhi_a; | |
372 | case 52 : /* fall through */ | |
373 | case 60 : itype = M32R2F_INSN_MACHI_A; goto extract_sfmt_machi_a; | |
374 | case 53 : /* fall through */ | |
375 | case 61 : itype = M32R2F_INSN_MACLO_A; goto extract_sfmt_machi_a; | |
376 | case 54 : /* fall through */ | |
377 | case 62 : itype = M32R2F_INSN_MACWHI_A; goto extract_sfmt_machi_a; | |
378 | case 55 : /* fall through */ | |
379 | case 63 : itype = M32R2F_INSN_MACWLO_A; goto extract_sfmt_machi_a; | |
380 | case 64 : /* fall through */ | |
381 | case 65 : /* fall through */ | |
382 | case 66 : /* fall through */ | |
383 | case 67 : /* fall through */ | |
384 | case 68 : /* fall through */ | |
385 | case 69 : /* fall through */ | |
386 | case 70 : /* fall through */ | |
387 | case 71 : /* fall through */ | |
388 | case 72 : /* fall through */ | |
389 | case 73 : /* fall through */ | |
390 | case 74 : /* fall through */ | |
391 | case 75 : /* fall through */ | |
392 | case 76 : /* fall through */ | |
393 | case 77 : /* fall through */ | |
394 | case 78 : /* fall through */ | |
395 | case 79 : itype = M32R2F_INSN_ADDI; goto extract_sfmt_addi; | |
396 | case 80 : /* fall through */ | |
397 | case 81 : itype = M32R2F_INSN_SRLI; goto extract_sfmt_slli; | |
398 | case 82 : /* fall through */ | |
399 | case 83 : itype = M32R2F_INSN_SRAI; goto extract_sfmt_slli; | |
400 | case 84 : /* fall through */ | |
401 | case 85 : itype = M32R2F_INSN_SLLI; goto extract_sfmt_slli; | |
402 | case 87 : | |
403 | { | |
404 | unsigned int val = (((insn >> 0) & (1 << 0))); | |
405 | switch (val) | |
406 | { | |
e9c60591 DE |
407 | case 0 : |
408 | if ((entire_insn & 0xf0f3) == 0x5070) | |
409 | { itype = M32R2F_INSN_MVTACHI_A; goto extract_sfmt_mvtachi_a; } | |
410 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
411 | case 1 : | |
412 | if ((entire_insn & 0xf0f3) == 0x5071) | |
413 | { itype = M32R2F_INSN_MVTACLO_A; goto extract_sfmt_mvtachi_a; } | |
414 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
16b47b25 NC |
415 | default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; |
416 | } | |
417 | } | |
e9c60591 DE |
418 | case 88 : |
419 | if ((entire_insn & 0xf3f2) == 0x5080) | |
420 | { itype = M32R2F_INSN_RACH_DSI; goto extract_sfmt_rac_dsi; } | |
421 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
422 | case 89 : | |
423 | if ((entire_insn & 0xf3f2) == 0x5090) | |
424 | { itype = M32R2F_INSN_RAC_DSI; goto extract_sfmt_rac_dsi; } | |
425 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
16b47b25 NC |
426 | case 90 : itype = M32R2F_INSN_MULWU1; goto extract_sfmt_mulwu1; |
427 | case 91 : itype = M32R2F_INSN_MACWU1; goto extract_sfmt_macwu1; | |
428 | case 92 : itype = M32R2F_INSN_MACLH1; goto extract_sfmt_macwu1; | |
429 | case 93 : itype = M32R2F_INSN_MSBLO; goto extract_sfmt_msblo; | |
e9c60591 DE |
430 | case 94 : |
431 | if ((entire_insn & 0xffff) == 0x50e4) | |
432 | { itype = M32R2F_INSN_SADD; goto extract_sfmt_sadd; } | |
433 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
16b47b25 NC |
434 | case 95 : |
435 | { | |
436 | unsigned int val = (((insn >> 0) & (3 << 0))); | |
437 | switch (val) | |
438 | { | |
439 | case 0 : itype = M32R2F_INSN_MVFACHI_A; goto extract_sfmt_mvfachi_a; | |
440 | case 1 : itype = M32R2F_INSN_MVFACLO_A; goto extract_sfmt_mvfachi_a; | |
441 | case 2 : itype = M32R2F_INSN_MVFACMI_A; goto extract_sfmt_mvfachi_a; | |
442 | default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
443 | } | |
444 | } | |
445 | case 96 : /* fall through */ | |
446 | case 97 : /* fall through */ | |
447 | case 98 : /* fall through */ | |
448 | case 99 : /* fall through */ | |
449 | case 100 : /* fall through */ | |
450 | case 101 : /* fall through */ | |
451 | case 102 : /* fall through */ | |
452 | case 103 : /* fall through */ | |
453 | case 104 : /* fall through */ | |
454 | case 105 : /* fall through */ | |
455 | case 106 : /* fall through */ | |
456 | case 107 : /* fall through */ | |
457 | case 108 : /* fall through */ | |
458 | case 109 : /* fall through */ | |
459 | case 110 : /* fall through */ | |
460 | case 111 : itype = M32R2F_INSN_LDI8; goto extract_sfmt_ldi8; | |
461 | case 112 : | |
462 | { | |
463 | unsigned int val = (((insn >> 7) & (15 << 1)) | ((insn >> 0) & (1 << 0))); | |
464 | switch (val) | |
465 | { | |
e9c60591 DE |
466 | case 0 : |
467 | if ((entire_insn & 0xffff) == 0x7000) | |
468 | { itype = M32R2F_INSN_NOP; goto extract_sfmt_nop; } | |
469 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
16b47b25 NC |
470 | case 2 : /* fall through */ |
471 | case 3 : itype = M32R2F_INSN_SETPSW; goto extract_sfmt_setpsw; | |
472 | case 4 : /* fall through */ | |
473 | case 5 : itype = M32R2F_INSN_CLRPSW; goto extract_sfmt_clrpsw; | |
e9c60591 DE |
474 | case 9 : |
475 | if ((entire_insn & 0xffff) == 0x7401) | |
476 | { itype = M32R2F_INSN_SC; goto extract_sfmt_sc; } | |
477 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
478 | case 11 : | |
479 | if ((entire_insn & 0xffff) == 0x7501) | |
480 | { itype = M32R2F_INSN_SNC; goto extract_sfmt_sc; } | |
481 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
16b47b25 NC |
482 | case 16 : /* fall through */ |
483 | case 17 : itype = M32R2F_INSN_BCL8; goto extract_sfmt_bcl8; | |
484 | case 18 : /* fall through */ | |
485 | case 19 : itype = M32R2F_INSN_BNCL8; goto extract_sfmt_bcl8; | |
486 | case 24 : /* fall through */ | |
487 | case 25 : itype = M32R2F_INSN_BC8; goto extract_sfmt_bc8; | |
488 | case 26 : /* fall through */ | |
489 | case 27 : itype = M32R2F_INSN_BNC8; goto extract_sfmt_bc8; | |
490 | case 28 : /* fall through */ | |
491 | case 29 : itype = M32R2F_INSN_BL8; goto extract_sfmt_bl8; | |
492 | case 30 : /* fall through */ | |
493 | case 31 : itype = M32R2F_INSN_BRA8; goto extract_sfmt_bra8; | |
494 | default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
495 | } | |
496 | } | |
497 | case 113 : /* fall through */ | |
498 | case 114 : /* fall through */ | |
499 | case 115 : /* fall through */ | |
500 | case 116 : /* fall through */ | |
501 | case 117 : /* fall through */ | |
502 | case 118 : /* fall through */ | |
503 | case 119 : /* fall through */ | |
504 | case 120 : /* fall through */ | |
505 | case 121 : /* fall through */ | |
506 | case 122 : /* fall through */ | |
507 | case 123 : /* fall through */ | |
508 | case 124 : /* fall through */ | |
509 | case 125 : /* fall through */ | |
510 | case 126 : /* fall through */ | |
511 | case 127 : | |
512 | { | |
513 | unsigned int val = (((insn >> 8) & (15 << 0))); | |
514 | switch (val) | |
515 | { | |
516 | case 1 : itype = M32R2F_INSN_SETPSW; goto extract_sfmt_setpsw; | |
517 | case 2 : itype = M32R2F_INSN_CLRPSW; goto extract_sfmt_clrpsw; | |
518 | case 8 : itype = M32R2F_INSN_BCL8; goto extract_sfmt_bcl8; | |
519 | case 9 : itype = M32R2F_INSN_BNCL8; goto extract_sfmt_bcl8; | |
520 | case 12 : itype = M32R2F_INSN_BC8; goto extract_sfmt_bc8; | |
521 | case 13 : itype = M32R2F_INSN_BNC8; goto extract_sfmt_bc8; | |
522 | case 14 : itype = M32R2F_INSN_BL8; goto extract_sfmt_bl8; | |
523 | case 15 : itype = M32R2F_INSN_BRA8; goto extract_sfmt_bra8; | |
524 | default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
525 | } | |
526 | } | |
e9c60591 DE |
527 | case 132 : |
528 | if ((entire_insn & 0xfff00000) == 0x80400000) | |
529 | { itype = M32R2F_INSN_CMPI; goto extract_sfmt_cmpi; } | |
530 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
531 | case 133 : | |
532 | if ((entire_insn & 0xfff00000) == 0x80500000) | |
533 | { itype = M32R2F_INSN_CMPUI; goto extract_sfmt_cmpi; } | |
534 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
16b47b25 NC |
535 | case 134 : |
536 | { | |
e9c60591 | 537 | unsigned int val = (((entire_insn >> 8) & (3 << 0))); |
16b47b25 NC |
538 | switch (val) |
539 | { | |
e9c60591 DE |
540 | case 0 : |
541 | if ((entire_insn & 0xf0f0ffff) == 0x80600000) | |
542 | { itype = M32R2F_INSN_SAT; goto extract_sfmt_sat; } | |
543 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
544 | case 2 : | |
545 | if ((entire_insn & 0xf0f0ffff) == 0x80600200) | |
546 | { itype = M32R2F_INSN_SATH; goto extract_sfmt_satb; } | |
547 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
548 | case 3 : | |
549 | if ((entire_insn & 0xf0f0ffff) == 0x80600300) | |
550 | { itype = M32R2F_INSN_SATB; goto extract_sfmt_satb; } | |
551 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
16b47b25 NC |
552 | default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; |
553 | } | |
554 | } | |
555 | case 136 : itype = M32R2F_INSN_ADDV3; goto extract_sfmt_addv3; | |
556 | case 138 : itype = M32R2F_INSN_ADD3; goto extract_sfmt_add3; | |
557 | case 140 : itype = M32R2F_INSN_AND3; goto extract_sfmt_and3; | |
558 | case 141 : itype = M32R2F_INSN_XOR3; goto extract_sfmt_and3; | |
559 | case 142 : itype = M32R2F_INSN_OR3; goto extract_sfmt_or3; | |
560 | case 144 : | |
561 | { | |
e9c60591 | 562 | unsigned int val = (((entire_insn >> 3) & (3 << 0))); |
16b47b25 NC |
563 | switch (val) |
564 | { | |
e9c60591 DE |
565 | case 0 : |
566 | if ((entire_insn & 0xf0f0ffff) == 0x90000000) | |
567 | { itype = M32R2F_INSN_DIV; goto extract_sfmt_div; } | |
568 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
569 | case 2 : | |
570 | if ((entire_insn & 0xf0f0ffff) == 0x90000010) | |
571 | { itype = M32R2F_INSN_DIVH; goto extract_sfmt_div; } | |
572 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
573 | case 3 : | |
574 | if ((entire_insn & 0xf0f0ffff) == 0x90000018) | |
575 | { itype = M32R2F_INSN_DIVB; goto extract_sfmt_div; } | |
576 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
16b47b25 NC |
577 | default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; |
578 | } | |
579 | } | |
580 | case 145 : | |
581 | { | |
e9c60591 | 582 | unsigned int val = (((entire_insn >> 3) & (3 << 0))); |
16b47b25 NC |
583 | switch (val) |
584 | { | |
e9c60591 DE |
585 | case 0 : |
586 | if ((entire_insn & 0xf0f0ffff) == 0x90100000) | |
587 | { itype = M32R2F_INSN_DIVU; goto extract_sfmt_div; } | |
588 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
589 | case 2 : | |
590 | if ((entire_insn & 0xf0f0ffff) == 0x90100010) | |
591 | { itype = M32R2F_INSN_DIVUH; goto extract_sfmt_div; } | |
592 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
593 | case 3 : | |
594 | if ((entire_insn & 0xf0f0ffff) == 0x90100018) | |
595 | { itype = M32R2F_INSN_DIVUB; goto extract_sfmt_div; } | |
596 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
16b47b25 NC |
597 | default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; |
598 | } | |
599 | } | |
600 | case 146 : | |
601 | { | |
e9c60591 | 602 | unsigned int val = (((entire_insn >> 3) & (3 << 0))); |
16b47b25 NC |
603 | switch (val) |
604 | { | |
e9c60591 DE |
605 | case 0 : |
606 | if ((entire_insn & 0xf0f0ffff) == 0x90200000) | |
607 | { itype = M32R2F_INSN_REM; goto extract_sfmt_div; } | |
608 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
609 | case 2 : | |
610 | if ((entire_insn & 0xf0f0ffff) == 0x90200010) | |
611 | { itype = M32R2F_INSN_REMH; goto extract_sfmt_div; } | |
612 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
613 | case 3 : | |
614 | if ((entire_insn & 0xf0f0ffff) == 0x90200018) | |
615 | { itype = M32R2F_INSN_REMB; goto extract_sfmt_div; } | |
616 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
16b47b25 NC |
617 | default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; |
618 | } | |
619 | } | |
620 | case 147 : | |
621 | { | |
e9c60591 | 622 | unsigned int val = (((entire_insn >> 3) & (3 << 0))); |
16b47b25 NC |
623 | switch (val) |
624 | { | |
e9c60591 DE |
625 | case 0 : |
626 | if ((entire_insn & 0xf0f0ffff) == 0x90300000) | |
627 | { itype = M32R2F_INSN_REMU; goto extract_sfmt_div; } | |
628 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
629 | case 2 : | |
630 | if ((entire_insn & 0xf0f0ffff) == 0x90300010) | |
631 | { itype = M32R2F_INSN_REMUH; goto extract_sfmt_div; } | |
632 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
633 | case 3 : | |
634 | if ((entire_insn & 0xf0f0ffff) == 0x90300018) | |
635 | { itype = M32R2F_INSN_REMUB; goto extract_sfmt_div; } | |
636 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
16b47b25 NC |
637 | default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; |
638 | } | |
639 | } | |
640 | case 152 : itype = M32R2F_INSN_SRL3; goto extract_sfmt_sll3; | |
641 | case 154 : itype = M32R2F_INSN_SRA3; goto extract_sfmt_sll3; | |
642 | case 156 : itype = M32R2F_INSN_SLL3; goto extract_sfmt_sll3; | |
e9c60591 DE |
643 | case 159 : |
644 | if ((entire_insn & 0xf0ff0000) == 0x90f00000) | |
645 | { itype = M32R2F_INSN_LDI16; goto extract_sfmt_ldi16; } | |
646 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
16b47b25 NC |
647 | case 160 : itype = M32R2F_INSN_STB_D; goto extract_sfmt_stb_d; |
648 | case 162 : itype = M32R2F_INSN_STH_D; goto extract_sfmt_sth_d; | |
649 | case 164 : itype = M32R2F_INSN_ST_D; goto extract_sfmt_st_d; | |
e9c60591 DE |
650 | case 166 : |
651 | if ((entire_insn & 0xf8f00000) == 0xa0600000) | |
652 | { itype = M32R2F_INSN_BSET; goto extract_sfmt_bset; } | |
653 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
654 | case 167 : | |
655 | if ((entire_insn & 0xf8f00000) == 0xa0700000) | |
656 | { itype = M32R2F_INSN_BCLR; goto extract_sfmt_bset; } | |
657 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
16b47b25 NC |
658 | case 168 : itype = M32R2F_INSN_LDB_D; goto extract_sfmt_ldb_d; |
659 | case 169 : itype = M32R2F_INSN_LDUB_D; goto extract_sfmt_ldb_d; | |
660 | case 170 : itype = M32R2F_INSN_LDH_D; goto extract_sfmt_ldh_d; | |
661 | case 171 : itype = M32R2F_INSN_LDUH_D; goto extract_sfmt_ldh_d; | |
662 | case 172 : itype = M32R2F_INSN_LD_D; goto extract_sfmt_ld_d; | |
663 | case 176 : itype = M32R2F_INSN_BEQ; goto extract_sfmt_beq; | |
664 | case 177 : itype = M32R2F_INSN_BNE; goto extract_sfmt_beq; | |
e9c60591 DE |
665 | case 184 : |
666 | if ((entire_insn & 0xfff00000) == 0xb0800000) | |
667 | { itype = M32R2F_INSN_BEQZ; goto extract_sfmt_beqz; } | |
668 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
669 | case 185 : | |
670 | if ((entire_insn & 0xfff00000) == 0xb0900000) | |
671 | { itype = M32R2F_INSN_BNEZ; goto extract_sfmt_beqz; } | |
672 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
673 | case 186 : | |
674 | if ((entire_insn & 0xfff00000) == 0xb0a00000) | |
675 | { itype = M32R2F_INSN_BLTZ; goto extract_sfmt_beqz; } | |
676 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
677 | case 187 : | |
678 | if ((entire_insn & 0xfff00000) == 0xb0b00000) | |
679 | { itype = M32R2F_INSN_BGEZ; goto extract_sfmt_beqz; } | |
680 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
681 | case 188 : | |
682 | if ((entire_insn & 0xfff00000) == 0xb0c00000) | |
683 | { itype = M32R2F_INSN_BLEZ; goto extract_sfmt_beqz; } | |
684 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
685 | case 189 : | |
686 | if ((entire_insn & 0xfff00000) == 0xb0d00000) | |
687 | { itype = M32R2F_INSN_BGTZ; goto extract_sfmt_beqz; } | |
688 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
689 | case 220 : | |
690 | if ((entire_insn & 0xf0ff0000) == 0xd0c00000) | |
691 | { itype = M32R2F_INSN_SETH; goto extract_sfmt_seth; } | |
692 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
16b47b25 NC |
693 | case 224 : /* fall through */ |
694 | case 225 : /* fall through */ | |
695 | case 226 : /* fall through */ | |
696 | case 227 : /* fall through */ | |
697 | case 228 : /* fall through */ | |
698 | case 229 : /* fall through */ | |
699 | case 230 : /* fall through */ | |
700 | case 231 : /* fall through */ | |
701 | case 232 : /* fall through */ | |
702 | case 233 : /* fall through */ | |
703 | case 234 : /* fall through */ | |
704 | case 235 : /* fall through */ | |
705 | case 236 : /* fall through */ | |
706 | case 237 : /* fall through */ | |
707 | case 238 : /* fall through */ | |
708 | case 239 : itype = M32R2F_INSN_LD24; goto extract_sfmt_ld24; | |
709 | case 240 : /* fall through */ | |
710 | case 241 : /* fall through */ | |
711 | case 242 : /* fall through */ | |
712 | case 243 : /* fall through */ | |
713 | case 244 : /* fall through */ | |
714 | case 245 : /* fall through */ | |
715 | case 246 : /* fall through */ | |
716 | case 247 : /* fall through */ | |
717 | case 248 : /* fall through */ | |
718 | case 249 : /* fall through */ | |
719 | case 250 : /* fall through */ | |
720 | case 251 : /* fall through */ | |
721 | case 252 : /* fall through */ | |
722 | case 253 : /* fall through */ | |
723 | case 254 : /* fall through */ | |
724 | case 255 : | |
725 | { | |
726 | unsigned int val = (((insn >> 8) & (7 << 0))); | |
727 | switch (val) | |
728 | { | |
e9c60591 DE |
729 | case 0 : |
730 | if ((entire_insn & 0xff000000) == 0xf8000000) | |
731 | { itype = M32R2F_INSN_BCL24; goto extract_sfmt_bcl24; } | |
732 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
733 | case 1 : | |
734 | if ((entire_insn & 0xff000000) == 0xf9000000) | |
735 | { itype = M32R2F_INSN_BNCL24; goto extract_sfmt_bcl24; } | |
736 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
737 | case 4 : | |
738 | if ((entire_insn & 0xff000000) == 0xfc000000) | |
739 | { itype = M32R2F_INSN_BC24; goto extract_sfmt_bc24; } | |
740 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
741 | case 5 : | |
742 | if ((entire_insn & 0xff000000) == 0xfd000000) | |
743 | { itype = M32R2F_INSN_BNC24; goto extract_sfmt_bc24; } | |
744 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
745 | case 6 : | |
746 | if ((entire_insn & 0xff000000) == 0xfe000000) | |
747 | { itype = M32R2F_INSN_BL24; goto extract_sfmt_bl24; } | |
748 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
749 | case 7 : | |
750 | if ((entire_insn & 0xff000000) == 0xff000000) | |
751 | { itype = M32R2F_INSN_BRA24; goto extract_sfmt_bra24; } | |
752 | itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
16b47b25 NC |
753 | default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; |
754 | } | |
755 | } | |
756 | default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; | |
757 | } | |
758 | } | |
759 | } | |
760 | ||
761 | /* The instruction has been decoded, now extract the fields. */ | |
762 | ||
763 | extract_sfmt_empty: | |
764 | { | |
765 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
2310652a | 766 | #define FLD(f) abuf->fields.sfmt_empty.f |
16b47b25 NC |
767 | |
768 | ||
769 | /* Record the fields for the semantic handler. */ | |
770 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_empty", (char *) 0)); | |
771 | ||
772 | #undef FLD | |
773 | return idesc; | |
774 | } | |
775 | ||
776 | extract_sfmt_add: | |
777 | { | |
778 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 779 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
780 | #define FLD(f) abuf->fields.sfmt_add.f |
781 | UINT f_r1; | |
782 | UINT f_r2; | |
783 | ||
784 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
785 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
786 | ||
787 | /* Record the fields for the semantic handler. */ | |
788 | FLD (f_r1) = f_r1; | |
789 | FLD (f_r2) = f_r2; | |
790 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
791 | FLD (i_sr) = & CPU (h_gr)[f_r2]; | |
792 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0)); | |
793 | ||
794 | #if WITH_PROFILE_MODEL_P | |
795 | /* Record the fields for profiling. */ | |
796 | if (PROFILE_MODEL_P (current_cpu)) | |
797 | { | |
798 | FLD (in_dr) = f_r1; | |
799 | FLD (in_sr) = f_r2; | |
800 | FLD (out_dr) = f_r1; | |
801 | } | |
802 | #endif | |
803 | #undef FLD | |
804 | return idesc; | |
805 | } | |
806 | ||
807 | extract_sfmt_add3: | |
808 | { | |
809 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 810 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
811 | #define FLD(f) abuf->fields.sfmt_add3.f |
812 | UINT f_r1; | |
813 | UINT f_r2; | |
814 | INT f_simm16; | |
815 | ||
816 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); | |
817 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); | |
62836bf4 | 818 | f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); |
16b47b25 NC |
819 | |
820 | /* Record the fields for the semantic handler. */ | |
821 | FLD (f_simm16) = f_simm16; | |
822 | FLD (f_r2) = f_r2; | |
823 | FLD (f_r1) = f_r1; | |
824 | FLD (i_sr) = & CPU (h_gr)[f_r2]; | |
825 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
826 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add3", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); | |
827 | ||
828 | #if WITH_PROFILE_MODEL_P | |
829 | /* Record the fields for profiling. */ | |
830 | if (PROFILE_MODEL_P (current_cpu)) | |
831 | { | |
832 | FLD (in_sr) = f_r2; | |
833 | FLD (out_dr) = f_r1; | |
834 | } | |
835 | #endif | |
836 | #undef FLD | |
837 | return idesc; | |
838 | } | |
839 | ||
840 | extract_sfmt_and3: | |
841 | { | |
842 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 843 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
844 | #define FLD(f) abuf->fields.sfmt_and3.f |
845 | UINT f_r1; | |
846 | UINT f_r2; | |
847 | UINT f_uimm16; | |
848 | ||
849 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); | |
850 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); | |
851 | f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); | |
852 | ||
853 | /* Record the fields for the semantic handler. */ | |
854 | FLD (f_r2) = f_r2; | |
855 | FLD (f_uimm16) = f_uimm16; | |
856 | FLD (f_r1) = f_r1; | |
857 | FLD (i_sr) = & CPU (h_gr)[f_r2]; | |
858 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
859 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_and3", "f_r2 0x%x", 'x', f_r2, "f_uimm16 0x%x", 'x', f_uimm16, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); | |
860 | ||
861 | #if WITH_PROFILE_MODEL_P | |
862 | /* Record the fields for profiling. */ | |
863 | if (PROFILE_MODEL_P (current_cpu)) | |
864 | { | |
865 | FLD (in_sr) = f_r2; | |
866 | FLD (out_dr) = f_r1; | |
867 | } | |
868 | #endif | |
869 | #undef FLD | |
870 | return idesc; | |
871 | } | |
872 | ||
873 | extract_sfmt_or3: | |
874 | { | |
875 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 876 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
877 | #define FLD(f) abuf->fields.sfmt_and3.f |
878 | UINT f_r1; | |
879 | UINT f_r2; | |
880 | UINT f_uimm16; | |
881 | ||
882 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); | |
883 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); | |
884 | f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); | |
885 | ||
886 | /* Record the fields for the semantic handler. */ | |
887 | FLD (f_r2) = f_r2; | |
888 | FLD (f_uimm16) = f_uimm16; | |
889 | FLD (f_r1) = f_r1; | |
890 | FLD (i_sr) = & CPU (h_gr)[f_r2]; | |
891 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
892 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_or3", "f_r2 0x%x", 'x', f_r2, "f_uimm16 0x%x", 'x', f_uimm16, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); | |
893 | ||
894 | #if WITH_PROFILE_MODEL_P | |
895 | /* Record the fields for profiling. */ | |
896 | if (PROFILE_MODEL_P (current_cpu)) | |
897 | { | |
898 | FLD (in_sr) = f_r2; | |
899 | FLD (out_dr) = f_r1; | |
900 | } | |
901 | #endif | |
902 | #undef FLD | |
903 | return idesc; | |
904 | } | |
905 | ||
906 | extract_sfmt_addi: | |
907 | { | |
908 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 909 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
910 | #define FLD(f) abuf->fields.sfmt_addi.f |
911 | UINT f_r1; | |
912 | INT f_simm8; | |
913 | ||
914 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
62836bf4 | 915 | f_simm8 = EXTRACT_MSB0_SINT (insn, 16, 8, 8); |
16b47b25 NC |
916 | |
917 | /* Record the fields for the semantic handler. */ | |
918 | FLD (f_r1) = f_r1; | |
919 | FLD (f_simm8) = f_simm8; | |
920 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
921 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addi", "f_r1 0x%x", 'x', f_r1, "f_simm8 0x%x", 'x', f_simm8, "dr 0x%x", 'x', f_r1, (char *) 0)); | |
922 | ||
923 | #if WITH_PROFILE_MODEL_P | |
924 | /* Record the fields for profiling. */ | |
925 | if (PROFILE_MODEL_P (current_cpu)) | |
926 | { | |
927 | FLD (in_dr) = f_r1; | |
928 | FLD (out_dr) = f_r1; | |
929 | } | |
930 | #endif | |
931 | #undef FLD | |
932 | return idesc; | |
933 | } | |
934 | ||
935 | extract_sfmt_addv: | |
936 | { | |
937 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 938 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
939 | #define FLD(f) abuf->fields.sfmt_add.f |
940 | UINT f_r1; | |
941 | UINT f_r2; | |
942 | ||
943 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
944 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
945 | ||
946 | /* Record the fields for the semantic handler. */ | |
947 | FLD (f_r1) = f_r1; | |
948 | FLD (f_r2) = f_r2; | |
949 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
950 | FLD (i_sr) = & CPU (h_gr)[f_r2]; | |
951 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addv", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0)); | |
952 | ||
953 | #if WITH_PROFILE_MODEL_P | |
954 | /* Record the fields for profiling. */ | |
955 | if (PROFILE_MODEL_P (current_cpu)) | |
956 | { | |
957 | FLD (in_dr) = f_r1; | |
958 | FLD (in_sr) = f_r2; | |
959 | FLD (out_dr) = f_r1; | |
960 | } | |
961 | #endif | |
962 | #undef FLD | |
963 | return idesc; | |
964 | } | |
965 | ||
966 | extract_sfmt_addv3: | |
967 | { | |
968 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 969 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
970 | #define FLD(f) abuf->fields.sfmt_add3.f |
971 | UINT f_r1; | |
972 | UINT f_r2; | |
973 | INT f_simm16; | |
974 | ||
975 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); | |
976 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); | |
62836bf4 | 977 | f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); |
16b47b25 NC |
978 | |
979 | /* Record the fields for the semantic handler. */ | |
980 | FLD (f_simm16) = f_simm16; | |
981 | FLD (f_r2) = f_r2; | |
982 | FLD (f_r1) = f_r1; | |
983 | FLD (i_sr) = & CPU (h_gr)[f_r2]; | |
984 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
985 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addv3", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); | |
986 | ||
987 | #if WITH_PROFILE_MODEL_P | |
988 | /* Record the fields for profiling. */ | |
989 | if (PROFILE_MODEL_P (current_cpu)) | |
990 | { | |
991 | FLD (in_sr) = f_r2; | |
992 | FLD (out_dr) = f_r1; | |
993 | } | |
994 | #endif | |
995 | #undef FLD | |
996 | return idesc; | |
997 | } | |
998 | ||
999 | extract_sfmt_addx: | |
1000 | { | |
1001 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 1002 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
1003 | #define FLD(f) abuf->fields.sfmt_add.f |
1004 | UINT f_r1; | |
1005 | UINT f_r2; | |
1006 | ||
1007 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
1008 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
1009 | ||
1010 | /* Record the fields for the semantic handler. */ | |
1011 | FLD (f_r1) = f_r1; | |
1012 | FLD (f_r2) = f_r2; | |
1013 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
1014 | FLD (i_sr) = & CPU (h_gr)[f_r2]; | |
1015 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addx", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0)); | |
1016 | ||
1017 | #if WITH_PROFILE_MODEL_P | |
1018 | /* Record the fields for profiling. */ | |
1019 | if (PROFILE_MODEL_P (current_cpu)) | |
1020 | { | |
1021 | FLD (in_dr) = f_r1; | |
1022 | FLD (in_sr) = f_r2; | |
1023 | FLD (out_dr) = f_r1; | |
1024 | } | |
1025 | #endif | |
1026 | #undef FLD | |
1027 | return idesc; | |
1028 | } | |
1029 | ||
1030 | extract_sfmt_bc8: | |
1031 | { | |
1032 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 1033 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
1034 | #define FLD(f) abuf->fields.sfmt_bl8.f |
1035 | SI f_disp8; | |
1036 | ||
62836bf4 | 1037 | f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); |
16b47b25 NC |
1038 | |
1039 | /* Record the fields for the semantic handler. */ | |
1040 | FLD (i_disp8) = f_disp8; | |
1041 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bc8", "disp8 0x%x", 'x', f_disp8, (char *) 0)); | |
1042 | ||
1043 | #if WITH_PROFILE_MODEL_P | |
1044 | /* Record the fields for profiling. */ | |
1045 | if (PROFILE_MODEL_P (current_cpu)) | |
1046 | { | |
1047 | } | |
1048 | #endif | |
1049 | #undef FLD | |
1050 | return idesc; | |
1051 | } | |
1052 | ||
1053 | extract_sfmt_bc24: | |
1054 | { | |
1055 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 1056 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
1057 | #define FLD(f) abuf->fields.sfmt_bl24.f |
1058 | SI f_disp24; | |
1059 | ||
62836bf4 | 1060 | f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) << (2))) + (pc)); |
16b47b25 NC |
1061 | |
1062 | /* Record the fields for the semantic handler. */ | |
1063 | FLD (i_disp24) = f_disp24; | |
1064 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bc24", "disp24 0x%x", 'x', f_disp24, (char *) 0)); | |
1065 | ||
1066 | #if WITH_PROFILE_MODEL_P | |
1067 | /* Record the fields for profiling. */ | |
1068 | if (PROFILE_MODEL_P (current_cpu)) | |
1069 | { | |
1070 | } | |
1071 | #endif | |
1072 | #undef FLD | |
1073 | return idesc; | |
1074 | } | |
1075 | ||
1076 | extract_sfmt_beq: | |
1077 | { | |
1078 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 1079 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
1080 | #define FLD(f) abuf->fields.sfmt_beq.f |
1081 | UINT f_r1; | |
1082 | UINT f_r2; | |
1083 | SI f_disp16; | |
1084 | ||
1085 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); | |
1086 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); | |
62836bf4 | 1087 | f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) << (2))) + (pc)); |
16b47b25 NC |
1088 | |
1089 | /* Record the fields for the semantic handler. */ | |
1090 | FLD (f_r1) = f_r1; | |
1091 | FLD (f_r2) = f_r2; | |
1092 | FLD (i_disp16) = f_disp16; | |
1093 | FLD (i_src1) = & CPU (h_gr)[f_r1]; | |
1094 | FLD (i_src2) = & CPU (h_gr)[f_r2]; | |
1095 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_beq", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "disp16 0x%x", 'x', f_disp16, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); | |
1096 | ||
1097 | #if WITH_PROFILE_MODEL_P | |
1098 | /* Record the fields for profiling. */ | |
1099 | if (PROFILE_MODEL_P (current_cpu)) | |
1100 | { | |
1101 | FLD (in_src1) = f_r1; | |
1102 | FLD (in_src2) = f_r2; | |
1103 | } | |
1104 | #endif | |
1105 | #undef FLD | |
1106 | return idesc; | |
1107 | } | |
1108 | ||
1109 | extract_sfmt_beqz: | |
1110 | { | |
1111 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 1112 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
1113 | #define FLD(f) abuf->fields.sfmt_beq.f |
1114 | UINT f_r2; | |
1115 | SI f_disp16; | |
1116 | ||
1117 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); | |
62836bf4 | 1118 | f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) << (2))) + (pc)); |
16b47b25 NC |
1119 | |
1120 | /* Record the fields for the semantic handler. */ | |
1121 | FLD (f_r2) = f_r2; | |
1122 | FLD (i_disp16) = f_disp16; | |
1123 | FLD (i_src2) = & CPU (h_gr)[f_r2]; | |
1124 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_beqz", "f_r2 0x%x", 'x', f_r2, "disp16 0x%x", 'x', f_disp16, "src2 0x%x", 'x', f_r2, (char *) 0)); | |
1125 | ||
1126 | #if WITH_PROFILE_MODEL_P | |
1127 | /* Record the fields for profiling. */ | |
1128 | if (PROFILE_MODEL_P (current_cpu)) | |
1129 | { | |
1130 | FLD (in_src2) = f_r2; | |
1131 | } | |
1132 | #endif | |
1133 | #undef FLD | |
1134 | return idesc; | |
1135 | } | |
1136 | ||
1137 | extract_sfmt_bl8: | |
1138 | { | |
1139 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 1140 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
1141 | #define FLD(f) abuf->fields.sfmt_bl8.f |
1142 | SI f_disp8; | |
1143 | ||
62836bf4 | 1144 | f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); |
16b47b25 NC |
1145 | |
1146 | /* Record the fields for the semantic handler. */ | |
1147 | FLD (i_disp8) = f_disp8; | |
1148 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bl8", "disp8 0x%x", 'x', f_disp8, (char *) 0)); | |
1149 | ||
1150 | #if WITH_PROFILE_MODEL_P | |
1151 | /* Record the fields for profiling. */ | |
1152 | if (PROFILE_MODEL_P (current_cpu)) | |
1153 | { | |
1154 | FLD (out_h_gr_SI_14) = 14; | |
1155 | } | |
1156 | #endif | |
1157 | #undef FLD | |
1158 | return idesc; | |
1159 | } | |
1160 | ||
1161 | extract_sfmt_bl24: | |
1162 | { | |
1163 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 1164 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
1165 | #define FLD(f) abuf->fields.sfmt_bl24.f |
1166 | SI f_disp24; | |
1167 | ||
62836bf4 | 1168 | f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) << (2))) + (pc)); |
16b47b25 NC |
1169 | |
1170 | /* Record the fields for the semantic handler. */ | |
1171 | FLD (i_disp24) = f_disp24; | |
1172 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bl24", "disp24 0x%x", 'x', f_disp24, (char *) 0)); | |
1173 | ||
1174 | #if WITH_PROFILE_MODEL_P | |
1175 | /* Record the fields for profiling. */ | |
1176 | if (PROFILE_MODEL_P (current_cpu)) | |
1177 | { | |
1178 | FLD (out_h_gr_SI_14) = 14; | |
1179 | } | |
1180 | #endif | |
1181 | #undef FLD | |
1182 | return idesc; | |
1183 | } | |
1184 | ||
1185 | extract_sfmt_bcl8: | |
1186 | { | |
1187 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 1188 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
1189 | #define FLD(f) abuf->fields.sfmt_bl8.f |
1190 | SI f_disp8; | |
1191 | ||
62836bf4 | 1192 | f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); |
16b47b25 NC |
1193 | |
1194 | /* Record the fields for the semantic handler. */ | |
1195 | FLD (i_disp8) = f_disp8; | |
1196 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bcl8", "disp8 0x%x", 'x', f_disp8, (char *) 0)); | |
1197 | ||
1198 | #if WITH_PROFILE_MODEL_P | |
1199 | /* Record the fields for profiling. */ | |
1200 | if (PROFILE_MODEL_P (current_cpu)) | |
1201 | { | |
1202 | FLD (out_h_gr_SI_14) = 14; | |
1203 | } | |
1204 | #endif | |
1205 | #undef FLD | |
1206 | return idesc; | |
1207 | } | |
1208 | ||
1209 | extract_sfmt_bcl24: | |
1210 | { | |
1211 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 1212 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
1213 | #define FLD(f) abuf->fields.sfmt_bl24.f |
1214 | SI f_disp24; | |
1215 | ||
62836bf4 | 1216 | f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) << (2))) + (pc)); |
16b47b25 NC |
1217 | |
1218 | /* Record the fields for the semantic handler. */ | |
1219 | FLD (i_disp24) = f_disp24; | |
1220 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bcl24", "disp24 0x%x", 'x', f_disp24, (char *) 0)); | |
1221 | ||
1222 | #if WITH_PROFILE_MODEL_P | |
1223 | /* Record the fields for profiling. */ | |
1224 | if (PROFILE_MODEL_P (current_cpu)) | |
1225 | { | |
1226 | FLD (out_h_gr_SI_14) = 14; | |
1227 | } | |
1228 | #endif | |
1229 | #undef FLD | |
1230 | return idesc; | |
1231 | } | |
1232 | ||
1233 | extract_sfmt_bra8: | |
1234 | { | |
1235 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 1236 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
1237 | #define FLD(f) abuf->fields.sfmt_bl8.f |
1238 | SI f_disp8; | |
1239 | ||
62836bf4 | 1240 | f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); |
16b47b25 NC |
1241 | |
1242 | /* Record the fields for the semantic handler. */ | |
1243 | FLD (i_disp8) = f_disp8; | |
1244 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bra8", "disp8 0x%x", 'x', f_disp8, (char *) 0)); | |
1245 | ||
1246 | #if WITH_PROFILE_MODEL_P | |
1247 | /* Record the fields for profiling. */ | |
1248 | if (PROFILE_MODEL_P (current_cpu)) | |
1249 | { | |
1250 | } | |
1251 | #endif | |
1252 | #undef FLD | |
1253 | return idesc; | |
1254 | } | |
1255 | ||
1256 | extract_sfmt_bra24: | |
1257 | { | |
1258 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 1259 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
1260 | #define FLD(f) abuf->fields.sfmt_bl24.f |
1261 | SI f_disp24; | |
1262 | ||
62836bf4 | 1263 | f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) << (2))) + (pc)); |
16b47b25 NC |
1264 | |
1265 | /* Record the fields for the semantic handler. */ | |
1266 | FLD (i_disp24) = f_disp24; | |
1267 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bra24", "disp24 0x%x", 'x', f_disp24, (char *) 0)); | |
1268 | ||
1269 | #if WITH_PROFILE_MODEL_P | |
1270 | /* Record the fields for profiling. */ | |
1271 | if (PROFILE_MODEL_P (current_cpu)) | |
1272 | { | |
1273 | } | |
1274 | #endif | |
1275 | #undef FLD | |
1276 | return idesc; | |
1277 | } | |
1278 | ||
1279 | extract_sfmt_cmp: | |
1280 | { | |
1281 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 1282 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
1283 | #define FLD(f) abuf->fields.sfmt_st_plus.f |
1284 | UINT f_r1; | |
1285 | UINT f_r2; | |
1286 | ||
1287 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
1288 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
1289 | ||
1290 | /* Record the fields for the semantic handler. */ | |
1291 | FLD (f_r1) = f_r1; | |
1292 | FLD (f_r2) = f_r2; | |
1293 | FLD (i_src1) = & CPU (h_gr)[f_r1]; | |
1294 | FLD (i_src2) = & CPU (h_gr)[f_r2]; | |
1295 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmp", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); | |
1296 | ||
1297 | #if WITH_PROFILE_MODEL_P | |
1298 | /* Record the fields for profiling. */ | |
1299 | if (PROFILE_MODEL_P (current_cpu)) | |
1300 | { | |
1301 | FLD (in_src1) = f_r1; | |
1302 | FLD (in_src2) = f_r2; | |
1303 | } | |
1304 | #endif | |
1305 | #undef FLD | |
1306 | return idesc; | |
1307 | } | |
1308 | ||
1309 | extract_sfmt_cmpi: | |
1310 | { | |
1311 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 1312 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
1313 | #define FLD(f) abuf->fields.sfmt_st_d.f |
1314 | UINT f_r2; | |
1315 | INT f_simm16; | |
1316 | ||
1317 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); | |
62836bf4 | 1318 | f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); |
16b47b25 NC |
1319 | |
1320 | /* Record the fields for the semantic handler. */ | |
1321 | FLD (f_simm16) = f_simm16; | |
1322 | FLD (f_r2) = f_r2; | |
1323 | FLD (i_src2) = & CPU (h_gr)[f_r2]; | |
1324 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpi", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "src2 0x%x", 'x', f_r2, (char *) 0)); | |
1325 | ||
1326 | #if WITH_PROFILE_MODEL_P | |
1327 | /* Record the fields for profiling. */ | |
1328 | if (PROFILE_MODEL_P (current_cpu)) | |
1329 | { | |
1330 | FLD (in_src2) = f_r2; | |
1331 | } | |
1332 | #endif | |
1333 | #undef FLD | |
1334 | return idesc; | |
1335 | } | |
1336 | ||
1337 | extract_sfmt_cmpz: | |
1338 | { | |
1339 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 1340 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
1341 | #define FLD(f) abuf->fields.sfmt_st_plus.f |
1342 | UINT f_r2; | |
1343 | ||
1344 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
1345 | ||
1346 | /* Record the fields for the semantic handler. */ | |
1347 | FLD (f_r2) = f_r2; | |
1348 | FLD (i_src2) = & CPU (h_gr)[f_r2]; | |
1349 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpz", "f_r2 0x%x", 'x', f_r2, "src2 0x%x", 'x', f_r2, (char *) 0)); | |
1350 | ||
1351 | #if WITH_PROFILE_MODEL_P | |
1352 | /* Record the fields for profiling. */ | |
1353 | if (PROFILE_MODEL_P (current_cpu)) | |
1354 | { | |
1355 | FLD (in_src2) = f_r2; | |
1356 | } | |
1357 | #endif | |
1358 | #undef FLD | |
1359 | return idesc; | |
1360 | } | |
1361 | ||
1362 | extract_sfmt_div: | |
1363 | { | |
1364 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 1365 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
1366 | #define FLD(f) abuf->fields.sfmt_add.f |
1367 | UINT f_r1; | |
1368 | UINT f_r2; | |
1369 | ||
1370 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); | |
1371 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); | |
1372 | ||
1373 | /* Record the fields for the semantic handler. */ | |
1374 | FLD (f_r1) = f_r1; | |
1375 | FLD (f_r2) = f_r2; | |
1376 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
1377 | FLD (i_sr) = & CPU (h_gr)[f_r2]; | |
1378 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_div", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0)); | |
1379 | ||
1380 | #if WITH_PROFILE_MODEL_P | |
1381 | /* Record the fields for profiling. */ | |
1382 | if (PROFILE_MODEL_P (current_cpu)) | |
1383 | { | |
1384 | FLD (in_dr) = f_r1; | |
1385 | FLD (in_sr) = f_r2; | |
1386 | FLD (out_dr) = f_r1; | |
1387 | } | |
1388 | #endif | |
1389 | #undef FLD | |
1390 | return idesc; | |
1391 | } | |
1392 | ||
1393 | extract_sfmt_jc: | |
1394 | { | |
1395 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 1396 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
1397 | #define FLD(f) abuf->fields.sfmt_jl.f |
1398 | UINT f_r2; | |
1399 | ||
1400 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
1401 | ||
1402 | /* Record the fields for the semantic handler. */ | |
1403 | FLD (f_r2) = f_r2; | |
1404 | FLD (i_sr) = & CPU (h_gr)[f_r2]; | |
1405 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jc", "f_r2 0x%x", 'x', f_r2, "sr 0x%x", 'x', f_r2, (char *) 0)); | |
1406 | ||
1407 | #if WITH_PROFILE_MODEL_P | |
1408 | /* Record the fields for profiling. */ | |
1409 | if (PROFILE_MODEL_P (current_cpu)) | |
1410 | { | |
1411 | FLD (in_sr) = f_r2; | |
1412 | } | |
1413 | #endif | |
1414 | #undef FLD | |
1415 | return idesc; | |
1416 | } | |
1417 | ||
1418 | extract_sfmt_jl: | |
1419 | { | |
1420 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 1421 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
1422 | #define FLD(f) abuf->fields.sfmt_jl.f |
1423 | UINT f_r2; | |
1424 | ||
1425 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
1426 | ||
1427 | /* Record the fields for the semantic handler. */ | |
1428 | FLD (f_r2) = f_r2; | |
1429 | FLD (i_sr) = & CPU (h_gr)[f_r2]; | |
1430 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jl", "f_r2 0x%x", 'x', f_r2, "sr 0x%x", 'x', f_r2, (char *) 0)); | |
1431 | ||
1432 | #if WITH_PROFILE_MODEL_P | |
1433 | /* Record the fields for profiling. */ | |
1434 | if (PROFILE_MODEL_P (current_cpu)) | |
1435 | { | |
1436 | FLD (in_sr) = f_r2; | |
1437 | FLD (out_h_gr_SI_14) = 14; | |
1438 | } | |
1439 | #endif | |
1440 | #undef FLD | |
1441 | return idesc; | |
1442 | } | |
1443 | ||
1444 | extract_sfmt_jmp: | |
1445 | { | |
1446 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 1447 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
1448 | #define FLD(f) abuf->fields.sfmt_jl.f |
1449 | UINT f_r2; | |
1450 | ||
1451 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
1452 | ||
1453 | /* Record the fields for the semantic handler. */ | |
1454 | FLD (f_r2) = f_r2; | |
1455 | FLD (i_sr) = & CPU (h_gr)[f_r2]; | |
1456 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jmp", "f_r2 0x%x", 'x', f_r2, "sr 0x%x", 'x', f_r2, (char *) 0)); | |
1457 | ||
1458 | #if WITH_PROFILE_MODEL_P | |
1459 | /* Record the fields for profiling. */ | |
1460 | if (PROFILE_MODEL_P (current_cpu)) | |
1461 | { | |
1462 | FLD (in_sr) = f_r2; | |
1463 | } | |
1464 | #endif | |
1465 | #undef FLD | |
1466 | return idesc; | |
1467 | } | |
1468 | ||
1469 | extract_sfmt_ld: | |
1470 | { | |
1471 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 1472 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
1473 | #define FLD(f) abuf->fields.sfmt_ld_plus.f |
1474 | UINT f_r1; | |
1475 | UINT f_r2; | |
1476 | ||
1477 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
1478 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
1479 | ||
1480 | /* Record the fields for the semantic handler. */ | |
1481 | FLD (f_r2) = f_r2; | |
1482 | FLD (f_r1) = f_r1; | |
1483 | FLD (i_sr) = & CPU (h_gr)[f_r2]; | |
1484 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
1485 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); | |
1486 | ||
1487 | #if WITH_PROFILE_MODEL_P | |
1488 | /* Record the fields for profiling. */ | |
1489 | if (PROFILE_MODEL_P (current_cpu)) | |
1490 | { | |
1491 | FLD (in_sr) = f_r2; | |
1492 | FLD (out_dr) = f_r1; | |
1493 | } | |
1494 | #endif | |
1495 | #undef FLD | |
1496 | return idesc; | |
1497 | } | |
1498 | ||
1499 | extract_sfmt_ld_d: | |
1500 | { | |
1501 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 1502 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
1503 | #define FLD(f) abuf->fields.sfmt_add3.f |
1504 | UINT f_r1; | |
1505 | UINT f_r2; | |
1506 | INT f_simm16; | |
1507 | ||
1508 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); | |
1509 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); | |
62836bf4 | 1510 | f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); |
16b47b25 NC |
1511 | |
1512 | /* Record the fields for the semantic handler. */ | |
1513 | FLD (f_simm16) = f_simm16; | |
1514 | FLD (f_r2) = f_r2; | |
1515 | FLD (f_r1) = f_r1; | |
1516 | FLD (i_sr) = & CPU (h_gr)[f_r2]; | |
1517 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
1518 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_d", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); | |
1519 | ||
1520 | #if WITH_PROFILE_MODEL_P | |
1521 | /* Record the fields for profiling. */ | |
1522 | if (PROFILE_MODEL_P (current_cpu)) | |
1523 | { | |
1524 | FLD (in_sr) = f_r2; | |
1525 | FLD (out_dr) = f_r1; | |
1526 | } | |
1527 | #endif | |
1528 | #undef FLD | |
1529 | return idesc; | |
1530 | } | |
1531 | ||
1532 | extract_sfmt_ldb: | |
1533 | { | |
1534 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 1535 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
1536 | #define FLD(f) abuf->fields.sfmt_ld_plus.f |
1537 | UINT f_r1; | |
1538 | UINT f_r2; | |
1539 | ||
1540 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
1541 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
1542 | ||
1543 | /* Record the fields for the semantic handler. */ | |
1544 | FLD (f_r2) = f_r2; | |
1545 | FLD (f_r1) = f_r1; | |
1546 | FLD (i_sr) = & CPU (h_gr)[f_r2]; | |
1547 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
1548 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); | |
1549 | ||
1550 | #if WITH_PROFILE_MODEL_P | |
1551 | /* Record the fields for profiling. */ | |
1552 | if (PROFILE_MODEL_P (current_cpu)) | |
1553 | { | |
1554 | FLD (in_sr) = f_r2; | |
1555 | FLD (out_dr) = f_r1; | |
1556 | } | |
1557 | #endif | |
1558 | #undef FLD | |
1559 | return idesc; | |
1560 | } | |
1561 | ||
1562 | extract_sfmt_ldb_d: | |
1563 | { | |
1564 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 1565 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
1566 | #define FLD(f) abuf->fields.sfmt_add3.f |
1567 | UINT f_r1; | |
1568 | UINT f_r2; | |
1569 | INT f_simm16; | |
1570 | ||
1571 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); | |
1572 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); | |
62836bf4 | 1573 | f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); |
16b47b25 NC |
1574 | |
1575 | /* Record the fields for the semantic handler. */ | |
1576 | FLD (f_simm16) = f_simm16; | |
1577 | FLD (f_r2) = f_r2; | |
1578 | FLD (f_r1) = f_r1; | |
1579 | FLD (i_sr) = & CPU (h_gr)[f_r2]; | |
1580 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
1581 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb_d", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); | |
1582 | ||
1583 | #if WITH_PROFILE_MODEL_P | |
1584 | /* Record the fields for profiling. */ | |
1585 | if (PROFILE_MODEL_P (current_cpu)) | |
1586 | { | |
1587 | FLD (in_sr) = f_r2; | |
1588 | FLD (out_dr) = f_r1; | |
1589 | } | |
1590 | #endif | |
1591 | #undef FLD | |
1592 | return idesc; | |
1593 | } | |
1594 | ||
1595 | extract_sfmt_ldh: | |
1596 | { | |
1597 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 1598 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
1599 | #define FLD(f) abuf->fields.sfmt_ld_plus.f |
1600 | UINT f_r1; | |
1601 | UINT f_r2; | |
1602 | ||
1603 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
1604 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
1605 | ||
1606 | /* Record the fields for the semantic handler. */ | |
1607 | FLD (f_r2) = f_r2; | |
1608 | FLD (f_r1) = f_r1; | |
1609 | FLD (i_sr) = & CPU (h_gr)[f_r2]; | |
1610 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
1611 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldh", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); | |
1612 | ||
1613 | #if WITH_PROFILE_MODEL_P | |
1614 | /* Record the fields for profiling. */ | |
1615 | if (PROFILE_MODEL_P (current_cpu)) | |
1616 | { | |
1617 | FLD (in_sr) = f_r2; | |
1618 | FLD (out_dr) = f_r1; | |
1619 | } | |
1620 | #endif | |
1621 | #undef FLD | |
1622 | return idesc; | |
1623 | } | |
1624 | ||
1625 | extract_sfmt_ldh_d: | |
1626 | { | |
1627 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 1628 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
1629 | #define FLD(f) abuf->fields.sfmt_add3.f |
1630 | UINT f_r1; | |
1631 | UINT f_r2; | |
1632 | INT f_simm16; | |
1633 | ||
1634 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); | |
1635 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); | |
62836bf4 | 1636 | f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); |
16b47b25 NC |
1637 | |
1638 | /* Record the fields for the semantic handler. */ | |
1639 | FLD (f_simm16) = f_simm16; | |
1640 | FLD (f_r2) = f_r2; | |
1641 | FLD (f_r1) = f_r1; | |
1642 | FLD (i_sr) = & CPU (h_gr)[f_r2]; | |
1643 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
1644 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldh_d", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); | |
1645 | ||
1646 | #if WITH_PROFILE_MODEL_P | |
1647 | /* Record the fields for profiling. */ | |
1648 | if (PROFILE_MODEL_P (current_cpu)) | |
1649 | { | |
1650 | FLD (in_sr) = f_r2; | |
1651 | FLD (out_dr) = f_r1; | |
1652 | } | |
1653 | #endif | |
1654 | #undef FLD | |
1655 | return idesc; | |
1656 | } | |
1657 | ||
1658 | extract_sfmt_ld_plus: | |
1659 | { | |
1660 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 1661 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
1662 | #define FLD(f) abuf->fields.sfmt_ld_plus.f |
1663 | UINT f_r1; | |
1664 | UINT f_r2; | |
1665 | ||
1666 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
1667 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
1668 | ||
1669 | /* Record the fields for the semantic handler. */ | |
1670 | FLD (f_r2) = f_r2; | |
1671 | FLD (f_r1) = f_r1; | |
1672 | FLD (i_sr) = & CPU (h_gr)[f_r2]; | |
1673 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
1674 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_plus", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); | |
1675 | ||
1676 | #if WITH_PROFILE_MODEL_P | |
1677 | /* Record the fields for profiling. */ | |
1678 | if (PROFILE_MODEL_P (current_cpu)) | |
1679 | { | |
1680 | FLD (in_sr) = f_r2; | |
1681 | FLD (out_dr) = f_r1; | |
1682 | FLD (out_sr) = f_r2; | |
1683 | } | |
1684 | #endif | |
1685 | #undef FLD | |
1686 | return idesc; | |
1687 | } | |
1688 | ||
1689 | extract_sfmt_ld24: | |
1690 | { | |
1691 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 1692 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
1693 | #define FLD(f) abuf->fields.sfmt_ld24.f |
1694 | UINT f_r1; | |
1695 | UINT f_uimm24; | |
1696 | ||
1697 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); | |
1698 | f_uimm24 = EXTRACT_MSB0_UINT (insn, 32, 8, 24); | |
1699 | ||
1700 | /* Record the fields for the semantic handler. */ | |
1701 | FLD (f_r1) = f_r1; | |
1702 | FLD (i_uimm24) = f_uimm24; | |
1703 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
1704 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld24", "f_r1 0x%x", 'x', f_r1, "uimm24 0x%x", 'x', f_uimm24, "dr 0x%x", 'x', f_r1, (char *) 0)); | |
1705 | ||
1706 | #if WITH_PROFILE_MODEL_P | |
1707 | /* Record the fields for profiling. */ | |
1708 | if (PROFILE_MODEL_P (current_cpu)) | |
1709 | { | |
1710 | FLD (out_dr) = f_r1; | |
1711 | } | |
1712 | #endif | |
1713 | #undef FLD | |
1714 | return idesc; | |
1715 | } | |
1716 | ||
1717 | extract_sfmt_ldi8: | |
1718 | { | |
1719 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 1720 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
1721 | #define FLD(f) abuf->fields.sfmt_addi.f |
1722 | UINT f_r1; | |
1723 | INT f_simm8; | |
1724 | ||
1725 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
62836bf4 | 1726 | f_simm8 = EXTRACT_MSB0_SINT (insn, 16, 8, 8); |
16b47b25 NC |
1727 | |
1728 | /* Record the fields for the semantic handler. */ | |
1729 | FLD (f_simm8) = f_simm8; | |
1730 | FLD (f_r1) = f_r1; | |
1731 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
1732 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldi8", "f_simm8 0x%x", 'x', f_simm8, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0)); | |
1733 | ||
1734 | #if WITH_PROFILE_MODEL_P | |
1735 | /* Record the fields for profiling. */ | |
1736 | if (PROFILE_MODEL_P (current_cpu)) | |
1737 | { | |
1738 | FLD (out_dr) = f_r1; | |
1739 | } | |
1740 | #endif | |
1741 | #undef FLD | |
1742 | return idesc; | |
1743 | } | |
1744 | ||
1745 | extract_sfmt_ldi16: | |
1746 | { | |
1747 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 1748 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
1749 | #define FLD(f) abuf->fields.sfmt_add3.f |
1750 | UINT f_r1; | |
1751 | INT f_simm16; | |
1752 | ||
1753 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); | |
62836bf4 | 1754 | f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); |
16b47b25 NC |
1755 | |
1756 | /* Record the fields for the semantic handler. */ | |
1757 | FLD (f_simm16) = f_simm16; | |
1758 | FLD (f_r1) = f_r1; | |
1759 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
1760 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldi16", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0)); | |
1761 | ||
1762 | #if WITH_PROFILE_MODEL_P | |
1763 | /* Record the fields for profiling. */ | |
1764 | if (PROFILE_MODEL_P (current_cpu)) | |
1765 | { | |
1766 | FLD (out_dr) = f_r1; | |
1767 | } | |
1768 | #endif | |
1769 | #undef FLD | |
1770 | return idesc; | |
1771 | } | |
1772 | ||
1773 | extract_sfmt_lock: | |
1774 | { | |
1775 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 1776 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
1777 | #define FLD(f) abuf->fields.sfmt_ld_plus.f |
1778 | UINT f_r1; | |
1779 | UINT f_r2; | |
1780 | ||
1781 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
1782 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
1783 | ||
1784 | /* Record the fields for the semantic handler. */ | |
1785 | FLD (f_r2) = f_r2; | |
1786 | FLD (f_r1) = f_r1; | |
1787 | FLD (i_sr) = & CPU (h_gr)[f_r2]; | |
1788 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
1789 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lock", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); | |
1790 | ||
1791 | #if WITH_PROFILE_MODEL_P | |
1792 | /* Record the fields for profiling. */ | |
1793 | if (PROFILE_MODEL_P (current_cpu)) | |
1794 | { | |
1795 | FLD (in_sr) = f_r2; | |
1796 | FLD (out_dr) = f_r1; | |
1797 | } | |
1798 | #endif | |
1799 | #undef FLD | |
1800 | return idesc; | |
1801 | } | |
1802 | ||
1803 | extract_sfmt_machi_a: | |
1804 | { | |
1805 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 1806 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
1807 | #define FLD(f) abuf->fields.sfmt_machi_a.f |
1808 | UINT f_r1; | |
1809 | UINT f_acc; | |
1810 | UINT f_r2; | |
1811 | ||
1812 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
1813 | f_acc = EXTRACT_MSB0_UINT (insn, 16, 8, 1); | |
1814 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
1815 | ||
1816 | /* Record the fields for the semantic handler. */ | |
1817 | FLD (f_acc) = f_acc; | |
1818 | FLD (f_r1) = f_r1; | |
1819 | FLD (f_r2) = f_r2; | |
1820 | FLD (i_src1) = & CPU (h_gr)[f_r1]; | |
1821 | FLD (i_src2) = & CPU (h_gr)[f_r2]; | |
1822 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_machi_a", "f_acc 0x%x", 'x', f_acc, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); | |
1823 | ||
1824 | #if WITH_PROFILE_MODEL_P | |
1825 | /* Record the fields for profiling. */ | |
1826 | if (PROFILE_MODEL_P (current_cpu)) | |
1827 | { | |
1828 | FLD (in_src1) = f_r1; | |
1829 | FLD (in_src2) = f_r2; | |
1830 | } | |
1831 | #endif | |
1832 | #undef FLD | |
1833 | return idesc; | |
1834 | } | |
1835 | ||
1836 | extract_sfmt_mulhi_a: | |
1837 | { | |
1838 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 1839 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
1840 | #define FLD(f) abuf->fields.sfmt_machi_a.f |
1841 | UINT f_r1; | |
1842 | UINT f_acc; | |
1843 | UINT f_r2; | |
1844 | ||
1845 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
1846 | f_acc = EXTRACT_MSB0_UINT (insn, 16, 8, 1); | |
1847 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
1848 | ||
1849 | /* Record the fields for the semantic handler. */ | |
1850 | FLD (f_r1) = f_r1; | |
1851 | FLD (f_r2) = f_r2; | |
1852 | FLD (f_acc) = f_acc; | |
1853 | FLD (i_src1) = & CPU (h_gr)[f_r1]; | |
1854 | FLD (i_src2) = & CPU (h_gr)[f_r2]; | |
1855 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mulhi_a", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "f_acc 0x%x", 'x', f_acc, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); | |
1856 | ||
1857 | #if WITH_PROFILE_MODEL_P | |
1858 | /* Record the fields for profiling. */ | |
1859 | if (PROFILE_MODEL_P (current_cpu)) | |
1860 | { | |
1861 | FLD (in_src1) = f_r1; | |
1862 | FLD (in_src2) = f_r2; | |
1863 | } | |
1864 | #endif | |
1865 | #undef FLD | |
1866 | return idesc; | |
1867 | } | |
1868 | ||
1869 | extract_sfmt_mv: | |
1870 | { | |
1871 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 1872 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
1873 | #define FLD(f) abuf->fields.sfmt_ld_plus.f |
1874 | UINT f_r1; | |
1875 | UINT f_r2; | |
1876 | ||
1877 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
1878 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
1879 | ||
1880 | /* Record the fields for the semantic handler. */ | |
1881 | FLD (f_r2) = f_r2; | |
1882 | FLD (f_r1) = f_r1; | |
1883 | FLD (i_sr) = & CPU (h_gr)[f_r2]; | |
1884 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
1885 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mv", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); | |
1886 | ||
1887 | #if WITH_PROFILE_MODEL_P | |
1888 | /* Record the fields for profiling. */ | |
1889 | if (PROFILE_MODEL_P (current_cpu)) | |
1890 | { | |
1891 | FLD (in_sr) = f_r2; | |
1892 | FLD (out_dr) = f_r1; | |
1893 | } | |
1894 | #endif | |
1895 | #undef FLD | |
1896 | return idesc; | |
1897 | } | |
1898 | ||
1899 | extract_sfmt_mvfachi_a: | |
1900 | { | |
1901 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 1902 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
1903 | #define FLD(f) abuf->fields.sfmt_mvfachi_a.f |
1904 | UINT f_r1; | |
1905 | UINT f_accs; | |
1906 | ||
1907 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
1908 | f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); | |
1909 | ||
1910 | /* Record the fields for the semantic handler. */ | |
1911 | FLD (f_accs) = f_accs; | |
1912 | FLD (f_r1) = f_r1; | |
1913 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
1914 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvfachi_a", "f_accs 0x%x", 'x', f_accs, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0)); | |
1915 | ||
1916 | #if WITH_PROFILE_MODEL_P | |
1917 | /* Record the fields for profiling. */ | |
1918 | if (PROFILE_MODEL_P (current_cpu)) | |
1919 | { | |
1920 | FLD (out_dr) = f_r1; | |
1921 | } | |
1922 | #endif | |
1923 | #undef FLD | |
1924 | return idesc; | |
1925 | } | |
1926 | ||
1927 | extract_sfmt_mvfc: | |
1928 | { | |
1929 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 1930 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
1931 | #define FLD(f) abuf->fields.sfmt_ld_plus.f |
1932 | UINT f_r1; | |
1933 | UINT f_r2; | |
1934 | ||
1935 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
1936 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
1937 | ||
1938 | /* Record the fields for the semantic handler. */ | |
1939 | FLD (f_r2) = f_r2; | |
1940 | FLD (f_r1) = f_r1; | |
1941 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
1942 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvfc", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0)); | |
1943 | ||
1944 | #if WITH_PROFILE_MODEL_P | |
1945 | /* Record the fields for profiling. */ | |
1946 | if (PROFILE_MODEL_P (current_cpu)) | |
1947 | { | |
1948 | FLD (out_dr) = f_r1; | |
1949 | } | |
1950 | #endif | |
1951 | #undef FLD | |
1952 | return idesc; | |
1953 | } | |
1954 | ||
1955 | extract_sfmt_mvtachi_a: | |
1956 | { | |
1957 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 1958 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
1959 | #define FLD(f) abuf->fields.sfmt_mvtachi_a.f |
1960 | UINT f_r1; | |
1961 | UINT f_accs; | |
1962 | ||
1963 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
1964 | f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); | |
1965 | ||
1966 | /* Record the fields for the semantic handler. */ | |
1967 | FLD (f_accs) = f_accs; | |
1968 | FLD (f_r1) = f_r1; | |
1969 | FLD (i_src1) = & CPU (h_gr)[f_r1]; | |
1970 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvtachi_a", "f_accs 0x%x", 'x', f_accs, "f_r1 0x%x", 'x', f_r1, "src1 0x%x", 'x', f_r1, (char *) 0)); | |
1971 | ||
1972 | #if WITH_PROFILE_MODEL_P | |
1973 | /* Record the fields for profiling. */ | |
1974 | if (PROFILE_MODEL_P (current_cpu)) | |
1975 | { | |
1976 | FLD (in_src1) = f_r1; | |
1977 | } | |
1978 | #endif | |
1979 | #undef FLD | |
1980 | return idesc; | |
1981 | } | |
1982 | ||
1983 | extract_sfmt_mvtc: | |
1984 | { | |
1985 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 1986 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
1987 | #define FLD(f) abuf->fields.sfmt_ld_plus.f |
1988 | UINT f_r1; | |
1989 | UINT f_r2; | |
1990 | ||
1991 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
1992 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
1993 | ||
1994 | /* Record the fields for the semantic handler. */ | |
1995 | FLD (f_r2) = f_r2; | |
1996 | FLD (f_r1) = f_r1; | |
1997 | FLD (i_sr) = & CPU (h_gr)[f_r2]; | |
1998 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvtc", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0)); | |
1999 | ||
2000 | #if WITH_PROFILE_MODEL_P | |
2001 | /* Record the fields for profiling. */ | |
2002 | if (PROFILE_MODEL_P (current_cpu)) | |
2003 | { | |
2004 | FLD (in_sr) = f_r2; | |
2005 | } | |
2006 | #endif | |
2007 | #undef FLD | |
2008 | return idesc; | |
2009 | } | |
2010 | ||
2011 | extract_sfmt_nop: | |
2012 | { | |
2013 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
2310652a | 2014 | #define FLD(f) abuf->fields.sfmt_empty.f |
16b47b25 NC |
2015 | |
2016 | ||
2017 | /* Record the fields for the semantic handler. */ | |
2018 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nop", (char *) 0)); | |
2019 | ||
2020 | #undef FLD | |
2021 | return idesc; | |
2022 | } | |
2023 | ||
2024 | extract_sfmt_rac_dsi: | |
2025 | { | |
2026 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 2027 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
2028 | #define FLD(f) abuf->fields.sfmt_rac_dsi.f |
2029 | UINT f_accd; | |
2030 | UINT f_accs; | |
2031 | SI f_imm1; | |
2032 | ||
2033 | f_accd = EXTRACT_MSB0_UINT (insn, 16, 4, 2); | |
2034 | f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); | |
2035 | f_imm1 = ((EXTRACT_MSB0_UINT (insn, 16, 15, 1)) + (1)); | |
2036 | ||
2037 | /* Record the fields for the semantic handler. */ | |
2038 | FLD (f_accs) = f_accs; | |
2039 | FLD (f_imm1) = f_imm1; | |
2040 | FLD (f_accd) = f_accd; | |
2041 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rac_dsi", "f_accs 0x%x", 'x', f_accs, "f_imm1 0x%x", 'x', f_imm1, "f_accd 0x%x", 'x', f_accd, (char *) 0)); | |
2042 | ||
2043 | #undef FLD | |
2044 | return idesc; | |
2045 | } | |
2046 | ||
2047 | extract_sfmt_rte: | |
2048 | { | |
2049 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
2310652a | 2050 | #define FLD(f) abuf->fields.sfmt_empty.f |
16b47b25 NC |
2051 | |
2052 | ||
2053 | /* Record the fields for the semantic handler. */ | |
2054 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rte", (char *) 0)); | |
2055 | ||
2056 | #if WITH_PROFILE_MODEL_P | |
2057 | /* Record the fields for profiling. */ | |
2058 | if (PROFILE_MODEL_P (current_cpu)) | |
2059 | { | |
2060 | } | |
2061 | #endif | |
2062 | #undef FLD | |
2063 | return idesc; | |
2064 | } | |
2065 | ||
2066 | extract_sfmt_seth: | |
2067 | { | |
2068 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 2069 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
2070 | #define FLD(f) abuf->fields.sfmt_seth.f |
2071 | UINT f_r1; | |
2072 | UINT f_hi16; | |
2073 | ||
2074 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); | |
2075 | f_hi16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); | |
2076 | ||
2077 | /* Record the fields for the semantic handler. */ | |
2078 | FLD (f_hi16) = f_hi16; | |
2079 | FLD (f_r1) = f_r1; | |
2080 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
2081 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_seth", "f_hi16 0x%x", 'x', f_hi16, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0)); | |
2082 | ||
2083 | #if WITH_PROFILE_MODEL_P | |
2084 | /* Record the fields for profiling. */ | |
2085 | if (PROFILE_MODEL_P (current_cpu)) | |
2086 | { | |
2087 | FLD (out_dr) = f_r1; | |
2088 | } | |
2089 | #endif | |
2090 | #undef FLD | |
2091 | return idesc; | |
2092 | } | |
2093 | ||
2094 | extract_sfmt_sll3: | |
2095 | { | |
2096 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 2097 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
2098 | #define FLD(f) abuf->fields.sfmt_add3.f |
2099 | UINT f_r1; | |
2100 | UINT f_r2; | |
2101 | INT f_simm16; | |
2102 | ||
2103 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); | |
2104 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); | |
62836bf4 | 2105 | f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); |
16b47b25 NC |
2106 | |
2107 | /* Record the fields for the semantic handler. */ | |
2108 | FLD (f_simm16) = f_simm16; | |
2109 | FLD (f_r2) = f_r2; | |
2110 | FLD (f_r1) = f_r1; | |
2111 | FLD (i_sr) = & CPU (h_gr)[f_r2]; | |
2112 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
2113 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sll3", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); | |
2114 | ||
2115 | #if WITH_PROFILE_MODEL_P | |
2116 | /* Record the fields for profiling. */ | |
2117 | if (PROFILE_MODEL_P (current_cpu)) | |
2118 | { | |
2119 | FLD (in_sr) = f_r2; | |
2120 | FLD (out_dr) = f_r1; | |
2121 | } | |
2122 | #endif | |
2123 | #undef FLD | |
2124 | return idesc; | |
2125 | } | |
2126 | ||
2127 | extract_sfmt_slli: | |
2128 | { | |
2129 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 2130 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
2131 | #define FLD(f) abuf->fields.sfmt_slli.f |
2132 | UINT f_r1; | |
2133 | UINT f_uimm5; | |
2134 | ||
2135 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
2136 | f_uimm5 = EXTRACT_MSB0_UINT (insn, 16, 11, 5); | |
2137 | ||
2138 | /* Record the fields for the semantic handler. */ | |
2139 | FLD (f_r1) = f_r1; | |
2140 | FLD (f_uimm5) = f_uimm5; | |
2141 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
2142 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_slli", "f_r1 0x%x", 'x', f_r1, "f_uimm5 0x%x", 'x', f_uimm5, "dr 0x%x", 'x', f_r1, (char *) 0)); | |
2143 | ||
2144 | #if WITH_PROFILE_MODEL_P | |
2145 | /* Record the fields for profiling. */ | |
2146 | if (PROFILE_MODEL_P (current_cpu)) | |
2147 | { | |
2148 | FLD (in_dr) = f_r1; | |
2149 | FLD (out_dr) = f_r1; | |
2150 | } | |
2151 | #endif | |
2152 | #undef FLD | |
2153 | return idesc; | |
2154 | } | |
2155 | ||
2156 | extract_sfmt_st: | |
2157 | { | |
2158 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 2159 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
2160 | #define FLD(f) abuf->fields.sfmt_st_plus.f |
2161 | UINT f_r1; | |
2162 | UINT f_r2; | |
2163 | ||
2164 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
2165 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
2166 | ||
2167 | /* Record the fields for the semantic handler. */ | |
2168 | FLD (f_r1) = f_r1; | |
2169 | FLD (f_r2) = f_r2; | |
2170 | FLD (i_src1) = & CPU (h_gr)[f_r1]; | |
2171 | FLD (i_src2) = & CPU (h_gr)[f_r2]; | |
2172 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); | |
2173 | ||
2174 | #if WITH_PROFILE_MODEL_P | |
2175 | /* Record the fields for profiling. */ | |
2176 | if (PROFILE_MODEL_P (current_cpu)) | |
2177 | { | |
2178 | FLD (in_src1) = f_r1; | |
2179 | FLD (in_src2) = f_r2; | |
2180 | } | |
2181 | #endif | |
2182 | #undef FLD | |
2183 | return idesc; | |
2184 | } | |
2185 | ||
2186 | extract_sfmt_st_d: | |
2187 | { | |
2188 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 2189 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
2190 | #define FLD(f) abuf->fields.sfmt_st_d.f |
2191 | UINT f_r1; | |
2192 | UINT f_r2; | |
2193 | INT f_simm16; | |
2194 | ||
2195 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); | |
2196 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); | |
62836bf4 | 2197 | f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); |
16b47b25 NC |
2198 | |
2199 | /* Record the fields for the semantic handler. */ | |
2200 | FLD (f_simm16) = f_simm16; | |
2201 | FLD (f_r1) = f_r1; | |
2202 | FLD (f_r2) = f_r2; | |
2203 | FLD (i_src1) = & CPU (h_gr)[f_r1]; | |
2204 | FLD (i_src2) = & CPU (h_gr)[f_r2]; | |
2205 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st_d", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); | |
2206 | ||
2207 | #if WITH_PROFILE_MODEL_P | |
2208 | /* Record the fields for profiling. */ | |
2209 | if (PROFILE_MODEL_P (current_cpu)) | |
2210 | { | |
2211 | FLD (in_src1) = f_r1; | |
2212 | FLD (in_src2) = f_r2; | |
2213 | } | |
2214 | #endif | |
2215 | #undef FLD | |
2216 | return idesc; | |
2217 | } | |
2218 | ||
2219 | extract_sfmt_stb: | |
2220 | { | |
2221 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 2222 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
2223 | #define FLD(f) abuf->fields.sfmt_st_plus.f |
2224 | UINT f_r1; | |
2225 | UINT f_r2; | |
2226 | ||
2227 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
2228 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
2229 | ||
2230 | /* Record the fields for the semantic handler. */ | |
2231 | FLD (f_r1) = f_r1; | |
2232 | FLD (f_r2) = f_r2; | |
2233 | FLD (i_src1) = & CPU (h_gr)[f_r1]; | |
2234 | FLD (i_src2) = & CPU (h_gr)[f_r2]; | |
2235 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); | |
2236 | ||
2237 | #if WITH_PROFILE_MODEL_P | |
2238 | /* Record the fields for profiling. */ | |
2239 | if (PROFILE_MODEL_P (current_cpu)) | |
2240 | { | |
2241 | FLD (in_src1) = f_r1; | |
2242 | FLD (in_src2) = f_r2; | |
2243 | } | |
2244 | #endif | |
2245 | #undef FLD | |
2246 | return idesc; | |
2247 | } | |
2248 | ||
2249 | extract_sfmt_stb_d: | |
2250 | { | |
2251 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 2252 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
2253 | #define FLD(f) abuf->fields.sfmt_st_d.f |
2254 | UINT f_r1; | |
2255 | UINT f_r2; | |
2256 | INT f_simm16; | |
2257 | ||
2258 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); | |
2259 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); | |
62836bf4 | 2260 | f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); |
16b47b25 NC |
2261 | |
2262 | /* Record the fields for the semantic handler. */ | |
2263 | FLD (f_simm16) = f_simm16; | |
2264 | FLD (f_r1) = f_r1; | |
2265 | FLD (f_r2) = f_r2; | |
2266 | FLD (i_src1) = & CPU (h_gr)[f_r1]; | |
2267 | FLD (i_src2) = & CPU (h_gr)[f_r2]; | |
2268 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb_d", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); | |
2269 | ||
2270 | #if WITH_PROFILE_MODEL_P | |
2271 | /* Record the fields for profiling. */ | |
2272 | if (PROFILE_MODEL_P (current_cpu)) | |
2273 | { | |
2274 | FLD (in_src1) = f_r1; | |
2275 | FLD (in_src2) = f_r2; | |
2276 | } | |
2277 | #endif | |
2278 | #undef FLD | |
2279 | return idesc; | |
2280 | } | |
2281 | ||
2282 | extract_sfmt_sth: | |
2283 | { | |
2284 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 2285 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
2286 | #define FLD(f) abuf->fields.sfmt_st_plus.f |
2287 | UINT f_r1; | |
2288 | UINT f_r2; | |
2289 | ||
2290 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
2291 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
2292 | ||
2293 | /* Record the fields for the semantic handler. */ | |
2294 | FLD (f_r1) = f_r1; | |
2295 | FLD (f_r2) = f_r2; | |
2296 | FLD (i_src1) = & CPU (h_gr)[f_r1]; | |
2297 | FLD (i_src2) = & CPU (h_gr)[f_r2]; | |
2298 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sth", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); | |
2299 | ||
2300 | #if WITH_PROFILE_MODEL_P | |
2301 | /* Record the fields for profiling. */ | |
2302 | if (PROFILE_MODEL_P (current_cpu)) | |
2303 | { | |
2304 | FLD (in_src1) = f_r1; | |
2305 | FLD (in_src2) = f_r2; | |
2306 | } | |
2307 | #endif | |
2308 | #undef FLD | |
2309 | return idesc; | |
2310 | } | |
2311 | ||
2312 | extract_sfmt_sth_d: | |
2313 | { | |
2314 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 2315 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
2316 | #define FLD(f) abuf->fields.sfmt_st_d.f |
2317 | UINT f_r1; | |
2318 | UINT f_r2; | |
2319 | INT f_simm16; | |
2320 | ||
2321 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); | |
2322 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); | |
62836bf4 | 2323 | f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); |
16b47b25 NC |
2324 | |
2325 | /* Record the fields for the semantic handler. */ | |
2326 | FLD (f_simm16) = f_simm16; | |
2327 | FLD (f_r1) = f_r1; | |
2328 | FLD (f_r2) = f_r2; | |
2329 | FLD (i_src1) = & CPU (h_gr)[f_r1]; | |
2330 | FLD (i_src2) = & CPU (h_gr)[f_r2]; | |
2331 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sth_d", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); | |
2332 | ||
2333 | #if WITH_PROFILE_MODEL_P | |
2334 | /* Record the fields for profiling. */ | |
2335 | if (PROFILE_MODEL_P (current_cpu)) | |
2336 | { | |
2337 | FLD (in_src1) = f_r1; | |
2338 | FLD (in_src2) = f_r2; | |
2339 | } | |
2340 | #endif | |
2341 | #undef FLD | |
2342 | return idesc; | |
2343 | } | |
2344 | ||
2345 | extract_sfmt_st_plus: | |
2346 | { | |
2347 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 2348 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
2349 | #define FLD(f) abuf->fields.sfmt_st_plus.f |
2350 | UINT f_r1; | |
2351 | UINT f_r2; | |
2352 | ||
2353 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
2354 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
2355 | ||
2356 | /* Record the fields for the semantic handler. */ | |
2357 | FLD (f_r1) = f_r1; | |
2358 | FLD (f_r2) = f_r2; | |
2359 | FLD (i_src1) = & CPU (h_gr)[f_r1]; | |
2360 | FLD (i_src2) = & CPU (h_gr)[f_r2]; | |
2361 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st_plus", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); | |
2362 | ||
2363 | #if WITH_PROFILE_MODEL_P | |
2364 | /* Record the fields for profiling. */ | |
2365 | if (PROFILE_MODEL_P (current_cpu)) | |
2366 | { | |
2367 | FLD (in_src1) = f_r1; | |
2368 | FLD (in_src2) = f_r2; | |
2369 | FLD (out_src2) = f_r2; | |
2370 | } | |
2371 | #endif | |
2372 | #undef FLD | |
2373 | return idesc; | |
2374 | } | |
2375 | ||
2376 | extract_sfmt_sth_plus: | |
2377 | { | |
2378 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 2379 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
2380 | #define FLD(f) abuf->fields.sfmt_st_plus.f |
2381 | UINT f_r1; | |
2382 | UINT f_r2; | |
2383 | ||
2384 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
2385 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
2386 | ||
2387 | /* Record the fields for the semantic handler. */ | |
2388 | FLD (f_r1) = f_r1; | |
2389 | FLD (f_r2) = f_r2; | |
2390 | FLD (i_src1) = & CPU (h_gr)[f_r1]; | |
2391 | FLD (i_src2) = & CPU (h_gr)[f_r2]; | |
2392 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sth_plus", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); | |
2393 | ||
2394 | #if WITH_PROFILE_MODEL_P | |
2395 | /* Record the fields for profiling. */ | |
2396 | if (PROFILE_MODEL_P (current_cpu)) | |
2397 | { | |
2398 | FLD (in_src1) = f_r1; | |
2399 | FLD (in_src2) = f_r2; | |
2400 | FLD (out_src2) = f_r2; | |
2401 | } | |
2402 | #endif | |
2403 | #undef FLD | |
2404 | return idesc; | |
2405 | } | |
2406 | ||
2407 | extract_sfmt_stb_plus: | |
2408 | { | |
2409 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 2410 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
2411 | #define FLD(f) abuf->fields.sfmt_st_plus.f |
2412 | UINT f_r1; | |
2413 | UINT f_r2; | |
2414 | ||
2415 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
2416 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
2417 | ||
2418 | /* Record the fields for the semantic handler. */ | |
2419 | FLD (f_r1) = f_r1; | |
2420 | FLD (f_r2) = f_r2; | |
2421 | FLD (i_src1) = & CPU (h_gr)[f_r1]; | |
2422 | FLD (i_src2) = & CPU (h_gr)[f_r2]; | |
2423 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb_plus", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); | |
2424 | ||
2425 | #if WITH_PROFILE_MODEL_P | |
2426 | /* Record the fields for profiling. */ | |
2427 | if (PROFILE_MODEL_P (current_cpu)) | |
2428 | { | |
2429 | FLD (in_src1) = f_r1; | |
2430 | FLD (in_src2) = f_r2; | |
2431 | FLD (out_src2) = f_r2; | |
2432 | } | |
2433 | #endif | |
2434 | #undef FLD | |
2435 | return idesc; | |
2436 | } | |
2437 | ||
2438 | extract_sfmt_trap: | |
2439 | { | |
2440 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 2441 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
2442 | #define FLD(f) abuf->fields.sfmt_trap.f |
2443 | UINT f_uimm4; | |
2444 | ||
2445 | f_uimm4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
2446 | ||
2447 | /* Record the fields for the semantic handler. */ | |
2448 | FLD (f_uimm4) = f_uimm4; | |
2449 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_trap", "f_uimm4 0x%x", 'x', f_uimm4, (char *) 0)); | |
2450 | ||
2451 | #if WITH_PROFILE_MODEL_P | |
2452 | /* Record the fields for profiling. */ | |
2453 | if (PROFILE_MODEL_P (current_cpu)) | |
2454 | { | |
2455 | } | |
2456 | #endif | |
2457 | #undef FLD | |
2458 | return idesc; | |
2459 | } | |
2460 | ||
2461 | extract_sfmt_unlock: | |
2462 | { | |
2463 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 2464 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
2465 | #define FLD(f) abuf->fields.sfmt_st_plus.f |
2466 | UINT f_r1; | |
2467 | UINT f_r2; | |
2468 | ||
2469 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
2470 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
2471 | ||
2472 | /* Record the fields for the semantic handler. */ | |
2473 | FLD (f_r1) = f_r1; | |
2474 | FLD (f_r2) = f_r2; | |
2475 | FLD (i_src1) = & CPU (h_gr)[f_r1]; | |
2476 | FLD (i_src2) = & CPU (h_gr)[f_r2]; | |
2477 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_unlock", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); | |
2478 | ||
2479 | #if WITH_PROFILE_MODEL_P | |
2480 | /* Record the fields for profiling. */ | |
2481 | if (PROFILE_MODEL_P (current_cpu)) | |
2482 | { | |
2483 | FLD (in_src1) = f_r1; | |
2484 | FLD (in_src2) = f_r2; | |
2485 | } | |
2486 | #endif | |
2487 | #undef FLD | |
2488 | return idesc; | |
2489 | } | |
2490 | ||
2491 | extract_sfmt_satb: | |
2492 | { | |
2493 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 2494 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
2495 | #define FLD(f) abuf->fields.sfmt_ld_plus.f |
2496 | UINT f_r1; | |
2497 | UINT f_r2; | |
2498 | ||
2499 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); | |
2500 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); | |
2501 | ||
2502 | /* Record the fields for the semantic handler. */ | |
2503 | FLD (f_r2) = f_r2; | |
2504 | FLD (f_r1) = f_r1; | |
2505 | FLD (i_sr) = & CPU (h_gr)[f_r2]; | |
2506 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
2507 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_satb", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); | |
2508 | ||
2509 | #if WITH_PROFILE_MODEL_P | |
2510 | /* Record the fields for profiling. */ | |
2511 | if (PROFILE_MODEL_P (current_cpu)) | |
2512 | { | |
2513 | FLD (in_sr) = f_r2; | |
2514 | FLD (out_dr) = f_r1; | |
2515 | } | |
2516 | #endif | |
2517 | #undef FLD | |
2518 | return idesc; | |
2519 | } | |
2520 | ||
2521 | extract_sfmt_sat: | |
2522 | { | |
2523 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 2524 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
2525 | #define FLD(f) abuf->fields.sfmt_ld_plus.f |
2526 | UINT f_r1; | |
2527 | UINT f_r2; | |
2528 | ||
2529 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); | |
2530 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); | |
2531 | ||
2532 | /* Record the fields for the semantic handler. */ | |
2533 | FLD (f_r2) = f_r2; | |
2534 | FLD (f_r1) = f_r1; | |
2535 | FLD (i_sr) = & CPU (h_gr)[f_r2]; | |
2536 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
2537 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sat", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); | |
2538 | ||
2539 | #if WITH_PROFILE_MODEL_P | |
2540 | /* Record the fields for profiling. */ | |
2541 | if (PROFILE_MODEL_P (current_cpu)) | |
2542 | { | |
2543 | FLD (in_sr) = f_r2; | |
2544 | FLD (out_dr) = f_r1; | |
2545 | } | |
2546 | #endif | |
2547 | #undef FLD | |
2548 | return idesc; | |
2549 | } | |
2550 | ||
2551 | extract_sfmt_sadd: | |
2552 | { | |
2553 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
2310652a | 2554 | #define FLD(f) abuf->fields.sfmt_empty.f |
16b47b25 NC |
2555 | |
2556 | ||
2557 | /* Record the fields for the semantic handler. */ | |
2558 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sadd", (char *) 0)); | |
2559 | ||
2560 | #undef FLD | |
2561 | return idesc; | |
2562 | } | |
2563 | ||
2564 | extract_sfmt_macwu1: | |
2565 | { | |
2566 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 2567 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
2568 | #define FLD(f) abuf->fields.sfmt_st_plus.f |
2569 | UINT f_r1; | |
2570 | UINT f_r2; | |
2571 | ||
2572 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
2573 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
2574 | ||
2575 | /* Record the fields for the semantic handler. */ | |
2576 | FLD (f_r1) = f_r1; | |
2577 | FLD (f_r2) = f_r2; | |
2578 | FLD (i_src1) = & CPU (h_gr)[f_r1]; | |
2579 | FLD (i_src2) = & CPU (h_gr)[f_r2]; | |
2580 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_macwu1", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); | |
2581 | ||
2582 | #if WITH_PROFILE_MODEL_P | |
2583 | /* Record the fields for profiling. */ | |
2584 | if (PROFILE_MODEL_P (current_cpu)) | |
2585 | { | |
2586 | FLD (in_src1) = f_r1; | |
2587 | FLD (in_src2) = f_r2; | |
2588 | } | |
2589 | #endif | |
2590 | #undef FLD | |
2591 | return idesc; | |
2592 | } | |
2593 | ||
2594 | extract_sfmt_msblo: | |
2595 | { | |
2596 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 2597 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
2598 | #define FLD(f) abuf->fields.sfmt_st_plus.f |
2599 | UINT f_r1; | |
2600 | UINT f_r2; | |
2601 | ||
2602 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
2603 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
2604 | ||
2605 | /* Record the fields for the semantic handler. */ | |
2606 | FLD (f_r1) = f_r1; | |
2607 | FLD (f_r2) = f_r2; | |
2608 | FLD (i_src1) = & CPU (h_gr)[f_r1]; | |
2609 | FLD (i_src2) = & CPU (h_gr)[f_r2]; | |
2610 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_msblo", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); | |
2611 | ||
2612 | #if WITH_PROFILE_MODEL_P | |
2613 | /* Record the fields for profiling. */ | |
2614 | if (PROFILE_MODEL_P (current_cpu)) | |
2615 | { | |
2616 | FLD (in_src1) = f_r1; | |
2617 | FLD (in_src2) = f_r2; | |
2618 | } | |
2619 | #endif | |
2620 | #undef FLD | |
2621 | return idesc; | |
2622 | } | |
2623 | ||
2624 | extract_sfmt_mulwu1: | |
2625 | { | |
2626 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 2627 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
2628 | #define FLD(f) abuf->fields.sfmt_st_plus.f |
2629 | UINT f_r1; | |
2630 | UINT f_r2; | |
2631 | ||
2632 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
2633 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
2634 | ||
2635 | /* Record the fields for the semantic handler. */ | |
2636 | FLD (f_r1) = f_r1; | |
2637 | FLD (f_r2) = f_r2; | |
2638 | FLD (i_src1) = & CPU (h_gr)[f_r1]; | |
2639 | FLD (i_src2) = & CPU (h_gr)[f_r2]; | |
2640 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mulwu1", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); | |
2641 | ||
2642 | #if WITH_PROFILE_MODEL_P | |
2643 | /* Record the fields for profiling. */ | |
2644 | if (PROFILE_MODEL_P (current_cpu)) | |
2645 | { | |
2646 | FLD (in_src1) = f_r1; | |
2647 | FLD (in_src2) = f_r2; | |
2648 | } | |
2649 | #endif | |
2650 | #undef FLD | |
2651 | return idesc; | |
2652 | } | |
2653 | ||
2654 | extract_sfmt_sc: | |
2655 | { | |
2656 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
2310652a | 2657 | #define FLD(f) abuf->fields.sfmt_empty.f |
16b47b25 NC |
2658 | |
2659 | ||
2660 | /* Record the fields for the semantic handler. */ | |
2661 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sc", (char *) 0)); | |
2662 | ||
2663 | #undef FLD | |
2664 | return idesc; | |
2665 | } | |
2666 | ||
2667 | extract_sfmt_clrpsw: | |
2668 | { | |
2669 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 2670 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
2671 | #define FLD(f) abuf->fields.sfmt_clrpsw.f |
2672 | UINT f_uimm8; | |
2673 | ||
2674 | f_uimm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); | |
2675 | ||
2676 | /* Record the fields for the semantic handler. */ | |
2677 | FLD (f_uimm8) = f_uimm8; | |
2678 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_clrpsw", "f_uimm8 0x%x", 'x', f_uimm8, (char *) 0)); | |
2679 | ||
2680 | #undef FLD | |
2681 | return idesc; | |
2682 | } | |
2683 | ||
2684 | extract_sfmt_setpsw: | |
2685 | { | |
2686 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 2687 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
2688 | #define FLD(f) abuf->fields.sfmt_clrpsw.f |
2689 | UINT f_uimm8; | |
2690 | ||
2691 | f_uimm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); | |
2692 | ||
2693 | /* Record the fields for the semantic handler. */ | |
2694 | FLD (f_uimm8) = f_uimm8; | |
2695 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_setpsw", "f_uimm8 0x%x", 'x', f_uimm8, (char *) 0)); | |
2696 | ||
2697 | #undef FLD | |
2698 | return idesc; | |
2699 | } | |
2700 | ||
2701 | extract_sfmt_bset: | |
2702 | { | |
2703 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 2704 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
2705 | #define FLD(f) abuf->fields.sfmt_bset.f |
2706 | UINT f_uimm3; | |
2707 | UINT f_r2; | |
2708 | INT f_simm16; | |
2709 | ||
2710 | f_uimm3 = EXTRACT_MSB0_UINT (insn, 32, 5, 3); | |
2711 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); | |
62836bf4 | 2712 | f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); |
16b47b25 NC |
2713 | |
2714 | /* Record the fields for the semantic handler. */ | |
2715 | FLD (f_simm16) = f_simm16; | |
2716 | FLD (f_r2) = f_r2; | |
2717 | FLD (f_uimm3) = f_uimm3; | |
2718 | FLD (i_sr) = & CPU (h_gr)[f_r2]; | |
2719 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bset", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_uimm3 0x%x", 'x', f_uimm3, "sr 0x%x", 'x', f_r2, (char *) 0)); | |
2720 | ||
2721 | #if WITH_PROFILE_MODEL_P | |
2722 | /* Record the fields for profiling. */ | |
2723 | if (PROFILE_MODEL_P (current_cpu)) | |
2724 | { | |
2725 | FLD (in_sr) = f_r2; | |
2726 | } | |
2727 | #endif | |
2728 | #undef FLD | |
2729 | return idesc; | |
2730 | } | |
2731 | ||
2732 | extract_sfmt_btst: | |
2733 | { | |
2734 | const IDESC *idesc = &m32r2f_insn_data[itype]; | |
197fa1aa | 2735 | CGEN_INSN_WORD insn = entire_insn; |
16b47b25 NC |
2736 | #define FLD(f) abuf->fields.sfmt_bset.f |
2737 | UINT f_uimm3; | |
2738 | UINT f_r2; | |
2739 | ||
2740 | f_uimm3 = EXTRACT_MSB0_UINT (insn, 16, 5, 3); | |
2741 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
2742 | ||
2743 | /* Record the fields for the semantic handler. */ | |
2744 | FLD (f_r2) = f_r2; | |
2745 | FLD (f_uimm3) = f_uimm3; | |
2746 | FLD (i_sr) = & CPU (h_gr)[f_r2]; | |
2747 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_btst", "f_r2 0x%x", 'x', f_r2, "f_uimm3 0x%x", 'x', f_uimm3, "sr 0x%x", 'x', f_r2, (char *) 0)); | |
2748 | ||
2749 | #if WITH_PROFILE_MODEL_P | |
2750 | /* Record the fields for profiling. */ | |
2751 | if (PROFILE_MODEL_P (current_cpu)) | |
2752 | { | |
2753 | FLD (in_sr) = f_r2; | |
2754 | } | |
2755 | #endif | |
2756 | #undef FLD | |
2757 | return idesc; | |
2758 | } | |
2759 | ||
2760 | } |