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2df3850c JM |
1 | /* Simulator instruction decoder for m32rxf. |
2 | ||
3 | THIS FILE IS MACHINE GENERATED WITH CGEN. | |
4 | ||
55552082 | 5 | Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc. |
2df3850c JM |
6 | |
7 | This file is part of the GNU Simulators. | |
8 | ||
9 | This program is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 2, or (at your option) | |
12 | any later version. | |
13 | ||
14 | This program is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License along | |
20 | with this program; if not, write to the Free Software Foundation, Inc., | |
21 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
22 | ||
23 | */ | |
24 | ||
25 | #define WANT_CPU m32rxf | |
26 | #define WANT_CPU_M32RXF | |
27 | ||
28 | #include "sim-main.h" | |
29 | #include "sim-assert.h" | |
30 | ||
31 | /* Insn can't be executed in parallel. | |
32 | Or is that "do NOt Pass to Air defense Radar"? :-) */ | |
33 | #define NOPAR (-1) | |
34 | ||
35 | /* The instruction descriptor array. | |
36 | This is computed at runtime. Space for it is not malloc'd to save a | |
37 | teensy bit of cpu in the decoder. Moving it to malloc space is trivial | |
38 | but won't be done until necessary (we don't currently support the runtime | |
39 | addition of instructions nor an SMP machine with different cpus). */ | |
40 | static IDESC m32rxf_insn_data[M32RXF_INSN_MAX]; | |
41 | ||
42 | /* Commas between elements are contained in the macros. | |
43 | Some of these are conditionally compiled out. */ | |
44 | ||
45 | static const struct insn_sem m32rxf_insn_sem[] = | |
46 | { | |
47 | { VIRTUAL_INSN_X_INVALID, M32RXF_INSN_X_INVALID, M32RXF_SFMT_EMPTY, NOPAR, NOPAR }, | |
48 | { VIRTUAL_INSN_X_AFTER, M32RXF_INSN_X_AFTER, M32RXF_SFMT_EMPTY, NOPAR, NOPAR }, | |
49 | { VIRTUAL_INSN_X_BEFORE, M32RXF_INSN_X_BEFORE, M32RXF_SFMT_EMPTY, NOPAR, NOPAR }, | |
50 | { VIRTUAL_INSN_X_CTI_CHAIN, M32RXF_INSN_X_CTI_CHAIN, M32RXF_SFMT_EMPTY, NOPAR, NOPAR }, | |
51 | { VIRTUAL_INSN_X_CHAIN, M32RXF_INSN_X_CHAIN, M32RXF_SFMT_EMPTY, NOPAR, NOPAR }, | |
52 | { VIRTUAL_INSN_X_BEGIN, M32RXF_INSN_X_BEGIN, M32RXF_SFMT_EMPTY, NOPAR, NOPAR }, | |
53 | { M32R_INSN_ADD, M32RXF_INSN_ADD, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_ADD, M32RXF_INSN_WRITE_ADD }, | |
54 | { M32R_INSN_ADD3, M32RXF_INSN_ADD3, M32RXF_SFMT_ADD3, NOPAR, NOPAR }, | |
55 | { M32R_INSN_AND, M32RXF_INSN_AND, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_AND, M32RXF_INSN_WRITE_AND }, | |
56 | { M32R_INSN_AND3, M32RXF_INSN_AND3, M32RXF_SFMT_AND3, NOPAR, NOPAR }, | |
57 | { M32R_INSN_OR, M32RXF_INSN_OR, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_OR, M32RXF_INSN_WRITE_OR }, | |
58 | { M32R_INSN_OR3, M32RXF_INSN_OR3, M32RXF_SFMT_OR3, NOPAR, NOPAR }, | |
59 | { M32R_INSN_XOR, M32RXF_INSN_XOR, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_XOR, M32RXF_INSN_WRITE_XOR }, | |
60 | { M32R_INSN_XOR3, M32RXF_INSN_XOR3, M32RXF_SFMT_AND3, NOPAR, NOPAR }, | |
61 | { M32R_INSN_ADDI, M32RXF_INSN_ADDI, M32RXF_SFMT_ADDI, M32RXF_INSN_PAR_ADDI, M32RXF_INSN_WRITE_ADDI }, | |
62 | { M32R_INSN_ADDV, M32RXF_INSN_ADDV, M32RXF_SFMT_ADDV, M32RXF_INSN_PAR_ADDV, M32RXF_INSN_WRITE_ADDV }, | |
63 | { M32R_INSN_ADDV3, M32RXF_INSN_ADDV3, M32RXF_SFMT_ADDV3, NOPAR, NOPAR }, | |
64 | { M32R_INSN_ADDX, M32RXF_INSN_ADDX, M32RXF_SFMT_ADDX, M32RXF_INSN_PAR_ADDX, M32RXF_INSN_WRITE_ADDX }, | |
65 | { M32R_INSN_BC8, M32RXF_INSN_BC8, M32RXF_SFMT_BC8, M32RXF_INSN_PAR_BC8, M32RXF_INSN_WRITE_BC8 }, | |
66 | { M32R_INSN_BC24, M32RXF_INSN_BC24, M32RXF_SFMT_BC24, NOPAR, NOPAR }, | |
67 | { M32R_INSN_BEQ, M32RXF_INSN_BEQ, M32RXF_SFMT_BEQ, NOPAR, NOPAR }, | |
68 | { M32R_INSN_BEQZ, M32RXF_INSN_BEQZ, M32RXF_SFMT_BEQZ, NOPAR, NOPAR }, | |
69 | { M32R_INSN_BGEZ, M32RXF_INSN_BGEZ, M32RXF_SFMT_BEQZ, NOPAR, NOPAR }, | |
70 | { M32R_INSN_BGTZ, M32RXF_INSN_BGTZ, M32RXF_SFMT_BEQZ, NOPAR, NOPAR }, | |
71 | { M32R_INSN_BLEZ, M32RXF_INSN_BLEZ, M32RXF_SFMT_BEQZ, NOPAR, NOPAR }, | |
72 | { M32R_INSN_BLTZ, M32RXF_INSN_BLTZ, M32RXF_SFMT_BEQZ, NOPAR, NOPAR }, | |
73 | { M32R_INSN_BNEZ, M32RXF_INSN_BNEZ, M32RXF_SFMT_BEQZ, NOPAR, NOPAR }, | |
74 | { M32R_INSN_BL8, M32RXF_INSN_BL8, M32RXF_SFMT_BL8, M32RXF_INSN_PAR_BL8, M32RXF_INSN_WRITE_BL8 }, | |
75 | { M32R_INSN_BL24, M32RXF_INSN_BL24, M32RXF_SFMT_BL24, NOPAR, NOPAR }, | |
76 | { M32R_INSN_BCL8, M32RXF_INSN_BCL8, M32RXF_SFMT_BCL8, M32RXF_INSN_PAR_BCL8, M32RXF_INSN_WRITE_BCL8 }, | |
77 | { M32R_INSN_BCL24, M32RXF_INSN_BCL24, M32RXF_SFMT_BCL24, NOPAR, NOPAR }, | |
78 | { M32R_INSN_BNC8, M32RXF_INSN_BNC8, M32RXF_SFMT_BC8, M32RXF_INSN_PAR_BNC8, M32RXF_INSN_WRITE_BNC8 }, | |
79 | { M32R_INSN_BNC24, M32RXF_INSN_BNC24, M32RXF_SFMT_BC24, NOPAR, NOPAR }, | |
80 | { M32R_INSN_BNE, M32RXF_INSN_BNE, M32RXF_SFMT_BEQ, NOPAR, NOPAR }, | |
81 | { M32R_INSN_BRA8, M32RXF_INSN_BRA8, M32RXF_SFMT_BRA8, M32RXF_INSN_PAR_BRA8, M32RXF_INSN_WRITE_BRA8 }, | |
82 | { M32R_INSN_BRA24, M32RXF_INSN_BRA24, M32RXF_SFMT_BRA24, NOPAR, NOPAR }, | |
83 | { M32R_INSN_BNCL8, M32RXF_INSN_BNCL8, M32RXF_SFMT_BCL8, M32RXF_INSN_PAR_BNCL8, M32RXF_INSN_WRITE_BNCL8 }, | |
84 | { M32R_INSN_BNCL24, M32RXF_INSN_BNCL24, M32RXF_SFMT_BCL24, NOPAR, NOPAR }, | |
85 | { M32R_INSN_CMP, M32RXF_INSN_CMP, M32RXF_SFMT_CMP, M32RXF_INSN_PAR_CMP, M32RXF_INSN_WRITE_CMP }, | |
86 | { M32R_INSN_CMPI, M32RXF_INSN_CMPI, M32RXF_SFMT_CMPI, NOPAR, NOPAR }, | |
87 | { M32R_INSN_CMPU, M32RXF_INSN_CMPU, M32RXF_SFMT_CMP, M32RXF_INSN_PAR_CMPU, M32RXF_INSN_WRITE_CMPU }, | |
88 | { M32R_INSN_CMPUI, M32RXF_INSN_CMPUI, M32RXF_SFMT_CMPI, NOPAR, NOPAR }, | |
89 | { M32R_INSN_CMPEQ, M32RXF_INSN_CMPEQ, M32RXF_SFMT_CMP, M32RXF_INSN_PAR_CMPEQ, M32RXF_INSN_WRITE_CMPEQ }, | |
90 | { M32R_INSN_CMPZ, M32RXF_INSN_CMPZ, M32RXF_SFMT_CMPZ, M32RXF_INSN_PAR_CMPZ, M32RXF_INSN_WRITE_CMPZ }, | |
91 | { M32R_INSN_DIV, M32RXF_INSN_DIV, M32RXF_SFMT_DIV, NOPAR, NOPAR }, | |
92 | { M32R_INSN_DIVU, M32RXF_INSN_DIVU, M32RXF_SFMT_DIV, NOPAR, NOPAR }, | |
93 | { M32R_INSN_REM, M32RXF_INSN_REM, M32RXF_SFMT_DIV, NOPAR, NOPAR }, | |
94 | { M32R_INSN_REMU, M32RXF_INSN_REMU, M32RXF_SFMT_DIV, NOPAR, NOPAR }, | |
95 | { M32R_INSN_DIVH, M32RXF_INSN_DIVH, M32RXF_SFMT_DIV, NOPAR, NOPAR }, | |
96 | { M32R_INSN_JC, M32RXF_INSN_JC, M32RXF_SFMT_JC, M32RXF_INSN_PAR_JC, M32RXF_INSN_WRITE_JC }, | |
97 | { M32R_INSN_JNC, M32RXF_INSN_JNC, M32RXF_SFMT_JC, M32RXF_INSN_PAR_JNC, M32RXF_INSN_WRITE_JNC }, | |
98 | { M32R_INSN_JL, M32RXF_INSN_JL, M32RXF_SFMT_JL, M32RXF_INSN_PAR_JL, M32RXF_INSN_WRITE_JL }, | |
99 | { M32R_INSN_JMP, M32RXF_INSN_JMP, M32RXF_SFMT_JMP, M32RXF_INSN_PAR_JMP, M32RXF_INSN_WRITE_JMP }, | |
100 | { M32R_INSN_LD, M32RXF_INSN_LD, M32RXF_SFMT_LD, M32RXF_INSN_PAR_LD, M32RXF_INSN_WRITE_LD }, | |
101 | { M32R_INSN_LD_D, M32RXF_INSN_LD_D, M32RXF_SFMT_LD_D, NOPAR, NOPAR }, | |
102 | { M32R_INSN_LDB, M32RXF_INSN_LDB, M32RXF_SFMT_LD, M32RXF_INSN_PAR_LDB, M32RXF_INSN_WRITE_LDB }, | |
103 | { M32R_INSN_LDB_D, M32RXF_INSN_LDB_D, M32RXF_SFMT_LD_D, NOPAR, NOPAR }, | |
104 | { M32R_INSN_LDH, M32RXF_INSN_LDH, M32RXF_SFMT_LD, M32RXF_INSN_PAR_LDH, M32RXF_INSN_WRITE_LDH }, | |
105 | { M32R_INSN_LDH_D, M32RXF_INSN_LDH_D, M32RXF_SFMT_LD_D, NOPAR, NOPAR }, | |
106 | { M32R_INSN_LDUB, M32RXF_INSN_LDUB, M32RXF_SFMT_LD, M32RXF_INSN_PAR_LDUB, M32RXF_INSN_WRITE_LDUB }, | |
107 | { M32R_INSN_LDUB_D, M32RXF_INSN_LDUB_D, M32RXF_SFMT_LD_D, NOPAR, NOPAR }, | |
108 | { M32R_INSN_LDUH, M32RXF_INSN_LDUH, M32RXF_SFMT_LD, M32RXF_INSN_PAR_LDUH, M32RXF_INSN_WRITE_LDUH }, | |
109 | { M32R_INSN_LDUH_D, M32RXF_INSN_LDUH_D, M32RXF_SFMT_LD_D, NOPAR, NOPAR }, | |
110 | { M32R_INSN_LD_PLUS, M32RXF_INSN_LD_PLUS, M32RXF_SFMT_LD_PLUS, M32RXF_INSN_PAR_LD_PLUS, M32RXF_INSN_WRITE_LD_PLUS }, | |
111 | { M32R_INSN_LD24, M32RXF_INSN_LD24, M32RXF_SFMT_LD24, NOPAR, NOPAR }, | |
112 | { M32R_INSN_LDI8, M32RXF_INSN_LDI8, M32RXF_SFMT_LDI8, M32RXF_INSN_PAR_LDI8, M32RXF_INSN_WRITE_LDI8 }, | |
113 | { M32R_INSN_LDI16, M32RXF_INSN_LDI16, M32RXF_SFMT_LDI16, NOPAR, NOPAR }, | |
114 | { M32R_INSN_LOCK, M32RXF_INSN_LOCK, M32RXF_SFMT_LOCK, M32RXF_INSN_PAR_LOCK, M32RXF_INSN_WRITE_LOCK }, | |
115 | { M32R_INSN_MACHI_A, M32RXF_INSN_MACHI_A, M32RXF_SFMT_MACHI_A, M32RXF_INSN_PAR_MACHI_A, M32RXF_INSN_WRITE_MACHI_A }, | |
116 | { M32R_INSN_MACLO_A, M32RXF_INSN_MACLO_A, M32RXF_SFMT_MACHI_A, M32RXF_INSN_PAR_MACLO_A, M32RXF_INSN_WRITE_MACLO_A }, | |
117 | { M32R_INSN_MACWHI_A, M32RXF_INSN_MACWHI_A, M32RXF_SFMT_MACHI_A, M32RXF_INSN_PAR_MACWHI_A, M32RXF_INSN_WRITE_MACWHI_A }, | |
118 | { M32R_INSN_MACWLO_A, M32RXF_INSN_MACWLO_A, M32RXF_SFMT_MACHI_A, M32RXF_INSN_PAR_MACWLO_A, M32RXF_INSN_WRITE_MACWLO_A }, | |
119 | { M32R_INSN_MUL, M32RXF_INSN_MUL, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_MUL, M32RXF_INSN_WRITE_MUL }, | |
120 | { M32R_INSN_MULHI_A, M32RXF_INSN_MULHI_A, M32RXF_SFMT_MULHI_A, M32RXF_INSN_PAR_MULHI_A, M32RXF_INSN_WRITE_MULHI_A }, | |
121 | { M32R_INSN_MULLO_A, M32RXF_INSN_MULLO_A, M32RXF_SFMT_MULHI_A, M32RXF_INSN_PAR_MULLO_A, M32RXF_INSN_WRITE_MULLO_A }, | |
122 | { M32R_INSN_MULWHI_A, M32RXF_INSN_MULWHI_A, M32RXF_SFMT_MULHI_A, M32RXF_INSN_PAR_MULWHI_A, M32RXF_INSN_WRITE_MULWHI_A }, | |
123 | { M32R_INSN_MULWLO_A, M32RXF_INSN_MULWLO_A, M32RXF_SFMT_MULHI_A, M32RXF_INSN_PAR_MULWLO_A, M32RXF_INSN_WRITE_MULWLO_A }, | |
124 | { M32R_INSN_MV, M32RXF_INSN_MV, M32RXF_SFMT_MV, M32RXF_INSN_PAR_MV, M32RXF_INSN_WRITE_MV }, | |
125 | { M32R_INSN_MVFACHI_A, M32RXF_INSN_MVFACHI_A, M32RXF_SFMT_MVFACHI_A, M32RXF_INSN_PAR_MVFACHI_A, M32RXF_INSN_WRITE_MVFACHI_A }, | |
126 | { M32R_INSN_MVFACLO_A, M32RXF_INSN_MVFACLO_A, M32RXF_SFMT_MVFACHI_A, M32RXF_INSN_PAR_MVFACLO_A, M32RXF_INSN_WRITE_MVFACLO_A }, | |
127 | { M32R_INSN_MVFACMI_A, M32RXF_INSN_MVFACMI_A, M32RXF_SFMT_MVFACHI_A, M32RXF_INSN_PAR_MVFACMI_A, M32RXF_INSN_WRITE_MVFACMI_A }, | |
128 | { M32R_INSN_MVFC, M32RXF_INSN_MVFC, M32RXF_SFMT_MVFC, M32RXF_INSN_PAR_MVFC, M32RXF_INSN_WRITE_MVFC }, | |
129 | { M32R_INSN_MVTACHI_A, M32RXF_INSN_MVTACHI_A, M32RXF_SFMT_MVTACHI_A, M32RXF_INSN_PAR_MVTACHI_A, M32RXF_INSN_WRITE_MVTACHI_A }, | |
130 | { M32R_INSN_MVTACLO_A, M32RXF_INSN_MVTACLO_A, M32RXF_SFMT_MVTACHI_A, M32RXF_INSN_PAR_MVTACLO_A, M32RXF_INSN_WRITE_MVTACLO_A }, | |
131 | { M32R_INSN_MVTC, M32RXF_INSN_MVTC, M32RXF_SFMT_MVTC, M32RXF_INSN_PAR_MVTC, M32RXF_INSN_WRITE_MVTC }, | |
132 | { M32R_INSN_NEG, M32RXF_INSN_NEG, M32RXF_SFMT_MV, M32RXF_INSN_PAR_NEG, M32RXF_INSN_WRITE_NEG }, | |
133 | { M32R_INSN_NOP, M32RXF_INSN_NOP, M32RXF_SFMT_NOP, M32RXF_INSN_PAR_NOP, M32RXF_INSN_WRITE_NOP }, | |
134 | { M32R_INSN_NOT, M32RXF_INSN_NOT, M32RXF_SFMT_MV, M32RXF_INSN_PAR_NOT, M32RXF_INSN_WRITE_NOT }, | |
135 | { M32R_INSN_RAC_DSI, M32RXF_INSN_RAC_DSI, M32RXF_SFMT_RAC_DSI, M32RXF_INSN_PAR_RAC_DSI, M32RXF_INSN_WRITE_RAC_DSI }, | |
136 | { M32R_INSN_RACH_DSI, M32RXF_INSN_RACH_DSI, M32RXF_SFMT_RAC_DSI, M32RXF_INSN_PAR_RACH_DSI, M32RXF_INSN_WRITE_RACH_DSI }, | |
137 | { M32R_INSN_RTE, M32RXF_INSN_RTE, M32RXF_SFMT_RTE, M32RXF_INSN_PAR_RTE, M32RXF_INSN_WRITE_RTE }, | |
138 | { M32R_INSN_SETH, M32RXF_INSN_SETH, M32RXF_SFMT_SETH, NOPAR, NOPAR }, | |
139 | { M32R_INSN_SLL, M32RXF_INSN_SLL, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_SLL, M32RXF_INSN_WRITE_SLL }, | |
140 | { M32R_INSN_SLL3, M32RXF_INSN_SLL3, M32RXF_SFMT_SLL3, NOPAR, NOPAR }, | |
141 | { M32R_INSN_SLLI, M32RXF_INSN_SLLI, M32RXF_SFMT_SLLI, M32RXF_INSN_PAR_SLLI, M32RXF_INSN_WRITE_SLLI }, | |
142 | { M32R_INSN_SRA, M32RXF_INSN_SRA, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_SRA, M32RXF_INSN_WRITE_SRA }, | |
143 | { M32R_INSN_SRA3, M32RXF_INSN_SRA3, M32RXF_SFMT_SLL3, NOPAR, NOPAR }, | |
144 | { M32R_INSN_SRAI, M32RXF_INSN_SRAI, M32RXF_SFMT_SLLI, M32RXF_INSN_PAR_SRAI, M32RXF_INSN_WRITE_SRAI }, | |
145 | { M32R_INSN_SRL, M32RXF_INSN_SRL, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_SRL, M32RXF_INSN_WRITE_SRL }, | |
146 | { M32R_INSN_SRL3, M32RXF_INSN_SRL3, M32RXF_SFMT_SLL3, NOPAR, NOPAR }, | |
147 | { M32R_INSN_SRLI, M32RXF_INSN_SRLI, M32RXF_SFMT_SLLI, M32RXF_INSN_PAR_SRLI, M32RXF_INSN_WRITE_SRLI }, | |
148 | { M32R_INSN_ST, M32RXF_INSN_ST, M32RXF_SFMT_ST, M32RXF_INSN_PAR_ST, M32RXF_INSN_WRITE_ST }, | |
149 | { M32R_INSN_ST_D, M32RXF_INSN_ST_D, M32RXF_SFMT_ST_D, NOPAR, NOPAR }, | |
150 | { M32R_INSN_STB, M32RXF_INSN_STB, M32RXF_SFMT_STB, M32RXF_INSN_PAR_STB, M32RXF_INSN_WRITE_STB }, | |
151 | { M32R_INSN_STB_D, M32RXF_INSN_STB_D, M32RXF_SFMT_STB_D, NOPAR, NOPAR }, | |
152 | { M32R_INSN_STH, M32RXF_INSN_STH, M32RXF_SFMT_STH, M32RXF_INSN_PAR_STH, M32RXF_INSN_WRITE_STH }, | |
153 | { M32R_INSN_STH_D, M32RXF_INSN_STH_D, M32RXF_SFMT_STH_D, NOPAR, NOPAR }, | |
154 | { M32R_INSN_ST_PLUS, M32RXF_INSN_ST_PLUS, M32RXF_SFMT_ST_PLUS, M32RXF_INSN_PAR_ST_PLUS, M32RXF_INSN_WRITE_ST_PLUS }, | |
155 | { M32R_INSN_ST_MINUS, M32RXF_INSN_ST_MINUS, M32RXF_SFMT_ST_PLUS, M32RXF_INSN_PAR_ST_MINUS, M32RXF_INSN_WRITE_ST_MINUS }, | |
156 | { M32R_INSN_SUB, M32RXF_INSN_SUB, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_SUB, M32RXF_INSN_WRITE_SUB }, | |
157 | { M32R_INSN_SUBV, M32RXF_INSN_SUBV, M32RXF_SFMT_ADDV, M32RXF_INSN_PAR_SUBV, M32RXF_INSN_WRITE_SUBV }, | |
158 | { M32R_INSN_SUBX, M32RXF_INSN_SUBX, M32RXF_SFMT_ADDX, M32RXF_INSN_PAR_SUBX, M32RXF_INSN_WRITE_SUBX }, | |
159 | { M32R_INSN_TRAP, M32RXF_INSN_TRAP, M32RXF_SFMT_TRAP, M32RXF_INSN_PAR_TRAP, M32RXF_INSN_WRITE_TRAP }, | |
160 | { M32R_INSN_UNLOCK, M32RXF_INSN_UNLOCK, M32RXF_SFMT_UNLOCK, M32RXF_INSN_PAR_UNLOCK, M32RXF_INSN_WRITE_UNLOCK }, | |
161 | { M32R_INSN_SATB, M32RXF_INSN_SATB, M32RXF_SFMT_SATB, NOPAR, NOPAR }, | |
162 | { M32R_INSN_SATH, M32RXF_INSN_SATH, M32RXF_SFMT_SATB, NOPAR, NOPAR }, | |
163 | { M32R_INSN_SAT, M32RXF_INSN_SAT, M32RXF_SFMT_SAT, NOPAR, NOPAR }, | |
164 | { M32R_INSN_PCMPBZ, M32RXF_INSN_PCMPBZ, M32RXF_SFMT_CMPZ, M32RXF_INSN_PAR_PCMPBZ, M32RXF_INSN_WRITE_PCMPBZ }, | |
165 | { M32R_INSN_SADD, M32RXF_INSN_SADD, M32RXF_SFMT_SADD, M32RXF_INSN_PAR_SADD, M32RXF_INSN_WRITE_SADD }, | |
166 | { M32R_INSN_MACWU1, M32RXF_INSN_MACWU1, M32RXF_SFMT_MACWU1, M32RXF_INSN_PAR_MACWU1, M32RXF_INSN_WRITE_MACWU1 }, | |
167 | { M32R_INSN_MSBLO, M32RXF_INSN_MSBLO, M32RXF_SFMT_MSBLO, M32RXF_INSN_PAR_MSBLO, M32RXF_INSN_WRITE_MSBLO }, | |
168 | { M32R_INSN_MULWU1, M32RXF_INSN_MULWU1, M32RXF_SFMT_MULWU1, M32RXF_INSN_PAR_MULWU1, M32RXF_INSN_WRITE_MULWU1 }, | |
169 | { M32R_INSN_MACLH1, M32RXF_INSN_MACLH1, M32RXF_SFMT_MACWU1, M32RXF_INSN_PAR_MACLH1, M32RXF_INSN_WRITE_MACLH1 }, | |
170 | { M32R_INSN_SC, M32RXF_INSN_SC, M32RXF_SFMT_SC, M32RXF_INSN_PAR_SC, M32RXF_INSN_WRITE_SC }, | |
171 | { M32R_INSN_SNC, M32RXF_INSN_SNC, M32RXF_SFMT_SC, M32RXF_INSN_PAR_SNC, M32RXF_INSN_WRITE_SNC }, | |
172 | }; | |
173 | ||
174 | static const struct insn_sem m32rxf_insn_sem_invalid = { | |
175 | VIRTUAL_INSN_X_INVALID, M32RXF_INSN_X_INVALID, M32RXF_SFMT_EMPTY, NOPAR, NOPAR | |
176 | }; | |
177 | ||
178 | /* Initialize an IDESC from the compile-time computable parts. */ | |
179 | ||
180 | static INLINE void | |
181 | init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t) | |
182 | { | |
183 | const CGEN_INSN *insn_table = CGEN_CPU_INSN_TABLE (CPU_CPU_DESC (cpu))->init_entries; | |
184 | ||
185 | id->num = t->index; | |
186 | id->sfmt = t->sfmt; | |
187 | if ((int) t->type <= 0) | |
188 | id->idata = & cgen_virtual_insn_table[- (int) t->type]; | |
189 | else | |
190 | id->idata = & insn_table[t->type]; | |
191 | id->attrs = CGEN_INSN_ATTRS (id->idata); | |
192 | /* Oh my god, a magic number. */ | |
193 | id->length = CGEN_INSN_BITSIZE (id->idata) / 8; | |
194 | ||
195 | #if WITH_PROFILE_MODEL_P | |
196 | id->timing = & MODEL_TIMING (CPU_MODEL (cpu)) [t->index]; | |
197 | { | |
198 | SIM_DESC sd = CPU_STATE (cpu); | |
199 | SIM_ASSERT (t->index == id->timing->num); | |
200 | } | |
201 | #endif | |
202 | ||
203 | /* Semantic pointers are initialized elsewhere. */ | |
204 | } | |
205 | ||
206 | /* Initialize the instruction descriptor table. */ | |
207 | ||
208 | void | |
209 | m32rxf_init_idesc_table (SIM_CPU *cpu) | |
210 | { | |
211 | IDESC *id,*tabend; | |
212 | const struct insn_sem *t,*tend; | |
213 | int tabsize = M32RXF_INSN_MAX; | |
214 | IDESC *table = m32rxf_insn_data; | |
215 | ||
216 | memset (table, 0, tabsize * sizeof (IDESC)); | |
217 | ||
218 | /* First set all entries to the `invalid insn'. */ | |
219 | t = & m32rxf_insn_sem_invalid; | |
220 | for (id = table, tabend = table + tabsize; id < tabend; ++id) | |
221 | init_idesc (cpu, id, t); | |
222 | ||
223 | /* Now fill in the values for the chosen cpu. */ | |
224 | for (t = m32rxf_insn_sem, tend = t + sizeof (m32rxf_insn_sem) / sizeof (*t); | |
225 | t != tend; ++t) | |
226 | { | |
227 | init_idesc (cpu, & table[t->index], t); | |
228 | if (t->par_index != NOPAR) | |
229 | { | |
230 | init_idesc (cpu, &table[t->par_index], t); | |
231 | table[t->index].par_idesc = &table[t->par_index]; | |
232 | } | |
233 | if (t->par_index != NOPAR) | |
234 | { | |
235 | init_idesc (cpu, &table[t->write_index], t); | |
236 | table[t->par_index].par_idesc = &table[t->write_index]; | |
237 | } | |
238 | } | |
239 | ||
240 | /* Link the IDESC table into the cpu. */ | |
241 | CPU_IDESC (cpu) = table; | |
242 | } | |
243 | ||
244 | /* Given an instruction, return a pointer to its IDESC entry. */ | |
245 | ||
246 | const IDESC * | |
247 | m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, | |
248 | CGEN_INSN_INT base_insn, CGEN_INSN_INT entire_insn, | |
249 | ARGBUF *abuf) | |
250 | { | |
251 | /* Result of decoder. */ | |
252 | M32RXF_INSN_TYPE itype; | |
253 | ||
254 | { | |
255 | CGEN_INSN_INT insn = base_insn; | |
256 | ||
257 | { | |
258 | unsigned int val = (((insn >> 8) & (15 << 4)) | ((insn >> 4) & (15 << 0))); | |
259 | switch (val) | |
260 | { | |
55552082 | 261 | case 0 : itype = M32RXF_INSN_SUBV; goto extract_sfmt_addv; case 1 : itype = M32RXF_INSN_SUBX; goto extract_sfmt_addx; case 2 : itype = M32RXF_INSN_SUB; goto extract_sfmt_add; case 3 : itype = M32RXF_INSN_NEG; goto extract_sfmt_mv; case 4 : itype = M32RXF_INSN_CMP; goto extract_sfmt_cmp; case 5 : itype = M32RXF_INSN_CMPU; goto extract_sfmt_cmp; case 6 : itype = M32RXF_INSN_CMPEQ; goto extract_sfmt_cmp; case 7 : |
2df3850c | 262 | { |
55552082 | 263 | unsigned int val = (((insn >> 8) & (3 << 0))); |
2df3850c JM |
264 | switch (val) |
265 | { | |
55552082 | 266 | case 0 : itype = M32RXF_INSN_CMPZ; goto extract_sfmt_cmpz; case 3 : itype = M32RXF_INSN_PCMPBZ; goto extract_sfmt_cmpz; default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; |
2df3850c JM |
267 | } |
268 | } | |
55552082 | 269 | case 8 : itype = M32RXF_INSN_ADDV; goto extract_sfmt_addv; case 9 : itype = M32RXF_INSN_ADDX; goto extract_sfmt_addx; case 10 : itype = M32RXF_INSN_ADD; goto extract_sfmt_add; case 11 : itype = M32RXF_INSN_NOT; goto extract_sfmt_mv; case 12 : itype = M32RXF_INSN_AND; goto extract_sfmt_add; case 13 : itype = M32RXF_INSN_XOR; goto extract_sfmt_add; case 14 : itype = M32RXF_INSN_OR; goto extract_sfmt_add; case 16 : itype = M32RXF_INSN_SRL; goto extract_sfmt_add; case 18 : itype = M32RXF_INSN_SRA; goto extract_sfmt_add; case 20 : itype = M32RXF_INSN_SLL; goto extract_sfmt_add; case 22 : itype = M32RXF_INSN_MUL; goto extract_sfmt_add; case 24 : itype = M32RXF_INSN_MV; goto extract_sfmt_mv; case 25 : itype = M32RXF_INSN_MVFC; goto extract_sfmt_mvfc; case 26 : itype = M32RXF_INSN_MVTC; goto extract_sfmt_mvtc; case 28 : |
2df3850c | 270 | { |
55552082 | 271 | unsigned int val = (((insn >> 8) & (3 << 0))); |
2df3850c JM |
272 | switch (val) |
273 | { | |
55552082 | 274 | case 0 : itype = M32RXF_INSN_JC; goto extract_sfmt_jc; case 1 : itype = M32RXF_INSN_JNC; goto extract_sfmt_jc; case 2 : itype = M32RXF_INSN_JL; goto extract_sfmt_jl; case 3 : itype = M32RXF_INSN_JMP; goto extract_sfmt_jmp; default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; |
2df3850c JM |
275 | } |
276 | } | |
55552082 DB |
277 | case 29 : itype = M32RXF_INSN_RTE; goto extract_sfmt_rte; case 31 : itype = M32RXF_INSN_TRAP; goto extract_sfmt_trap; case 32 : itype = M32RXF_INSN_STB; goto extract_sfmt_stb; case 34 : itype = M32RXF_INSN_STH; goto extract_sfmt_sth; case 36 : itype = M32RXF_INSN_ST; goto extract_sfmt_st; case 37 : itype = M32RXF_INSN_UNLOCK; goto extract_sfmt_unlock; case 38 : itype = M32RXF_INSN_ST_PLUS; goto extract_sfmt_st_plus; case 39 : itype = M32RXF_INSN_ST_MINUS; goto extract_sfmt_st_plus; case 40 : itype = M32RXF_INSN_LDB; goto extract_sfmt_ld; case 41 : itype = M32RXF_INSN_LDUB; goto extract_sfmt_ld; case 42 : itype = M32RXF_INSN_LDH; goto extract_sfmt_ld; case 43 : itype = M32RXF_INSN_LDUH; goto extract_sfmt_ld; case 44 : itype = M32RXF_INSN_LD; goto extract_sfmt_ld; case 45 : itype = M32RXF_INSN_LOCK; goto extract_sfmt_lock; case 46 : itype = M32RXF_INSN_LD_PLUS; goto extract_sfmt_ld_plus; case 48 : /* fall through */ |
278 | case 56 : itype = M32RXF_INSN_MULHI_A; goto extract_sfmt_mulhi_a; case 49 : /* fall through */ | |
279 | case 57 : itype = M32RXF_INSN_MULLO_A; goto extract_sfmt_mulhi_a; case 50 : /* fall through */ | |
280 | case 58 : itype = M32RXF_INSN_MULWHI_A; goto extract_sfmt_mulhi_a; case 51 : /* fall through */ | |
281 | case 59 : itype = M32RXF_INSN_MULWLO_A; goto extract_sfmt_mulhi_a; case 52 : /* fall through */ | |
282 | case 60 : itype = M32RXF_INSN_MACHI_A; goto extract_sfmt_machi_a; case 53 : /* fall through */ | |
283 | case 61 : itype = M32RXF_INSN_MACLO_A; goto extract_sfmt_machi_a; case 54 : /* fall through */ | |
284 | case 62 : itype = M32RXF_INSN_MACWHI_A; goto extract_sfmt_machi_a; case 55 : /* fall through */ | |
285 | case 63 : itype = M32RXF_INSN_MACWLO_A; goto extract_sfmt_machi_a; case 64 : /* fall through */ | |
2df3850c JM |
286 | case 65 : /* fall through */ |
287 | case 66 : /* fall through */ | |
288 | case 67 : /* fall through */ | |
289 | case 68 : /* fall through */ | |
290 | case 69 : /* fall through */ | |
291 | case 70 : /* fall through */ | |
292 | case 71 : /* fall through */ | |
293 | case 72 : /* fall through */ | |
294 | case 73 : /* fall through */ | |
295 | case 74 : /* fall through */ | |
296 | case 75 : /* fall through */ | |
297 | case 76 : /* fall through */ | |
298 | case 77 : /* fall through */ | |
299 | case 78 : /* fall through */ | |
55552082 DB |
300 | case 79 : itype = M32RXF_INSN_ADDI; goto extract_sfmt_addi; case 80 : /* fall through */ |
301 | case 81 : itype = M32RXF_INSN_SRLI; goto extract_sfmt_slli; case 82 : /* fall through */ | |
302 | case 83 : itype = M32RXF_INSN_SRAI; goto extract_sfmt_slli; case 84 : /* fall through */ | |
303 | case 85 : itype = M32RXF_INSN_SLLI; goto extract_sfmt_slli; case 87 : | |
2df3850c | 304 | { |
55552082 | 305 | unsigned int val = (((insn >> 0) & (1 << 0))); |
2df3850c JM |
306 | switch (val) |
307 | { | |
55552082 | 308 | case 0 : itype = M32RXF_INSN_MVTACHI_A; goto extract_sfmt_mvtachi_a; case 1 : itype = M32RXF_INSN_MVTACLO_A; goto extract_sfmt_mvtachi_a; default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; |
2df3850c JM |
309 | } |
310 | } | |
55552082 | 311 | case 88 : itype = M32RXF_INSN_RACH_DSI; goto extract_sfmt_rac_dsi; case 89 : itype = M32RXF_INSN_RAC_DSI; goto extract_sfmt_rac_dsi; case 90 : itype = M32RXF_INSN_MULWU1; goto extract_sfmt_mulwu1; case 91 : itype = M32RXF_INSN_MACWU1; goto extract_sfmt_macwu1; case 92 : itype = M32RXF_INSN_MACLH1; goto extract_sfmt_macwu1; case 93 : itype = M32RXF_INSN_MSBLO; goto extract_sfmt_msblo; case 94 : itype = M32RXF_INSN_SADD; goto extract_sfmt_sadd; case 95 : |
2df3850c JM |
312 | { |
313 | unsigned int val = (((insn >> 0) & (3 << 0))); | |
314 | switch (val) | |
315 | { | |
55552082 | 316 | case 0 : itype = M32RXF_INSN_MVFACHI_A; goto extract_sfmt_mvfachi_a; case 1 : itype = M32RXF_INSN_MVFACLO_A; goto extract_sfmt_mvfachi_a; case 2 : itype = M32RXF_INSN_MVFACMI_A; goto extract_sfmt_mvfachi_a; default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; |
2df3850c JM |
317 | } |
318 | } | |
319 | case 96 : /* fall through */ | |
320 | case 97 : /* fall through */ | |
321 | case 98 : /* fall through */ | |
322 | case 99 : /* fall through */ | |
323 | case 100 : /* fall through */ | |
324 | case 101 : /* fall through */ | |
325 | case 102 : /* fall through */ | |
326 | case 103 : /* fall through */ | |
327 | case 104 : /* fall through */ | |
328 | case 105 : /* fall through */ | |
329 | case 106 : /* fall through */ | |
330 | case 107 : /* fall through */ | |
331 | case 108 : /* fall through */ | |
332 | case 109 : /* fall through */ | |
333 | case 110 : /* fall through */ | |
55552082 | 334 | case 111 : itype = M32RXF_INSN_LDI8; goto extract_sfmt_ldi8; case 112 : |
2df3850c JM |
335 | { |
336 | unsigned int val = (((insn >> 8) & (15 << 0))); | |
337 | switch (val) | |
338 | { | |
55552082 | 339 | case 0 : itype = M32RXF_INSN_NOP; goto extract_sfmt_nop; case 4 : itype = M32RXF_INSN_SC; goto extract_sfmt_sc; case 5 : itype = M32RXF_INSN_SNC; goto extract_sfmt_sc; case 8 : itype = M32RXF_INSN_BCL8; goto extract_sfmt_bcl8; case 9 : itype = M32RXF_INSN_BNCL8; goto extract_sfmt_bcl8; case 12 : itype = M32RXF_INSN_BC8; goto extract_sfmt_bc8; case 13 : itype = M32RXF_INSN_BNC8; goto extract_sfmt_bc8; case 14 : itype = M32RXF_INSN_BL8; goto extract_sfmt_bl8; case 15 : itype = M32RXF_INSN_BRA8; goto extract_sfmt_bra8; default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; |
2df3850c JM |
340 | } |
341 | } | |
342 | case 113 : /* fall through */ | |
343 | case 114 : /* fall through */ | |
344 | case 115 : /* fall through */ | |
345 | case 116 : /* fall through */ | |
346 | case 117 : /* fall through */ | |
347 | case 118 : /* fall through */ | |
348 | case 119 : /* fall through */ | |
349 | case 120 : /* fall through */ | |
350 | case 121 : /* fall through */ | |
351 | case 122 : /* fall through */ | |
352 | case 123 : /* fall through */ | |
353 | case 124 : /* fall through */ | |
354 | case 125 : /* fall through */ | |
355 | case 126 : /* fall through */ | |
356 | case 127 : | |
357 | { | |
55552082 | 358 | unsigned int val = (((insn >> 8) & (7 << 0))); |
2df3850c JM |
359 | switch (val) |
360 | { | |
55552082 | 361 | case 0 : itype = M32RXF_INSN_BCL8; goto extract_sfmt_bcl8; case 1 : itype = M32RXF_INSN_BNCL8; goto extract_sfmt_bcl8; case 4 : itype = M32RXF_INSN_BC8; goto extract_sfmt_bc8; case 5 : itype = M32RXF_INSN_BNC8; goto extract_sfmt_bc8; case 6 : itype = M32RXF_INSN_BL8; goto extract_sfmt_bl8; case 7 : itype = M32RXF_INSN_BRA8; goto extract_sfmt_bra8; default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; |
2df3850c JM |
362 | } |
363 | } | |
55552082 | 364 | case 132 : itype = M32RXF_INSN_CMPI; goto extract_sfmt_cmpi; case 133 : itype = M32RXF_INSN_CMPUI; goto extract_sfmt_cmpi; case 134 : |
2df3850c | 365 | { |
55552082 | 366 | unsigned int val = (((insn >> -8) & (3 << 0))); |
2df3850c JM |
367 | switch (val) |
368 | { | |
55552082 | 369 | case 0 : itype = M32RXF_INSN_SAT; goto extract_sfmt_sat; case 2 : itype = M32RXF_INSN_SATH; goto extract_sfmt_satb; case 3 : itype = M32RXF_INSN_SATB; goto extract_sfmt_satb; default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; |
2df3850c JM |
370 | } |
371 | } | |
55552082 | 372 | case 136 : itype = M32RXF_INSN_ADDV3; goto extract_sfmt_addv3; case 138 : itype = M32RXF_INSN_ADD3; goto extract_sfmt_add3; case 140 : itype = M32RXF_INSN_AND3; goto extract_sfmt_and3; case 141 : itype = M32RXF_INSN_XOR3; goto extract_sfmt_and3; case 142 : itype = M32RXF_INSN_OR3; goto extract_sfmt_or3; case 144 : |
2df3850c | 373 | { |
55552082 | 374 | unsigned int val = (((insn >> -12) & (1 << 0))); |
2df3850c JM |
375 | switch (val) |
376 | { | |
55552082 | 377 | case 0 : itype = M32RXF_INSN_DIV; goto extract_sfmt_div; case 1 : itype = M32RXF_INSN_DIVH; goto extract_sfmt_div; default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; |
2df3850c JM |
378 | } |
379 | } | |
55552082 | 380 | case 145 : itype = M32RXF_INSN_DIVU; goto extract_sfmt_div; case 146 : itype = M32RXF_INSN_REM; goto extract_sfmt_div; case 147 : itype = M32RXF_INSN_REMU; goto extract_sfmt_div; case 152 : itype = M32RXF_INSN_SRL3; goto extract_sfmt_sll3; case 154 : itype = M32RXF_INSN_SRA3; goto extract_sfmt_sll3; case 156 : itype = M32RXF_INSN_SLL3; goto extract_sfmt_sll3; case 159 : itype = M32RXF_INSN_LDI16; goto extract_sfmt_ldi16; case 160 : itype = M32RXF_INSN_STB_D; goto extract_sfmt_stb_d; case 162 : itype = M32RXF_INSN_STH_D; goto extract_sfmt_sth_d; case 164 : itype = M32RXF_INSN_ST_D; goto extract_sfmt_st_d; case 168 : itype = M32RXF_INSN_LDB_D; goto extract_sfmt_ld_d; case 169 : itype = M32RXF_INSN_LDUB_D; goto extract_sfmt_ld_d; case 170 : itype = M32RXF_INSN_LDH_D; goto extract_sfmt_ld_d; case 171 : itype = M32RXF_INSN_LDUH_D; goto extract_sfmt_ld_d; case 172 : itype = M32RXF_INSN_LD_D; goto extract_sfmt_ld_d; case 176 : itype = M32RXF_INSN_BEQ; goto extract_sfmt_beq; case 177 : itype = M32RXF_INSN_BNE; goto extract_sfmt_beq; case 184 : itype = M32RXF_INSN_BEQZ; goto extract_sfmt_beqz; case 185 : itype = M32RXF_INSN_BNEZ; goto extract_sfmt_beqz; case 186 : itype = M32RXF_INSN_BLTZ; goto extract_sfmt_beqz; case 187 : itype = M32RXF_INSN_BGEZ; goto extract_sfmt_beqz; case 188 : itype = M32RXF_INSN_BLEZ; goto extract_sfmt_beqz; case 189 : itype = M32RXF_INSN_BGTZ; goto extract_sfmt_beqz; case 220 : itype = M32RXF_INSN_SETH; goto extract_sfmt_seth; case 224 : /* fall through */ |
2df3850c JM |
381 | case 225 : /* fall through */ |
382 | case 226 : /* fall through */ | |
383 | case 227 : /* fall through */ | |
384 | case 228 : /* fall through */ | |
385 | case 229 : /* fall through */ | |
386 | case 230 : /* fall through */ | |
387 | case 231 : /* fall through */ | |
388 | case 232 : /* fall through */ | |
389 | case 233 : /* fall through */ | |
390 | case 234 : /* fall through */ | |
391 | case 235 : /* fall through */ | |
392 | case 236 : /* fall through */ | |
393 | case 237 : /* fall through */ | |
394 | case 238 : /* fall through */ | |
55552082 | 395 | case 239 : itype = M32RXF_INSN_LD24; goto extract_sfmt_ld24; case 240 : /* fall through */ |
2df3850c JM |
396 | case 241 : /* fall through */ |
397 | case 242 : /* fall through */ | |
398 | case 243 : /* fall through */ | |
399 | case 244 : /* fall through */ | |
400 | case 245 : /* fall through */ | |
401 | case 246 : /* fall through */ | |
402 | case 247 : /* fall through */ | |
403 | case 248 : /* fall through */ | |
404 | case 249 : /* fall through */ | |
405 | case 250 : /* fall through */ | |
406 | case 251 : /* fall through */ | |
407 | case 252 : /* fall through */ | |
408 | case 253 : /* fall through */ | |
409 | case 254 : /* fall through */ | |
410 | case 255 : | |
411 | { | |
55552082 | 412 | unsigned int val = (((insn >> 8) & (7 << 0))); |
2df3850c JM |
413 | switch (val) |
414 | { | |
55552082 | 415 | case 0 : itype = M32RXF_INSN_BCL24; goto extract_sfmt_bcl24; case 1 : itype = M32RXF_INSN_BNCL24; goto extract_sfmt_bcl24; case 4 : itype = M32RXF_INSN_BC24; goto extract_sfmt_bc24; case 5 : itype = M32RXF_INSN_BNC24; goto extract_sfmt_bc24; case 6 : itype = M32RXF_INSN_BL24; goto extract_sfmt_bl24; case 7 : itype = M32RXF_INSN_BRA24; goto extract_sfmt_bra24; default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; |
2df3850c JM |
416 | } |
417 | } | |
418 | default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; | |
419 | } | |
420 | } | |
421 | } | |
422 | ||
423 | /* The instruction has been decoded, now extract the fields. */ | |
424 | ||
425 | extract_sfmt_empty: | |
426 | { | |
427 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
2df3850c JM |
428 | #define FLD(f) abuf->fields.fmt_empty.f |
429 | ||
430 | ||
431 | /* Record the fields for the semantic handler. */ | |
432 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_empty", (char *) 0)); | |
433 | ||
434 | #undef FLD | |
435 | return idesc; | |
436 | } | |
437 | ||
438 | extract_sfmt_add: | |
439 | { | |
440 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
441 | CGEN_INSN_INT insn = entire_insn; | |
442 | #define FLD(f) abuf->fields.sfmt_add.f | |
443 | UINT f_r1; | |
444 | UINT f_r2; | |
445 | ||
446 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
447 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
448 | ||
449 | /* Record the fields for the semantic handler. */ | |
de8f5985 DB |
450 | FLD (f_r1) = f_r1; |
451 | FLD (f_r2) = f_r2; | |
2df3850c JM |
452 | FLD (i_dr) = & CPU (h_gr)[f_r1]; |
453 | FLD (i_sr) = & CPU (h_gr)[f_r2]; | |
de8f5985 | 454 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0)); |
2df3850c JM |
455 | |
456 | #if WITH_PROFILE_MODEL_P | |
457 | /* Record the fields for profiling. */ | |
458 | if (PROFILE_MODEL_P (current_cpu)) | |
459 | { | |
460 | FLD (in_dr) = f_r1; | |
461 | FLD (in_sr) = f_r2; | |
462 | FLD (out_dr) = f_r1; | |
463 | } | |
464 | #endif | |
465 | #undef FLD | |
466 | return idesc; | |
467 | } | |
468 | ||
469 | extract_sfmt_add3: | |
470 | { | |
471 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
472 | CGEN_INSN_INT insn = entire_insn; | |
473 | #define FLD(f) abuf->fields.sfmt_add3.f | |
474 | UINT f_r1; | |
475 | UINT f_r2; | |
476 | INT f_simm16; | |
477 | ||
478 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); | |
479 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); | |
480 | f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); | |
481 | ||
482 | /* Record the fields for the semantic handler. */ | |
483 | FLD (f_simm16) = f_simm16; | |
de8f5985 DB |
484 | FLD (f_r2) = f_r2; |
485 | FLD (f_r1) = f_r1; | |
2df3850c JM |
486 | FLD (i_sr) = & CPU (h_gr)[f_r2]; |
487 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
de8f5985 | 488 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add3", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); |
2df3850c JM |
489 | |
490 | #if WITH_PROFILE_MODEL_P | |
491 | /* Record the fields for profiling. */ | |
492 | if (PROFILE_MODEL_P (current_cpu)) | |
493 | { | |
494 | FLD (in_sr) = f_r2; | |
495 | FLD (out_dr) = f_r1; | |
496 | } | |
497 | #endif | |
498 | #undef FLD | |
499 | return idesc; | |
500 | } | |
501 | ||
502 | extract_sfmt_and3: | |
503 | { | |
504 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
505 | CGEN_INSN_INT insn = entire_insn; | |
506 | #define FLD(f) abuf->fields.sfmt_and3.f | |
507 | UINT f_r1; | |
508 | UINT f_r2; | |
509 | UINT f_uimm16; | |
510 | ||
511 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); | |
512 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); | |
513 | f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); | |
514 | ||
515 | /* Record the fields for the semantic handler. */ | |
de8f5985 | 516 | FLD (f_r2) = f_r2; |
2df3850c | 517 | FLD (f_uimm16) = f_uimm16; |
de8f5985 | 518 | FLD (f_r1) = f_r1; |
2df3850c JM |
519 | FLD (i_sr) = & CPU (h_gr)[f_r2]; |
520 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
de8f5985 | 521 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_and3", "f_r2 0x%x", 'x', f_r2, "f_uimm16 0x%x", 'x', f_uimm16, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); |
2df3850c JM |
522 | |
523 | #if WITH_PROFILE_MODEL_P | |
524 | /* Record the fields for profiling. */ | |
525 | if (PROFILE_MODEL_P (current_cpu)) | |
526 | { | |
527 | FLD (in_sr) = f_r2; | |
528 | FLD (out_dr) = f_r1; | |
529 | } | |
530 | #endif | |
531 | #undef FLD | |
532 | return idesc; | |
533 | } | |
534 | ||
535 | extract_sfmt_or3: | |
536 | { | |
537 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
538 | CGEN_INSN_INT insn = entire_insn; | |
539 | #define FLD(f) abuf->fields.sfmt_and3.f | |
540 | UINT f_r1; | |
541 | UINT f_r2; | |
542 | UINT f_uimm16; | |
543 | ||
544 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); | |
545 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); | |
546 | f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); | |
547 | ||
548 | /* Record the fields for the semantic handler. */ | |
de8f5985 | 549 | FLD (f_r2) = f_r2; |
2df3850c | 550 | FLD (f_uimm16) = f_uimm16; |
de8f5985 | 551 | FLD (f_r1) = f_r1; |
2df3850c JM |
552 | FLD (i_sr) = & CPU (h_gr)[f_r2]; |
553 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
de8f5985 | 554 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_or3", "f_r2 0x%x", 'x', f_r2, "f_uimm16 0x%x", 'x', f_uimm16, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); |
2df3850c JM |
555 | |
556 | #if WITH_PROFILE_MODEL_P | |
557 | /* Record the fields for profiling. */ | |
558 | if (PROFILE_MODEL_P (current_cpu)) | |
559 | { | |
560 | FLD (in_sr) = f_r2; | |
561 | FLD (out_dr) = f_r1; | |
562 | } | |
563 | #endif | |
564 | #undef FLD | |
565 | return idesc; | |
566 | } | |
567 | ||
568 | extract_sfmt_addi: | |
569 | { | |
570 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
571 | CGEN_INSN_INT insn = entire_insn; | |
572 | #define FLD(f) abuf->fields.sfmt_addi.f | |
573 | UINT f_r1; | |
574 | INT f_simm8; | |
575 | ||
576 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
577 | f_simm8 = EXTRACT_MSB0_INT (insn, 16, 8, 8); | |
578 | ||
579 | /* Record the fields for the semantic handler. */ | |
de8f5985 | 580 | FLD (f_r1) = f_r1; |
2df3850c JM |
581 | FLD (f_simm8) = f_simm8; |
582 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
de8f5985 | 583 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addi", "f_r1 0x%x", 'x', f_r1, "f_simm8 0x%x", 'x', f_simm8, "dr 0x%x", 'x', f_r1, (char *) 0)); |
2df3850c JM |
584 | |
585 | #if WITH_PROFILE_MODEL_P | |
586 | /* Record the fields for profiling. */ | |
587 | if (PROFILE_MODEL_P (current_cpu)) | |
588 | { | |
589 | FLD (in_dr) = f_r1; | |
590 | FLD (out_dr) = f_r1; | |
591 | } | |
592 | #endif | |
593 | #undef FLD | |
594 | return idesc; | |
595 | } | |
596 | ||
597 | extract_sfmt_addv: | |
598 | { | |
599 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
600 | CGEN_INSN_INT insn = entire_insn; | |
601 | #define FLD(f) abuf->fields.sfmt_add.f | |
602 | UINT f_r1; | |
603 | UINT f_r2; | |
604 | ||
605 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
606 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
607 | ||
608 | /* Record the fields for the semantic handler. */ | |
de8f5985 DB |
609 | FLD (f_r1) = f_r1; |
610 | FLD (f_r2) = f_r2; | |
2df3850c JM |
611 | FLD (i_dr) = & CPU (h_gr)[f_r1]; |
612 | FLD (i_sr) = & CPU (h_gr)[f_r2]; | |
de8f5985 | 613 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addv", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0)); |
2df3850c JM |
614 | |
615 | #if WITH_PROFILE_MODEL_P | |
616 | /* Record the fields for profiling. */ | |
617 | if (PROFILE_MODEL_P (current_cpu)) | |
618 | { | |
619 | FLD (in_dr) = f_r1; | |
620 | FLD (in_sr) = f_r2; | |
621 | FLD (out_dr) = f_r1; | |
622 | } | |
623 | #endif | |
624 | #undef FLD | |
625 | return idesc; | |
626 | } | |
627 | ||
628 | extract_sfmt_addv3: | |
629 | { | |
630 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
631 | CGEN_INSN_INT insn = entire_insn; | |
632 | #define FLD(f) abuf->fields.sfmt_add3.f | |
633 | UINT f_r1; | |
634 | UINT f_r2; | |
635 | INT f_simm16; | |
636 | ||
637 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); | |
638 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); | |
639 | f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); | |
640 | ||
641 | /* Record the fields for the semantic handler. */ | |
642 | FLD (f_simm16) = f_simm16; | |
de8f5985 DB |
643 | FLD (f_r2) = f_r2; |
644 | FLD (f_r1) = f_r1; | |
2df3850c JM |
645 | FLD (i_sr) = & CPU (h_gr)[f_r2]; |
646 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
de8f5985 | 647 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addv3", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); |
2df3850c JM |
648 | |
649 | #if WITH_PROFILE_MODEL_P | |
650 | /* Record the fields for profiling. */ | |
651 | if (PROFILE_MODEL_P (current_cpu)) | |
652 | { | |
653 | FLD (in_sr) = f_r2; | |
654 | FLD (out_dr) = f_r1; | |
655 | } | |
656 | #endif | |
657 | #undef FLD | |
658 | return idesc; | |
659 | } | |
660 | ||
661 | extract_sfmt_addx: | |
662 | { | |
663 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
664 | CGEN_INSN_INT insn = entire_insn; | |
665 | #define FLD(f) abuf->fields.sfmt_add.f | |
666 | UINT f_r1; | |
667 | UINT f_r2; | |
668 | ||
669 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
670 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
671 | ||
672 | /* Record the fields for the semantic handler. */ | |
de8f5985 DB |
673 | FLD (f_r1) = f_r1; |
674 | FLD (f_r2) = f_r2; | |
2df3850c JM |
675 | FLD (i_dr) = & CPU (h_gr)[f_r1]; |
676 | FLD (i_sr) = & CPU (h_gr)[f_r2]; | |
de8f5985 | 677 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addx", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0)); |
2df3850c JM |
678 | |
679 | #if WITH_PROFILE_MODEL_P | |
680 | /* Record the fields for profiling. */ | |
681 | if (PROFILE_MODEL_P (current_cpu)) | |
682 | { | |
683 | FLD (in_dr) = f_r1; | |
684 | FLD (in_sr) = f_r2; | |
685 | FLD (out_dr) = f_r1; | |
686 | } | |
687 | #endif | |
688 | #undef FLD | |
689 | return idesc; | |
690 | } | |
691 | ||
692 | extract_sfmt_bc8: | |
693 | { | |
694 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
695 | CGEN_INSN_INT insn = entire_insn; | |
696 | #define FLD(f) abuf->fields.sfmt_bl8.f | |
697 | SI f_disp8; | |
698 | ||
699 | f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); | |
700 | ||
701 | /* Record the fields for the semantic handler. */ | |
702 | FLD (i_disp8) = f_disp8; | |
703 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bc8", "disp8 0x%x", 'x', f_disp8, (char *) 0)); | |
704 | ||
705 | #if WITH_PROFILE_MODEL_P | |
706 | /* Record the fields for profiling. */ | |
707 | if (PROFILE_MODEL_P (current_cpu)) | |
708 | { | |
709 | } | |
710 | #endif | |
711 | #undef FLD | |
712 | return idesc; | |
713 | } | |
714 | ||
715 | extract_sfmt_bc24: | |
716 | { | |
717 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
718 | CGEN_INSN_INT insn = entire_insn; | |
719 | #define FLD(f) abuf->fields.sfmt_bl24.f | |
720 | SI f_disp24; | |
721 | ||
722 | f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc)); | |
723 | ||
724 | /* Record the fields for the semantic handler. */ | |
725 | FLD (i_disp24) = f_disp24; | |
726 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bc24", "disp24 0x%x", 'x', f_disp24, (char *) 0)); | |
727 | ||
728 | #if WITH_PROFILE_MODEL_P | |
729 | /* Record the fields for profiling. */ | |
730 | if (PROFILE_MODEL_P (current_cpu)) | |
731 | { | |
732 | } | |
733 | #endif | |
734 | #undef FLD | |
735 | return idesc; | |
736 | } | |
737 | ||
738 | extract_sfmt_beq: | |
739 | { | |
740 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
741 | CGEN_INSN_INT insn = entire_insn; | |
742 | #define FLD(f) abuf->fields.sfmt_beq.f | |
743 | UINT f_r1; | |
744 | UINT f_r2; | |
745 | SI f_disp16; | |
746 | ||
747 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); | |
748 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); | |
749 | f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc)); | |
750 | ||
751 | /* Record the fields for the semantic handler. */ | |
de8f5985 DB |
752 | FLD (f_r1) = f_r1; |
753 | FLD (f_r2) = f_r2; | |
2df3850c JM |
754 | FLD (i_disp16) = f_disp16; |
755 | FLD (i_src1) = & CPU (h_gr)[f_r1]; | |
756 | FLD (i_src2) = & CPU (h_gr)[f_r2]; | |
de8f5985 | 757 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_beq", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "disp16 0x%x", 'x', f_disp16, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); |
2df3850c JM |
758 | |
759 | #if WITH_PROFILE_MODEL_P | |
760 | /* Record the fields for profiling. */ | |
761 | if (PROFILE_MODEL_P (current_cpu)) | |
762 | { | |
763 | FLD (in_src1) = f_r1; | |
764 | FLD (in_src2) = f_r2; | |
765 | } | |
766 | #endif | |
767 | #undef FLD | |
768 | return idesc; | |
769 | } | |
770 | ||
771 | extract_sfmt_beqz: | |
772 | { | |
773 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
774 | CGEN_INSN_INT insn = entire_insn; | |
775 | #define FLD(f) abuf->fields.sfmt_beq.f | |
776 | UINT f_r2; | |
777 | SI f_disp16; | |
778 | ||
779 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); | |
780 | f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc)); | |
781 | ||
782 | /* Record the fields for the semantic handler. */ | |
de8f5985 | 783 | FLD (f_r2) = f_r2; |
2df3850c JM |
784 | FLD (i_disp16) = f_disp16; |
785 | FLD (i_src2) = & CPU (h_gr)[f_r2]; | |
de8f5985 | 786 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_beqz", "f_r2 0x%x", 'x', f_r2, "disp16 0x%x", 'x', f_disp16, "src2 0x%x", 'x', f_r2, (char *) 0)); |
2df3850c JM |
787 | |
788 | #if WITH_PROFILE_MODEL_P | |
789 | /* Record the fields for profiling. */ | |
790 | if (PROFILE_MODEL_P (current_cpu)) | |
791 | { | |
792 | FLD (in_src2) = f_r2; | |
793 | } | |
794 | #endif | |
795 | #undef FLD | |
796 | return idesc; | |
797 | } | |
798 | ||
799 | extract_sfmt_bl8: | |
800 | { | |
801 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
802 | CGEN_INSN_INT insn = entire_insn; | |
803 | #define FLD(f) abuf->fields.sfmt_bl8.f | |
804 | SI f_disp8; | |
805 | ||
806 | f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); | |
807 | ||
808 | /* Record the fields for the semantic handler. */ | |
809 | FLD (i_disp8) = f_disp8; | |
810 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bl8", "disp8 0x%x", 'x', f_disp8, (char *) 0)); | |
811 | ||
812 | #if WITH_PROFILE_MODEL_P | |
813 | /* Record the fields for profiling. */ | |
814 | if (PROFILE_MODEL_P (current_cpu)) | |
815 | { | |
816 | FLD (out_h_gr_14) = 14; | |
817 | } | |
818 | #endif | |
819 | #undef FLD | |
820 | return idesc; | |
821 | } | |
822 | ||
823 | extract_sfmt_bl24: | |
824 | { | |
825 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
826 | CGEN_INSN_INT insn = entire_insn; | |
827 | #define FLD(f) abuf->fields.sfmt_bl24.f | |
828 | SI f_disp24; | |
829 | ||
830 | f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc)); | |
831 | ||
832 | /* Record the fields for the semantic handler. */ | |
833 | FLD (i_disp24) = f_disp24; | |
834 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bl24", "disp24 0x%x", 'x', f_disp24, (char *) 0)); | |
835 | ||
836 | #if WITH_PROFILE_MODEL_P | |
837 | /* Record the fields for profiling. */ | |
838 | if (PROFILE_MODEL_P (current_cpu)) | |
839 | { | |
840 | FLD (out_h_gr_14) = 14; | |
841 | } | |
842 | #endif | |
843 | #undef FLD | |
844 | return idesc; | |
845 | } | |
846 | ||
847 | extract_sfmt_bcl8: | |
848 | { | |
849 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
850 | CGEN_INSN_INT insn = entire_insn; | |
851 | #define FLD(f) abuf->fields.sfmt_bl8.f | |
852 | SI f_disp8; | |
853 | ||
854 | f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); | |
855 | ||
856 | /* Record the fields for the semantic handler. */ | |
857 | FLD (i_disp8) = f_disp8; | |
858 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bcl8", "disp8 0x%x", 'x', f_disp8, (char *) 0)); | |
859 | ||
860 | #if WITH_PROFILE_MODEL_P | |
861 | /* Record the fields for profiling. */ | |
862 | if (PROFILE_MODEL_P (current_cpu)) | |
863 | { | |
864 | FLD (out_h_gr_14) = 14; | |
865 | } | |
866 | #endif | |
867 | #undef FLD | |
868 | return idesc; | |
869 | } | |
870 | ||
871 | extract_sfmt_bcl24: | |
872 | { | |
873 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
874 | CGEN_INSN_INT insn = entire_insn; | |
875 | #define FLD(f) abuf->fields.sfmt_bl24.f | |
876 | SI f_disp24; | |
877 | ||
878 | f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc)); | |
879 | ||
880 | /* Record the fields for the semantic handler. */ | |
881 | FLD (i_disp24) = f_disp24; | |
882 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bcl24", "disp24 0x%x", 'x', f_disp24, (char *) 0)); | |
883 | ||
884 | #if WITH_PROFILE_MODEL_P | |
885 | /* Record the fields for profiling. */ | |
886 | if (PROFILE_MODEL_P (current_cpu)) | |
887 | { | |
888 | FLD (out_h_gr_14) = 14; | |
889 | } | |
890 | #endif | |
891 | #undef FLD | |
892 | return idesc; | |
893 | } | |
894 | ||
895 | extract_sfmt_bra8: | |
896 | { | |
897 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
898 | CGEN_INSN_INT insn = entire_insn; | |
899 | #define FLD(f) abuf->fields.sfmt_bl8.f | |
900 | SI f_disp8; | |
901 | ||
902 | f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); | |
903 | ||
904 | /* Record the fields for the semantic handler. */ | |
905 | FLD (i_disp8) = f_disp8; | |
906 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bra8", "disp8 0x%x", 'x', f_disp8, (char *) 0)); | |
907 | ||
908 | #if WITH_PROFILE_MODEL_P | |
909 | /* Record the fields for profiling. */ | |
910 | if (PROFILE_MODEL_P (current_cpu)) | |
911 | { | |
912 | } | |
913 | #endif | |
914 | #undef FLD | |
915 | return idesc; | |
916 | } | |
917 | ||
918 | extract_sfmt_bra24: | |
919 | { | |
920 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
921 | CGEN_INSN_INT insn = entire_insn; | |
922 | #define FLD(f) abuf->fields.sfmt_bl24.f | |
923 | SI f_disp24; | |
924 | ||
925 | f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc)); | |
926 | ||
927 | /* Record the fields for the semantic handler. */ | |
928 | FLD (i_disp24) = f_disp24; | |
929 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bra24", "disp24 0x%x", 'x', f_disp24, (char *) 0)); | |
930 | ||
931 | #if WITH_PROFILE_MODEL_P | |
932 | /* Record the fields for profiling. */ | |
933 | if (PROFILE_MODEL_P (current_cpu)) | |
934 | { | |
935 | } | |
936 | #endif | |
937 | #undef FLD | |
938 | return idesc; | |
939 | } | |
940 | ||
941 | extract_sfmt_cmp: | |
942 | { | |
943 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
944 | CGEN_INSN_INT insn = entire_insn; | |
945 | #define FLD(f) abuf->fields.sfmt_st_plus.f | |
946 | UINT f_r1; | |
947 | UINT f_r2; | |
948 | ||
949 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
950 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
951 | ||
952 | /* Record the fields for the semantic handler. */ | |
de8f5985 DB |
953 | FLD (f_r1) = f_r1; |
954 | FLD (f_r2) = f_r2; | |
2df3850c JM |
955 | FLD (i_src1) = & CPU (h_gr)[f_r1]; |
956 | FLD (i_src2) = & CPU (h_gr)[f_r2]; | |
de8f5985 | 957 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmp", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); |
2df3850c JM |
958 | |
959 | #if WITH_PROFILE_MODEL_P | |
960 | /* Record the fields for profiling. */ | |
961 | if (PROFILE_MODEL_P (current_cpu)) | |
962 | { | |
963 | FLD (in_src1) = f_r1; | |
964 | FLD (in_src2) = f_r2; | |
965 | } | |
966 | #endif | |
967 | #undef FLD | |
968 | return idesc; | |
969 | } | |
970 | ||
971 | extract_sfmt_cmpi: | |
972 | { | |
973 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
974 | CGEN_INSN_INT insn = entire_insn; | |
975 | #define FLD(f) abuf->fields.sfmt_st_d.f | |
976 | UINT f_r2; | |
977 | INT f_simm16; | |
978 | ||
979 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); | |
980 | f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); | |
981 | ||
982 | /* Record the fields for the semantic handler. */ | |
983 | FLD (f_simm16) = f_simm16; | |
de8f5985 | 984 | FLD (f_r2) = f_r2; |
2df3850c | 985 | FLD (i_src2) = & CPU (h_gr)[f_r2]; |
de8f5985 | 986 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpi", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "src2 0x%x", 'x', f_r2, (char *) 0)); |
2df3850c JM |
987 | |
988 | #if WITH_PROFILE_MODEL_P | |
989 | /* Record the fields for profiling. */ | |
990 | if (PROFILE_MODEL_P (current_cpu)) | |
991 | { | |
992 | FLD (in_src2) = f_r2; | |
993 | } | |
994 | #endif | |
995 | #undef FLD | |
996 | return idesc; | |
997 | } | |
998 | ||
999 | extract_sfmt_cmpz: | |
1000 | { | |
1001 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
1002 | CGEN_INSN_INT insn = entire_insn; | |
1003 | #define FLD(f) abuf->fields.sfmt_st_plus.f | |
1004 | UINT f_r2; | |
1005 | ||
1006 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
1007 | ||
1008 | /* Record the fields for the semantic handler. */ | |
de8f5985 | 1009 | FLD (f_r2) = f_r2; |
2df3850c | 1010 | FLD (i_src2) = & CPU (h_gr)[f_r2]; |
de8f5985 | 1011 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpz", "f_r2 0x%x", 'x', f_r2, "src2 0x%x", 'x', f_r2, (char *) 0)); |
2df3850c JM |
1012 | |
1013 | #if WITH_PROFILE_MODEL_P | |
1014 | /* Record the fields for profiling. */ | |
1015 | if (PROFILE_MODEL_P (current_cpu)) | |
1016 | { | |
1017 | FLD (in_src2) = f_r2; | |
1018 | } | |
1019 | #endif | |
1020 | #undef FLD | |
1021 | return idesc; | |
1022 | } | |
1023 | ||
1024 | extract_sfmt_div: | |
1025 | { | |
1026 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
1027 | CGEN_INSN_INT insn = entire_insn; | |
1028 | #define FLD(f) abuf->fields.sfmt_add.f | |
1029 | UINT f_r1; | |
1030 | UINT f_r2; | |
1031 | ||
1032 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); | |
1033 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); | |
1034 | ||
1035 | /* Record the fields for the semantic handler. */ | |
de8f5985 DB |
1036 | FLD (f_r1) = f_r1; |
1037 | FLD (f_r2) = f_r2; | |
2df3850c JM |
1038 | FLD (i_dr) = & CPU (h_gr)[f_r1]; |
1039 | FLD (i_sr) = & CPU (h_gr)[f_r2]; | |
de8f5985 | 1040 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_div", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0)); |
2df3850c JM |
1041 | |
1042 | #if WITH_PROFILE_MODEL_P | |
1043 | /* Record the fields for profiling. */ | |
1044 | if (PROFILE_MODEL_P (current_cpu)) | |
1045 | { | |
1046 | FLD (in_dr) = f_r1; | |
1047 | FLD (in_sr) = f_r2; | |
1048 | FLD (out_dr) = f_r1; | |
1049 | } | |
1050 | #endif | |
1051 | #undef FLD | |
1052 | return idesc; | |
1053 | } | |
1054 | ||
1055 | extract_sfmt_jc: | |
1056 | { | |
1057 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
1058 | CGEN_INSN_INT insn = entire_insn; | |
de8f5985 | 1059 | #define FLD(f) abuf->fields.sfmt_jl.f |
2df3850c JM |
1060 | UINT f_r2; |
1061 | ||
1062 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
1063 | ||
1064 | /* Record the fields for the semantic handler. */ | |
de8f5985 | 1065 | FLD (f_r2) = f_r2; |
2df3850c | 1066 | FLD (i_sr) = & CPU (h_gr)[f_r2]; |
de8f5985 | 1067 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jc", "f_r2 0x%x", 'x', f_r2, "sr 0x%x", 'x', f_r2, (char *) 0)); |
2df3850c JM |
1068 | |
1069 | #if WITH_PROFILE_MODEL_P | |
1070 | /* Record the fields for profiling. */ | |
1071 | if (PROFILE_MODEL_P (current_cpu)) | |
1072 | { | |
1073 | FLD (in_sr) = f_r2; | |
1074 | } | |
1075 | #endif | |
1076 | #undef FLD | |
1077 | return idesc; | |
1078 | } | |
1079 | ||
1080 | extract_sfmt_jl: | |
1081 | { | |
1082 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
1083 | CGEN_INSN_INT insn = entire_insn; | |
1084 | #define FLD(f) abuf->fields.sfmt_jl.f | |
1085 | UINT f_r2; | |
1086 | ||
1087 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
1088 | ||
1089 | /* Record the fields for the semantic handler. */ | |
de8f5985 | 1090 | FLD (f_r2) = f_r2; |
2df3850c | 1091 | FLD (i_sr) = & CPU (h_gr)[f_r2]; |
de8f5985 | 1092 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jl", "f_r2 0x%x", 'x', f_r2, "sr 0x%x", 'x', f_r2, (char *) 0)); |
2df3850c JM |
1093 | |
1094 | #if WITH_PROFILE_MODEL_P | |
1095 | /* Record the fields for profiling. */ | |
1096 | if (PROFILE_MODEL_P (current_cpu)) | |
1097 | { | |
1098 | FLD (in_sr) = f_r2; | |
1099 | FLD (out_h_gr_14) = 14; | |
1100 | } | |
1101 | #endif | |
1102 | #undef FLD | |
1103 | return idesc; | |
1104 | } | |
1105 | ||
1106 | extract_sfmt_jmp: | |
1107 | { | |
1108 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
1109 | CGEN_INSN_INT insn = entire_insn; | |
de8f5985 | 1110 | #define FLD(f) abuf->fields.sfmt_jl.f |
2df3850c JM |
1111 | UINT f_r2; |
1112 | ||
1113 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
1114 | ||
1115 | /* Record the fields for the semantic handler. */ | |
de8f5985 | 1116 | FLD (f_r2) = f_r2; |
2df3850c | 1117 | FLD (i_sr) = & CPU (h_gr)[f_r2]; |
de8f5985 | 1118 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jmp", "f_r2 0x%x", 'x', f_r2, "sr 0x%x", 'x', f_r2, (char *) 0)); |
2df3850c JM |
1119 | |
1120 | #if WITH_PROFILE_MODEL_P | |
1121 | /* Record the fields for profiling. */ | |
1122 | if (PROFILE_MODEL_P (current_cpu)) | |
1123 | { | |
1124 | FLD (in_sr) = f_r2; | |
1125 | } | |
1126 | #endif | |
1127 | #undef FLD | |
1128 | return idesc; | |
1129 | } | |
1130 | ||
1131 | extract_sfmt_ld: | |
1132 | { | |
1133 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
1134 | CGEN_INSN_INT insn = entire_insn; | |
1135 | #define FLD(f) abuf->fields.sfmt_ld_plus.f | |
1136 | UINT f_r1; | |
1137 | UINT f_r2; | |
1138 | ||
1139 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
1140 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
1141 | ||
1142 | /* Record the fields for the semantic handler. */ | |
de8f5985 DB |
1143 | FLD (f_r2) = f_r2; |
1144 | FLD (f_r1) = f_r1; | |
2df3850c JM |
1145 | FLD (i_sr) = & CPU (h_gr)[f_r2]; |
1146 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
de8f5985 | 1147 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); |
2df3850c JM |
1148 | |
1149 | #if WITH_PROFILE_MODEL_P | |
1150 | /* Record the fields for profiling. */ | |
1151 | if (PROFILE_MODEL_P (current_cpu)) | |
1152 | { | |
1153 | FLD (in_sr) = f_r2; | |
1154 | FLD (out_dr) = f_r1; | |
1155 | } | |
1156 | #endif | |
1157 | #undef FLD | |
1158 | return idesc; | |
1159 | } | |
1160 | ||
1161 | extract_sfmt_ld_d: | |
1162 | { | |
1163 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
1164 | CGEN_INSN_INT insn = entire_insn; | |
1165 | #define FLD(f) abuf->fields.sfmt_add3.f | |
1166 | UINT f_r1; | |
1167 | UINT f_r2; | |
1168 | INT f_simm16; | |
1169 | ||
1170 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); | |
1171 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); | |
1172 | f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); | |
1173 | ||
1174 | /* Record the fields for the semantic handler. */ | |
1175 | FLD (f_simm16) = f_simm16; | |
de8f5985 DB |
1176 | FLD (f_r2) = f_r2; |
1177 | FLD (f_r1) = f_r1; | |
2df3850c JM |
1178 | FLD (i_sr) = & CPU (h_gr)[f_r2]; |
1179 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
de8f5985 | 1180 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_d", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); |
2df3850c JM |
1181 | |
1182 | #if WITH_PROFILE_MODEL_P | |
1183 | /* Record the fields for profiling. */ | |
1184 | if (PROFILE_MODEL_P (current_cpu)) | |
1185 | { | |
1186 | FLD (in_sr) = f_r2; | |
1187 | FLD (out_dr) = f_r1; | |
1188 | } | |
1189 | #endif | |
1190 | #undef FLD | |
1191 | return idesc; | |
1192 | } | |
1193 | ||
1194 | extract_sfmt_ld_plus: | |
1195 | { | |
1196 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
1197 | CGEN_INSN_INT insn = entire_insn; | |
1198 | #define FLD(f) abuf->fields.sfmt_ld_plus.f | |
1199 | UINT f_r1; | |
1200 | UINT f_r2; | |
1201 | ||
1202 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
1203 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
1204 | ||
1205 | /* Record the fields for the semantic handler. */ | |
de8f5985 DB |
1206 | FLD (f_r2) = f_r2; |
1207 | FLD (f_r1) = f_r1; | |
2df3850c JM |
1208 | FLD (i_sr) = & CPU (h_gr)[f_r2]; |
1209 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
de8f5985 | 1210 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_plus", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); |
2df3850c JM |
1211 | |
1212 | #if WITH_PROFILE_MODEL_P | |
1213 | /* Record the fields for profiling. */ | |
1214 | if (PROFILE_MODEL_P (current_cpu)) | |
1215 | { | |
1216 | FLD (in_sr) = f_r2; | |
1217 | FLD (out_dr) = f_r1; | |
1218 | FLD (out_sr) = f_r2; | |
1219 | } | |
1220 | #endif | |
1221 | #undef FLD | |
1222 | return idesc; | |
1223 | } | |
1224 | ||
1225 | extract_sfmt_ld24: | |
1226 | { | |
1227 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
1228 | CGEN_INSN_INT insn = entire_insn; | |
1229 | #define FLD(f) abuf->fields.sfmt_ld24.f | |
1230 | UINT f_r1; | |
1231 | UINT f_uimm24; | |
1232 | ||
1233 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); | |
1234 | f_uimm24 = EXTRACT_MSB0_UINT (insn, 32, 8, 24); | |
1235 | ||
1236 | /* Record the fields for the semantic handler. */ | |
de8f5985 | 1237 | FLD (f_r1) = f_r1; |
2df3850c JM |
1238 | FLD (i_uimm24) = f_uimm24; |
1239 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
de8f5985 | 1240 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld24", "f_r1 0x%x", 'x', f_r1, "uimm24 0x%x", 'x', f_uimm24, "dr 0x%x", 'x', f_r1, (char *) 0)); |
2df3850c JM |
1241 | |
1242 | #if WITH_PROFILE_MODEL_P | |
1243 | /* Record the fields for profiling. */ | |
1244 | if (PROFILE_MODEL_P (current_cpu)) | |
1245 | { | |
1246 | FLD (out_dr) = f_r1; | |
1247 | } | |
1248 | #endif | |
1249 | #undef FLD | |
1250 | return idesc; | |
1251 | } | |
1252 | ||
1253 | extract_sfmt_ldi8: | |
1254 | { | |
1255 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
1256 | CGEN_INSN_INT insn = entire_insn; | |
1257 | #define FLD(f) abuf->fields.sfmt_addi.f | |
1258 | UINT f_r1; | |
1259 | INT f_simm8; | |
1260 | ||
1261 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
1262 | f_simm8 = EXTRACT_MSB0_INT (insn, 16, 8, 8); | |
1263 | ||
1264 | /* Record the fields for the semantic handler. */ | |
1265 | FLD (f_simm8) = f_simm8; | |
de8f5985 | 1266 | FLD (f_r1) = f_r1; |
2df3850c | 1267 | FLD (i_dr) = & CPU (h_gr)[f_r1]; |
de8f5985 | 1268 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldi8", "f_simm8 0x%x", 'x', f_simm8, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0)); |
2df3850c JM |
1269 | |
1270 | #if WITH_PROFILE_MODEL_P | |
1271 | /* Record the fields for profiling. */ | |
1272 | if (PROFILE_MODEL_P (current_cpu)) | |
1273 | { | |
1274 | FLD (out_dr) = f_r1; | |
1275 | } | |
1276 | #endif | |
1277 | #undef FLD | |
1278 | return idesc; | |
1279 | } | |
1280 | ||
1281 | extract_sfmt_ldi16: | |
1282 | { | |
1283 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
1284 | CGEN_INSN_INT insn = entire_insn; | |
1285 | #define FLD(f) abuf->fields.sfmt_add3.f | |
1286 | UINT f_r1; | |
1287 | INT f_simm16; | |
1288 | ||
1289 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); | |
1290 | f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); | |
1291 | ||
1292 | /* Record the fields for the semantic handler. */ | |
1293 | FLD (f_simm16) = f_simm16; | |
de8f5985 | 1294 | FLD (f_r1) = f_r1; |
2df3850c | 1295 | FLD (i_dr) = & CPU (h_gr)[f_r1]; |
de8f5985 | 1296 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldi16", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0)); |
2df3850c JM |
1297 | |
1298 | #if WITH_PROFILE_MODEL_P | |
1299 | /* Record the fields for profiling. */ | |
1300 | if (PROFILE_MODEL_P (current_cpu)) | |
1301 | { | |
1302 | FLD (out_dr) = f_r1; | |
1303 | } | |
1304 | #endif | |
1305 | #undef FLD | |
1306 | return idesc; | |
1307 | } | |
1308 | ||
1309 | extract_sfmt_lock: | |
1310 | { | |
1311 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
1312 | CGEN_INSN_INT insn = entire_insn; | |
1313 | #define FLD(f) abuf->fields.sfmt_ld_plus.f | |
1314 | UINT f_r1; | |
1315 | UINT f_r2; | |
1316 | ||
1317 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
1318 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
1319 | ||
1320 | /* Record the fields for the semantic handler. */ | |
de8f5985 DB |
1321 | FLD (f_r2) = f_r2; |
1322 | FLD (f_r1) = f_r1; | |
2df3850c JM |
1323 | FLD (i_sr) = & CPU (h_gr)[f_r2]; |
1324 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
de8f5985 | 1325 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lock", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); |
2df3850c JM |
1326 | |
1327 | #if WITH_PROFILE_MODEL_P | |
1328 | /* Record the fields for profiling. */ | |
1329 | if (PROFILE_MODEL_P (current_cpu)) | |
1330 | { | |
1331 | FLD (in_sr) = f_r2; | |
1332 | FLD (out_dr) = f_r1; | |
1333 | } | |
1334 | #endif | |
1335 | #undef FLD | |
1336 | return idesc; | |
1337 | } | |
1338 | ||
1339 | extract_sfmt_machi_a: | |
1340 | { | |
1341 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
1342 | CGEN_INSN_INT insn = entire_insn; | |
1343 | #define FLD(f) abuf->fields.sfmt_machi_a.f | |
1344 | UINT f_r1; | |
1345 | UINT f_acc; | |
1346 | UINT f_r2; | |
1347 | ||
1348 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
1349 | f_acc = EXTRACT_MSB0_UINT (insn, 16, 8, 1); | |
1350 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
1351 | ||
1352 | /* Record the fields for the semantic handler. */ | |
1353 | FLD (f_acc) = f_acc; | |
de8f5985 DB |
1354 | FLD (f_r1) = f_r1; |
1355 | FLD (f_r2) = f_r2; | |
2df3850c JM |
1356 | FLD (i_src1) = & CPU (h_gr)[f_r1]; |
1357 | FLD (i_src2) = & CPU (h_gr)[f_r2]; | |
de8f5985 | 1358 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_machi_a", "f_acc 0x%x", 'x', f_acc, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); |
2df3850c JM |
1359 | |
1360 | #if WITH_PROFILE_MODEL_P | |
1361 | /* Record the fields for profiling. */ | |
1362 | if (PROFILE_MODEL_P (current_cpu)) | |
1363 | { | |
1364 | FLD (in_src1) = f_r1; | |
1365 | FLD (in_src2) = f_r2; | |
1366 | } | |
1367 | #endif | |
1368 | #undef FLD | |
1369 | return idesc; | |
1370 | } | |
1371 | ||
1372 | extract_sfmt_mulhi_a: | |
1373 | { | |
1374 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
1375 | CGEN_INSN_INT insn = entire_insn; | |
1376 | #define FLD(f) abuf->fields.sfmt_machi_a.f | |
1377 | UINT f_r1; | |
1378 | UINT f_acc; | |
1379 | UINT f_r2; | |
1380 | ||
1381 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
1382 | f_acc = EXTRACT_MSB0_UINT (insn, 16, 8, 1); | |
1383 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
1384 | ||
1385 | /* Record the fields for the semantic handler. */ | |
de8f5985 DB |
1386 | FLD (f_r1) = f_r1; |
1387 | FLD (f_r2) = f_r2; | |
2df3850c JM |
1388 | FLD (f_acc) = f_acc; |
1389 | FLD (i_src1) = & CPU (h_gr)[f_r1]; | |
1390 | FLD (i_src2) = & CPU (h_gr)[f_r2]; | |
de8f5985 | 1391 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mulhi_a", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "f_acc 0x%x", 'x', f_acc, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); |
2df3850c JM |
1392 | |
1393 | #if WITH_PROFILE_MODEL_P | |
1394 | /* Record the fields for profiling. */ | |
1395 | if (PROFILE_MODEL_P (current_cpu)) | |
1396 | { | |
1397 | FLD (in_src1) = f_r1; | |
1398 | FLD (in_src2) = f_r2; | |
1399 | } | |
1400 | #endif | |
1401 | #undef FLD | |
1402 | return idesc; | |
1403 | } | |
1404 | ||
1405 | extract_sfmt_mv: | |
1406 | { | |
1407 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
1408 | CGEN_INSN_INT insn = entire_insn; | |
1409 | #define FLD(f) abuf->fields.sfmt_ld_plus.f | |
1410 | UINT f_r1; | |
1411 | UINT f_r2; | |
1412 | ||
1413 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
1414 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
1415 | ||
1416 | /* Record the fields for the semantic handler. */ | |
de8f5985 DB |
1417 | FLD (f_r2) = f_r2; |
1418 | FLD (f_r1) = f_r1; | |
2df3850c JM |
1419 | FLD (i_sr) = & CPU (h_gr)[f_r2]; |
1420 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
de8f5985 | 1421 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mv", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); |
2df3850c JM |
1422 | |
1423 | #if WITH_PROFILE_MODEL_P | |
1424 | /* Record the fields for profiling. */ | |
1425 | if (PROFILE_MODEL_P (current_cpu)) | |
1426 | { | |
1427 | FLD (in_sr) = f_r2; | |
1428 | FLD (out_dr) = f_r1; | |
1429 | } | |
1430 | #endif | |
1431 | #undef FLD | |
1432 | return idesc; | |
1433 | } | |
1434 | ||
1435 | extract_sfmt_mvfachi_a: | |
1436 | { | |
1437 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
1438 | CGEN_INSN_INT insn = entire_insn; | |
1439 | #define FLD(f) abuf->fields.sfmt_mvfachi_a.f | |
1440 | UINT f_r1; | |
1441 | UINT f_accs; | |
1442 | ||
1443 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
1444 | f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); | |
1445 | ||
1446 | /* Record the fields for the semantic handler. */ | |
1447 | FLD (f_accs) = f_accs; | |
de8f5985 | 1448 | FLD (f_r1) = f_r1; |
2df3850c | 1449 | FLD (i_dr) = & CPU (h_gr)[f_r1]; |
de8f5985 | 1450 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvfachi_a", "f_accs 0x%x", 'x', f_accs, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0)); |
2df3850c JM |
1451 | |
1452 | #if WITH_PROFILE_MODEL_P | |
1453 | /* Record the fields for profiling. */ | |
1454 | if (PROFILE_MODEL_P (current_cpu)) | |
1455 | { | |
1456 | FLD (out_dr) = f_r1; | |
1457 | } | |
1458 | #endif | |
1459 | #undef FLD | |
1460 | return idesc; | |
1461 | } | |
1462 | ||
1463 | extract_sfmt_mvfc: | |
1464 | { | |
1465 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
1466 | CGEN_INSN_INT insn = entire_insn; | |
de8f5985 | 1467 | #define FLD(f) abuf->fields.sfmt_ld_plus.f |
2df3850c JM |
1468 | UINT f_r1; |
1469 | UINT f_r2; | |
1470 | ||
1471 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
1472 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
1473 | ||
1474 | /* Record the fields for the semantic handler. */ | |
1475 | FLD (f_r2) = f_r2; | |
de8f5985 | 1476 | FLD (f_r1) = f_r1; |
2df3850c | 1477 | FLD (i_dr) = & CPU (h_gr)[f_r1]; |
de8f5985 | 1478 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvfc", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0)); |
2df3850c JM |
1479 | |
1480 | #if WITH_PROFILE_MODEL_P | |
1481 | /* Record the fields for profiling. */ | |
1482 | if (PROFILE_MODEL_P (current_cpu)) | |
1483 | { | |
1484 | FLD (out_dr) = f_r1; | |
1485 | } | |
1486 | #endif | |
1487 | #undef FLD | |
1488 | return idesc; | |
1489 | } | |
1490 | ||
1491 | extract_sfmt_mvtachi_a: | |
1492 | { | |
1493 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
1494 | CGEN_INSN_INT insn = entire_insn; | |
1495 | #define FLD(f) abuf->fields.sfmt_mvtachi_a.f | |
1496 | UINT f_r1; | |
1497 | UINT f_accs; | |
1498 | ||
1499 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
1500 | f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); | |
1501 | ||
1502 | /* Record the fields for the semantic handler. */ | |
1503 | FLD (f_accs) = f_accs; | |
de8f5985 | 1504 | FLD (f_r1) = f_r1; |
2df3850c | 1505 | FLD (i_src1) = & CPU (h_gr)[f_r1]; |
de8f5985 | 1506 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvtachi_a", "f_accs 0x%x", 'x', f_accs, "f_r1 0x%x", 'x', f_r1, "src1 0x%x", 'x', f_r1, (char *) 0)); |
2df3850c JM |
1507 | |
1508 | #if WITH_PROFILE_MODEL_P | |
1509 | /* Record the fields for profiling. */ | |
1510 | if (PROFILE_MODEL_P (current_cpu)) | |
1511 | { | |
1512 | FLD (in_src1) = f_r1; | |
1513 | } | |
1514 | #endif | |
1515 | #undef FLD | |
1516 | return idesc; | |
1517 | } | |
1518 | ||
1519 | extract_sfmt_mvtc: | |
1520 | { | |
1521 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
1522 | CGEN_INSN_INT insn = entire_insn; | |
de8f5985 | 1523 | #define FLD(f) abuf->fields.sfmt_ld_plus.f |
2df3850c JM |
1524 | UINT f_r1; |
1525 | UINT f_r2; | |
1526 | ||
1527 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
1528 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
1529 | ||
1530 | /* Record the fields for the semantic handler. */ | |
de8f5985 | 1531 | FLD (f_r2) = f_r2; |
2df3850c JM |
1532 | FLD (f_r1) = f_r1; |
1533 | FLD (i_sr) = & CPU (h_gr)[f_r2]; | |
de8f5985 | 1534 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvtc", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0)); |
2df3850c JM |
1535 | |
1536 | #if WITH_PROFILE_MODEL_P | |
1537 | /* Record the fields for profiling. */ | |
1538 | if (PROFILE_MODEL_P (current_cpu)) | |
1539 | { | |
1540 | FLD (in_sr) = f_r2; | |
1541 | } | |
1542 | #endif | |
1543 | #undef FLD | |
1544 | return idesc; | |
1545 | } | |
1546 | ||
1547 | extract_sfmt_nop: | |
1548 | { | |
1549 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
2df3850c JM |
1550 | #define FLD(f) abuf->fields.fmt_empty.f |
1551 | ||
1552 | ||
1553 | /* Record the fields for the semantic handler. */ | |
1554 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nop", (char *) 0)); | |
1555 | ||
1556 | #undef FLD | |
1557 | return idesc; | |
1558 | } | |
1559 | ||
1560 | extract_sfmt_rac_dsi: | |
1561 | { | |
1562 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
1563 | CGEN_INSN_INT insn = entire_insn; | |
1564 | #define FLD(f) abuf->fields.sfmt_rac_dsi.f | |
1565 | UINT f_accd; | |
1566 | UINT f_accs; | |
1567 | SI f_imm1; | |
1568 | ||
1569 | f_accd = EXTRACT_MSB0_UINT (insn, 16, 4, 2); | |
1570 | f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); | |
1571 | f_imm1 = ((EXTRACT_MSB0_UINT (insn, 16, 15, 1)) + (1)); | |
1572 | ||
1573 | /* Record the fields for the semantic handler. */ | |
1574 | FLD (f_accs) = f_accs; | |
1575 | FLD (f_imm1) = f_imm1; | |
1576 | FLD (f_accd) = f_accd; | |
1577 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rac_dsi", "f_accs 0x%x", 'x', f_accs, "f_imm1 0x%x", 'x', f_imm1, "f_accd 0x%x", 'x', f_accd, (char *) 0)); | |
1578 | ||
1579 | #undef FLD | |
1580 | return idesc; | |
1581 | } | |
1582 | ||
1583 | extract_sfmt_rte: | |
1584 | { | |
1585 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
2df3850c JM |
1586 | #define FLD(f) abuf->fields.fmt_empty.f |
1587 | ||
1588 | ||
1589 | /* Record the fields for the semantic handler. */ | |
1590 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rte", (char *) 0)); | |
1591 | ||
1592 | #if WITH_PROFILE_MODEL_P | |
1593 | /* Record the fields for profiling. */ | |
1594 | if (PROFILE_MODEL_P (current_cpu)) | |
1595 | { | |
1596 | } | |
1597 | #endif | |
1598 | #undef FLD | |
1599 | return idesc; | |
1600 | } | |
1601 | ||
1602 | extract_sfmt_seth: | |
1603 | { | |
1604 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
1605 | CGEN_INSN_INT insn = entire_insn; | |
1606 | #define FLD(f) abuf->fields.sfmt_seth.f | |
1607 | UINT f_r1; | |
1608 | UINT f_hi16; | |
1609 | ||
1610 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); | |
1611 | f_hi16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); | |
1612 | ||
1613 | /* Record the fields for the semantic handler. */ | |
1614 | FLD (f_hi16) = f_hi16; | |
de8f5985 | 1615 | FLD (f_r1) = f_r1; |
2df3850c | 1616 | FLD (i_dr) = & CPU (h_gr)[f_r1]; |
de8f5985 | 1617 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_seth", "f_hi16 0x%x", 'x', f_hi16, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0)); |
2df3850c JM |
1618 | |
1619 | #if WITH_PROFILE_MODEL_P | |
1620 | /* Record the fields for profiling. */ | |
1621 | if (PROFILE_MODEL_P (current_cpu)) | |
1622 | { | |
1623 | FLD (out_dr) = f_r1; | |
1624 | } | |
1625 | #endif | |
1626 | #undef FLD | |
1627 | return idesc; | |
1628 | } | |
1629 | ||
1630 | extract_sfmt_sll3: | |
1631 | { | |
1632 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
1633 | CGEN_INSN_INT insn = entire_insn; | |
1634 | #define FLD(f) abuf->fields.sfmt_add3.f | |
1635 | UINT f_r1; | |
1636 | UINT f_r2; | |
1637 | INT f_simm16; | |
1638 | ||
1639 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); | |
1640 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); | |
1641 | f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); | |
1642 | ||
1643 | /* Record the fields for the semantic handler. */ | |
1644 | FLD (f_simm16) = f_simm16; | |
de8f5985 DB |
1645 | FLD (f_r2) = f_r2; |
1646 | FLD (f_r1) = f_r1; | |
2df3850c JM |
1647 | FLD (i_sr) = & CPU (h_gr)[f_r2]; |
1648 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
de8f5985 | 1649 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sll3", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); |
2df3850c JM |
1650 | |
1651 | #if WITH_PROFILE_MODEL_P | |
1652 | /* Record the fields for profiling. */ | |
1653 | if (PROFILE_MODEL_P (current_cpu)) | |
1654 | { | |
1655 | FLD (in_sr) = f_r2; | |
1656 | FLD (out_dr) = f_r1; | |
1657 | } | |
1658 | #endif | |
1659 | #undef FLD | |
1660 | return idesc; | |
1661 | } | |
1662 | ||
1663 | extract_sfmt_slli: | |
1664 | { | |
1665 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
1666 | CGEN_INSN_INT insn = entire_insn; | |
1667 | #define FLD(f) abuf->fields.sfmt_slli.f | |
1668 | UINT f_r1; | |
1669 | UINT f_uimm5; | |
1670 | ||
1671 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
1672 | f_uimm5 = EXTRACT_MSB0_UINT (insn, 16, 11, 5); | |
1673 | ||
1674 | /* Record the fields for the semantic handler. */ | |
de8f5985 | 1675 | FLD (f_r1) = f_r1; |
2df3850c JM |
1676 | FLD (f_uimm5) = f_uimm5; |
1677 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
de8f5985 | 1678 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_slli", "f_r1 0x%x", 'x', f_r1, "f_uimm5 0x%x", 'x', f_uimm5, "dr 0x%x", 'x', f_r1, (char *) 0)); |
2df3850c JM |
1679 | |
1680 | #if WITH_PROFILE_MODEL_P | |
1681 | /* Record the fields for profiling. */ | |
1682 | if (PROFILE_MODEL_P (current_cpu)) | |
1683 | { | |
1684 | FLD (in_dr) = f_r1; | |
1685 | FLD (out_dr) = f_r1; | |
1686 | } | |
1687 | #endif | |
1688 | #undef FLD | |
1689 | return idesc; | |
1690 | } | |
1691 | ||
1692 | extract_sfmt_st: | |
1693 | { | |
1694 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
1695 | CGEN_INSN_INT insn = entire_insn; | |
1696 | #define FLD(f) abuf->fields.sfmt_st_plus.f | |
1697 | UINT f_r1; | |
1698 | UINT f_r2; | |
1699 | ||
1700 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
1701 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
1702 | ||
1703 | /* Record the fields for the semantic handler. */ | |
de8f5985 DB |
1704 | FLD (f_r1) = f_r1; |
1705 | FLD (f_r2) = f_r2; | |
2df3850c JM |
1706 | FLD (i_src1) = & CPU (h_gr)[f_r1]; |
1707 | FLD (i_src2) = & CPU (h_gr)[f_r2]; | |
de8f5985 | 1708 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); |
2df3850c JM |
1709 | |
1710 | #if WITH_PROFILE_MODEL_P | |
1711 | /* Record the fields for profiling. */ | |
1712 | if (PROFILE_MODEL_P (current_cpu)) | |
1713 | { | |
1714 | FLD (in_src1) = f_r1; | |
1715 | FLD (in_src2) = f_r2; | |
1716 | } | |
1717 | #endif | |
1718 | #undef FLD | |
1719 | return idesc; | |
1720 | } | |
1721 | ||
1722 | extract_sfmt_st_d: | |
1723 | { | |
1724 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
1725 | CGEN_INSN_INT insn = entire_insn; | |
1726 | #define FLD(f) abuf->fields.sfmt_st_d.f | |
1727 | UINT f_r1; | |
1728 | UINT f_r2; | |
1729 | INT f_simm16; | |
1730 | ||
1731 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); | |
1732 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); | |
1733 | f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); | |
1734 | ||
1735 | /* Record the fields for the semantic handler. */ | |
1736 | FLD (f_simm16) = f_simm16; | |
de8f5985 DB |
1737 | FLD (f_r1) = f_r1; |
1738 | FLD (f_r2) = f_r2; | |
2df3850c JM |
1739 | FLD (i_src1) = & CPU (h_gr)[f_r1]; |
1740 | FLD (i_src2) = & CPU (h_gr)[f_r2]; | |
de8f5985 | 1741 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st_d", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); |
2df3850c JM |
1742 | |
1743 | #if WITH_PROFILE_MODEL_P | |
1744 | /* Record the fields for profiling. */ | |
1745 | if (PROFILE_MODEL_P (current_cpu)) | |
1746 | { | |
1747 | FLD (in_src1) = f_r1; | |
1748 | FLD (in_src2) = f_r2; | |
1749 | } | |
1750 | #endif | |
1751 | #undef FLD | |
1752 | return idesc; | |
1753 | } | |
1754 | ||
1755 | extract_sfmt_stb: | |
1756 | { | |
1757 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
1758 | CGEN_INSN_INT insn = entire_insn; | |
1759 | #define FLD(f) abuf->fields.sfmt_st_plus.f | |
1760 | UINT f_r1; | |
1761 | UINT f_r2; | |
1762 | ||
1763 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
1764 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
1765 | ||
1766 | /* Record the fields for the semantic handler. */ | |
de8f5985 DB |
1767 | FLD (f_r1) = f_r1; |
1768 | FLD (f_r2) = f_r2; | |
2df3850c JM |
1769 | FLD (i_src1) = & CPU (h_gr)[f_r1]; |
1770 | FLD (i_src2) = & CPU (h_gr)[f_r2]; | |
de8f5985 | 1771 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); |
2df3850c JM |
1772 | |
1773 | #if WITH_PROFILE_MODEL_P | |
1774 | /* Record the fields for profiling. */ | |
1775 | if (PROFILE_MODEL_P (current_cpu)) | |
1776 | { | |
1777 | FLD (in_src1) = f_r1; | |
1778 | FLD (in_src2) = f_r2; | |
1779 | } | |
1780 | #endif | |
1781 | #undef FLD | |
1782 | return idesc; | |
1783 | } | |
1784 | ||
1785 | extract_sfmt_stb_d: | |
1786 | { | |
1787 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
1788 | CGEN_INSN_INT insn = entire_insn; | |
1789 | #define FLD(f) abuf->fields.sfmt_st_d.f | |
1790 | UINT f_r1; | |
1791 | UINT f_r2; | |
1792 | INT f_simm16; | |
1793 | ||
1794 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); | |
1795 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); | |
1796 | f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); | |
1797 | ||
1798 | /* Record the fields for the semantic handler. */ | |
1799 | FLD (f_simm16) = f_simm16; | |
de8f5985 DB |
1800 | FLD (f_r1) = f_r1; |
1801 | FLD (f_r2) = f_r2; | |
2df3850c JM |
1802 | FLD (i_src1) = & CPU (h_gr)[f_r1]; |
1803 | FLD (i_src2) = & CPU (h_gr)[f_r2]; | |
de8f5985 | 1804 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb_d", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); |
2df3850c JM |
1805 | |
1806 | #if WITH_PROFILE_MODEL_P | |
1807 | /* Record the fields for profiling. */ | |
1808 | if (PROFILE_MODEL_P (current_cpu)) | |
1809 | { | |
1810 | FLD (in_src1) = f_r1; | |
1811 | FLD (in_src2) = f_r2; | |
1812 | } | |
1813 | #endif | |
1814 | #undef FLD | |
1815 | return idesc; | |
1816 | } | |
1817 | ||
1818 | extract_sfmt_sth: | |
1819 | { | |
1820 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
1821 | CGEN_INSN_INT insn = entire_insn; | |
1822 | #define FLD(f) abuf->fields.sfmt_st_plus.f | |
1823 | UINT f_r1; | |
1824 | UINT f_r2; | |
1825 | ||
1826 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
1827 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
1828 | ||
1829 | /* Record the fields for the semantic handler. */ | |
de8f5985 DB |
1830 | FLD (f_r1) = f_r1; |
1831 | FLD (f_r2) = f_r2; | |
2df3850c JM |
1832 | FLD (i_src1) = & CPU (h_gr)[f_r1]; |
1833 | FLD (i_src2) = & CPU (h_gr)[f_r2]; | |
de8f5985 | 1834 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sth", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); |
2df3850c JM |
1835 | |
1836 | #if WITH_PROFILE_MODEL_P | |
1837 | /* Record the fields for profiling. */ | |
1838 | if (PROFILE_MODEL_P (current_cpu)) | |
1839 | { | |
1840 | FLD (in_src1) = f_r1; | |
1841 | FLD (in_src2) = f_r2; | |
1842 | } | |
1843 | #endif | |
1844 | #undef FLD | |
1845 | return idesc; | |
1846 | } | |
1847 | ||
1848 | extract_sfmt_sth_d: | |
1849 | { | |
1850 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
1851 | CGEN_INSN_INT insn = entire_insn; | |
1852 | #define FLD(f) abuf->fields.sfmt_st_d.f | |
1853 | UINT f_r1; | |
1854 | UINT f_r2; | |
1855 | INT f_simm16; | |
1856 | ||
1857 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); | |
1858 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); | |
1859 | f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); | |
1860 | ||
1861 | /* Record the fields for the semantic handler. */ | |
1862 | FLD (f_simm16) = f_simm16; | |
de8f5985 DB |
1863 | FLD (f_r1) = f_r1; |
1864 | FLD (f_r2) = f_r2; | |
2df3850c JM |
1865 | FLD (i_src1) = & CPU (h_gr)[f_r1]; |
1866 | FLD (i_src2) = & CPU (h_gr)[f_r2]; | |
de8f5985 | 1867 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sth_d", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); |
2df3850c JM |
1868 | |
1869 | #if WITH_PROFILE_MODEL_P | |
1870 | /* Record the fields for profiling. */ | |
1871 | if (PROFILE_MODEL_P (current_cpu)) | |
1872 | { | |
1873 | FLD (in_src1) = f_r1; | |
1874 | FLD (in_src2) = f_r2; | |
1875 | } | |
1876 | #endif | |
1877 | #undef FLD | |
1878 | return idesc; | |
1879 | } | |
1880 | ||
1881 | extract_sfmt_st_plus: | |
1882 | { | |
1883 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
1884 | CGEN_INSN_INT insn = entire_insn; | |
1885 | #define FLD(f) abuf->fields.sfmt_st_plus.f | |
1886 | UINT f_r1; | |
1887 | UINT f_r2; | |
1888 | ||
1889 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
1890 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
1891 | ||
1892 | /* Record the fields for the semantic handler. */ | |
de8f5985 DB |
1893 | FLD (f_r1) = f_r1; |
1894 | FLD (f_r2) = f_r2; | |
2df3850c JM |
1895 | FLD (i_src1) = & CPU (h_gr)[f_r1]; |
1896 | FLD (i_src2) = & CPU (h_gr)[f_r2]; | |
de8f5985 | 1897 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st_plus", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); |
2df3850c JM |
1898 | |
1899 | #if WITH_PROFILE_MODEL_P | |
1900 | /* Record the fields for profiling. */ | |
1901 | if (PROFILE_MODEL_P (current_cpu)) | |
1902 | { | |
1903 | FLD (in_src1) = f_r1; | |
1904 | FLD (in_src2) = f_r2; | |
1905 | FLD (out_src2) = f_r2; | |
1906 | } | |
1907 | #endif | |
1908 | #undef FLD | |
1909 | return idesc; | |
1910 | } | |
1911 | ||
1912 | extract_sfmt_trap: | |
1913 | { | |
1914 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
1915 | CGEN_INSN_INT insn = entire_insn; | |
1916 | #define FLD(f) abuf->fields.sfmt_trap.f | |
1917 | UINT f_uimm4; | |
1918 | ||
1919 | f_uimm4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
1920 | ||
1921 | /* Record the fields for the semantic handler. */ | |
1922 | FLD (f_uimm4) = f_uimm4; | |
1923 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_trap", "f_uimm4 0x%x", 'x', f_uimm4, (char *) 0)); | |
1924 | ||
1925 | #if WITH_PROFILE_MODEL_P | |
1926 | /* Record the fields for profiling. */ | |
1927 | if (PROFILE_MODEL_P (current_cpu)) | |
1928 | { | |
1929 | } | |
1930 | #endif | |
1931 | #undef FLD | |
1932 | return idesc; | |
1933 | } | |
1934 | ||
1935 | extract_sfmt_unlock: | |
1936 | { | |
1937 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
1938 | CGEN_INSN_INT insn = entire_insn; | |
1939 | #define FLD(f) abuf->fields.sfmt_st_plus.f | |
1940 | UINT f_r1; | |
1941 | UINT f_r2; | |
1942 | ||
1943 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
1944 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
1945 | ||
1946 | /* Record the fields for the semantic handler. */ | |
de8f5985 DB |
1947 | FLD (f_r1) = f_r1; |
1948 | FLD (f_r2) = f_r2; | |
2df3850c JM |
1949 | FLD (i_src1) = & CPU (h_gr)[f_r1]; |
1950 | FLD (i_src2) = & CPU (h_gr)[f_r2]; | |
de8f5985 | 1951 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_unlock", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); |
2df3850c JM |
1952 | |
1953 | #if WITH_PROFILE_MODEL_P | |
1954 | /* Record the fields for profiling. */ | |
1955 | if (PROFILE_MODEL_P (current_cpu)) | |
1956 | { | |
1957 | FLD (in_src1) = f_r1; | |
1958 | FLD (in_src2) = f_r2; | |
1959 | } | |
1960 | #endif | |
1961 | #undef FLD | |
1962 | return idesc; | |
1963 | } | |
1964 | ||
1965 | extract_sfmt_satb: | |
1966 | { | |
1967 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
1968 | CGEN_INSN_INT insn = entire_insn; | |
1969 | #define FLD(f) abuf->fields.sfmt_ld_plus.f | |
1970 | UINT f_r1; | |
1971 | UINT f_r2; | |
1972 | ||
1973 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); | |
1974 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); | |
1975 | ||
1976 | /* Record the fields for the semantic handler. */ | |
de8f5985 DB |
1977 | FLD (f_r2) = f_r2; |
1978 | FLD (f_r1) = f_r1; | |
2df3850c JM |
1979 | FLD (i_sr) = & CPU (h_gr)[f_r2]; |
1980 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
de8f5985 | 1981 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_satb", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); |
2df3850c JM |
1982 | |
1983 | #if WITH_PROFILE_MODEL_P | |
1984 | /* Record the fields for profiling. */ | |
1985 | if (PROFILE_MODEL_P (current_cpu)) | |
1986 | { | |
1987 | FLD (in_sr) = f_r2; | |
1988 | FLD (out_dr) = f_r1; | |
1989 | } | |
1990 | #endif | |
1991 | #undef FLD | |
1992 | return idesc; | |
1993 | } | |
1994 | ||
1995 | extract_sfmt_sat: | |
1996 | { | |
1997 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
1998 | CGEN_INSN_INT insn = entire_insn; | |
1999 | #define FLD(f) abuf->fields.sfmt_ld_plus.f | |
2000 | UINT f_r1; | |
2001 | UINT f_r2; | |
2002 | ||
2003 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); | |
2004 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); | |
2005 | ||
2006 | /* Record the fields for the semantic handler. */ | |
de8f5985 DB |
2007 | FLD (f_r2) = f_r2; |
2008 | FLD (f_r1) = f_r1; | |
2df3850c JM |
2009 | FLD (i_sr) = & CPU (h_gr)[f_r2]; |
2010 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
de8f5985 | 2011 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sat", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); |
2df3850c JM |
2012 | |
2013 | #if WITH_PROFILE_MODEL_P | |
2014 | /* Record the fields for profiling. */ | |
2015 | if (PROFILE_MODEL_P (current_cpu)) | |
2016 | { | |
2017 | FLD (in_sr) = f_r2; | |
2018 | FLD (out_dr) = f_r1; | |
2019 | } | |
2020 | #endif | |
2021 | #undef FLD | |
2022 | return idesc; | |
2023 | } | |
2024 | ||
2025 | extract_sfmt_sadd: | |
2026 | { | |
2027 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
2df3850c JM |
2028 | #define FLD(f) abuf->fields.fmt_empty.f |
2029 | ||
2030 | ||
2031 | /* Record the fields for the semantic handler. */ | |
2032 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sadd", (char *) 0)); | |
2033 | ||
2034 | #undef FLD | |
2035 | return idesc; | |
2036 | } | |
2037 | ||
2038 | extract_sfmt_macwu1: | |
2039 | { | |
2040 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
2041 | CGEN_INSN_INT insn = entire_insn; | |
2042 | #define FLD(f) abuf->fields.sfmt_st_plus.f | |
2043 | UINT f_r1; | |
2044 | UINT f_r2; | |
2045 | ||
2046 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
2047 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
2048 | ||
2049 | /* Record the fields for the semantic handler. */ | |
de8f5985 DB |
2050 | FLD (f_r1) = f_r1; |
2051 | FLD (f_r2) = f_r2; | |
2df3850c JM |
2052 | FLD (i_src1) = & CPU (h_gr)[f_r1]; |
2053 | FLD (i_src2) = & CPU (h_gr)[f_r2]; | |
de8f5985 | 2054 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_macwu1", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); |
2df3850c JM |
2055 | |
2056 | #if WITH_PROFILE_MODEL_P | |
2057 | /* Record the fields for profiling. */ | |
2058 | if (PROFILE_MODEL_P (current_cpu)) | |
2059 | { | |
2060 | FLD (in_src1) = f_r1; | |
2061 | FLD (in_src2) = f_r2; | |
2062 | } | |
2063 | #endif | |
2064 | #undef FLD | |
2065 | return idesc; | |
2066 | } | |
2067 | ||
2068 | extract_sfmt_msblo: | |
2069 | { | |
2070 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
2071 | CGEN_INSN_INT insn = entire_insn; | |
2072 | #define FLD(f) abuf->fields.sfmt_st_plus.f | |
2073 | UINT f_r1; | |
2074 | UINT f_r2; | |
2075 | ||
2076 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
2077 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
2078 | ||
2079 | /* Record the fields for the semantic handler. */ | |
de8f5985 DB |
2080 | FLD (f_r1) = f_r1; |
2081 | FLD (f_r2) = f_r2; | |
2df3850c JM |
2082 | FLD (i_src1) = & CPU (h_gr)[f_r1]; |
2083 | FLD (i_src2) = & CPU (h_gr)[f_r2]; | |
de8f5985 | 2084 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_msblo", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); |
2df3850c JM |
2085 | |
2086 | #if WITH_PROFILE_MODEL_P | |
2087 | /* Record the fields for profiling. */ | |
2088 | if (PROFILE_MODEL_P (current_cpu)) | |
2089 | { | |
2090 | FLD (in_src1) = f_r1; | |
2091 | FLD (in_src2) = f_r2; | |
2092 | } | |
2093 | #endif | |
2094 | #undef FLD | |
2095 | return idesc; | |
2096 | } | |
2097 | ||
2098 | extract_sfmt_mulwu1: | |
2099 | { | |
2100 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
2101 | CGEN_INSN_INT insn = entire_insn; | |
2102 | #define FLD(f) abuf->fields.sfmt_st_plus.f | |
2103 | UINT f_r1; | |
2104 | UINT f_r2; | |
2105 | ||
2106 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
2107 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
2108 | ||
2109 | /* Record the fields for the semantic handler. */ | |
de8f5985 DB |
2110 | FLD (f_r1) = f_r1; |
2111 | FLD (f_r2) = f_r2; | |
2df3850c JM |
2112 | FLD (i_src1) = & CPU (h_gr)[f_r1]; |
2113 | FLD (i_src2) = & CPU (h_gr)[f_r2]; | |
de8f5985 | 2114 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mulwu1", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); |
2df3850c JM |
2115 | |
2116 | #if WITH_PROFILE_MODEL_P | |
2117 | /* Record the fields for profiling. */ | |
2118 | if (PROFILE_MODEL_P (current_cpu)) | |
2119 | { | |
2120 | FLD (in_src1) = f_r1; | |
2121 | FLD (in_src2) = f_r2; | |
2122 | } | |
2123 | #endif | |
2124 | #undef FLD | |
2125 | return idesc; | |
2126 | } | |
2127 | ||
2128 | extract_sfmt_sc: | |
2129 | { | |
2130 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
2df3850c JM |
2131 | #define FLD(f) abuf->fields.fmt_empty.f |
2132 | ||
2133 | ||
2134 | /* Record the fields for the semantic handler. */ | |
2135 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sc", (char *) 0)); | |
2136 | ||
2137 | #undef FLD | |
2138 | return idesc; | |
2139 | } | |
2140 | ||
2141 | } |