Commit | Line | Data |
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2df3850c JM |
1 | /* Simulator instruction decoder for m32rxf. |
2 | ||
3 | THIS FILE IS MACHINE GENERATED WITH CGEN. | |
4 | ||
16b47b25 | 5 | Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. |
2df3850c | 6 | |
378af1d6 | 7 | This file is part of the GNU simulators. |
2df3850c JM |
8 | |
9 | This program is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 2, or (at your option) | |
12 | any later version. | |
13 | ||
14 | This program is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License along | |
20 | with this program; if not, write to the Free Software Foundation, Inc., | |
21 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
22 | ||
23 | */ | |
24 | ||
25 | #define WANT_CPU m32rxf | |
26 | #define WANT_CPU_M32RXF | |
27 | ||
28 | #include "sim-main.h" | |
29 | #include "sim-assert.h" | |
30 | ||
31 | /* Insn can't be executed in parallel. | |
32 | Or is that "do NOt Pass to Air defense Radar"? :-) */ | |
33 | #define NOPAR (-1) | |
34 | ||
35 | /* The instruction descriptor array. | |
36 | This is computed at runtime. Space for it is not malloc'd to save a | |
37 | teensy bit of cpu in the decoder. Moving it to malloc space is trivial | |
38 | but won't be done until necessary (we don't currently support the runtime | |
39 | addition of instructions nor an SMP machine with different cpus). */ | |
57465455 | 40 | static IDESC m32rxf_insn_data[M32RXF_INSN__MAX]; |
2df3850c JM |
41 | |
42 | /* Commas between elements are contained in the macros. | |
43 | Some of these are conditionally compiled out. */ | |
44 | ||
45 | static const struct insn_sem m32rxf_insn_sem[] = | |
46 | { | |
47 | { VIRTUAL_INSN_X_INVALID, M32RXF_INSN_X_INVALID, M32RXF_SFMT_EMPTY, NOPAR, NOPAR }, | |
48 | { VIRTUAL_INSN_X_AFTER, M32RXF_INSN_X_AFTER, M32RXF_SFMT_EMPTY, NOPAR, NOPAR }, | |
49 | { VIRTUAL_INSN_X_BEFORE, M32RXF_INSN_X_BEFORE, M32RXF_SFMT_EMPTY, NOPAR, NOPAR }, | |
50 | { VIRTUAL_INSN_X_CTI_CHAIN, M32RXF_INSN_X_CTI_CHAIN, M32RXF_SFMT_EMPTY, NOPAR, NOPAR }, | |
51 | { VIRTUAL_INSN_X_CHAIN, M32RXF_INSN_X_CHAIN, M32RXF_SFMT_EMPTY, NOPAR, NOPAR }, | |
52 | { VIRTUAL_INSN_X_BEGIN, M32RXF_INSN_X_BEGIN, M32RXF_SFMT_EMPTY, NOPAR, NOPAR }, | |
53 | { M32R_INSN_ADD, M32RXF_INSN_ADD, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_ADD, M32RXF_INSN_WRITE_ADD }, | |
54 | { M32R_INSN_ADD3, M32RXF_INSN_ADD3, M32RXF_SFMT_ADD3, NOPAR, NOPAR }, | |
55 | { M32R_INSN_AND, M32RXF_INSN_AND, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_AND, M32RXF_INSN_WRITE_AND }, | |
56 | { M32R_INSN_AND3, M32RXF_INSN_AND3, M32RXF_SFMT_AND3, NOPAR, NOPAR }, | |
57 | { M32R_INSN_OR, M32RXF_INSN_OR, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_OR, M32RXF_INSN_WRITE_OR }, | |
58 | { M32R_INSN_OR3, M32RXF_INSN_OR3, M32RXF_SFMT_OR3, NOPAR, NOPAR }, | |
59 | { M32R_INSN_XOR, M32RXF_INSN_XOR, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_XOR, M32RXF_INSN_WRITE_XOR }, | |
60 | { M32R_INSN_XOR3, M32RXF_INSN_XOR3, M32RXF_SFMT_AND3, NOPAR, NOPAR }, | |
61 | { M32R_INSN_ADDI, M32RXF_INSN_ADDI, M32RXF_SFMT_ADDI, M32RXF_INSN_PAR_ADDI, M32RXF_INSN_WRITE_ADDI }, | |
62 | { M32R_INSN_ADDV, M32RXF_INSN_ADDV, M32RXF_SFMT_ADDV, M32RXF_INSN_PAR_ADDV, M32RXF_INSN_WRITE_ADDV }, | |
63 | { M32R_INSN_ADDV3, M32RXF_INSN_ADDV3, M32RXF_SFMT_ADDV3, NOPAR, NOPAR }, | |
64 | { M32R_INSN_ADDX, M32RXF_INSN_ADDX, M32RXF_SFMT_ADDX, M32RXF_INSN_PAR_ADDX, M32RXF_INSN_WRITE_ADDX }, | |
65 | { M32R_INSN_BC8, M32RXF_INSN_BC8, M32RXF_SFMT_BC8, M32RXF_INSN_PAR_BC8, M32RXF_INSN_WRITE_BC8 }, | |
66 | { M32R_INSN_BC24, M32RXF_INSN_BC24, M32RXF_SFMT_BC24, NOPAR, NOPAR }, | |
67 | { M32R_INSN_BEQ, M32RXF_INSN_BEQ, M32RXF_SFMT_BEQ, NOPAR, NOPAR }, | |
68 | { M32R_INSN_BEQZ, M32RXF_INSN_BEQZ, M32RXF_SFMT_BEQZ, NOPAR, NOPAR }, | |
69 | { M32R_INSN_BGEZ, M32RXF_INSN_BGEZ, M32RXF_SFMT_BEQZ, NOPAR, NOPAR }, | |
70 | { M32R_INSN_BGTZ, M32RXF_INSN_BGTZ, M32RXF_SFMT_BEQZ, NOPAR, NOPAR }, | |
71 | { M32R_INSN_BLEZ, M32RXF_INSN_BLEZ, M32RXF_SFMT_BEQZ, NOPAR, NOPAR }, | |
72 | { M32R_INSN_BLTZ, M32RXF_INSN_BLTZ, M32RXF_SFMT_BEQZ, NOPAR, NOPAR }, | |
73 | { M32R_INSN_BNEZ, M32RXF_INSN_BNEZ, M32RXF_SFMT_BEQZ, NOPAR, NOPAR }, | |
74 | { M32R_INSN_BL8, M32RXF_INSN_BL8, M32RXF_SFMT_BL8, M32RXF_INSN_PAR_BL8, M32RXF_INSN_WRITE_BL8 }, | |
75 | { M32R_INSN_BL24, M32RXF_INSN_BL24, M32RXF_SFMT_BL24, NOPAR, NOPAR }, | |
76 | { M32R_INSN_BCL8, M32RXF_INSN_BCL8, M32RXF_SFMT_BCL8, M32RXF_INSN_PAR_BCL8, M32RXF_INSN_WRITE_BCL8 }, | |
77 | { M32R_INSN_BCL24, M32RXF_INSN_BCL24, M32RXF_SFMT_BCL24, NOPAR, NOPAR }, | |
78 | { M32R_INSN_BNC8, M32RXF_INSN_BNC8, M32RXF_SFMT_BC8, M32RXF_INSN_PAR_BNC8, M32RXF_INSN_WRITE_BNC8 }, | |
79 | { M32R_INSN_BNC24, M32RXF_INSN_BNC24, M32RXF_SFMT_BC24, NOPAR, NOPAR }, | |
80 | { M32R_INSN_BNE, M32RXF_INSN_BNE, M32RXF_SFMT_BEQ, NOPAR, NOPAR }, | |
81 | { M32R_INSN_BRA8, M32RXF_INSN_BRA8, M32RXF_SFMT_BRA8, M32RXF_INSN_PAR_BRA8, M32RXF_INSN_WRITE_BRA8 }, | |
82 | { M32R_INSN_BRA24, M32RXF_INSN_BRA24, M32RXF_SFMT_BRA24, NOPAR, NOPAR }, | |
83 | { M32R_INSN_BNCL8, M32RXF_INSN_BNCL8, M32RXF_SFMT_BCL8, M32RXF_INSN_PAR_BNCL8, M32RXF_INSN_WRITE_BNCL8 }, | |
84 | { M32R_INSN_BNCL24, M32RXF_INSN_BNCL24, M32RXF_SFMT_BCL24, NOPAR, NOPAR }, | |
85 | { M32R_INSN_CMP, M32RXF_INSN_CMP, M32RXF_SFMT_CMP, M32RXF_INSN_PAR_CMP, M32RXF_INSN_WRITE_CMP }, | |
86 | { M32R_INSN_CMPI, M32RXF_INSN_CMPI, M32RXF_SFMT_CMPI, NOPAR, NOPAR }, | |
87 | { M32R_INSN_CMPU, M32RXF_INSN_CMPU, M32RXF_SFMT_CMP, M32RXF_INSN_PAR_CMPU, M32RXF_INSN_WRITE_CMPU }, | |
88 | { M32R_INSN_CMPUI, M32RXF_INSN_CMPUI, M32RXF_SFMT_CMPI, NOPAR, NOPAR }, | |
89 | { M32R_INSN_CMPEQ, M32RXF_INSN_CMPEQ, M32RXF_SFMT_CMP, M32RXF_INSN_PAR_CMPEQ, M32RXF_INSN_WRITE_CMPEQ }, | |
90 | { M32R_INSN_CMPZ, M32RXF_INSN_CMPZ, M32RXF_SFMT_CMPZ, M32RXF_INSN_PAR_CMPZ, M32RXF_INSN_WRITE_CMPZ }, | |
91 | { M32R_INSN_DIV, M32RXF_INSN_DIV, M32RXF_SFMT_DIV, NOPAR, NOPAR }, | |
92 | { M32R_INSN_DIVU, M32RXF_INSN_DIVU, M32RXF_SFMT_DIV, NOPAR, NOPAR }, | |
93 | { M32R_INSN_REM, M32RXF_INSN_REM, M32RXF_SFMT_DIV, NOPAR, NOPAR }, | |
94 | { M32R_INSN_REMU, M32RXF_INSN_REMU, M32RXF_SFMT_DIV, NOPAR, NOPAR }, | |
95 | { M32R_INSN_DIVH, M32RXF_INSN_DIVH, M32RXF_SFMT_DIV, NOPAR, NOPAR }, | |
96 | { M32R_INSN_JC, M32RXF_INSN_JC, M32RXF_SFMT_JC, M32RXF_INSN_PAR_JC, M32RXF_INSN_WRITE_JC }, | |
97 | { M32R_INSN_JNC, M32RXF_INSN_JNC, M32RXF_SFMT_JC, M32RXF_INSN_PAR_JNC, M32RXF_INSN_WRITE_JNC }, | |
98 | { M32R_INSN_JL, M32RXF_INSN_JL, M32RXF_SFMT_JL, M32RXF_INSN_PAR_JL, M32RXF_INSN_WRITE_JL }, | |
99 | { M32R_INSN_JMP, M32RXF_INSN_JMP, M32RXF_SFMT_JMP, M32RXF_INSN_PAR_JMP, M32RXF_INSN_WRITE_JMP }, | |
100 | { M32R_INSN_LD, M32RXF_INSN_LD, M32RXF_SFMT_LD, M32RXF_INSN_PAR_LD, M32RXF_INSN_WRITE_LD }, | |
101 | { M32R_INSN_LD_D, M32RXF_INSN_LD_D, M32RXF_SFMT_LD_D, NOPAR, NOPAR }, | |
378af1d6 DB |
102 | { M32R_INSN_LDB, M32RXF_INSN_LDB, M32RXF_SFMT_LDB, M32RXF_INSN_PAR_LDB, M32RXF_INSN_WRITE_LDB }, |
103 | { M32R_INSN_LDB_D, M32RXF_INSN_LDB_D, M32RXF_SFMT_LDB_D, NOPAR, NOPAR }, | |
104 | { M32R_INSN_LDH, M32RXF_INSN_LDH, M32RXF_SFMT_LDH, M32RXF_INSN_PAR_LDH, M32RXF_INSN_WRITE_LDH }, | |
105 | { M32R_INSN_LDH_D, M32RXF_INSN_LDH_D, M32RXF_SFMT_LDH_D, NOPAR, NOPAR }, | |
106 | { M32R_INSN_LDUB, M32RXF_INSN_LDUB, M32RXF_SFMT_LDB, M32RXF_INSN_PAR_LDUB, M32RXF_INSN_WRITE_LDUB }, | |
107 | { M32R_INSN_LDUB_D, M32RXF_INSN_LDUB_D, M32RXF_SFMT_LDB_D, NOPAR, NOPAR }, | |
108 | { M32R_INSN_LDUH, M32RXF_INSN_LDUH, M32RXF_SFMT_LDH, M32RXF_INSN_PAR_LDUH, M32RXF_INSN_WRITE_LDUH }, | |
109 | { M32R_INSN_LDUH_D, M32RXF_INSN_LDUH_D, M32RXF_SFMT_LDH_D, NOPAR, NOPAR }, | |
2df3850c JM |
110 | { M32R_INSN_LD_PLUS, M32RXF_INSN_LD_PLUS, M32RXF_SFMT_LD_PLUS, M32RXF_INSN_PAR_LD_PLUS, M32RXF_INSN_WRITE_LD_PLUS }, |
111 | { M32R_INSN_LD24, M32RXF_INSN_LD24, M32RXF_SFMT_LD24, NOPAR, NOPAR }, | |
112 | { M32R_INSN_LDI8, M32RXF_INSN_LDI8, M32RXF_SFMT_LDI8, M32RXF_INSN_PAR_LDI8, M32RXF_INSN_WRITE_LDI8 }, | |
113 | { M32R_INSN_LDI16, M32RXF_INSN_LDI16, M32RXF_SFMT_LDI16, NOPAR, NOPAR }, | |
114 | { M32R_INSN_LOCK, M32RXF_INSN_LOCK, M32RXF_SFMT_LOCK, M32RXF_INSN_PAR_LOCK, M32RXF_INSN_WRITE_LOCK }, | |
115 | { M32R_INSN_MACHI_A, M32RXF_INSN_MACHI_A, M32RXF_SFMT_MACHI_A, M32RXF_INSN_PAR_MACHI_A, M32RXF_INSN_WRITE_MACHI_A }, | |
116 | { M32R_INSN_MACLO_A, M32RXF_INSN_MACLO_A, M32RXF_SFMT_MACHI_A, M32RXF_INSN_PAR_MACLO_A, M32RXF_INSN_WRITE_MACLO_A }, | |
117 | { M32R_INSN_MACWHI_A, M32RXF_INSN_MACWHI_A, M32RXF_SFMT_MACHI_A, M32RXF_INSN_PAR_MACWHI_A, M32RXF_INSN_WRITE_MACWHI_A }, | |
118 | { M32R_INSN_MACWLO_A, M32RXF_INSN_MACWLO_A, M32RXF_SFMT_MACHI_A, M32RXF_INSN_PAR_MACWLO_A, M32RXF_INSN_WRITE_MACWLO_A }, | |
119 | { M32R_INSN_MUL, M32RXF_INSN_MUL, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_MUL, M32RXF_INSN_WRITE_MUL }, | |
120 | { M32R_INSN_MULHI_A, M32RXF_INSN_MULHI_A, M32RXF_SFMT_MULHI_A, M32RXF_INSN_PAR_MULHI_A, M32RXF_INSN_WRITE_MULHI_A }, | |
121 | { M32R_INSN_MULLO_A, M32RXF_INSN_MULLO_A, M32RXF_SFMT_MULHI_A, M32RXF_INSN_PAR_MULLO_A, M32RXF_INSN_WRITE_MULLO_A }, | |
122 | { M32R_INSN_MULWHI_A, M32RXF_INSN_MULWHI_A, M32RXF_SFMT_MULHI_A, M32RXF_INSN_PAR_MULWHI_A, M32RXF_INSN_WRITE_MULWHI_A }, | |
123 | { M32R_INSN_MULWLO_A, M32RXF_INSN_MULWLO_A, M32RXF_SFMT_MULHI_A, M32RXF_INSN_PAR_MULWLO_A, M32RXF_INSN_WRITE_MULWLO_A }, | |
124 | { M32R_INSN_MV, M32RXF_INSN_MV, M32RXF_SFMT_MV, M32RXF_INSN_PAR_MV, M32RXF_INSN_WRITE_MV }, | |
125 | { M32R_INSN_MVFACHI_A, M32RXF_INSN_MVFACHI_A, M32RXF_SFMT_MVFACHI_A, M32RXF_INSN_PAR_MVFACHI_A, M32RXF_INSN_WRITE_MVFACHI_A }, | |
126 | { M32R_INSN_MVFACLO_A, M32RXF_INSN_MVFACLO_A, M32RXF_SFMT_MVFACHI_A, M32RXF_INSN_PAR_MVFACLO_A, M32RXF_INSN_WRITE_MVFACLO_A }, | |
127 | { M32R_INSN_MVFACMI_A, M32RXF_INSN_MVFACMI_A, M32RXF_SFMT_MVFACHI_A, M32RXF_INSN_PAR_MVFACMI_A, M32RXF_INSN_WRITE_MVFACMI_A }, | |
128 | { M32R_INSN_MVFC, M32RXF_INSN_MVFC, M32RXF_SFMT_MVFC, M32RXF_INSN_PAR_MVFC, M32RXF_INSN_WRITE_MVFC }, | |
129 | { M32R_INSN_MVTACHI_A, M32RXF_INSN_MVTACHI_A, M32RXF_SFMT_MVTACHI_A, M32RXF_INSN_PAR_MVTACHI_A, M32RXF_INSN_WRITE_MVTACHI_A }, | |
130 | { M32R_INSN_MVTACLO_A, M32RXF_INSN_MVTACLO_A, M32RXF_SFMT_MVTACHI_A, M32RXF_INSN_PAR_MVTACLO_A, M32RXF_INSN_WRITE_MVTACLO_A }, | |
131 | { M32R_INSN_MVTC, M32RXF_INSN_MVTC, M32RXF_SFMT_MVTC, M32RXF_INSN_PAR_MVTC, M32RXF_INSN_WRITE_MVTC }, | |
132 | { M32R_INSN_NEG, M32RXF_INSN_NEG, M32RXF_SFMT_MV, M32RXF_INSN_PAR_NEG, M32RXF_INSN_WRITE_NEG }, | |
133 | { M32R_INSN_NOP, M32RXF_INSN_NOP, M32RXF_SFMT_NOP, M32RXF_INSN_PAR_NOP, M32RXF_INSN_WRITE_NOP }, | |
134 | { M32R_INSN_NOT, M32RXF_INSN_NOT, M32RXF_SFMT_MV, M32RXF_INSN_PAR_NOT, M32RXF_INSN_WRITE_NOT }, | |
135 | { M32R_INSN_RAC_DSI, M32RXF_INSN_RAC_DSI, M32RXF_SFMT_RAC_DSI, M32RXF_INSN_PAR_RAC_DSI, M32RXF_INSN_WRITE_RAC_DSI }, | |
136 | { M32R_INSN_RACH_DSI, M32RXF_INSN_RACH_DSI, M32RXF_SFMT_RAC_DSI, M32RXF_INSN_PAR_RACH_DSI, M32RXF_INSN_WRITE_RACH_DSI }, | |
137 | { M32R_INSN_RTE, M32RXF_INSN_RTE, M32RXF_SFMT_RTE, M32RXF_INSN_PAR_RTE, M32RXF_INSN_WRITE_RTE }, | |
138 | { M32R_INSN_SETH, M32RXF_INSN_SETH, M32RXF_SFMT_SETH, NOPAR, NOPAR }, | |
139 | { M32R_INSN_SLL, M32RXF_INSN_SLL, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_SLL, M32RXF_INSN_WRITE_SLL }, | |
140 | { M32R_INSN_SLL3, M32RXF_INSN_SLL3, M32RXF_SFMT_SLL3, NOPAR, NOPAR }, | |
141 | { M32R_INSN_SLLI, M32RXF_INSN_SLLI, M32RXF_SFMT_SLLI, M32RXF_INSN_PAR_SLLI, M32RXF_INSN_WRITE_SLLI }, | |
142 | { M32R_INSN_SRA, M32RXF_INSN_SRA, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_SRA, M32RXF_INSN_WRITE_SRA }, | |
143 | { M32R_INSN_SRA3, M32RXF_INSN_SRA3, M32RXF_SFMT_SLL3, NOPAR, NOPAR }, | |
144 | { M32R_INSN_SRAI, M32RXF_INSN_SRAI, M32RXF_SFMT_SLLI, M32RXF_INSN_PAR_SRAI, M32RXF_INSN_WRITE_SRAI }, | |
145 | { M32R_INSN_SRL, M32RXF_INSN_SRL, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_SRL, M32RXF_INSN_WRITE_SRL }, | |
146 | { M32R_INSN_SRL3, M32RXF_INSN_SRL3, M32RXF_SFMT_SLL3, NOPAR, NOPAR }, | |
147 | { M32R_INSN_SRLI, M32RXF_INSN_SRLI, M32RXF_SFMT_SLLI, M32RXF_INSN_PAR_SRLI, M32RXF_INSN_WRITE_SRLI }, | |
148 | { M32R_INSN_ST, M32RXF_INSN_ST, M32RXF_SFMT_ST, M32RXF_INSN_PAR_ST, M32RXF_INSN_WRITE_ST }, | |
149 | { M32R_INSN_ST_D, M32RXF_INSN_ST_D, M32RXF_SFMT_ST_D, NOPAR, NOPAR }, | |
150 | { M32R_INSN_STB, M32RXF_INSN_STB, M32RXF_SFMT_STB, M32RXF_INSN_PAR_STB, M32RXF_INSN_WRITE_STB }, | |
151 | { M32R_INSN_STB_D, M32RXF_INSN_STB_D, M32RXF_SFMT_STB_D, NOPAR, NOPAR }, | |
152 | { M32R_INSN_STH, M32RXF_INSN_STH, M32RXF_SFMT_STH, M32RXF_INSN_PAR_STH, M32RXF_INSN_WRITE_STH }, | |
153 | { M32R_INSN_STH_D, M32RXF_INSN_STH_D, M32RXF_SFMT_STH_D, NOPAR, NOPAR }, | |
154 | { M32R_INSN_ST_PLUS, M32RXF_INSN_ST_PLUS, M32RXF_SFMT_ST_PLUS, M32RXF_INSN_PAR_ST_PLUS, M32RXF_INSN_WRITE_ST_PLUS }, | |
16b47b25 NC |
155 | { M32R_INSN_STH_PLUS, M32RXF_INSN_STH_PLUS, M32RXF_SFMT_STH_PLUS, M32RXF_INSN_PAR_STH_PLUS, M32RXF_INSN_WRITE_STH_PLUS }, |
156 | { M32R_INSN_STB_PLUS, M32RXF_INSN_STB_PLUS, M32RXF_SFMT_STB_PLUS, M32RXF_INSN_PAR_STB_PLUS, M32RXF_INSN_WRITE_STB_PLUS }, | |
2df3850c JM |
157 | { M32R_INSN_ST_MINUS, M32RXF_INSN_ST_MINUS, M32RXF_SFMT_ST_PLUS, M32RXF_INSN_PAR_ST_MINUS, M32RXF_INSN_WRITE_ST_MINUS }, |
158 | { M32R_INSN_SUB, M32RXF_INSN_SUB, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_SUB, M32RXF_INSN_WRITE_SUB }, | |
159 | { M32R_INSN_SUBV, M32RXF_INSN_SUBV, M32RXF_SFMT_ADDV, M32RXF_INSN_PAR_SUBV, M32RXF_INSN_WRITE_SUBV }, | |
160 | { M32R_INSN_SUBX, M32RXF_INSN_SUBX, M32RXF_SFMT_ADDX, M32RXF_INSN_PAR_SUBX, M32RXF_INSN_WRITE_SUBX }, | |
161 | { M32R_INSN_TRAP, M32RXF_INSN_TRAP, M32RXF_SFMT_TRAP, M32RXF_INSN_PAR_TRAP, M32RXF_INSN_WRITE_TRAP }, | |
162 | { M32R_INSN_UNLOCK, M32RXF_INSN_UNLOCK, M32RXF_SFMT_UNLOCK, M32RXF_INSN_PAR_UNLOCK, M32RXF_INSN_WRITE_UNLOCK }, | |
163 | { M32R_INSN_SATB, M32RXF_INSN_SATB, M32RXF_SFMT_SATB, NOPAR, NOPAR }, | |
164 | { M32R_INSN_SATH, M32RXF_INSN_SATH, M32RXF_SFMT_SATB, NOPAR, NOPAR }, | |
165 | { M32R_INSN_SAT, M32RXF_INSN_SAT, M32RXF_SFMT_SAT, NOPAR, NOPAR }, | |
166 | { M32R_INSN_PCMPBZ, M32RXF_INSN_PCMPBZ, M32RXF_SFMT_CMPZ, M32RXF_INSN_PAR_PCMPBZ, M32RXF_INSN_WRITE_PCMPBZ }, | |
167 | { M32R_INSN_SADD, M32RXF_INSN_SADD, M32RXF_SFMT_SADD, M32RXF_INSN_PAR_SADD, M32RXF_INSN_WRITE_SADD }, | |
168 | { M32R_INSN_MACWU1, M32RXF_INSN_MACWU1, M32RXF_SFMT_MACWU1, M32RXF_INSN_PAR_MACWU1, M32RXF_INSN_WRITE_MACWU1 }, | |
169 | { M32R_INSN_MSBLO, M32RXF_INSN_MSBLO, M32RXF_SFMT_MSBLO, M32RXF_INSN_PAR_MSBLO, M32RXF_INSN_WRITE_MSBLO }, | |
170 | { M32R_INSN_MULWU1, M32RXF_INSN_MULWU1, M32RXF_SFMT_MULWU1, M32RXF_INSN_PAR_MULWU1, M32RXF_INSN_WRITE_MULWU1 }, | |
171 | { M32R_INSN_MACLH1, M32RXF_INSN_MACLH1, M32RXF_SFMT_MACWU1, M32RXF_INSN_PAR_MACLH1, M32RXF_INSN_WRITE_MACLH1 }, | |
172 | { M32R_INSN_SC, M32RXF_INSN_SC, M32RXF_SFMT_SC, M32RXF_INSN_PAR_SC, M32RXF_INSN_WRITE_SC }, | |
173 | { M32R_INSN_SNC, M32RXF_INSN_SNC, M32RXF_SFMT_SC, M32RXF_INSN_PAR_SNC, M32RXF_INSN_WRITE_SNC }, | |
16b47b25 NC |
174 | { M32R_INSN_CLRPSW, M32RXF_INSN_CLRPSW, M32RXF_SFMT_CLRPSW, M32RXF_INSN_PAR_CLRPSW, M32RXF_INSN_WRITE_CLRPSW }, |
175 | { M32R_INSN_SETPSW, M32RXF_INSN_SETPSW, M32RXF_SFMT_SETPSW, M32RXF_INSN_PAR_SETPSW, M32RXF_INSN_WRITE_SETPSW }, | |
176 | { M32R_INSN_BSET, M32RXF_INSN_BSET, M32RXF_SFMT_BSET, NOPAR, NOPAR }, | |
177 | { M32R_INSN_BCLR, M32RXF_INSN_BCLR, M32RXF_SFMT_BSET, NOPAR, NOPAR }, | |
178 | { M32R_INSN_BTST, M32RXF_INSN_BTST, M32RXF_SFMT_BTST, M32RXF_INSN_PAR_BTST, M32RXF_INSN_WRITE_BTST }, | |
2df3850c JM |
179 | }; |
180 | ||
181 | static const struct insn_sem m32rxf_insn_sem_invalid = { | |
182 | VIRTUAL_INSN_X_INVALID, M32RXF_INSN_X_INVALID, M32RXF_SFMT_EMPTY, NOPAR, NOPAR | |
183 | }; | |
184 | ||
185 | /* Initialize an IDESC from the compile-time computable parts. */ | |
186 | ||
187 | static INLINE void | |
188 | init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t) | |
189 | { | |
190 | const CGEN_INSN *insn_table = CGEN_CPU_INSN_TABLE (CPU_CPU_DESC (cpu))->init_entries; | |
191 | ||
192 | id->num = t->index; | |
193 | id->sfmt = t->sfmt; | |
194 | if ((int) t->type <= 0) | |
195 | id->idata = & cgen_virtual_insn_table[- (int) t->type]; | |
196 | else | |
197 | id->idata = & insn_table[t->type]; | |
198 | id->attrs = CGEN_INSN_ATTRS (id->idata); | |
199 | /* Oh my god, a magic number. */ | |
200 | id->length = CGEN_INSN_BITSIZE (id->idata) / 8; | |
201 | ||
202 | #if WITH_PROFILE_MODEL_P | |
203 | id->timing = & MODEL_TIMING (CPU_MODEL (cpu)) [t->index]; | |
204 | { | |
205 | SIM_DESC sd = CPU_STATE (cpu); | |
206 | SIM_ASSERT (t->index == id->timing->num); | |
207 | } | |
208 | #endif | |
209 | ||
210 | /* Semantic pointers are initialized elsewhere. */ | |
211 | } | |
212 | ||
213 | /* Initialize the instruction descriptor table. */ | |
214 | ||
215 | void | |
216 | m32rxf_init_idesc_table (SIM_CPU *cpu) | |
217 | { | |
218 | IDESC *id,*tabend; | |
219 | const struct insn_sem *t,*tend; | |
57465455 | 220 | int tabsize = M32RXF_INSN__MAX; |
2df3850c JM |
221 | IDESC *table = m32rxf_insn_data; |
222 | ||
223 | memset (table, 0, tabsize * sizeof (IDESC)); | |
224 | ||
225 | /* First set all entries to the `invalid insn'. */ | |
226 | t = & m32rxf_insn_sem_invalid; | |
227 | for (id = table, tabend = table + tabsize; id < tabend; ++id) | |
228 | init_idesc (cpu, id, t); | |
229 | ||
230 | /* Now fill in the values for the chosen cpu. */ | |
231 | for (t = m32rxf_insn_sem, tend = t + sizeof (m32rxf_insn_sem) / sizeof (*t); | |
232 | t != tend; ++t) | |
233 | { | |
234 | init_idesc (cpu, & table[t->index], t); | |
235 | if (t->par_index != NOPAR) | |
236 | { | |
237 | init_idesc (cpu, &table[t->par_index], t); | |
238 | table[t->index].par_idesc = &table[t->par_index]; | |
239 | } | |
240 | if (t->par_index != NOPAR) | |
241 | { | |
242 | init_idesc (cpu, &table[t->write_index], t); | |
243 | table[t->par_index].par_idesc = &table[t->write_index]; | |
244 | } | |
245 | } | |
246 | ||
247 | /* Link the IDESC table into the cpu. */ | |
248 | CPU_IDESC (cpu) = table; | |
249 | } | |
250 | ||
251 | /* Given an instruction, return a pointer to its IDESC entry. */ | |
252 | ||
253 | const IDESC * | |
254 | m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, | |
255 | CGEN_INSN_INT base_insn, CGEN_INSN_INT entire_insn, | |
256 | ARGBUF *abuf) | |
257 | { | |
258 | /* Result of decoder. */ | |
259 | M32RXF_INSN_TYPE itype; | |
260 | ||
261 | { | |
262 | CGEN_INSN_INT insn = base_insn; | |
263 | ||
264 | { | |
265 | unsigned int val = (((insn >> 8) & (15 << 4)) | ((insn >> 4) & (15 << 0))); | |
266 | switch (val) | |
267 | { | |
57465455 DE |
268 | case 0 : itype = M32RXF_INSN_SUBV; goto extract_sfmt_addv; |
269 | case 1 : itype = M32RXF_INSN_SUBX; goto extract_sfmt_addx; | |
270 | case 2 : itype = M32RXF_INSN_SUB; goto extract_sfmt_add; | |
271 | case 3 : itype = M32RXF_INSN_NEG; goto extract_sfmt_mv; | |
272 | case 4 : itype = M32RXF_INSN_CMP; goto extract_sfmt_cmp; | |
273 | case 5 : itype = M32RXF_INSN_CMPU; goto extract_sfmt_cmp; | |
274 | case 6 : itype = M32RXF_INSN_CMPEQ; goto extract_sfmt_cmp; | |
378af1d6 | 275 | case 7 : |
2df3850c | 276 | { |
55552082 | 277 | unsigned int val = (((insn >> 8) & (3 << 0))); |
2df3850c JM |
278 | switch (val) |
279 | { | |
57465455 DE |
280 | case 0 : itype = M32RXF_INSN_CMPZ; goto extract_sfmt_cmpz; |
281 | case 3 : itype = M32RXF_INSN_PCMPBZ; goto extract_sfmt_cmpz; | |
378af1d6 | 282 | default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; |
2df3850c JM |
283 | } |
284 | } | |
57465455 DE |
285 | case 8 : itype = M32RXF_INSN_ADDV; goto extract_sfmt_addv; |
286 | case 9 : itype = M32RXF_INSN_ADDX; goto extract_sfmt_addx; | |
287 | case 10 : itype = M32RXF_INSN_ADD; goto extract_sfmt_add; | |
288 | case 11 : itype = M32RXF_INSN_NOT; goto extract_sfmt_mv; | |
289 | case 12 : itype = M32RXF_INSN_AND; goto extract_sfmt_add; | |
290 | case 13 : itype = M32RXF_INSN_XOR; goto extract_sfmt_add; | |
291 | case 14 : itype = M32RXF_INSN_OR; goto extract_sfmt_add; | |
16b47b25 | 292 | case 15 : itype = M32RXF_INSN_BTST; goto extract_sfmt_btst; |
57465455 DE |
293 | case 16 : itype = M32RXF_INSN_SRL; goto extract_sfmt_add; |
294 | case 18 : itype = M32RXF_INSN_SRA; goto extract_sfmt_add; | |
295 | case 20 : itype = M32RXF_INSN_SLL; goto extract_sfmt_add; | |
296 | case 22 : itype = M32RXF_INSN_MUL; goto extract_sfmt_add; | |
297 | case 24 : itype = M32RXF_INSN_MV; goto extract_sfmt_mv; | |
298 | case 25 : itype = M32RXF_INSN_MVFC; goto extract_sfmt_mvfc; | |
299 | case 26 : itype = M32RXF_INSN_MVTC; goto extract_sfmt_mvtc; | |
378af1d6 | 300 | case 28 : |
2df3850c | 301 | { |
55552082 | 302 | unsigned int val = (((insn >> 8) & (3 << 0))); |
2df3850c JM |
303 | switch (val) |
304 | { | |
57465455 DE |
305 | case 0 : itype = M32RXF_INSN_JC; goto extract_sfmt_jc; |
306 | case 1 : itype = M32RXF_INSN_JNC; goto extract_sfmt_jc; | |
307 | case 2 : itype = M32RXF_INSN_JL; goto extract_sfmt_jl; | |
308 | case 3 : itype = M32RXF_INSN_JMP; goto extract_sfmt_jmp; | |
378af1d6 | 309 | default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; |
2df3850c JM |
310 | } |
311 | } | |
57465455 DE |
312 | case 29 : itype = M32RXF_INSN_RTE; goto extract_sfmt_rte; |
313 | case 31 : itype = M32RXF_INSN_TRAP; goto extract_sfmt_trap; | |
314 | case 32 : itype = M32RXF_INSN_STB; goto extract_sfmt_stb; | |
16b47b25 | 315 | case 33 : itype = M32RXF_INSN_STB_PLUS; goto extract_sfmt_stb_plus; |
57465455 | 316 | case 34 : itype = M32RXF_INSN_STH; goto extract_sfmt_sth; |
16b47b25 | 317 | case 35 : itype = M32RXF_INSN_STH_PLUS; goto extract_sfmt_sth_plus; |
57465455 DE |
318 | case 36 : itype = M32RXF_INSN_ST; goto extract_sfmt_st; |
319 | case 37 : itype = M32RXF_INSN_UNLOCK; goto extract_sfmt_unlock; | |
320 | case 38 : itype = M32RXF_INSN_ST_PLUS; goto extract_sfmt_st_plus; | |
321 | case 39 : itype = M32RXF_INSN_ST_MINUS; goto extract_sfmt_st_plus; | |
322 | case 40 : itype = M32RXF_INSN_LDB; goto extract_sfmt_ldb; | |
323 | case 41 : itype = M32RXF_INSN_LDUB; goto extract_sfmt_ldb; | |
324 | case 42 : itype = M32RXF_INSN_LDH; goto extract_sfmt_ldh; | |
325 | case 43 : itype = M32RXF_INSN_LDUH; goto extract_sfmt_ldh; | |
326 | case 44 : itype = M32RXF_INSN_LD; goto extract_sfmt_ld; | |
327 | case 45 : itype = M32RXF_INSN_LOCK; goto extract_sfmt_lock; | |
328 | case 46 : itype = M32RXF_INSN_LD_PLUS; goto extract_sfmt_ld_plus; | |
378af1d6 | 329 | case 48 : /* fall through */ |
57465455 | 330 | case 56 : itype = M32RXF_INSN_MULHI_A; goto extract_sfmt_mulhi_a; |
378af1d6 | 331 | case 49 : /* fall through */ |
57465455 | 332 | case 57 : itype = M32RXF_INSN_MULLO_A; goto extract_sfmt_mulhi_a; |
378af1d6 | 333 | case 50 : /* fall through */ |
57465455 | 334 | case 58 : itype = M32RXF_INSN_MULWHI_A; goto extract_sfmt_mulhi_a; |
378af1d6 | 335 | case 51 : /* fall through */ |
57465455 | 336 | case 59 : itype = M32RXF_INSN_MULWLO_A; goto extract_sfmt_mulhi_a; |
378af1d6 | 337 | case 52 : /* fall through */ |
57465455 | 338 | case 60 : itype = M32RXF_INSN_MACHI_A; goto extract_sfmt_machi_a; |
378af1d6 | 339 | case 53 : /* fall through */ |
57465455 | 340 | case 61 : itype = M32RXF_INSN_MACLO_A; goto extract_sfmt_machi_a; |
378af1d6 | 341 | case 54 : /* fall through */ |
57465455 | 342 | case 62 : itype = M32RXF_INSN_MACWHI_A; goto extract_sfmt_machi_a; |
378af1d6 | 343 | case 55 : /* fall through */ |
57465455 | 344 | case 63 : itype = M32RXF_INSN_MACWLO_A; goto extract_sfmt_machi_a; |
378af1d6 | 345 | case 64 : /* fall through */ |
2df3850c JM |
346 | case 65 : /* fall through */ |
347 | case 66 : /* fall through */ | |
348 | case 67 : /* fall through */ | |
349 | case 68 : /* fall through */ | |
350 | case 69 : /* fall through */ | |
351 | case 70 : /* fall through */ | |
352 | case 71 : /* fall through */ | |
353 | case 72 : /* fall through */ | |
354 | case 73 : /* fall through */ | |
355 | case 74 : /* fall through */ | |
356 | case 75 : /* fall through */ | |
357 | case 76 : /* fall through */ | |
358 | case 77 : /* fall through */ | |
359 | case 78 : /* fall through */ | |
57465455 | 360 | case 79 : itype = M32RXF_INSN_ADDI; goto extract_sfmt_addi; |
378af1d6 | 361 | case 80 : /* fall through */ |
57465455 | 362 | case 81 : itype = M32RXF_INSN_SRLI; goto extract_sfmt_slli; |
378af1d6 | 363 | case 82 : /* fall through */ |
57465455 | 364 | case 83 : itype = M32RXF_INSN_SRAI; goto extract_sfmt_slli; |
378af1d6 | 365 | case 84 : /* fall through */ |
57465455 | 366 | case 85 : itype = M32RXF_INSN_SLLI; goto extract_sfmt_slli; |
378af1d6 | 367 | case 87 : |
2df3850c | 368 | { |
55552082 | 369 | unsigned int val = (((insn >> 0) & (1 << 0))); |
2df3850c JM |
370 | switch (val) |
371 | { | |
57465455 DE |
372 | case 0 : itype = M32RXF_INSN_MVTACHI_A; goto extract_sfmt_mvtachi_a; |
373 | case 1 : itype = M32RXF_INSN_MVTACLO_A; goto extract_sfmt_mvtachi_a; | |
378af1d6 | 374 | default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; |
2df3850c JM |
375 | } |
376 | } | |
57465455 DE |
377 | case 88 : itype = M32RXF_INSN_RACH_DSI; goto extract_sfmt_rac_dsi; |
378 | case 89 : itype = M32RXF_INSN_RAC_DSI; goto extract_sfmt_rac_dsi; | |
379 | case 90 : itype = M32RXF_INSN_MULWU1; goto extract_sfmt_mulwu1; | |
380 | case 91 : itype = M32RXF_INSN_MACWU1; goto extract_sfmt_macwu1; | |
381 | case 92 : itype = M32RXF_INSN_MACLH1; goto extract_sfmt_macwu1; | |
382 | case 93 : itype = M32RXF_INSN_MSBLO; goto extract_sfmt_msblo; | |
383 | case 94 : itype = M32RXF_INSN_SADD; goto extract_sfmt_sadd; | |
378af1d6 | 384 | case 95 : |
2df3850c JM |
385 | { |
386 | unsigned int val = (((insn >> 0) & (3 << 0))); | |
387 | switch (val) | |
388 | { | |
57465455 DE |
389 | case 0 : itype = M32RXF_INSN_MVFACHI_A; goto extract_sfmt_mvfachi_a; |
390 | case 1 : itype = M32RXF_INSN_MVFACLO_A; goto extract_sfmt_mvfachi_a; | |
391 | case 2 : itype = M32RXF_INSN_MVFACMI_A; goto extract_sfmt_mvfachi_a; | |
378af1d6 | 392 | default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; |
2df3850c JM |
393 | } |
394 | } | |
395 | case 96 : /* fall through */ | |
396 | case 97 : /* fall through */ | |
397 | case 98 : /* fall through */ | |
398 | case 99 : /* fall through */ | |
399 | case 100 : /* fall through */ | |
400 | case 101 : /* fall through */ | |
401 | case 102 : /* fall through */ | |
402 | case 103 : /* fall through */ | |
403 | case 104 : /* fall through */ | |
404 | case 105 : /* fall through */ | |
405 | case 106 : /* fall through */ | |
406 | case 107 : /* fall through */ | |
407 | case 108 : /* fall through */ | |
408 | case 109 : /* fall through */ | |
409 | case 110 : /* fall through */ | |
57465455 | 410 | case 111 : itype = M32RXF_INSN_LDI8; goto extract_sfmt_ldi8; |
378af1d6 | 411 | case 112 : |
2df3850c | 412 | { |
57465455 | 413 | unsigned int val = (((insn >> 7) & (15 << 1)) | ((insn >> 0) & (1 << 0))); |
2df3850c JM |
414 | switch (val) |
415 | { | |
57465455 | 416 | case 0 : itype = M32RXF_INSN_NOP; goto extract_sfmt_nop; |
16b47b25 NC |
417 | case 2 : /* fall through */ |
418 | case 3 : itype = M32RXF_INSN_SETPSW; goto extract_sfmt_setpsw; | |
419 | case 4 : /* fall through */ | |
420 | case 5 : itype = M32RXF_INSN_CLRPSW; goto extract_sfmt_clrpsw; | |
57465455 DE |
421 | case 9 : itype = M32RXF_INSN_SC; goto extract_sfmt_sc; |
422 | case 11 : itype = M32RXF_INSN_SNC; goto extract_sfmt_sc; | |
423 | case 16 : /* fall through */ | |
424 | case 17 : itype = M32RXF_INSN_BCL8; goto extract_sfmt_bcl8; | |
425 | case 18 : /* fall through */ | |
426 | case 19 : itype = M32RXF_INSN_BNCL8; goto extract_sfmt_bcl8; | |
427 | case 24 : /* fall through */ | |
428 | case 25 : itype = M32RXF_INSN_BC8; goto extract_sfmt_bc8; | |
429 | case 26 : /* fall through */ | |
430 | case 27 : itype = M32RXF_INSN_BNC8; goto extract_sfmt_bc8; | |
431 | case 28 : /* fall through */ | |
432 | case 29 : itype = M32RXF_INSN_BL8; goto extract_sfmt_bl8; | |
433 | case 30 : /* fall through */ | |
434 | case 31 : itype = M32RXF_INSN_BRA8; goto extract_sfmt_bra8; | |
378af1d6 | 435 | default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; |
2df3850c JM |
436 | } |
437 | } | |
438 | case 113 : /* fall through */ | |
439 | case 114 : /* fall through */ | |
440 | case 115 : /* fall through */ | |
441 | case 116 : /* fall through */ | |
442 | case 117 : /* fall through */ | |
443 | case 118 : /* fall through */ | |
444 | case 119 : /* fall through */ | |
445 | case 120 : /* fall through */ | |
446 | case 121 : /* fall through */ | |
447 | case 122 : /* fall through */ | |
448 | case 123 : /* fall through */ | |
449 | case 124 : /* fall through */ | |
450 | case 125 : /* fall through */ | |
451 | case 126 : /* fall through */ | |
452 | case 127 : | |
453 | { | |
16b47b25 | 454 | unsigned int val = (((insn >> 8) & (15 << 0))); |
2df3850c JM |
455 | switch (val) |
456 | { | |
16b47b25 NC |
457 | case 1 : itype = M32RXF_INSN_SETPSW; goto extract_sfmt_setpsw; |
458 | case 2 : itype = M32RXF_INSN_CLRPSW; goto extract_sfmt_clrpsw; | |
459 | case 8 : itype = M32RXF_INSN_BCL8; goto extract_sfmt_bcl8; | |
460 | case 9 : itype = M32RXF_INSN_BNCL8; goto extract_sfmt_bcl8; | |
461 | case 12 : itype = M32RXF_INSN_BC8; goto extract_sfmt_bc8; | |
462 | case 13 : itype = M32RXF_INSN_BNC8; goto extract_sfmt_bc8; | |
463 | case 14 : itype = M32RXF_INSN_BL8; goto extract_sfmt_bl8; | |
464 | case 15 : itype = M32RXF_INSN_BRA8; goto extract_sfmt_bra8; | |
378af1d6 | 465 | default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; |
2df3850c JM |
466 | } |
467 | } | |
57465455 DE |
468 | case 132 : itype = M32RXF_INSN_CMPI; goto extract_sfmt_cmpi; |
469 | case 133 : itype = M32RXF_INSN_CMPUI; goto extract_sfmt_cmpi; | |
378af1d6 | 470 | case 134 : |
2df3850c | 471 | { |
55552082 | 472 | unsigned int val = (((insn >> -8) & (3 << 0))); |
2df3850c JM |
473 | switch (val) |
474 | { | |
57465455 DE |
475 | case 0 : itype = M32RXF_INSN_SAT; goto extract_sfmt_sat; |
476 | case 2 : itype = M32RXF_INSN_SATH; goto extract_sfmt_satb; | |
477 | case 3 : itype = M32RXF_INSN_SATB; goto extract_sfmt_satb; | |
378af1d6 | 478 | default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; |
2df3850c JM |
479 | } |
480 | } | |
57465455 DE |
481 | case 136 : itype = M32RXF_INSN_ADDV3; goto extract_sfmt_addv3; |
482 | case 138 : itype = M32RXF_INSN_ADD3; goto extract_sfmt_add3; | |
483 | case 140 : itype = M32RXF_INSN_AND3; goto extract_sfmt_and3; | |
484 | case 141 : itype = M32RXF_INSN_XOR3; goto extract_sfmt_and3; | |
485 | case 142 : itype = M32RXF_INSN_OR3; goto extract_sfmt_or3; | |
378af1d6 | 486 | case 144 : |
2df3850c | 487 | { |
55552082 | 488 | unsigned int val = (((insn >> -12) & (1 << 0))); |
2df3850c JM |
489 | switch (val) |
490 | { | |
57465455 DE |
491 | case 0 : itype = M32RXF_INSN_DIV; goto extract_sfmt_div; |
492 | case 1 : itype = M32RXF_INSN_DIVH; goto extract_sfmt_div; | |
378af1d6 | 493 | default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; |
2df3850c JM |
494 | } |
495 | } | |
57465455 DE |
496 | case 145 : itype = M32RXF_INSN_DIVU; goto extract_sfmt_div; |
497 | case 146 : itype = M32RXF_INSN_REM; goto extract_sfmt_div; | |
498 | case 147 : itype = M32RXF_INSN_REMU; goto extract_sfmt_div; | |
499 | case 152 : itype = M32RXF_INSN_SRL3; goto extract_sfmt_sll3; | |
500 | case 154 : itype = M32RXF_INSN_SRA3; goto extract_sfmt_sll3; | |
501 | case 156 : itype = M32RXF_INSN_SLL3; goto extract_sfmt_sll3; | |
502 | case 159 : itype = M32RXF_INSN_LDI16; goto extract_sfmt_ldi16; | |
503 | case 160 : itype = M32RXF_INSN_STB_D; goto extract_sfmt_stb_d; | |
504 | case 162 : itype = M32RXF_INSN_STH_D; goto extract_sfmt_sth_d; | |
505 | case 164 : itype = M32RXF_INSN_ST_D; goto extract_sfmt_st_d; | |
16b47b25 NC |
506 | case 166 : itype = M32RXF_INSN_BSET; goto extract_sfmt_bset; |
507 | case 167 : itype = M32RXF_INSN_BCLR; goto extract_sfmt_bset; | |
57465455 DE |
508 | case 168 : itype = M32RXF_INSN_LDB_D; goto extract_sfmt_ldb_d; |
509 | case 169 : itype = M32RXF_INSN_LDUB_D; goto extract_sfmt_ldb_d; | |
510 | case 170 : itype = M32RXF_INSN_LDH_D; goto extract_sfmt_ldh_d; | |
511 | case 171 : itype = M32RXF_INSN_LDUH_D; goto extract_sfmt_ldh_d; | |
512 | case 172 : itype = M32RXF_INSN_LD_D; goto extract_sfmt_ld_d; | |
513 | case 176 : itype = M32RXF_INSN_BEQ; goto extract_sfmt_beq; | |
514 | case 177 : itype = M32RXF_INSN_BNE; goto extract_sfmt_beq; | |
515 | case 184 : itype = M32RXF_INSN_BEQZ; goto extract_sfmt_beqz; | |
516 | case 185 : itype = M32RXF_INSN_BNEZ; goto extract_sfmt_beqz; | |
517 | case 186 : itype = M32RXF_INSN_BLTZ; goto extract_sfmt_beqz; | |
518 | case 187 : itype = M32RXF_INSN_BGEZ; goto extract_sfmt_beqz; | |
519 | case 188 : itype = M32RXF_INSN_BLEZ; goto extract_sfmt_beqz; | |
520 | case 189 : itype = M32RXF_INSN_BGTZ; goto extract_sfmt_beqz; | |
521 | case 220 : itype = M32RXF_INSN_SETH; goto extract_sfmt_seth; | |
378af1d6 | 522 | case 224 : /* fall through */ |
2df3850c JM |
523 | case 225 : /* fall through */ |
524 | case 226 : /* fall through */ | |
525 | case 227 : /* fall through */ | |
526 | case 228 : /* fall through */ | |
527 | case 229 : /* fall through */ | |
528 | case 230 : /* fall through */ | |
529 | case 231 : /* fall through */ | |
530 | case 232 : /* fall through */ | |
531 | case 233 : /* fall through */ | |
532 | case 234 : /* fall through */ | |
533 | case 235 : /* fall through */ | |
534 | case 236 : /* fall through */ | |
535 | case 237 : /* fall through */ | |
536 | case 238 : /* fall through */ | |
57465455 | 537 | case 239 : itype = M32RXF_INSN_LD24; goto extract_sfmt_ld24; |
378af1d6 | 538 | case 240 : /* fall through */ |
2df3850c JM |
539 | case 241 : /* fall through */ |
540 | case 242 : /* fall through */ | |
541 | case 243 : /* fall through */ | |
542 | case 244 : /* fall through */ | |
543 | case 245 : /* fall through */ | |
544 | case 246 : /* fall through */ | |
545 | case 247 : /* fall through */ | |
546 | case 248 : /* fall through */ | |
547 | case 249 : /* fall through */ | |
548 | case 250 : /* fall through */ | |
549 | case 251 : /* fall through */ | |
550 | case 252 : /* fall through */ | |
551 | case 253 : /* fall through */ | |
552 | case 254 : /* fall through */ | |
553 | case 255 : | |
554 | { | |
55552082 | 555 | unsigned int val = (((insn >> 8) & (7 << 0))); |
2df3850c JM |
556 | switch (val) |
557 | { | |
57465455 DE |
558 | case 0 : itype = M32RXF_INSN_BCL24; goto extract_sfmt_bcl24; |
559 | case 1 : itype = M32RXF_INSN_BNCL24; goto extract_sfmt_bcl24; | |
560 | case 4 : itype = M32RXF_INSN_BC24; goto extract_sfmt_bc24; | |
561 | case 5 : itype = M32RXF_INSN_BNC24; goto extract_sfmt_bc24; | |
562 | case 6 : itype = M32RXF_INSN_BL24; goto extract_sfmt_bl24; | |
563 | case 7 : itype = M32RXF_INSN_BRA24; goto extract_sfmt_bra24; | |
378af1d6 | 564 | default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; |
2df3850c JM |
565 | } |
566 | } | |
567 | default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; | |
568 | } | |
569 | } | |
570 | } | |
571 | ||
572 | /* The instruction has been decoded, now extract the fields. */ | |
573 | ||
574 | extract_sfmt_empty: | |
575 | { | |
576 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
2df3850c JM |
577 | #define FLD(f) abuf->fields.fmt_empty.f |
578 | ||
579 | ||
580 | /* Record the fields for the semantic handler. */ | |
581 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_empty", (char *) 0)); | |
582 | ||
583 | #undef FLD | |
584 | return idesc; | |
585 | } | |
586 | ||
587 | extract_sfmt_add: | |
588 | { | |
589 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
590 | CGEN_INSN_INT insn = entire_insn; | |
591 | #define FLD(f) abuf->fields.sfmt_add.f | |
592 | UINT f_r1; | |
593 | UINT f_r2; | |
594 | ||
595 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
596 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
597 | ||
598 | /* Record the fields for the semantic handler. */ | |
de8f5985 DB |
599 | FLD (f_r1) = f_r1; |
600 | FLD (f_r2) = f_r2; | |
2df3850c JM |
601 | FLD (i_dr) = & CPU (h_gr)[f_r1]; |
602 | FLD (i_sr) = & CPU (h_gr)[f_r2]; | |
de8f5985 | 603 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0)); |
2df3850c JM |
604 | |
605 | #if WITH_PROFILE_MODEL_P | |
606 | /* Record the fields for profiling. */ | |
607 | if (PROFILE_MODEL_P (current_cpu)) | |
608 | { | |
609 | FLD (in_dr) = f_r1; | |
610 | FLD (in_sr) = f_r2; | |
611 | FLD (out_dr) = f_r1; | |
612 | } | |
613 | #endif | |
614 | #undef FLD | |
615 | return idesc; | |
616 | } | |
617 | ||
618 | extract_sfmt_add3: | |
619 | { | |
620 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
621 | CGEN_INSN_INT insn = entire_insn; | |
622 | #define FLD(f) abuf->fields.sfmt_add3.f | |
623 | UINT f_r1; | |
624 | UINT f_r2; | |
625 | INT f_simm16; | |
626 | ||
627 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); | |
628 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); | |
629 | f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); | |
630 | ||
631 | /* Record the fields for the semantic handler. */ | |
632 | FLD (f_simm16) = f_simm16; | |
de8f5985 DB |
633 | FLD (f_r2) = f_r2; |
634 | FLD (f_r1) = f_r1; | |
2df3850c JM |
635 | FLD (i_sr) = & CPU (h_gr)[f_r2]; |
636 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
de8f5985 | 637 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add3", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); |
2df3850c JM |
638 | |
639 | #if WITH_PROFILE_MODEL_P | |
640 | /* Record the fields for profiling. */ | |
641 | if (PROFILE_MODEL_P (current_cpu)) | |
642 | { | |
643 | FLD (in_sr) = f_r2; | |
644 | FLD (out_dr) = f_r1; | |
645 | } | |
646 | #endif | |
647 | #undef FLD | |
648 | return idesc; | |
649 | } | |
650 | ||
651 | extract_sfmt_and3: | |
652 | { | |
653 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
654 | CGEN_INSN_INT insn = entire_insn; | |
655 | #define FLD(f) abuf->fields.sfmt_and3.f | |
656 | UINT f_r1; | |
657 | UINT f_r2; | |
658 | UINT f_uimm16; | |
659 | ||
660 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); | |
661 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); | |
662 | f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); | |
663 | ||
664 | /* Record the fields for the semantic handler. */ | |
de8f5985 | 665 | FLD (f_r2) = f_r2; |
2df3850c | 666 | FLD (f_uimm16) = f_uimm16; |
de8f5985 | 667 | FLD (f_r1) = f_r1; |
2df3850c JM |
668 | FLD (i_sr) = & CPU (h_gr)[f_r2]; |
669 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
de8f5985 | 670 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_and3", "f_r2 0x%x", 'x', f_r2, "f_uimm16 0x%x", 'x', f_uimm16, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); |
2df3850c JM |
671 | |
672 | #if WITH_PROFILE_MODEL_P | |
673 | /* Record the fields for profiling. */ | |
674 | if (PROFILE_MODEL_P (current_cpu)) | |
675 | { | |
676 | FLD (in_sr) = f_r2; | |
677 | FLD (out_dr) = f_r1; | |
678 | } | |
679 | #endif | |
680 | #undef FLD | |
681 | return idesc; | |
682 | } | |
683 | ||
684 | extract_sfmt_or3: | |
685 | { | |
686 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
687 | CGEN_INSN_INT insn = entire_insn; | |
688 | #define FLD(f) abuf->fields.sfmt_and3.f | |
689 | UINT f_r1; | |
690 | UINT f_r2; | |
691 | UINT f_uimm16; | |
692 | ||
693 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); | |
694 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); | |
695 | f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); | |
696 | ||
697 | /* Record the fields for the semantic handler. */ | |
de8f5985 | 698 | FLD (f_r2) = f_r2; |
2df3850c | 699 | FLD (f_uimm16) = f_uimm16; |
de8f5985 | 700 | FLD (f_r1) = f_r1; |
2df3850c JM |
701 | FLD (i_sr) = & CPU (h_gr)[f_r2]; |
702 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
de8f5985 | 703 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_or3", "f_r2 0x%x", 'x', f_r2, "f_uimm16 0x%x", 'x', f_uimm16, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); |
2df3850c JM |
704 | |
705 | #if WITH_PROFILE_MODEL_P | |
706 | /* Record the fields for profiling. */ | |
707 | if (PROFILE_MODEL_P (current_cpu)) | |
708 | { | |
709 | FLD (in_sr) = f_r2; | |
710 | FLD (out_dr) = f_r1; | |
711 | } | |
712 | #endif | |
713 | #undef FLD | |
714 | return idesc; | |
715 | } | |
716 | ||
717 | extract_sfmt_addi: | |
718 | { | |
719 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
720 | CGEN_INSN_INT insn = entire_insn; | |
721 | #define FLD(f) abuf->fields.sfmt_addi.f | |
722 | UINT f_r1; | |
723 | INT f_simm8; | |
724 | ||
725 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
726 | f_simm8 = EXTRACT_MSB0_INT (insn, 16, 8, 8); | |
727 | ||
728 | /* Record the fields for the semantic handler. */ | |
de8f5985 | 729 | FLD (f_r1) = f_r1; |
2df3850c JM |
730 | FLD (f_simm8) = f_simm8; |
731 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
de8f5985 | 732 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addi", "f_r1 0x%x", 'x', f_r1, "f_simm8 0x%x", 'x', f_simm8, "dr 0x%x", 'x', f_r1, (char *) 0)); |
2df3850c JM |
733 | |
734 | #if WITH_PROFILE_MODEL_P | |
735 | /* Record the fields for profiling. */ | |
736 | if (PROFILE_MODEL_P (current_cpu)) | |
737 | { | |
738 | FLD (in_dr) = f_r1; | |
739 | FLD (out_dr) = f_r1; | |
740 | } | |
741 | #endif | |
742 | #undef FLD | |
743 | return idesc; | |
744 | } | |
745 | ||
746 | extract_sfmt_addv: | |
747 | { | |
748 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
749 | CGEN_INSN_INT insn = entire_insn; | |
750 | #define FLD(f) abuf->fields.sfmt_add.f | |
751 | UINT f_r1; | |
752 | UINT f_r2; | |
753 | ||
754 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
755 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
756 | ||
757 | /* Record the fields for the semantic handler. */ | |
de8f5985 DB |
758 | FLD (f_r1) = f_r1; |
759 | FLD (f_r2) = f_r2; | |
2df3850c JM |
760 | FLD (i_dr) = & CPU (h_gr)[f_r1]; |
761 | FLD (i_sr) = & CPU (h_gr)[f_r2]; | |
de8f5985 | 762 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addv", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0)); |
2df3850c JM |
763 | |
764 | #if WITH_PROFILE_MODEL_P | |
765 | /* Record the fields for profiling. */ | |
766 | if (PROFILE_MODEL_P (current_cpu)) | |
767 | { | |
768 | FLD (in_dr) = f_r1; | |
769 | FLD (in_sr) = f_r2; | |
770 | FLD (out_dr) = f_r1; | |
771 | } | |
772 | #endif | |
773 | #undef FLD | |
774 | return idesc; | |
775 | } | |
776 | ||
777 | extract_sfmt_addv3: | |
778 | { | |
779 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
780 | CGEN_INSN_INT insn = entire_insn; | |
781 | #define FLD(f) abuf->fields.sfmt_add3.f | |
782 | UINT f_r1; | |
783 | UINT f_r2; | |
784 | INT f_simm16; | |
785 | ||
786 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); | |
787 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); | |
788 | f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); | |
789 | ||
790 | /* Record the fields for the semantic handler. */ | |
791 | FLD (f_simm16) = f_simm16; | |
de8f5985 DB |
792 | FLD (f_r2) = f_r2; |
793 | FLD (f_r1) = f_r1; | |
2df3850c JM |
794 | FLD (i_sr) = & CPU (h_gr)[f_r2]; |
795 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
de8f5985 | 796 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addv3", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); |
2df3850c JM |
797 | |
798 | #if WITH_PROFILE_MODEL_P | |
799 | /* Record the fields for profiling. */ | |
800 | if (PROFILE_MODEL_P (current_cpu)) | |
801 | { | |
802 | FLD (in_sr) = f_r2; | |
803 | FLD (out_dr) = f_r1; | |
804 | } | |
805 | #endif | |
806 | #undef FLD | |
807 | return idesc; | |
808 | } | |
809 | ||
810 | extract_sfmt_addx: | |
811 | { | |
812 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
813 | CGEN_INSN_INT insn = entire_insn; | |
814 | #define FLD(f) abuf->fields.sfmt_add.f | |
815 | UINT f_r1; | |
816 | UINT f_r2; | |
817 | ||
818 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
819 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
820 | ||
821 | /* Record the fields for the semantic handler. */ | |
de8f5985 DB |
822 | FLD (f_r1) = f_r1; |
823 | FLD (f_r2) = f_r2; | |
2df3850c JM |
824 | FLD (i_dr) = & CPU (h_gr)[f_r1]; |
825 | FLD (i_sr) = & CPU (h_gr)[f_r2]; | |
de8f5985 | 826 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addx", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0)); |
2df3850c JM |
827 | |
828 | #if WITH_PROFILE_MODEL_P | |
829 | /* Record the fields for profiling. */ | |
830 | if (PROFILE_MODEL_P (current_cpu)) | |
831 | { | |
832 | FLD (in_dr) = f_r1; | |
833 | FLD (in_sr) = f_r2; | |
834 | FLD (out_dr) = f_r1; | |
835 | } | |
836 | #endif | |
837 | #undef FLD | |
838 | return idesc; | |
839 | } | |
840 | ||
841 | extract_sfmt_bc8: | |
842 | { | |
843 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
844 | CGEN_INSN_INT insn = entire_insn; | |
845 | #define FLD(f) abuf->fields.sfmt_bl8.f | |
846 | SI f_disp8; | |
847 | ||
848 | f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); | |
849 | ||
850 | /* Record the fields for the semantic handler. */ | |
851 | FLD (i_disp8) = f_disp8; | |
852 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bc8", "disp8 0x%x", 'x', f_disp8, (char *) 0)); | |
853 | ||
854 | #if WITH_PROFILE_MODEL_P | |
855 | /* Record the fields for profiling. */ | |
856 | if (PROFILE_MODEL_P (current_cpu)) | |
857 | { | |
858 | } | |
859 | #endif | |
860 | #undef FLD | |
861 | return idesc; | |
862 | } | |
863 | ||
864 | extract_sfmt_bc24: | |
865 | { | |
866 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
867 | CGEN_INSN_INT insn = entire_insn; | |
868 | #define FLD(f) abuf->fields.sfmt_bl24.f | |
869 | SI f_disp24; | |
870 | ||
871 | f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc)); | |
872 | ||
873 | /* Record the fields for the semantic handler. */ | |
874 | FLD (i_disp24) = f_disp24; | |
875 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bc24", "disp24 0x%x", 'x', f_disp24, (char *) 0)); | |
876 | ||
877 | #if WITH_PROFILE_MODEL_P | |
878 | /* Record the fields for profiling. */ | |
879 | if (PROFILE_MODEL_P (current_cpu)) | |
880 | { | |
881 | } | |
882 | #endif | |
883 | #undef FLD | |
884 | return idesc; | |
885 | } | |
886 | ||
887 | extract_sfmt_beq: | |
888 | { | |
889 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
890 | CGEN_INSN_INT insn = entire_insn; | |
891 | #define FLD(f) abuf->fields.sfmt_beq.f | |
892 | UINT f_r1; | |
893 | UINT f_r2; | |
894 | SI f_disp16; | |
895 | ||
896 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); | |
897 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); | |
898 | f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc)); | |
899 | ||
900 | /* Record the fields for the semantic handler. */ | |
de8f5985 DB |
901 | FLD (f_r1) = f_r1; |
902 | FLD (f_r2) = f_r2; | |
2df3850c JM |
903 | FLD (i_disp16) = f_disp16; |
904 | FLD (i_src1) = & CPU (h_gr)[f_r1]; | |
905 | FLD (i_src2) = & CPU (h_gr)[f_r2]; | |
de8f5985 | 906 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_beq", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "disp16 0x%x", 'x', f_disp16, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); |
2df3850c JM |
907 | |
908 | #if WITH_PROFILE_MODEL_P | |
909 | /* Record the fields for profiling. */ | |
910 | if (PROFILE_MODEL_P (current_cpu)) | |
911 | { | |
912 | FLD (in_src1) = f_r1; | |
913 | FLD (in_src2) = f_r2; | |
914 | } | |
915 | #endif | |
916 | #undef FLD | |
917 | return idesc; | |
918 | } | |
919 | ||
920 | extract_sfmt_beqz: | |
921 | { | |
922 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
923 | CGEN_INSN_INT insn = entire_insn; | |
924 | #define FLD(f) abuf->fields.sfmt_beq.f | |
925 | UINT f_r2; | |
926 | SI f_disp16; | |
927 | ||
928 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); | |
929 | f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc)); | |
930 | ||
931 | /* Record the fields for the semantic handler. */ | |
de8f5985 | 932 | FLD (f_r2) = f_r2; |
2df3850c JM |
933 | FLD (i_disp16) = f_disp16; |
934 | FLD (i_src2) = & CPU (h_gr)[f_r2]; | |
de8f5985 | 935 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_beqz", "f_r2 0x%x", 'x', f_r2, "disp16 0x%x", 'x', f_disp16, "src2 0x%x", 'x', f_r2, (char *) 0)); |
2df3850c JM |
936 | |
937 | #if WITH_PROFILE_MODEL_P | |
938 | /* Record the fields for profiling. */ | |
939 | if (PROFILE_MODEL_P (current_cpu)) | |
940 | { | |
941 | FLD (in_src2) = f_r2; | |
942 | } | |
943 | #endif | |
944 | #undef FLD | |
945 | return idesc; | |
946 | } | |
947 | ||
948 | extract_sfmt_bl8: | |
949 | { | |
950 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
951 | CGEN_INSN_INT insn = entire_insn; | |
952 | #define FLD(f) abuf->fields.sfmt_bl8.f | |
953 | SI f_disp8; | |
954 | ||
955 | f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); | |
956 | ||
957 | /* Record the fields for the semantic handler. */ | |
958 | FLD (i_disp8) = f_disp8; | |
959 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bl8", "disp8 0x%x", 'x', f_disp8, (char *) 0)); | |
960 | ||
961 | #if WITH_PROFILE_MODEL_P | |
962 | /* Record the fields for profiling. */ | |
963 | if (PROFILE_MODEL_P (current_cpu)) | |
964 | { | |
378af1d6 | 965 | FLD (out_h_gr_SI_14) = 14; |
2df3850c JM |
966 | } |
967 | #endif | |
968 | #undef FLD | |
969 | return idesc; | |
970 | } | |
971 | ||
972 | extract_sfmt_bl24: | |
973 | { | |
974 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
975 | CGEN_INSN_INT insn = entire_insn; | |
976 | #define FLD(f) abuf->fields.sfmt_bl24.f | |
977 | SI f_disp24; | |
978 | ||
979 | f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc)); | |
980 | ||
981 | /* Record the fields for the semantic handler. */ | |
982 | FLD (i_disp24) = f_disp24; | |
983 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bl24", "disp24 0x%x", 'x', f_disp24, (char *) 0)); | |
984 | ||
985 | #if WITH_PROFILE_MODEL_P | |
986 | /* Record the fields for profiling. */ | |
987 | if (PROFILE_MODEL_P (current_cpu)) | |
988 | { | |
378af1d6 | 989 | FLD (out_h_gr_SI_14) = 14; |
2df3850c JM |
990 | } |
991 | #endif | |
992 | #undef FLD | |
993 | return idesc; | |
994 | } | |
995 | ||
996 | extract_sfmt_bcl8: | |
997 | { | |
998 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
999 | CGEN_INSN_INT insn = entire_insn; | |
1000 | #define FLD(f) abuf->fields.sfmt_bl8.f | |
1001 | SI f_disp8; | |
1002 | ||
1003 | f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); | |
1004 | ||
1005 | /* Record the fields for the semantic handler. */ | |
1006 | FLD (i_disp8) = f_disp8; | |
1007 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bcl8", "disp8 0x%x", 'x', f_disp8, (char *) 0)); | |
1008 | ||
1009 | #if WITH_PROFILE_MODEL_P | |
1010 | /* Record the fields for profiling. */ | |
1011 | if (PROFILE_MODEL_P (current_cpu)) | |
1012 | { | |
378af1d6 | 1013 | FLD (out_h_gr_SI_14) = 14; |
2df3850c JM |
1014 | } |
1015 | #endif | |
1016 | #undef FLD | |
1017 | return idesc; | |
1018 | } | |
1019 | ||
1020 | extract_sfmt_bcl24: | |
1021 | { | |
1022 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
1023 | CGEN_INSN_INT insn = entire_insn; | |
1024 | #define FLD(f) abuf->fields.sfmt_bl24.f | |
1025 | SI f_disp24; | |
1026 | ||
1027 | f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc)); | |
1028 | ||
1029 | /* Record the fields for the semantic handler. */ | |
1030 | FLD (i_disp24) = f_disp24; | |
1031 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bcl24", "disp24 0x%x", 'x', f_disp24, (char *) 0)); | |
1032 | ||
1033 | #if WITH_PROFILE_MODEL_P | |
1034 | /* Record the fields for profiling. */ | |
1035 | if (PROFILE_MODEL_P (current_cpu)) | |
1036 | { | |
378af1d6 | 1037 | FLD (out_h_gr_SI_14) = 14; |
2df3850c JM |
1038 | } |
1039 | #endif | |
1040 | #undef FLD | |
1041 | return idesc; | |
1042 | } | |
1043 | ||
1044 | extract_sfmt_bra8: | |
1045 | { | |
1046 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
1047 | CGEN_INSN_INT insn = entire_insn; | |
1048 | #define FLD(f) abuf->fields.sfmt_bl8.f | |
1049 | SI f_disp8; | |
1050 | ||
1051 | f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); | |
1052 | ||
1053 | /* Record the fields for the semantic handler. */ | |
1054 | FLD (i_disp8) = f_disp8; | |
1055 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bra8", "disp8 0x%x", 'x', f_disp8, (char *) 0)); | |
1056 | ||
1057 | #if WITH_PROFILE_MODEL_P | |
1058 | /* Record the fields for profiling. */ | |
1059 | if (PROFILE_MODEL_P (current_cpu)) | |
1060 | { | |
1061 | } | |
1062 | #endif | |
1063 | #undef FLD | |
1064 | return idesc; | |
1065 | } | |
1066 | ||
1067 | extract_sfmt_bra24: | |
1068 | { | |
1069 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
1070 | CGEN_INSN_INT insn = entire_insn; | |
1071 | #define FLD(f) abuf->fields.sfmt_bl24.f | |
1072 | SI f_disp24; | |
1073 | ||
1074 | f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc)); | |
1075 | ||
1076 | /* Record the fields for the semantic handler. */ | |
1077 | FLD (i_disp24) = f_disp24; | |
1078 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bra24", "disp24 0x%x", 'x', f_disp24, (char *) 0)); | |
1079 | ||
1080 | #if WITH_PROFILE_MODEL_P | |
1081 | /* Record the fields for profiling. */ | |
1082 | if (PROFILE_MODEL_P (current_cpu)) | |
1083 | { | |
1084 | } | |
1085 | #endif | |
1086 | #undef FLD | |
1087 | return idesc; | |
1088 | } | |
1089 | ||
1090 | extract_sfmt_cmp: | |
1091 | { | |
1092 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
1093 | CGEN_INSN_INT insn = entire_insn; | |
1094 | #define FLD(f) abuf->fields.sfmt_st_plus.f | |
1095 | UINT f_r1; | |
1096 | UINT f_r2; | |
1097 | ||
1098 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
1099 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
1100 | ||
1101 | /* Record the fields for the semantic handler. */ | |
de8f5985 DB |
1102 | FLD (f_r1) = f_r1; |
1103 | FLD (f_r2) = f_r2; | |
2df3850c JM |
1104 | FLD (i_src1) = & CPU (h_gr)[f_r1]; |
1105 | FLD (i_src2) = & CPU (h_gr)[f_r2]; | |
de8f5985 | 1106 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmp", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); |
2df3850c JM |
1107 | |
1108 | #if WITH_PROFILE_MODEL_P | |
1109 | /* Record the fields for profiling. */ | |
1110 | if (PROFILE_MODEL_P (current_cpu)) | |
1111 | { | |
1112 | FLD (in_src1) = f_r1; | |
1113 | FLD (in_src2) = f_r2; | |
1114 | } | |
1115 | #endif | |
1116 | #undef FLD | |
1117 | return idesc; | |
1118 | } | |
1119 | ||
1120 | extract_sfmt_cmpi: | |
1121 | { | |
1122 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
1123 | CGEN_INSN_INT insn = entire_insn; | |
1124 | #define FLD(f) abuf->fields.sfmt_st_d.f | |
1125 | UINT f_r2; | |
1126 | INT f_simm16; | |
1127 | ||
1128 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); | |
1129 | f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); | |
1130 | ||
1131 | /* Record the fields for the semantic handler. */ | |
1132 | FLD (f_simm16) = f_simm16; | |
de8f5985 | 1133 | FLD (f_r2) = f_r2; |
2df3850c | 1134 | FLD (i_src2) = & CPU (h_gr)[f_r2]; |
de8f5985 | 1135 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpi", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "src2 0x%x", 'x', f_r2, (char *) 0)); |
2df3850c JM |
1136 | |
1137 | #if WITH_PROFILE_MODEL_P | |
1138 | /* Record the fields for profiling. */ | |
1139 | if (PROFILE_MODEL_P (current_cpu)) | |
1140 | { | |
1141 | FLD (in_src2) = f_r2; | |
1142 | } | |
1143 | #endif | |
1144 | #undef FLD | |
1145 | return idesc; | |
1146 | } | |
1147 | ||
1148 | extract_sfmt_cmpz: | |
1149 | { | |
1150 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
1151 | CGEN_INSN_INT insn = entire_insn; | |
1152 | #define FLD(f) abuf->fields.sfmt_st_plus.f | |
1153 | UINT f_r2; | |
1154 | ||
1155 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
1156 | ||
1157 | /* Record the fields for the semantic handler. */ | |
de8f5985 | 1158 | FLD (f_r2) = f_r2; |
2df3850c | 1159 | FLD (i_src2) = & CPU (h_gr)[f_r2]; |
de8f5985 | 1160 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpz", "f_r2 0x%x", 'x', f_r2, "src2 0x%x", 'x', f_r2, (char *) 0)); |
2df3850c JM |
1161 | |
1162 | #if WITH_PROFILE_MODEL_P | |
1163 | /* Record the fields for profiling. */ | |
1164 | if (PROFILE_MODEL_P (current_cpu)) | |
1165 | { | |
1166 | FLD (in_src2) = f_r2; | |
1167 | } | |
1168 | #endif | |
1169 | #undef FLD | |
1170 | return idesc; | |
1171 | } | |
1172 | ||
1173 | extract_sfmt_div: | |
1174 | { | |
1175 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
1176 | CGEN_INSN_INT insn = entire_insn; | |
1177 | #define FLD(f) abuf->fields.sfmt_add.f | |
1178 | UINT f_r1; | |
1179 | UINT f_r2; | |
1180 | ||
1181 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); | |
1182 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); | |
1183 | ||
1184 | /* Record the fields for the semantic handler. */ | |
de8f5985 DB |
1185 | FLD (f_r1) = f_r1; |
1186 | FLD (f_r2) = f_r2; | |
2df3850c JM |
1187 | FLD (i_dr) = & CPU (h_gr)[f_r1]; |
1188 | FLD (i_sr) = & CPU (h_gr)[f_r2]; | |
de8f5985 | 1189 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_div", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0)); |
2df3850c JM |
1190 | |
1191 | #if WITH_PROFILE_MODEL_P | |
1192 | /* Record the fields for profiling. */ | |
1193 | if (PROFILE_MODEL_P (current_cpu)) | |
1194 | { | |
1195 | FLD (in_dr) = f_r1; | |
1196 | FLD (in_sr) = f_r2; | |
1197 | FLD (out_dr) = f_r1; | |
1198 | } | |
1199 | #endif | |
1200 | #undef FLD | |
1201 | return idesc; | |
1202 | } | |
1203 | ||
1204 | extract_sfmt_jc: | |
1205 | { | |
1206 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
1207 | CGEN_INSN_INT insn = entire_insn; | |
de8f5985 | 1208 | #define FLD(f) abuf->fields.sfmt_jl.f |
2df3850c JM |
1209 | UINT f_r2; |
1210 | ||
1211 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
1212 | ||
1213 | /* Record the fields for the semantic handler. */ | |
de8f5985 | 1214 | FLD (f_r2) = f_r2; |
2df3850c | 1215 | FLD (i_sr) = & CPU (h_gr)[f_r2]; |
de8f5985 | 1216 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jc", "f_r2 0x%x", 'x', f_r2, "sr 0x%x", 'x', f_r2, (char *) 0)); |
2df3850c JM |
1217 | |
1218 | #if WITH_PROFILE_MODEL_P | |
1219 | /* Record the fields for profiling. */ | |
1220 | if (PROFILE_MODEL_P (current_cpu)) | |
1221 | { | |
1222 | FLD (in_sr) = f_r2; | |
1223 | } | |
1224 | #endif | |
1225 | #undef FLD | |
1226 | return idesc; | |
1227 | } | |
1228 | ||
1229 | extract_sfmt_jl: | |
1230 | { | |
1231 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
1232 | CGEN_INSN_INT insn = entire_insn; | |
1233 | #define FLD(f) abuf->fields.sfmt_jl.f | |
1234 | UINT f_r2; | |
1235 | ||
1236 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
1237 | ||
1238 | /* Record the fields for the semantic handler. */ | |
de8f5985 | 1239 | FLD (f_r2) = f_r2; |
2df3850c | 1240 | FLD (i_sr) = & CPU (h_gr)[f_r2]; |
de8f5985 | 1241 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jl", "f_r2 0x%x", 'x', f_r2, "sr 0x%x", 'x', f_r2, (char *) 0)); |
2df3850c JM |
1242 | |
1243 | #if WITH_PROFILE_MODEL_P | |
1244 | /* Record the fields for profiling. */ | |
1245 | if (PROFILE_MODEL_P (current_cpu)) | |
1246 | { | |
1247 | FLD (in_sr) = f_r2; | |
378af1d6 | 1248 | FLD (out_h_gr_SI_14) = 14; |
2df3850c JM |
1249 | } |
1250 | #endif | |
1251 | #undef FLD | |
1252 | return idesc; | |
1253 | } | |
1254 | ||
1255 | extract_sfmt_jmp: | |
1256 | { | |
1257 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
1258 | CGEN_INSN_INT insn = entire_insn; | |
de8f5985 | 1259 | #define FLD(f) abuf->fields.sfmt_jl.f |
2df3850c JM |
1260 | UINT f_r2; |
1261 | ||
1262 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
1263 | ||
1264 | /* Record the fields for the semantic handler. */ | |
de8f5985 | 1265 | FLD (f_r2) = f_r2; |
2df3850c | 1266 | FLD (i_sr) = & CPU (h_gr)[f_r2]; |
de8f5985 | 1267 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jmp", "f_r2 0x%x", 'x', f_r2, "sr 0x%x", 'x', f_r2, (char *) 0)); |
2df3850c JM |
1268 | |
1269 | #if WITH_PROFILE_MODEL_P | |
1270 | /* Record the fields for profiling. */ | |
1271 | if (PROFILE_MODEL_P (current_cpu)) | |
1272 | { | |
1273 | FLD (in_sr) = f_r2; | |
1274 | } | |
1275 | #endif | |
1276 | #undef FLD | |
1277 | return idesc; | |
1278 | } | |
1279 | ||
1280 | extract_sfmt_ld: | |
1281 | { | |
1282 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
1283 | CGEN_INSN_INT insn = entire_insn; | |
1284 | #define FLD(f) abuf->fields.sfmt_ld_plus.f | |
1285 | UINT f_r1; | |
1286 | UINT f_r2; | |
1287 | ||
1288 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
1289 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
1290 | ||
1291 | /* Record the fields for the semantic handler. */ | |
de8f5985 DB |
1292 | FLD (f_r2) = f_r2; |
1293 | FLD (f_r1) = f_r1; | |
2df3850c JM |
1294 | FLD (i_sr) = & CPU (h_gr)[f_r2]; |
1295 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
de8f5985 | 1296 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); |
2df3850c JM |
1297 | |
1298 | #if WITH_PROFILE_MODEL_P | |
1299 | /* Record the fields for profiling. */ | |
1300 | if (PROFILE_MODEL_P (current_cpu)) | |
1301 | { | |
1302 | FLD (in_sr) = f_r2; | |
1303 | FLD (out_dr) = f_r1; | |
1304 | } | |
1305 | #endif | |
1306 | #undef FLD | |
1307 | return idesc; | |
1308 | } | |
1309 | ||
1310 | extract_sfmt_ld_d: | |
1311 | { | |
1312 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
1313 | CGEN_INSN_INT insn = entire_insn; | |
1314 | #define FLD(f) abuf->fields.sfmt_add3.f | |
1315 | UINT f_r1; | |
1316 | UINT f_r2; | |
1317 | INT f_simm16; | |
1318 | ||
1319 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); | |
1320 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); | |
1321 | f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); | |
1322 | ||
1323 | /* Record the fields for the semantic handler. */ | |
1324 | FLD (f_simm16) = f_simm16; | |
de8f5985 DB |
1325 | FLD (f_r2) = f_r2; |
1326 | FLD (f_r1) = f_r1; | |
2df3850c JM |
1327 | FLD (i_sr) = & CPU (h_gr)[f_r2]; |
1328 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
de8f5985 | 1329 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_d", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); |
2df3850c | 1330 | |
378af1d6 DB |
1331 | #if WITH_PROFILE_MODEL_P |
1332 | /* Record the fields for profiling. */ | |
1333 | if (PROFILE_MODEL_P (current_cpu)) | |
1334 | { | |
1335 | FLD (in_sr) = f_r2; | |
1336 | FLD (out_dr) = f_r1; | |
1337 | } | |
1338 | #endif | |
1339 | #undef FLD | |
1340 | return idesc; | |
1341 | } | |
1342 | ||
1343 | extract_sfmt_ldb: | |
1344 | { | |
1345 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
1346 | CGEN_INSN_INT insn = entire_insn; | |
1347 | #define FLD(f) abuf->fields.sfmt_ld_plus.f | |
1348 | UINT f_r1; | |
1349 | UINT f_r2; | |
1350 | ||
1351 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
1352 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
1353 | ||
1354 | /* Record the fields for the semantic handler. */ | |
1355 | FLD (f_r2) = f_r2; | |
1356 | FLD (f_r1) = f_r1; | |
1357 | FLD (i_sr) = & CPU (h_gr)[f_r2]; | |
1358 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
1359 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); | |
1360 | ||
1361 | #if WITH_PROFILE_MODEL_P | |
1362 | /* Record the fields for profiling. */ | |
1363 | if (PROFILE_MODEL_P (current_cpu)) | |
1364 | { | |
1365 | FLD (in_sr) = f_r2; | |
1366 | FLD (out_dr) = f_r1; | |
1367 | } | |
1368 | #endif | |
1369 | #undef FLD | |
1370 | return idesc; | |
1371 | } | |
1372 | ||
1373 | extract_sfmt_ldb_d: | |
1374 | { | |
1375 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
1376 | CGEN_INSN_INT insn = entire_insn; | |
1377 | #define FLD(f) abuf->fields.sfmt_add3.f | |
1378 | UINT f_r1; | |
1379 | UINT f_r2; | |
1380 | INT f_simm16; | |
1381 | ||
1382 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); | |
1383 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); | |
1384 | f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); | |
1385 | ||
1386 | /* Record the fields for the semantic handler. */ | |
1387 | FLD (f_simm16) = f_simm16; | |
1388 | FLD (f_r2) = f_r2; | |
1389 | FLD (f_r1) = f_r1; | |
1390 | FLD (i_sr) = & CPU (h_gr)[f_r2]; | |
1391 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
1392 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb_d", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); | |
1393 | ||
1394 | #if WITH_PROFILE_MODEL_P | |
1395 | /* Record the fields for profiling. */ | |
1396 | if (PROFILE_MODEL_P (current_cpu)) | |
1397 | { | |
1398 | FLD (in_sr) = f_r2; | |
1399 | FLD (out_dr) = f_r1; | |
1400 | } | |
1401 | #endif | |
1402 | #undef FLD | |
1403 | return idesc; | |
1404 | } | |
1405 | ||
1406 | extract_sfmt_ldh: | |
1407 | { | |
1408 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
1409 | CGEN_INSN_INT insn = entire_insn; | |
1410 | #define FLD(f) abuf->fields.sfmt_ld_plus.f | |
1411 | UINT f_r1; | |
1412 | UINT f_r2; | |
1413 | ||
1414 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
1415 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
1416 | ||
1417 | /* Record the fields for the semantic handler. */ | |
1418 | FLD (f_r2) = f_r2; | |
1419 | FLD (f_r1) = f_r1; | |
1420 | FLD (i_sr) = & CPU (h_gr)[f_r2]; | |
1421 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
1422 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldh", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); | |
1423 | ||
1424 | #if WITH_PROFILE_MODEL_P | |
1425 | /* Record the fields for profiling. */ | |
1426 | if (PROFILE_MODEL_P (current_cpu)) | |
1427 | { | |
1428 | FLD (in_sr) = f_r2; | |
1429 | FLD (out_dr) = f_r1; | |
1430 | } | |
1431 | #endif | |
1432 | #undef FLD | |
1433 | return idesc; | |
1434 | } | |
1435 | ||
1436 | extract_sfmt_ldh_d: | |
1437 | { | |
1438 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
1439 | CGEN_INSN_INT insn = entire_insn; | |
1440 | #define FLD(f) abuf->fields.sfmt_add3.f | |
1441 | UINT f_r1; | |
1442 | UINT f_r2; | |
1443 | INT f_simm16; | |
1444 | ||
1445 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); | |
1446 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); | |
1447 | f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); | |
1448 | ||
1449 | /* Record the fields for the semantic handler. */ | |
1450 | FLD (f_simm16) = f_simm16; | |
1451 | FLD (f_r2) = f_r2; | |
1452 | FLD (f_r1) = f_r1; | |
1453 | FLD (i_sr) = & CPU (h_gr)[f_r2]; | |
1454 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
1455 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldh_d", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); | |
1456 | ||
2df3850c JM |
1457 | #if WITH_PROFILE_MODEL_P |
1458 | /* Record the fields for profiling. */ | |
1459 | if (PROFILE_MODEL_P (current_cpu)) | |
1460 | { | |
1461 | FLD (in_sr) = f_r2; | |
1462 | FLD (out_dr) = f_r1; | |
1463 | } | |
1464 | #endif | |
1465 | #undef FLD | |
1466 | return idesc; | |
1467 | } | |
1468 | ||
1469 | extract_sfmt_ld_plus: | |
1470 | { | |
1471 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
1472 | CGEN_INSN_INT insn = entire_insn; | |
1473 | #define FLD(f) abuf->fields.sfmt_ld_plus.f | |
1474 | UINT f_r1; | |
1475 | UINT f_r2; | |
1476 | ||
1477 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
1478 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
1479 | ||
1480 | /* Record the fields for the semantic handler. */ | |
de8f5985 DB |
1481 | FLD (f_r2) = f_r2; |
1482 | FLD (f_r1) = f_r1; | |
2df3850c JM |
1483 | FLD (i_sr) = & CPU (h_gr)[f_r2]; |
1484 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
de8f5985 | 1485 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_plus", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); |
2df3850c JM |
1486 | |
1487 | #if WITH_PROFILE_MODEL_P | |
1488 | /* Record the fields for profiling. */ | |
1489 | if (PROFILE_MODEL_P (current_cpu)) | |
1490 | { | |
1491 | FLD (in_sr) = f_r2; | |
1492 | FLD (out_dr) = f_r1; | |
1493 | FLD (out_sr) = f_r2; | |
1494 | } | |
1495 | #endif | |
1496 | #undef FLD | |
1497 | return idesc; | |
1498 | } | |
1499 | ||
1500 | extract_sfmt_ld24: | |
1501 | { | |
1502 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
1503 | CGEN_INSN_INT insn = entire_insn; | |
1504 | #define FLD(f) abuf->fields.sfmt_ld24.f | |
1505 | UINT f_r1; | |
1506 | UINT f_uimm24; | |
1507 | ||
1508 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); | |
1509 | f_uimm24 = EXTRACT_MSB0_UINT (insn, 32, 8, 24); | |
1510 | ||
1511 | /* Record the fields for the semantic handler. */ | |
de8f5985 | 1512 | FLD (f_r1) = f_r1; |
2df3850c JM |
1513 | FLD (i_uimm24) = f_uimm24; |
1514 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
de8f5985 | 1515 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld24", "f_r1 0x%x", 'x', f_r1, "uimm24 0x%x", 'x', f_uimm24, "dr 0x%x", 'x', f_r1, (char *) 0)); |
2df3850c JM |
1516 | |
1517 | #if WITH_PROFILE_MODEL_P | |
1518 | /* Record the fields for profiling. */ | |
1519 | if (PROFILE_MODEL_P (current_cpu)) | |
1520 | { | |
1521 | FLD (out_dr) = f_r1; | |
1522 | } | |
1523 | #endif | |
1524 | #undef FLD | |
1525 | return idesc; | |
1526 | } | |
1527 | ||
1528 | extract_sfmt_ldi8: | |
1529 | { | |
1530 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
1531 | CGEN_INSN_INT insn = entire_insn; | |
1532 | #define FLD(f) abuf->fields.sfmt_addi.f | |
1533 | UINT f_r1; | |
1534 | INT f_simm8; | |
1535 | ||
1536 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
1537 | f_simm8 = EXTRACT_MSB0_INT (insn, 16, 8, 8); | |
1538 | ||
1539 | /* Record the fields for the semantic handler. */ | |
1540 | FLD (f_simm8) = f_simm8; | |
de8f5985 | 1541 | FLD (f_r1) = f_r1; |
2df3850c | 1542 | FLD (i_dr) = & CPU (h_gr)[f_r1]; |
de8f5985 | 1543 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldi8", "f_simm8 0x%x", 'x', f_simm8, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0)); |
2df3850c JM |
1544 | |
1545 | #if WITH_PROFILE_MODEL_P | |
1546 | /* Record the fields for profiling. */ | |
1547 | if (PROFILE_MODEL_P (current_cpu)) | |
1548 | { | |
1549 | FLD (out_dr) = f_r1; | |
1550 | } | |
1551 | #endif | |
1552 | #undef FLD | |
1553 | return idesc; | |
1554 | } | |
1555 | ||
1556 | extract_sfmt_ldi16: | |
1557 | { | |
1558 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
1559 | CGEN_INSN_INT insn = entire_insn; | |
1560 | #define FLD(f) abuf->fields.sfmt_add3.f | |
1561 | UINT f_r1; | |
1562 | INT f_simm16; | |
1563 | ||
1564 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); | |
1565 | f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); | |
1566 | ||
1567 | /* Record the fields for the semantic handler. */ | |
1568 | FLD (f_simm16) = f_simm16; | |
de8f5985 | 1569 | FLD (f_r1) = f_r1; |
2df3850c | 1570 | FLD (i_dr) = & CPU (h_gr)[f_r1]; |
de8f5985 | 1571 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldi16", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0)); |
2df3850c JM |
1572 | |
1573 | #if WITH_PROFILE_MODEL_P | |
1574 | /* Record the fields for profiling. */ | |
1575 | if (PROFILE_MODEL_P (current_cpu)) | |
1576 | { | |
1577 | FLD (out_dr) = f_r1; | |
1578 | } | |
1579 | #endif | |
1580 | #undef FLD | |
1581 | return idesc; | |
1582 | } | |
1583 | ||
1584 | extract_sfmt_lock: | |
1585 | { | |
1586 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
1587 | CGEN_INSN_INT insn = entire_insn; | |
1588 | #define FLD(f) abuf->fields.sfmt_ld_plus.f | |
1589 | UINT f_r1; | |
1590 | UINT f_r2; | |
1591 | ||
1592 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
1593 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
1594 | ||
1595 | /* Record the fields for the semantic handler. */ | |
de8f5985 DB |
1596 | FLD (f_r2) = f_r2; |
1597 | FLD (f_r1) = f_r1; | |
2df3850c JM |
1598 | FLD (i_sr) = & CPU (h_gr)[f_r2]; |
1599 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
de8f5985 | 1600 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lock", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); |
2df3850c JM |
1601 | |
1602 | #if WITH_PROFILE_MODEL_P | |
1603 | /* Record the fields for profiling. */ | |
1604 | if (PROFILE_MODEL_P (current_cpu)) | |
1605 | { | |
1606 | FLD (in_sr) = f_r2; | |
1607 | FLD (out_dr) = f_r1; | |
1608 | } | |
1609 | #endif | |
1610 | #undef FLD | |
1611 | return idesc; | |
1612 | } | |
1613 | ||
1614 | extract_sfmt_machi_a: | |
1615 | { | |
1616 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
1617 | CGEN_INSN_INT insn = entire_insn; | |
1618 | #define FLD(f) abuf->fields.sfmt_machi_a.f | |
1619 | UINT f_r1; | |
1620 | UINT f_acc; | |
1621 | UINT f_r2; | |
1622 | ||
1623 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
1624 | f_acc = EXTRACT_MSB0_UINT (insn, 16, 8, 1); | |
1625 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
1626 | ||
1627 | /* Record the fields for the semantic handler. */ | |
1628 | FLD (f_acc) = f_acc; | |
de8f5985 DB |
1629 | FLD (f_r1) = f_r1; |
1630 | FLD (f_r2) = f_r2; | |
2df3850c JM |
1631 | FLD (i_src1) = & CPU (h_gr)[f_r1]; |
1632 | FLD (i_src2) = & CPU (h_gr)[f_r2]; | |
de8f5985 | 1633 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_machi_a", "f_acc 0x%x", 'x', f_acc, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); |
2df3850c JM |
1634 | |
1635 | #if WITH_PROFILE_MODEL_P | |
1636 | /* Record the fields for profiling. */ | |
1637 | if (PROFILE_MODEL_P (current_cpu)) | |
1638 | { | |
1639 | FLD (in_src1) = f_r1; | |
1640 | FLD (in_src2) = f_r2; | |
1641 | } | |
1642 | #endif | |
1643 | #undef FLD | |
1644 | return idesc; | |
1645 | } | |
1646 | ||
1647 | extract_sfmt_mulhi_a: | |
1648 | { | |
1649 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
1650 | CGEN_INSN_INT insn = entire_insn; | |
1651 | #define FLD(f) abuf->fields.sfmt_machi_a.f | |
1652 | UINT f_r1; | |
1653 | UINT f_acc; | |
1654 | UINT f_r2; | |
1655 | ||
1656 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
1657 | f_acc = EXTRACT_MSB0_UINT (insn, 16, 8, 1); | |
1658 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
1659 | ||
1660 | /* Record the fields for the semantic handler. */ | |
de8f5985 DB |
1661 | FLD (f_r1) = f_r1; |
1662 | FLD (f_r2) = f_r2; | |
2df3850c JM |
1663 | FLD (f_acc) = f_acc; |
1664 | FLD (i_src1) = & CPU (h_gr)[f_r1]; | |
1665 | FLD (i_src2) = & CPU (h_gr)[f_r2]; | |
de8f5985 | 1666 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mulhi_a", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "f_acc 0x%x", 'x', f_acc, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); |
2df3850c JM |
1667 | |
1668 | #if WITH_PROFILE_MODEL_P | |
1669 | /* Record the fields for profiling. */ | |
1670 | if (PROFILE_MODEL_P (current_cpu)) | |
1671 | { | |
1672 | FLD (in_src1) = f_r1; | |
1673 | FLD (in_src2) = f_r2; | |
1674 | } | |
1675 | #endif | |
1676 | #undef FLD | |
1677 | return idesc; | |
1678 | } | |
1679 | ||
1680 | extract_sfmt_mv: | |
1681 | { | |
1682 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
1683 | CGEN_INSN_INT insn = entire_insn; | |
1684 | #define FLD(f) abuf->fields.sfmt_ld_plus.f | |
1685 | UINT f_r1; | |
1686 | UINT f_r2; | |
1687 | ||
1688 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
1689 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
1690 | ||
1691 | /* Record the fields for the semantic handler. */ | |
de8f5985 DB |
1692 | FLD (f_r2) = f_r2; |
1693 | FLD (f_r1) = f_r1; | |
2df3850c JM |
1694 | FLD (i_sr) = & CPU (h_gr)[f_r2]; |
1695 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
de8f5985 | 1696 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mv", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); |
2df3850c JM |
1697 | |
1698 | #if WITH_PROFILE_MODEL_P | |
1699 | /* Record the fields for profiling. */ | |
1700 | if (PROFILE_MODEL_P (current_cpu)) | |
1701 | { | |
1702 | FLD (in_sr) = f_r2; | |
1703 | FLD (out_dr) = f_r1; | |
1704 | } | |
1705 | #endif | |
1706 | #undef FLD | |
1707 | return idesc; | |
1708 | } | |
1709 | ||
1710 | extract_sfmt_mvfachi_a: | |
1711 | { | |
1712 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
1713 | CGEN_INSN_INT insn = entire_insn; | |
1714 | #define FLD(f) abuf->fields.sfmt_mvfachi_a.f | |
1715 | UINT f_r1; | |
1716 | UINT f_accs; | |
1717 | ||
1718 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
1719 | f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); | |
1720 | ||
1721 | /* Record the fields for the semantic handler. */ | |
1722 | FLD (f_accs) = f_accs; | |
de8f5985 | 1723 | FLD (f_r1) = f_r1; |
2df3850c | 1724 | FLD (i_dr) = & CPU (h_gr)[f_r1]; |
de8f5985 | 1725 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvfachi_a", "f_accs 0x%x", 'x', f_accs, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0)); |
2df3850c JM |
1726 | |
1727 | #if WITH_PROFILE_MODEL_P | |
1728 | /* Record the fields for profiling. */ | |
1729 | if (PROFILE_MODEL_P (current_cpu)) | |
1730 | { | |
1731 | FLD (out_dr) = f_r1; | |
1732 | } | |
1733 | #endif | |
1734 | #undef FLD | |
1735 | return idesc; | |
1736 | } | |
1737 | ||
1738 | extract_sfmt_mvfc: | |
1739 | { | |
1740 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
1741 | CGEN_INSN_INT insn = entire_insn; | |
de8f5985 | 1742 | #define FLD(f) abuf->fields.sfmt_ld_plus.f |
2df3850c JM |
1743 | UINT f_r1; |
1744 | UINT f_r2; | |
1745 | ||
1746 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
1747 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
1748 | ||
1749 | /* Record the fields for the semantic handler. */ | |
1750 | FLD (f_r2) = f_r2; | |
de8f5985 | 1751 | FLD (f_r1) = f_r1; |
2df3850c | 1752 | FLD (i_dr) = & CPU (h_gr)[f_r1]; |
de8f5985 | 1753 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvfc", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0)); |
2df3850c JM |
1754 | |
1755 | #if WITH_PROFILE_MODEL_P | |
1756 | /* Record the fields for profiling. */ | |
1757 | if (PROFILE_MODEL_P (current_cpu)) | |
1758 | { | |
1759 | FLD (out_dr) = f_r1; | |
1760 | } | |
1761 | #endif | |
1762 | #undef FLD | |
1763 | return idesc; | |
1764 | } | |
1765 | ||
1766 | extract_sfmt_mvtachi_a: | |
1767 | { | |
1768 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
1769 | CGEN_INSN_INT insn = entire_insn; | |
1770 | #define FLD(f) abuf->fields.sfmt_mvtachi_a.f | |
1771 | UINT f_r1; | |
1772 | UINT f_accs; | |
1773 | ||
1774 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
1775 | f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); | |
1776 | ||
1777 | /* Record the fields for the semantic handler. */ | |
1778 | FLD (f_accs) = f_accs; | |
de8f5985 | 1779 | FLD (f_r1) = f_r1; |
2df3850c | 1780 | FLD (i_src1) = & CPU (h_gr)[f_r1]; |
de8f5985 | 1781 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvtachi_a", "f_accs 0x%x", 'x', f_accs, "f_r1 0x%x", 'x', f_r1, "src1 0x%x", 'x', f_r1, (char *) 0)); |
2df3850c JM |
1782 | |
1783 | #if WITH_PROFILE_MODEL_P | |
1784 | /* Record the fields for profiling. */ | |
1785 | if (PROFILE_MODEL_P (current_cpu)) | |
1786 | { | |
1787 | FLD (in_src1) = f_r1; | |
1788 | } | |
1789 | #endif | |
1790 | #undef FLD | |
1791 | return idesc; | |
1792 | } | |
1793 | ||
1794 | extract_sfmt_mvtc: | |
1795 | { | |
1796 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
1797 | CGEN_INSN_INT insn = entire_insn; | |
de8f5985 | 1798 | #define FLD(f) abuf->fields.sfmt_ld_plus.f |
2df3850c JM |
1799 | UINT f_r1; |
1800 | UINT f_r2; | |
1801 | ||
1802 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
1803 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
1804 | ||
1805 | /* Record the fields for the semantic handler. */ | |
de8f5985 | 1806 | FLD (f_r2) = f_r2; |
2df3850c JM |
1807 | FLD (f_r1) = f_r1; |
1808 | FLD (i_sr) = & CPU (h_gr)[f_r2]; | |
de8f5985 | 1809 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvtc", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0)); |
2df3850c JM |
1810 | |
1811 | #if WITH_PROFILE_MODEL_P | |
1812 | /* Record the fields for profiling. */ | |
1813 | if (PROFILE_MODEL_P (current_cpu)) | |
1814 | { | |
1815 | FLD (in_sr) = f_r2; | |
1816 | } | |
1817 | #endif | |
1818 | #undef FLD | |
1819 | return idesc; | |
1820 | } | |
1821 | ||
1822 | extract_sfmt_nop: | |
1823 | { | |
1824 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
2df3850c JM |
1825 | #define FLD(f) abuf->fields.fmt_empty.f |
1826 | ||
1827 | ||
1828 | /* Record the fields for the semantic handler. */ | |
1829 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nop", (char *) 0)); | |
1830 | ||
1831 | #undef FLD | |
1832 | return idesc; | |
1833 | } | |
1834 | ||
1835 | extract_sfmt_rac_dsi: | |
1836 | { | |
1837 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
1838 | CGEN_INSN_INT insn = entire_insn; | |
1839 | #define FLD(f) abuf->fields.sfmt_rac_dsi.f | |
1840 | UINT f_accd; | |
1841 | UINT f_accs; | |
1842 | SI f_imm1; | |
1843 | ||
1844 | f_accd = EXTRACT_MSB0_UINT (insn, 16, 4, 2); | |
1845 | f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); | |
1846 | f_imm1 = ((EXTRACT_MSB0_UINT (insn, 16, 15, 1)) + (1)); | |
1847 | ||
1848 | /* Record the fields for the semantic handler. */ | |
1849 | FLD (f_accs) = f_accs; | |
1850 | FLD (f_imm1) = f_imm1; | |
1851 | FLD (f_accd) = f_accd; | |
1852 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rac_dsi", "f_accs 0x%x", 'x', f_accs, "f_imm1 0x%x", 'x', f_imm1, "f_accd 0x%x", 'x', f_accd, (char *) 0)); | |
1853 | ||
1854 | #undef FLD | |
1855 | return idesc; | |
1856 | } | |
1857 | ||
1858 | extract_sfmt_rte: | |
1859 | { | |
1860 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
2df3850c JM |
1861 | #define FLD(f) abuf->fields.fmt_empty.f |
1862 | ||
1863 | ||
1864 | /* Record the fields for the semantic handler. */ | |
1865 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rte", (char *) 0)); | |
1866 | ||
1867 | #if WITH_PROFILE_MODEL_P | |
1868 | /* Record the fields for profiling. */ | |
1869 | if (PROFILE_MODEL_P (current_cpu)) | |
1870 | { | |
1871 | } | |
1872 | #endif | |
1873 | #undef FLD | |
1874 | return idesc; | |
1875 | } | |
1876 | ||
1877 | extract_sfmt_seth: | |
1878 | { | |
1879 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
1880 | CGEN_INSN_INT insn = entire_insn; | |
1881 | #define FLD(f) abuf->fields.sfmt_seth.f | |
1882 | UINT f_r1; | |
1883 | UINT f_hi16; | |
1884 | ||
1885 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); | |
1886 | f_hi16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); | |
1887 | ||
1888 | /* Record the fields for the semantic handler. */ | |
1889 | FLD (f_hi16) = f_hi16; | |
de8f5985 | 1890 | FLD (f_r1) = f_r1; |
2df3850c | 1891 | FLD (i_dr) = & CPU (h_gr)[f_r1]; |
de8f5985 | 1892 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_seth", "f_hi16 0x%x", 'x', f_hi16, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0)); |
2df3850c JM |
1893 | |
1894 | #if WITH_PROFILE_MODEL_P | |
1895 | /* Record the fields for profiling. */ | |
1896 | if (PROFILE_MODEL_P (current_cpu)) | |
1897 | { | |
1898 | FLD (out_dr) = f_r1; | |
1899 | } | |
1900 | #endif | |
1901 | #undef FLD | |
1902 | return idesc; | |
1903 | } | |
1904 | ||
1905 | extract_sfmt_sll3: | |
1906 | { | |
1907 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
1908 | CGEN_INSN_INT insn = entire_insn; | |
1909 | #define FLD(f) abuf->fields.sfmt_add3.f | |
1910 | UINT f_r1; | |
1911 | UINT f_r2; | |
1912 | INT f_simm16; | |
1913 | ||
1914 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); | |
1915 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); | |
1916 | f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); | |
1917 | ||
1918 | /* Record the fields for the semantic handler. */ | |
1919 | FLD (f_simm16) = f_simm16; | |
de8f5985 DB |
1920 | FLD (f_r2) = f_r2; |
1921 | FLD (f_r1) = f_r1; | |
2df3850c JM |
1922 | FLD (i_sr) = & CPU (h_gr)[f_r2]; |
1923 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
de8f5985 | 1924 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sll3", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); |
2df3850c JM |
1925 | |
1926 | #if WITH_PROFILE_MODEL_P | |
1927 | /* Record the fields for profiling. */ | |
1928 | if (PROFILE_MODEL_P (current_cpu)) | |
1929 | { | |
1930 | FLD (in_sr) = f_r2; | |
1931 | FLD (out_dr) = f_r1; | |
1932 | } | |
1933 | #endif | |
1934 | #undef FLD | |
1935 | return idesc; | |
1936 | } | |
1937 | ||
1938 | extract_sfmt_slli: | |
1939 | { | |
1940 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
1941 | CGEN_INSN_INT insn = entire_insn; | |
1942 | #define FLD(f) abuf->fields.sfmt_slli.f | |
1943 | UINT f_r1; | |
1944 | UINT f_uimm5; | |
1945 | ||
1946 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
1947 | f_uimm5 = EXTRACT_MSB0_UINT (insn, 16, 11, 5); | |
1948 | ||
1949 | /* Record the fields for the semantic handler. */ | |
de8f5985 | 1950 | FLD (f_r1) = f_r1; |
2df3850c JM |
1951 | FLD (f_uimm5) = f_uimm5; |
1952 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
de8f5985 | 1953 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_slli", "f_r1 0x%x", 'x', f_r1, "f_uimm5 0x%x", 'x', f_uimm5, "dr 0x%x", 'x', f_r1, (char *) 0)); |
2df3850c JM |
1954 | |
1955 | #if WITH_PROFILE_MODEL_P | |
1956 | /* Record the fields for profiling. */ | |
1957 | if (PROFILE_MODEL_P (current_cpu)) | |
1958 | { | |
1959 | FLD (in_dr) = f_r1; | |
1960 | FLD (out_dr) = f_r1; | |
1961 | } | |
1962 | #endif | |
1963 | #undef FLD | |
1964 | return idesc; | |
1965 | } | |
1966 | ||
1967 | extract_sfmt_st: | |
1968 | { | |
1969 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
1970 | CGEN_INSN_INT insn = entire_insn; | |
1971 | #define FLD(f) abuf->fields.sfmt_st_plus.f | |
1972 | UINT f_r1; | |
1973 | UINT f_r2; | |
1974 | ||
1975 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
1976 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
1977 | ||
1978 | /* Record the fields for the semantic handler. */ | |
de8f5985 DB |
1979 | FLD (f_r1) = f_r1; |
1980 | FLD (f_r2) = f_r2; | |
2df3850c JM |
1981 | FLD (i_src1) = & CPU (h_gr)[f_r1]; |
1982 | FLD (i_src2) = & CPU (h_gr)[f_r2]; | |
de8f5985 | 1983 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); |
2df3850c JM |
1984 | |
1985 | #if WITH_PROFILE_MODEL_P | |
1986 | /* Record the fields for profiling. */ | |
1987 | if (PROFILE_MODEL_P (current_cpu)) | |
1988 | { | |
1989 | FLD (in_src1) = f_r1; | |
1990 | FLD (in_src2) = f_r2; | |
1991 | } | |
1992 | #endif | |
1993 | #undef FLD | |
1994 | return idesc; | |
1995 | } | |
1996 | ||
1997 | extract_sfmt_st_d: | |
1998 | { | |
1999 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
2000 | CGEN_INSN_INT insn = entire_insn; | |
2001 | #define FLD(f) abuf->fields.sfmt_st_d.f | |
2002 | UINT f_r1; | |
2003 | UINT f_r2; | |
2004 | INT f_simm16; | |
2005 | ||
2006 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); | |
2007 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); | |
2008 | f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); | |
2009 | ||
2010 | /* Record the fields for the semantic handler. */ | |
2011 | FLD (f_simm16) = f_simm16; | |
de8f5985 DB |
2012 | FLD (f_r1) = f_r1; |
2013 | FLD (f_r2) = f_r2; | |
2df3850c JM |
2014 | FLD (i_src1) = & CPU (h_gr)[f_r1]; |
2015 | FLD (i_src2) = & CPU (h_gr)[f_r2]; | |
de8f5985 | 2016 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st_d", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); |
2df3850c JM |
2017 | |
2018 | #if WITH_PROFILE_MODEL_P | |
2019 | /* Record the fields for profiling. */ | |
2020 | if (PROFILE_MODEL_P (current_cpu)) | |
2021 | { | |
2022 | FLD (in_src1) = f_r1; | |
2023 | FLD (in_src2) = f_r2; | |
2024 | } | |
2025 | #endif | |
2026 | #undef FLD | |
2027 | return idesc; | |
2028 | } | |
2029 | ||
2030 | extract_sfmt_stb: | |
2031 | { | |
2032 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
2033 | CGEN_INSN_INT insn = entire_insn; | |
2034 | #define FLD(f) abuf->fields.sfmt_st_plus.f | |
2035 | UINT f_r1; | |
2036 | UINT f_r2; | |
2037 | ||
2038 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
2039 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
2040 | ||
2041 | /* Record the fields for the semantic handler. */ | |
de8f5985 DB |
2042 | FLD (f_r1) = f_r1; |
2043 | FLD (f_r2) = f_r2; | |
2df3850c JM |
2044 | FLD (i_src1) = & CPU (h_gr)[f_r1]; |
2045 | FLD (i_src2) = & CPU (h_gr)[f_r2]; | |
de8f5985 | 2046 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); |
2df3850c JM |
2047 | |
2048 | #if WITH_PROFILE_MODEL_P | |
2049 | /* Record the fields for profiling. */ | |
2050 | if (PROFILE_MODEL_P (current_cpu)) | |
2051 | { | |
2052 | FLD (in_src1) = f_r1; | |
2053 | FLD (in_src2) = f_r2; | |
2054 | } | |
2055 | #endif | |
2056 | #undef FLD | |
2057 | return idesc; | |
2058 | } | |
2059 | ||
2060 | extract_sfmt_stb_d: | |
2061 | { | |
2062 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
2063 | CGEN_INSN_INT insn = entire_insn; | |
2064 | #define FLD(f) abuf->fields.sfmt_st_d.f | |
2065 | UINT f_r1; | |
2066 | UINT f_r2; | |
2067 | INT f_simm16; | |
2068 | ||
2069 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); | |
2070 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); | |
2071 | f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); | |
2072 | ||
2073 | /* Record the fields for the semantic handler. */ | |
2074 | FLD (f_simm16) = f_simm16; | |
de8f5985 DB |
2075 | FLD (f_r1) = f_r1; |
2076 | FLD (f_r2) = f_r2; | |
2df3850c JM |
2077 | FLD (i_src1) = & CPU (h_gr)[f_r1]; |
2078 | FLD (i_src2) = & CPU (h_gr)[f_r2]; | |
de8f5985 | 2079 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb_d", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); |
2df3850c JM |
2080 | |
2081 | #if WITH_PROFILE_MODEL_P | |
2082 | /* Record the fields for profiling. */ | |
2083 | if (PROFILE_MODEL_P (current_cpu)) | |
2084 | { | |
2085 | FLD (in_src1) = f_r1; | |
2086 | FLD (in_src2) = f_r2; | |
2087 | } | |
2088 | #endif | |
2089 | #undef FLD | |
2090 | return idesc; | |
2091 | } | |
2092 | ||
2093 | extract_sfmt_sth: | |
2094 | { | |
2095 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
2096 | CGEN_INSN_INT insn = entire_insn; | |
2097 | #define FLD(f) abuf->fields.sfmt_st_plus.f | |
2098 | UINT f_r1; | |
2099 | UINT f_r2; | |
2100 | ||
2101 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
2102 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
2103 | ||
2104 | /* Record the fields for the semantic handler. */ | |
de8f5985 DB |
2105 | FLD (f_r1) = f_r1; |
2106 | FLD (f_r2) = f_r2; | |
2df3850c JM |
2107 | FLD (i_src1) = & CPU (h_gr)[f_r1]; |
2108 | FLD (i_src2) = & CPU (h_gr)[f_r2]; | |
de8f5985 | 2109 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sth", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); |
2df3850c JM |
2110 | |
2111 | #if WITH_PROFILE_MODEL_P | |
2112 | /* Record the fields for profiling. */ | |
2113 | if (PROFILE_MODEL_P (current_cpu)) | |
2114 | { | |
2115 | FLD (in_src1) = f_r1; | |
2116 | FLD (in_src2) = f_r2; | |
2117 | } | |
2118 | #endif | |
2119 | #undef FLD | |
2120 | return idesc; | |
2121 | } | |
2122 | ||
2123 | extract_sfmt_sth_d: | |
2124 | { | |
2125 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
2126 | CGEN_INSN_INT insn = entire_insn; | |
2127 | #define FLD(f) abuf->fields.sfmt_st_d.f | |
2128 | UINT f_r1; | |
2129 | UINT f_r2; | |
2130 | INT f_simm16; | |
2131 | ||
2132 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); | |
2133 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); | |
2134 | f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); | |
2135 | ||
2136 | /* Record the fields for the semantic handler. */ | |
2137 | FLD (f_simm16) = f_simm16; | |
de8f5985 DB |
2138 | FLD (f_r1) = f_r1; |
2139 | FLD (f_r2) = f_r2; | |
2df3850c JM |
2140 | FLD (i_src1) = & CPU (h_gr)[f_r1]; |
2141 | FLD (i_src2) = & CPU (h_gr)[f_r2]; | |
de8f5985 | 2142 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sth_d", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); |
2df3850c JM |
2143 | |
2144 | #if WITH_PROFILE_MODEL_P | |
2145 | /* Record the fields for profiling. */ | |
2146 | if (PROFILE_MODEL_P (current_cpu)) | |
2147 | { | |
2148 | FLD (in_src1) = f_r1; | |
2149 | FLD (in_src2) = f_r2; | |
2150 | } | |
2151 | #endif | |
2152 | #undef FLD | |
2153 | return idesc; | |
2154 | } | |
2155 | ||
2156 | extract_sfmt_st_plus: | |
2157 | { | |
2158 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
2159 | CGEN_INSN_INT insn = entire_insn; | |
2160 | #define FLD(f) abuf->fields.sfmt_st_plus.f | |
2161 | UINT f_r1; | |
2162 | UINT f_r2; | |
2163 | ||
2164 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
2165 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
2166 | ||
2167 | /* Record the fields for the semantic handler. */ | |
de8f5985 DB |
2168 | FLD (f_r1) = f_r1; |
2169 | FLD (f_r2) = f_r2; | |
2df3850c JM |
2170 | FLD (i_src1) = & CPU (h_gr)[f_r1]; |
2171 | FLD (i_src2) = & CPU (h_gr)[f_r2]; | |
de8f5985 | 2172 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st_plus", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); |
2df3850c | 2173 | |
16b47b25 NC |
2174 | #if WITH_PROFILE_MODEL_P |
2175 | /* Record the fields for profiling. */ | |
2176 | if (PROFILE_MODEL_P (current_cpu)) | |
2177 | { | |
2178 | FLD (in_src1) = f_r1; | |
2179 | FLD (in_src2) = f_r2; | |
2180 | FLD (out_src2) = f_r2; | |
2181 | } | |
2182 | #endif | |
2183 | #undef FLD | |
2184 | return idesc; | |
2185 | } | |
2186 | ||
2187 | extract_sfmt_sth_plus: | |
2188 | { | |
2189 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
2190 | CGEN_INSN_INT insn = entire_insn; | |
2191 | #define FLD(f) abuf->fields.sfmt_st_plus.f | |
2192 | UINT f_r1; | |
2193 | UINT f_r2; | |
2194 | ||
2195 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
2196 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
2197 | ||
2198 | /* Record the fields for the semantic handler. */ | |
2199 | FLD (f_r1) = f_r1; | |
2200 | FLD (f_r2) = f_r2; | |
2201 | FLD (i_src1) = & CPU (h_gr)[f_r1]; | |
2202 | FLD (i_src2) = & CPU (h_gr)[f_r2]; | |
2203 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sth_plus", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); | |
2204 | ||
2205 | #if WITH_PROFILE_MODEL_P | |
2206 | /* Record the fields for profiling. */ | |
2207 | if (PROFILE_MODEL_P (current_cpu)) | |
2208 | { | |
2209 | FLD (in_src1) = f_r1; | |
2210 | FLD (in_src2) = f_r2; | |
2211 | FLD (out_src2) = f_r2; | |
2212 | } | |
2213 | #endif | |
2214 | #undef FLD | |
2215 | return idesc; | |
2216 | } | |
2217 | ||
2218 | extract_sfmt_stb_plus: | |
2219 | { | |
2220 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
2221 | CGEN_INSN_INT insn = entire_insn; | |
2222 | #define FLD(f) abuf->fields.sfmt_st_plus.f | |
2223 | UINT f_r1; | |
2224 | UINT f_r2; | |
2225 | ||
2226 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
2227 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
2228 | ||
2229 | /* Record the fields for the semantic handler. */ | |
2230 | FLD (f_r1) = f_r1; | |
2231 | FLD (f_r2) = f_r2; | |
2232 | FLD (i_src1) = & CPU (h_gr)[f_r1]; | |
2233 | FLD (i_src2) = & CPU (h_gr)[f_r2]; | |
2234 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb_plus", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); | |
2235 | ||
2df3850c JM |
2236 | #if WITH_PROFILE_MODEL_P |
2237 | /* Record the fields for profiling. */ | |
2238 | if (PROFILE_MODEL_P (current_cpu)) | |
2239 | { | |
2240 | FLD (in_src1) = f_r1; | |
2241 | FLD (in_src2) = f_r2; | |
2242 | FLD (out_src2) = f_r2; | |
2243 | } | |
2244 | #endif | |
2245 | #undef FLD | |
2246 | return idesc; | |
2247 | } | |
2248 | ||
2249 | extract_sfmt_trap: | |
2250 | { | |
2251 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
2252 | CGEN_INSN_INT insn = entire_insn; | |
2253 | #define FLD(f) abuf->fields.sfmt_trap.f | |
2254 | UINT f_uimm4; | |
2255 | ||
2256 | f_uimm4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
2257 | ||
2258 | /* Record the fields for the semantic handler. */ | |
2259 | FLD (f_uimm4) = f_uimm4; | |
2260 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_trap", "f_uimm4 0x%x", 'x', f_uimm4, (char *) 0)); | |
2261 | ||
2262 | #if WITH_PROFILE_MODEL_P | |
2263 | /* Record the fields for profiling. */ | |
2264 | if (PROFILE_MODEL_P (current_cpu)) | |
2265 | { | |
2266 | } | |
2267 | #endif | |
2268 | #undef FLD | |
2269 | return idesc; | |
2270 | } | |
2271 | ||
2272 | extract_sfmt_unlock: | |
2273 | { | |
2274 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
2275 | CGEN_INSN_INT insn = entire_insn; | |
2276 | #define FLD(f) abuf->fields.sfmt_st_plus.f | |
2277 | UINT f_r1; | |
2278 | UINT f_r2; | |
2279 | ||
2280 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
2281 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
2282 | ||
2283 | /* Record the fields for the semantic handler. */ | |
de8f5985 DB |
2284 | FLD (f_r1) = f_r1; |
2285 | FLD (f_r2) = f_r2; | |
2df3850c JM |
2286 | FLD (i_src1) = & CPU (h_gr)[f_r1]; |
2287 | FLD (i_src2) = & CPU (h_gr)[f_r2]; | |
de8f5985 | 2288 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_unlock", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); |
2df3850c JM |
2289 | |
2290 | #if WITH_PROFILE_MODEL_P | |
2291 | /* Record the fields for profiling. */ | |
2292 | if (PROFILE_MODEL_P (current_cpu)) | |
2293 | { | |
2294 | FLD (in_src1) = f_r1; | |
2295 | FLD (in_src2) = f_r2; | |
2296 | } | |
2297 | #endif | |
2298 | #undef FLD | |
2299 | return idesc; | |
2300 | } | |
2301 | ||
2302 | extract_sfmt_satb: | |
2303 | { | |
2304 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
2305 | CGEN_INSN_INT insn = entire_insn; | |
2306 | #define FLD(f) abuf->fields.sfmt_ld_plus.f | |
2307 | UINT f_r1; | |
2308 | UINT f_r2; | |
2309 | ||
2310 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); | |
2311 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); | |
2312 | ||
2313 | /* Record the fields for the semantic handler. */ | |
de8f5985 DB |
2314 | FLD (f_r2) = f_r2; |
2315 | FLD (f_r1) = f_r1; | |
2df3850c JM |
2316 | FLD (i_sr) = & CPU (h_gr)[f_r2]; |
2317 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
de8f5985 | 2318 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_satb", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); |
2df3850c JM |
2319 | |
2320 | #if WITH_PROFILE_MODEL_P | |
2321 | /* Record the fields for profiling. */ | |
2322 | if (PROFILE_MODEL_P (current_cpu)) | |
2323 | { | |
2324 | FLD (in_sr) = f_r2; | |
2325 | FLD (out_dr) = f_r1; | |
2326 | } | |
2327 | #endif | |
2328 | #undef FLD | |
2329 | return idesc; | |
2330 | } | |
2331 | ||
2332 | extract_sfmt_sat: | |
2333 | { | |
2334 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
2335 | CGEN_INSN_INT insn = entire_insn; | |
2336 | #define FLD(f) abuf->fields.sfmt_ld_plus.f | |
2337 | UINT f_r1; | |
2338 | UINT f_r2; | |
2339 | ||
2340 | f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); | |
2341 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); | |
2342 | ||
2343 | /* Record the fields for the semantic handler. */ | |
de8f5985 DB |
2344 | FLD (f_r2) = f_r2; |
2345 | FLD (f_r1) = f_r1; | |
2df3850c JM |
2346 | FLD (i_sr) = & CPU (h_gr)[f_r2]; |
2347 | FLD (i_dr) = & CPU (h_gr)[f_r1]; | |
de8f5985 | 2348 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sat", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); |
2df3850c JM |
2349 | |
2350 | #if WITH_PROFILE_MODEL_P | |
2351 | /* Record the fields for profiling. */ | |
2352 | if (PROFILE_MODEL_P (current_cpu)) | |
2353 | { | |
2354 | FLD (in_sr) = f_r2; | |
2355 | FLD (out_dr) = f_r1; | |
2356 | } | |
2357 | #endif | |
2358 | #undef FLD | |
2359 | return idesc; | |
2360 | } | |
2361 | ||
2362 | extract_sfmt_sadd: | |
2363 | { | |
2364 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
2df3850c JM |
2365 | #define FLD(f) abuf->fields.fmt_empty.f |
2366 | ||
2367 | ||
2368 | /* Record the fields for the semantic handler. */ | |
2369 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sadd", (char *) 0)); | |
2370 | ||
2371 | #undef FLD | |
2372 | return idesc; | |
2373 | } | |
2374 | ||
2375 | extract_sfmt_macwu1: | |
2376 | { | |
2377 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
2378 | CGEN_INSN_INT insn = entire_insn; | |
2379 | #define FLD(f) abuf->fields.sfmt_st_plus.f | |
2380 | UINT f_r1; | |
2381 | UINT f_r2; | |
2382 | ||
2383 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
2384 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
2385 | ||
2386 | /* Record the fields for the semantic handler. */ | |
de8f5985 DB |
2387 | FLD (f_r1) = f_r1; |
2388 | FLD (f_r2) = f_r2; | |
2df3850c JM |
2389 | FLD (i_src1) = & CPU (h_gr)[f_r1]; |
2390 | FLD (i_src2) = & CPU (h_gr)[f_r2]; | |
de8f5985 | 2391 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_macwu1", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); |
2df3850c JM |
2392 | |
2393 | #if WITH_PROFILE_MODEL_P | |
2394 | /* Record the fields for profiling. */ | |
2395 | if (PROFILE_MODEL_P (current_cpu)) | |
2396 | { | |
2397 | FLD (in_src1) = f_r1; | |
2398 | FLD (in_src2) = f_r2; | |
2399 | } | |
2400 | #endif | |
2401 | #undef FLD | |
2402 | return idesc; | |
2403 | } | |
2404 | ||
2405 | extract_sfmt_msblo: | |
2406 | { | |
2407 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
2408 | CGEN_INSN_INT insn = entire_insn; | |
2409 | #define FLD(f) abuf->fields.sfmt_st_plus.f | |
2410 | UINT f_r1; | |
2411 | UINT f_r2; | |
2412 | ||
2413 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
2414 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
2415 | ||
2416 | /* Record the fields for the semantic handler. */ | |
de8f5985 DB |
2417 | FLD (f_r1) = f_r1; |
2418 | FLD (f_r2) = f_r2; | |
2df3850c JM |
2419 | FLD (i_src1) = & CPU (h_gr)[f_r1]; |
2420 | FLD (i_src2) = & CPU (h_gr)[f_r2]; | |
de8f5985 | 2421 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_msblo", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); |
2df3850c JM |
2422 | |
2423 | #if WITH_PROFILE_MODEL_P | |
2424 | /* Record the fields for profiling. */ | |
2425 | if (PROFILE_MODEL_P (current_cpu)) | |
2426 | { | |
2427 | FLD (in_src1) = f_r1; | |
2428 | FLD (in_src2) = f_r2; | |
2429 | } | |
2430 | #endif | |
2431 | #undef FLD | |
2432 | return idesc; | |
2433 | } | |
2434 | ||
2435 | extract_sfmt_mulwu1: | |
2436 | { | |
2437 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
2438 | CGEN_INSN_INT insn = entire_insn; | |
2439 | #define FLD(f) abuf->fields.sfmt_st_plus.f | |
2440 | UINT f_r1; | |
2441 | UINT f_r2; | |
2442 | ||
2443 | f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); | |
2444 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
2445 | ||
2446 | /* Record the fields for the semantic handler. */ | |
de8f5985 DB |
2447 | FLD (f_r1) = f_r1; |
2448 | FLD (f_r2) = f_r2; | |
2df3850c JM |
2449 | FLD (i_src1) = & CPU (h_gr)[f_r1]; |
2450 | FLD (i_src2) = & CPU (h_gr)[f_r2]; | |
de8f5985 | 2451 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mulwu1", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); |
2df3850c JM |
2452 | |
2453 | #if WITH_PROFILE_MODEL_P | |
2454 | /* Record the fields for profiling. */ | |
2455 | if (PROFILE_MODEL_P (current_cpu)) | |
2456 | { | |
2457 | FLD (in_src1) = f_r1; | |
2458 | FLD (in_src2) = f_r2; | |
2459 | } | |
2460 | #endif | |
2461 | #undef FLD | |
2462 | return idesc; | |
2463 | } | |
2464 | ||
2465 | extract_sfmt_sc: | |
2466 | { | |
2467 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
2df3850c JM |
2468 | #define FLD(f) abuf->fields.fmt_empty.f |
2469 | ||
2470 | ||
2471 | /* Record the fields for the semantic handler. */ | |
2472 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sc", (char *) 0)); | |
2473 | ||
16b47b25 NC |
2474 | #undef FLD |
2475 | return idesc; | |
2476 | } | |
2477 | ||
2478 | extract_sfmt_clrpsw: | |
2479 | { | |
2480 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
2481 | CGEN_INSN_INT insn = entire_insn; | |
2482 | #define FLD(f) abuf->fields.sfmt_clrpsw.f | |
2483 | UINT f_uimm8; | |
2484 | ||
2485 | f_uimm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); | |
2486 | ||
2487 | /* Record the fields for the semantic handler. */ | |
2488 | FLD (f_uimm8) = f_uimm8; | |
2489 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_clrpsw", "f_uimm8 0x%x", 'x', f_uimm8, (char *) 0)); | |
2490 | ||
2491 | #undef FLD | |
2492 | return idesc; | |
2493 | } | |
2494 | ||
2495 | extract_sfmt_setpsw: | |
2496 | { | |
2497 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
2498 | CGEN_INSN_INT insn = entire_insn; | |
2499 | #define FLD(f) abuf->fields.sfmt_clrpsw.f | |
2500 | UINT f_uimm8; | |
2501 | ||
2502 | f_uimm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); | |
2503 | ||
2504 | /* Record the fields for the semantic handler. */ | |
2505 | FLD (f_uimm8) = f_uimm8; | |
2506 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_setpsw", "f_uimm8 0x%x", 'x', f_uimm8, (char *) 0)); | |
2507 | ||
2508 | #undef FLD | |
2509 | return idesc; | |
2510 | } | |
2511 | ||
2512 | extract_sfmt_bset: | |
2513 | { | |
2514 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
2515 | CGEN_INSN_INT insn = entire_insn; | |
2516 | #define FLD(f) abuf->fields.sfmt_bset.f | |
2517 | UINT f_uimm3; | |
2518 | UINT f_r2; | |
2519 | INT f_simm16; | |
2520 | ||
2521 | f_uimm3 = EXTRACT_MSB0_UINT (insn, 32, 5, 3); | |
2522 | f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); | |
2523 | f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); | |
2524 | ||
2525 | /* Record the fields for the semantic handler. */ | |
2526 | FLD (f_simm16) = f_simm16; | |
2527 | FLD (f_r2) = f_r2; | |
2528 | FLD (f_uimm3) = f_uimm3; | |
2529 | FLD (i_sr) = & CPU (h_gr)[f_r2]; | |
2530 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bset", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_uimm3 0x%x", 'x', f_uimm3, "sr 0x%x", 'x', f_r2, (char *) 0)); | |
2531 | ||
2532 | #if WITH_PROFILE_MODEL_P | |
2533 | /* Record the fields for profiling. */ | |
2534 | if (PROFILE_MODEL_P (current_cpu)) | |
2535 | { | |
2536 | FLD (in_sr) = f_r2; | |
2537 | } | |
2538 | #endif | |
2539 | #undef FLD | |
2540 | return idesc; | |
2541 | } | |
2542 | ||
2543 | extract_sfmt_btst: | |
2544 | { | |
2545 | const IDESC *idesc = &m32rxf_insn_data[itype]; | |
2546 | CGEN_INSN_INT insn = entire_insn; | |
2547 | #define FLD(f) abuf->fields.sfmt_bset.f | |
2548 | UINT f_uimm3; | |
2549 | UINT f_r2; | |
2550 | ||
2551 | f_uimm3 = EXTRACT_MSB0_UINT (insn, 16, 5, 3); | |
2552 | f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); | |
2553 | ||
2554 | /* Record the fields for the semantic handler. */ | |
2555 | FLD (f_r2) = f_r2; | |
2556 | FLD (f_uimm3) = f_uimm3; | |
2557 | FLD (i_sr) = & CPU (h_gr)[f_r2]; | |
2558 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_btst", "f_r2 0x%x", 'x', f_r2, "f_uimm3 0x%x", 'x', f_uimm3, "sr 0x%x", 'x', f_r2, (char *) 0)); | |
2559 | ||
2560 | #if WITH_PROFILE_MODEL_P | |
2561 | /* Record the fields for profiling. */ | |
2562 | if (PROFILE_MODEL_P (current_cpu)) | |
2563 | { | |
2564 | FLD (in_sr) = f_r2; | |
2565 | } | |
2566 | #endif | |
2df3850c JM |
2567 | #undef FLD |
2568 | return idesc; | |
2569 | } | |
2570 | ||
2571 | } |