* elf64-ppc.c (ppc64_elf_copy_indirect_symbol): Don't copy is_func
[deliverable/binutils-gdb.git] / sim / m32r / m32r.c
CommitLineData
c906108c
SS
1/* m32r simulator support code
2 Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
3 Contributed by Cygnus Support.
4
5This file is part of GDB, the GNU debugger.
6
7This program is free software; you can redistribute it and/or modify
8it under the terms of the GNU General Public License as published by
9the Free Software Foundation; either version 2, or (at your option)
10any later version.
11
12This program is distributed in the hope that it will be useful,
13but WITHOUT ANY WARRANTY; without even the implied warranty of
14MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15GNU General Public License for more details.
16
17You should have received a copy of the GNU General Public License along
18with this program; if not, write to the Free Software Foundation, Inc.,
1959 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
20
21#define WANT_CPU m32rbf
22#define WANT_CPU_M32RBF
23
24#include "sim-main.h"
25#include "cgen-mem.h"
26#include "cgen-ops.h"
27
28/* Decode gdb ctrl register number. */
29
30int
31m32r_decode_gdb_ctrl_regnum (int gdb_regnum)
32{
33 switch (gdb_regnum)
34 {
35 case PSW_REGNUM : return H_CR_PSW;
36 case CBR_REGNUM : return H_CR_CBR;
37 case SPI_REGNUM : return H_CR_SPI;
38 case SPU_REGNUM : return H_CR_SPU;
39 case BPC_REGNUM : return H_CR_BPC;
40 case BBPSW_REGNUM : return H_CR_BBPSW;
41 case BBPC_REGNUM : return H_CR_BBPC;
42 }
43 abort ();
44}
45
46/* The contents of BUF are in target byte order. */
47
48int
49m32rbf_fetch_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len)
50{
7a292a7a
SS
51 int mach = MACH_NUM (CPU_MACH (current_cpu));
52
c906108c
SS
53 if (rn < 16)
54 SETTWI (buf, a_m32r_h_gr_get (current_cpu, rn));
55 else
56 switch (rn)
57 {
58 case PSW_REGNUM :
59 case CBR_REGNUM :
60 case SPI_REGNUM :
61 case SPU_REGNUM :
62 case BPC_REGNUM :
63 case BBPSW_REGNUM :
64 case BBPC_REGNUM :
65 SETTWI (buf, a_m32r_h_cr_get (current_cpu,
66 m32r_decode_gdb_ctrl_regnum (rn)));
67 break;
68 case PC_REGNUM :
7a292a7a
SS
69 if (mach == MACH_M32R)
70 SETTWI (buf, m32rbf_h_pc_get (current_cpu));
71 else
72 SETTWI (buf, m32rxf_h_pc_get (current_cpu));
c906108c
SS
73 break;
74 case ACCL_REGNUM :
7a292a7a
SS
75 if (mach == MACH_M32R)
76 SETTWI (buf, GETLODI (m32rbf_h_accum_get (current_cpu)));
77 else
78 SETTWI (buf, GETLODI (m32rxf_h_accum_get (current_cpu)));
c906108c
SS
79 break;
80 case ACCH_REGNUM :
7a292a7a
SS
81 if (mach == MACH_M32R)
82 SETTWI (buf, GETHIDI (m32rbf_h_accum_get (current_cpu)));
83 else
84 SETTWI (buf, GETHIDI (m32rxf_h_accum_get (current_cpu)));
c906108c
SS
85 break;
86 default :
87 return 0;
88 }
89
90 return -1; /*FIXME*/
91}
92
93/* The contents of BUF are in target byte order. */
94
95int
96m32rbf_store_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len)
97{
7a292a7a
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98 int mach = MACH_NUM (CPU_MACH (current_cpu));
99
c906108c
SS
100 if (rn < 16)
101 a_m32r_h_gr_set (current_cpu, rn, GETTWI (buf));
102 else
103 switch (rn)
104 {
105 case PSW_REGNUM :
106 case CBR_REGNUM :
107 case SPI_REGNUM :
108 case SPU_REGNUM :
109 case BPC_REGNUM :
110 case BBPSW_REGNUM :
111 case BBPC_REGNUM :
112 a_m32r_h_cr_set (current_cpu,
113 m32r_decode_gdb_ctrl_regnum (rn),
114 GETTWI (buf));
115 break;
116 case PC_REGNUM :
7a292a7a
SS
117 if (mach == MACH_M32R)
118 m32rbf_h_pc_set (current_cpu, GETTWI (buf));
119 else
120 m32rxf_h_pc_set (current_cpu, GETTWI (buf));
c906108c
SS
121 break;
122 case ACCL_REGNUM :
123 {
7a292a7a
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124 DI val;
125 if (mach == MACH_M32R)
126 val = m32rbf_h_accum_get (current_cpu);
127 else
128 val = m32rxf_h_accum_get (current_cpu);
c906108c 129 SETLODI (val, GETTWI (buf));
7a292a7a
SS
130 if (mach == MACH_M32R)
131 m32rbf_h_accum_set (current_cpu, val);
132 else
133 m32rxf_h_accum_set (current_cpu, val);
c906108c
SS
134 break;
135 }
136 case ACCH_REGNUM :
137 {
7a292a7a
SS
138 DI val;
139 if (mach == MACH_M32R)
140 val = m32rbf_h_accum_get (current_cpu);
141 else
142 val = m32rxf_h_accum_get (current_cpu);
c906108c 143 SETHIDI (val, GETTWI (buf));
7a292a7a
SS
144 if (mach == MACH_M32R)
145 m32rbf_h_accum_set (current_cpu, val);
146 else
147 m32rxf_h_accum_set (current_cpu, val);
c906108c
SS
148 break;
149 }
150 default :
151 return 0;
152 }
153
154 return -1; /*FIXME*/
155}
156\f
7a292a7a
SS
157/* Cover fns for mach independent register accesses. */
158
159SI
160a_m32r_h_gr_get (SIM_CPU *current_cpu, UINT regno)
161{
162 switch (MACH_NUM (CPU_MACH (current_cpu)))
163 {
164#ifdef HAVE_CPU_M32RBF
165 case MACH_M32R :
166 return m32rbf_h_gr_get (current_cpu, regno);
167#endif
168#ifdef HAVE_CPU_M32RXF
169 case MACH_M32RX :
170 return m32rxf_h_gr_get (current_cpu, regno);
171#endif
172 default :
173 abort ();
174 }
175}
176
177void
178a_m32r_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
179{
180 switch (MACH_NUM (CPU_MACH (current_cpu)))
181 {
182#ifdef HAVE_CPU_M32RBF
183 case MACH_M32R :
184 m32rbf_h_gr_set (current_cpu, regno, newval);
185 break;
186#endif
187#ifdef HAVE_CPU_M32RXF
188 case MACH_M32RX :
189 m32rxf_h_gr_set (current_cpu, regno, newval);
190 break;
191#endif
192 default :
193 abort ();
194 }
195}
196
197USI
198a_m32r_h_cr_get (SIM_CPU *current_cpu, UINT regno)
199{
200 switch (MACH_NUM (CPU_MACH (current_cpu)))
201 {
202#ifdef HAVE_CPU_M32RBF
203 case MACH_M32R :
204 return m32rbf_h_cr_get (current_cpu, regno);
205#endif
206#ifdef HAVE_CPU_M32RXF
207 case MACH_M32RX :
208 return m32rxf_h_cr_get (current_cpu, regno);
209#endif
210 default :
211 abort ();
212 }
213}
214
215void
216a_m32r_h_cr_set (SIM_CPU *current_cpu, UINT regno, USI newval)
217{
218 switch (MACH_NUM (CPU_MACH (current_cpu)))
219 {
220#ifdef HAVE_CPU_M32RBF
221 case MACH_M32R :
222 m32rbf_h_cr_set (current_cpu, regno, newval);
223 break;
224#endif
225#ifdef HAVE_CPU_M32RXF
226 case MACH_M32RX :
227 m32rxf_h_cr_set (current_cpu, regno, newval);
228 break;
229#endif
230 default :
231 abort ();
232 }
233}
234\f
c906108c
SS
235USI
236m32rbf_h_cr_get_handler (SIM_CPU *current_cpu, UINT cr)
237{
238 switch (cr)
239 {
240 case H_CR_PSW : /* psw */
241 return (((CPU (h_bpsw) & 0xc1) << 8)
242 | ((CPU (h_psw) & 0xc0) << 0)
243 | GET_H_COND ());
244 case H_CR_BBPSW : /* backup backup psw */
245 return CPU (h_bbpsw) & 0xc1;
246 case H_CR_CBR : /* condition bit */
247 return GET_H_COND ();
248 case H_CR_SPI : /* interrupt stack pointer */
249 if (! GET_H_SM ())
250 return CPU (h_gr[H_GR_SP]);
251 else
252 return CPU (h_cr[H_CR_SPI]);
253 case H_CR_SPU : /* user stack pointer */
254 if (GET_H_SM ())
255 return CPU (h_gr[H_GR_SP]);
256 else
257 return CPU (h_cr[H_CR_SPU]);
258 case H_CR_BPC : /* backup pc */
259 return CPU (h_cr[H_CR_BPC]) & 0xfffffffe;
260 case H_CR_BBPC : /* backup backup pc */
261 return CPU (h_cr[H_CR_BBPC]) & 0xfffffffe;
262 case 4 : /* ??? unspecified, but apparently available */
263 case 5 : /* ??? unspecified, but apparently available */
264 return CPU (h_cr[cr]);
265 default :
266 return 0;
267 }
268}
269
270void
271m32rbf_h_cr_set_handler (SIM_CPU *current_cpu, UINT cr, USI newval)
272{
273 switch (cr)
274 {
275 case H_CR_PSW : /* psw */
276 {
277 int old_sm = (CPU (h_psw) & 0x80) != 0;
278 int new_sm = (newval & 0x80) != 0;
279 CPU (h_bpsw) = (newval >> 8) & 0xff;
280 CPU (h_psw) = newval & 0xff;
281 SET_H_COND (newval & 1);
282 /* When switching stack modes, update the registers. */
283 if (old_sm != new_sm)
284 {
285 if (old_sm)
286 {
287 /* Switching user -> system. */
288 CPU (h_cr[H_CR_SPU]) = CPU (h_gr[H_GR_SP]);
289 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPI]);
290 }
291 else
292 {
293 /* Switching system -> user. */
294 CPU (h_cr[H_CR_SPI]) = CPU (h_gr[H_GR_SP]);
295 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPU]);
296 }
297 }
298 break;
299 }
300 case H_CR_BBPSW : /* backup backup psw */
301 CPU (h_bbpsw) = newval & 0xff;
302 break;
303 case H_CR_CBR : /* condition bit */
304 SET_H_COND (newval & 1);
305 break;
306 case H_CR_SPI : /* interrupt stack pointer */
307 if (! GET_H_SM ())
308 CPU (h_gr[H_GR_SP]) = newval;
309 else
310 CPU (h_cr[H_CR_SPI]) = newval;
311 break;
312 case H_CR_SPU : /* user stack pointer */
313 if (GET_H_SM ())
314 CPU (h_gr[H_GR_SP]) = newval;
315 else
316 CPU (h_cr[H_CR_SPU]) = newval;
317 break;
318 case H_CR_BPC : /* backup pc */
319 CPU (h_cr[H_CR_BPC]) = newval;
320 break;
321 case H_CR_BBPC : /* backup backup pc */
322 CPU (h_cr[H_CR_BBPC]) = newval;
323 break;
324 case 4 : /* ??? unspecified, but apparently available */
325 case 5 : /* ??? unspecified, but apparently available */
326 CPU (h_cr[cr]) = newval;
327 break;
328 default :
329 /* ignore */
330 break;
331 }
332}
333
334/* Cover fns to access h-psw. */
335
336UQI
337m32rbf_h_psw_get_handler (SIM_CPU *current_cpu)
338{
339 return (CPU (h_psw) & 0xfe) | (CPU (h_cond) & 1);
340}
341
342void
343m32rbf_h_psw_set_handler (SIM_CPU *current_cpu, UQI newval)
344{
345 CPU (h_psw) = newval;
346 CPU (h_cond) = newval & 1;
347}
348
349/* Cover fns to access h-accum. */
350
351DI
352m32rbf_h_accum_get_handler (SIM_CPU *current_cpu)
353{
354 /* Sign extend the top 8 bits. */
355 DI r;
356#if 1
357 r = ANDDI (CPU (h_accum), MAKEDI (0xffffff, 0xffffffff));
358 r = XORDI (r, MAKEDI (0x800000, 0));
359 r = SUBDI (r, MAKEDI (0x800000, 0));
360#else
361 SI hi,lo;
362 r = CPU (h_accum);
363 hi = GETHIDI (r);
364 lo = GETLODI (r);
365 hi = ((hi & 0xffffff) ^ 0x800000) - 0x800000;
366 r = MAKEDI (hi, lo);
367#endif
368 return r;
369}
370
371void
372m32rbf_h_accum_set_handler (SIM_CPU *current_cpu, DI newval)
373{
374 CPU (h_accum) = newval;
375}
376\f
377#if WITH_PROFILE_MODEL_P
378
379/* FIXME: Some of these should be inline or macros. Later. */
380
381/* Initialize cycle counting for an insn.
382 FIRST_P is non-zero if this is the first insn in a set of parallel
383 insns. */
384
385void
386m32rbf_model_insn_before (SIM_CPU *cpu, int first_p)
387{
388 M32R_MISC_PROFILE *mp = CPU_M32R_MISC_PROFILE (cpu);
389 mp->cti_stall = 0;
390 mp->load_stall = 0;
391 if (first_p)
392 {
393 mp->load_regs_pending = 0;
394 mp->biggest_cycles = 0;
395 }
396}
397
398/* Record the cycles computed for an insn.
399 LAST_P is non-zero if this is the last insn in a set of parallel insns,
400 and we update the total cycle count.
401 CYCLES is the cycle count of the insn. */
402
403void
404m32rbf_model_insn_after (SIM_CPU *cpu, int last_p, int cycles)
405{
406 PROFILE_DATA *p = CPU_PROFILE_DATA (cpu);
407 M32R_MISC_PROFILE *mp = CPU_M32R_MISC_PROFILE (cpu);
408 unsigned long total = cycles + mp->cti_stall + mp->load_stall;
409
410 if (last_p)
411 {
412 unsigned long biggest = total > mp->biggest_cycles ? total : mp->biggest_cycles;
413 PROFILE_MODEL_TOTAL_CYCLES (p) += biggest;
414 PROFILE_MODEL_CUR_INSN_CYCLES (p) = total;
415 }
416 else
417 {
418 /* Here we take advantage of the fact that !last_p -> first_p. */
419 mp->biggest_cycles = total;
420 PROFILE_MODEL_CUR_INSN_CYCLES (p) = total;
421 }
422
423 /* Branch and load stall counts are recorded independently of the
424 total cycle count. */
425 PROFILE_MODEL_CTI_STALL_CYCLES (p) += mp->cti_stall;
426 PROFILE_MODEL_LOAD_STALL_CYCLES (p) += mp->load_stall;
427
428 mp->load_regs = mp->load_regs_pending;
429}
430
431static INLINE void
432check_load_stall (SIM_CPU *cpu, int regno)
433{
434 UINT h_gr = CPU_M32R_MISC_PROFILE (cpu)->load_regs;
435
436 if (regno != -1
437 && (h_gr & (1 << regno)) != 0)
438 {
439 CPU_M32R_MISC_PROFILE (cpu)->load_stall += 2;
440 if (TRACE_INSN_P (cpu))
441 cgen_trace_printf (cpu, " ; Load stall of 2 cycles.");
442 }
443}
444
445int
446m32rbf_model_m32r_d_u_exec (SIM_CPU *cpu, const IDESC *idesc,
447 int unit_num, int referenced,
448 INT sr, INT sr2, INT dr)
449{
450 check_load_stall (cpu, sr);
451 check_load_stall (cpu, sr2);
452 return idesc->timing->units[unit_num].done;
453}
454
455int
456m32rbf_model_m32r_d_u_cmp (SIM_CPU *cpu, const IDESC *idesc,
457 int unit_num, int referenced,
458 INT src1, INT src2)
459{
460 check_load_stall (cpu, src1);
461 check_load_stall (cpu, src2);
462 return idesc->timing->units[unit_num].done;
463}
464
465int
466m32rbf_model_m32r_d_u_mac (SIM_CPU *cpu, const IDESC *idesc,
467 int unit_num, int referenced,
468 INT src1, INT src2)
469{
470 check_load_stall (cpu, src1);
471 check_load_stall (cpu, src2);
472 return idesc->timing->units[unit_num].done;
473}
474
475int
476m32rbf_model_m32r_d_u_cti (SIM_CPU *cpu, const IDESC *idesc,
477 int unit_num, int referenced,
478 INT sr)
479{
480 PROFILE_DATA *profile = CPU_PROFILE_DATA (cpu);
481 int taken_p = (referenced & (1 << 1)) != 0;
482
483 check_load_stall (cpu, sr);
484 if (taken_p)
485 {
486 CPU_M32R_MISC_PROFILE (cpu)->cti_stall += 2;
487 PROFILE_MODEL_TAKEN_COUNT (profile) += 1;
488 }
489 else
490 PROFILE_MODEL_UNTAKEN_COUNT (profile) += 1;
491 return idesc->timing->units[unit_num].done;
492}
493
494int
495m32rbf_model_m32r_d_u_load (SIM_CPU *cpu, const IDESC *idesc,
496 int unit_num, int referenced,
497 INT sr, INT dr)
498{
499 CPU_M32R_MISC_PROFILE (cpu)->load_regs_pending |= (1 << dr);
500 check_load_stall (cpu, sr);
501 return idesc->timing->units[unit_num].done;
502}
503
504int
505m32rbf_model_m32r_d_u_store (SIM_CPU *cpu, const IDESC *idesc,
506 int unit_num, int referenced,
507 INT src1, INT src2)
508{
509 check_load_stall (cpu, src1);
510 check_load_stall (cpu, src2);
511 return idesc->timing->units[unit_num].done;
512}
513
514int
515m32rbf_model_test_u_exec (SIM_CPU *cpu, const IDESC *idesc,
516 int unit_num, int referenced)
517{
518 return idesc->timing->units[unit_num].done;
519}
520
521#endif /* WITH_PROFILE_MODEL_P */
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