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c906108c | 1 | # Simulator main loop for m32r. -*- C -*- |
a86de8e0 | 2 | # |
7b6bb8da | 3 | # Copyright (C) 1996, 1997, 1998, 2007, 2008, 2009, 2010, 2011 |
a86de8e0 | 4 | # Free Software Foundation, Inc. |
c906108c SS |
5 | # |
6 | # This file is part of the GNU Simulators. | |
7 | # | |
8 | # This program is free software; you can redistribute it and/or modify | |
9 | # it under the terms of the GNU General Public License as published by | |
4744ac1b JB |
10 | # the Free Software Foundation; either version 3 of the License, or |
11 | # (at your option) any later version. | |
c906108c SS |
12 | # |
13 | # This program is distributed in the hope that it will be useful, | |
14 | # but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | # GNU General Public License for more details. | |
17 | # | |
4744ac1b JB |
18 | # You should have received a copy of the GNU General Public License |
19 | # along with this program. If not, see <http://www.gnu.org/licenses/>. | |
c906108c SS |
20 | |
21 | # Syntax: | |
22 | # /bin/sh mainloop.in command | |
23 | # | |
24 | # Command is one of: | |
25 | # | |
26 | # init | |
27 | # support | |
28 | # extract-{simple,scache,pbb} | |
29 | # {full,fast}-exec-{simple,scache,pbb} | |
30 | # | |
31 | # A target need only provide a "full" version of one of simple,scache,pbb. | |
32 | # If the target wants it can also provide a fast version of same, or if | |
33 | # the slow (full featured) version is `simple', then the fast version can be | |
34 | # one of scache/pbb. | |
35 | # A target can't provide more than this. | |
36 | # However for illustration's sake this file provides examples of all. | |
37 | ||
38 | # ??? After a few more ports are done, revisit. | |
39 | # Will eventually need to machine generate a lot of this. | |
40 | ||
41 | case "x$1" in | |
42 | ||
43 | xsupport) | |
44 | ||
45 | cat <<EOF | |
46 | ||
47 | static INLINE const IDESC * | |
48 | extract16 (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn, | |
49 | ARGBUF *abuf, int fast_p) | |
50 | { | |
51 | const IDESC *id = @cpu@_decode (current_cpu, pc, insn, insn, abuf); | |
52 | ||
53 | @cpu@_fill_argbuf (current_cpu, abuf, id, pc, fast_p); | |
54 | if (! fast_p) | |
55 | { | |
56 | int trace_p = PC_IN_TRACE_RANGE_P (current_cpu, pc); | |
57 | int profile_p = PC_IN_PROFILE_RANGE_P (current_cpu, pc); | |
58 | @cpu@_fill_argbuf_tp (current_cpu, abuf, trace_p, profile_p); | |
59 | } | |
60 | return id; | |
61 | } | |
62 | ||
63 | static INLINE const IDESC * | |
64 | extract32 (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn, | |
65 | ARGBUF *abuf, int fast_p) | |
66 | { | |
67 | const IDESC *id = @cpu@_decode (current_cpu, pc, (USI) insn >> 16, insn, abuf); | |
68 | ||
69 | @cpu@_fill_argbuf (current_cpu, abuf, id, pc, fast_p); | |
70 | if (! fast_p) | |
71 | { | |
72 | int trace_p = PC_IN_TRACE_RANGE_P (current_cpu, pc); | |
73 | int profile_p = PC_IN_PROFILE_RANGE_P (current_cpu, pc); | |
74 | @cpu@_fill_argbuf_tp (current_cpu, abuf, trace_p, profile_p); | |
75 | } | |
76 | return id; | |
77 | } | |
78 | ||
79 | static INLINE SEM_PC | |
80 | execute (SIM_CPU *current_cpu, SCACHE *sc, int fast_p) | |
81 | { | |
82 | SEM_PC vpc; | |
83 | ||
84 | if (fast_p) | |
85 | { | |
86 | #if ! WITH_SEM_SWITCH_FAST | |
87 | #if WITH_SCACHE | |
88 | vpc = (*sc->argbuf.semantic.sem_fast) (current_cpu, sc); | |
89 | #else | |
90 | vpc = (*sc->argbuf.semantic.sem_fast) (current_cpu, &sc->argbuf); | |
91 | #endif | |
92 | #else | |
93 | abort (); | |
94 | #endif /* WITH_SEM_SWITCH_FAST */ | |
95 | } | |
96 | else | |
97 | { | |
98 | #if ! WITH_SEM_SWITCH_FULL | |
99 | ARGBUF *abuf = &sc->argbuf; | |
100 | const IDESC *idesc = abuf->idesc; | |
101 | const CGEN_INSN *idata = idesc->idata; | |
102 | #if WITH_SCACHE_PBB | |
103 | int virtual_p = CGEN_INSN_ATTR_VALUE (idata, CGEN_INSN_VIRTUAL); | |
104 | #else | |
105 | int virtual_p = 0; | |
106 | #endif | |
107 | ||
108 | if (! virtual_p) | |
109 | { | |
110 | /* FIXME: call x-before */ | |
111 | if (ARGBUF_PROFILE_P (abuf)) | |
112 | PROFILE_COUNT_INSN (current_cpu, abuf->addr, idesc->num); | |
113 | /* FIXME: Later make cover macros: PROFILE_INSN_{INIT,FINI}. */ | |
114 | if (PROFILE_MODEL_P (current_cpu) | |
115 | && ARGBUF_PROFILE_P (abuf)) | |
116 | @cpu@_model_insn_before (current_cpu, 1 /*first_p*/); | |
117 | TRACE_INSN_INIT (current_cpu, abuf, 1); | |
118 | TRACE_INSN (current_cpu, idata, | |
119 | (const struct argbuf *) abuf, abuf->addr); | |
120 | } | |
121 | #if WITH_SCACHE | |
122 | vpc = (*sc->argbuf.semantic.sem_full) (current_cpu, sc); | |
123 | #else | |
124 | vpc = (*sc->argbuf.semantic.sem_full) (current_cpu, abuf); | |
125 | #endif | |
126 | if (! virtual_p) | |
127 | { | |
128 | /* FIXME: call x-after */ | |
129 | if (PROFILE_MODEL_P (current_cpu) | |
130 | && ARGBUF_PROFILE_P (abuf)) | |
131 | { | |
132 | int cycles; | |
133 | ||
134 | cycles = (*idesc->timing->model_fn) (current_cpu, sc); | |
135 | @cpu@_model_insn_after (current_cpu, 1 /*last_p*/, cycles); | |
136 | } | |
137 | TRACE_INSN_FINI (current_cpu, abuf, 1); | |
138 | } | |
139 | #else | |
140 | abort (); | |
141 | #endif /* WITH_SEM_SWITCH_FULL */ | |
142 | } | |
143 | ||
144 | return vpc; | |
145 | } | |
146 | ||
147 | EOF | |
148 | ||
149 | ;; | |
150 | ||
151 | xinit) | |
152 | ||
153 | # Nothing needed. | |
154 | ||
155 | ;; | |
156 | ||
157 | xextract-simple | xextract-scache) | |
158 | ||
159 | cat <<EOF | |
160 | { | |
161 | if ((pc & 3) != 0) | |
162 | { | |
163 | /* This only occurs when single stepping. | |
164 | The test is unnecessary otherwise, but the cost is teensy, | |
165 | compared with decoding/extraction. */ | |
166 | UHI insn = GETIMEMUHI (current_cpu, pc); | |
167 | extract16 (current_cpu, pc, insn & 0x7fff, sc, FAST_P); | |
168 | } | |
169 | else | |
170 | { | |
171 | USI insn = GETIMEMUSI (current_cpu, pc); | |
172 | if ((SI) insn < 0) | |
173 | { | |
174 | extract32 (current_cpu, pc, insn, sc, FAST_P); | |
175 | } | |
176 | else | |
177 | { | |
178 | extract16 (current_cpu, pc, insn >> 16, sc, FAST_P); | |
179 | extract16 (current_cpu, pc + 2, insn & 0x7fff, sc + 1, FAST_P); | |
180 | /* The m32r doesn't support parallel execution. */ | |
181 | if ((insn & 0x8000) != 0 | |
182 | && (insn & 0x7fff) != 0x7000) /* parallel nops are ok */ | |
183 | sim_engine_illegal_insn (current_cpu, pc); | |
184 | } | |
185 | } | |
186 | } | |
187 | EOF | |
188 | ||
189 | ;; | |
190 | ||
191 | xextract-pbb) | |
192 | ||
193 | # Inputs: current_cpu, pc, sc, max_insns, FAST_P | |
194 | # Outputs: sc, pc | |
195 | # sc must be left pointing past the last created entry. | |
196 | # pc must be left pointing past the last created entry. | |
197 | # If the pbb is terminated by a cti insn, SET_CTI_VPC(sc) must be called | |
198 | # to record the vpc of the cti insn. | |
199 | # SET_INSN_COUNT(n) must be called to record number of real insns. | |
200 | ||
201 | cat <<EOF | |
202 | { | |
203 | const IDESC *idesc; | |
204 | int icount = 0; | |
205 | ||
206 | if ((pc & 3) != 0) | |
207 | { | |
208 | /* This only occurs when single stepping. | |
209 | The test is unnecessary otherwise, but the cost is teensy, | |
210 | compared with decoding/extraction. */ | |
211 | UHI insn = GETIMEMUHI (current_cpu, pc); | |
212 | idesc = extract16 (current_cpu, pc, insn & 0x7fff, &sc->argbuf, FAST_P); | |
213 | ++sc; | |
214 | --max_insns; | |
215 | ++icount; | |
216 | pc += 2; | |
217 | if (IDESC_CTI_P (idesc)) | |
218 | { | |
219 | SET_CTI_VPC (sc - 1); | |
220 | goto Finish; | |
221 | } | |
222 | } | |
223 | ||
224 | while (max_insns > 0) | |
225 | { | |
226 | USI insn = GETIMEMUSI (current_cpu, pc); | |
227 | if ((SI) insn < 0) | |
228 | { | |
229 | idesc = extract32 (current_cpu, pc, insn, &sc->argbuf, FAST_P); | |
230 | ++sc; | |
231 | --max_insns; | |
232 | ++icount; | |
233 | pc += 4; | |
234 | if (IDESC_CTI_P (idesc)) | |
235 | { | |
236 | SET_CTI_VPC (sc - 1); | |
237 | break; | |
238 | } | |
239 | } | |
240 | else | |
241 | { | |
242 | idesc = extract16 (current_cpu, pc, insn >> 16, &sc->argbuf, FAST_P); | |
243 | ++sc; | |
244 | --max_insns; | |
245 | ++icount; | |
246 | pc += 2; | |
247 | if (IDESC_CTI_P (idesc)) | |
248 | { | |
249 | SET_CTI_VPC (sc - 1); | |
250 | break; | |
251 | } | |
252 | /* The m32r doesn't support parallel execution. */ | |
253 | if ((insn & 0x8000) != 0) | |
254 | { | |
255 | /* ??? Defer signalling to execution. */ | |
256 | if ((insn & 0x7fff) != 0x7000) /* parallel nops are ok */ | |
2acceee2 | 257 | sim_engine_invalid_insn (current_cpu, pc - 2, 0); |
c906108c SS |
258 | /* There's no point in processing parallel nops in fast mode. |
259 | We might as well do this test since we've already tested | |
260 | that we have a parallel nop. */ | |
261 | if (0 && FAST_P) | |
262 | { | |
263 | pc += 2; | |
264 | continue; | |
265 | } | |
266 | } | |
267 | else | |
268 | { | |
269 | /* Non-parallel case. | |
270 | While we're guaranteed that there's room to extract the | |
271 | insn, when single stepping we can't; the pbb must stop | |
272 | after the first insn. */ | |
273 | if (max_insns == 0) | |
274 | break; | |
275 | } | |
276 | /* We're guaranteed that we can always process 16 bit insns in | |
277 | pairs. */ | |
278 | idesc = extract16 (current_cpu, pc, insn & 0x7fff, &sc->argbuf, FAST_P); | |
279 | ++sc; | |
280 | --max_insns; | |
281 | ++icount; | |
282 | pc += 2; | |
283 | if (IDESC_CTI_P (idesc)) | |
284 | { | |
285 | SET_CTI_VPC (sc - 1); | |
286 | break; | |
287 | } | |
288 | } | |
289 | } | |
290 | ||
291 | Finish: | |
292 | SET_INSN_COUNT (icount); | |
293 | } | |
294 | EOF | |
295 | ||
296 | ;; | |
297 | ||
298 | xfull-exec-* | xfast-exec-*) | |
299 | ||
300 | # Inputs: current_cpu, vpc, FAST_P | |
301 | # Outputs: vpc | |
302 | # vpc is the virtual program counter. | |
303 | ||
304 | cat <<EOF | |
305 | #if (! FAST_P && WITH_SEM_SWITCH_FULL) || (FAST_P && WITH_SEM_SWITCH_FAST) | |
306 | #define DEFINE_SWITCH | |
307 | #include "sem-switch.c" | |
308 | #else | |
309 | vpc = execute (current_cpu, vpc, FAST_P); | |
310 | #endif | |
311 | EOF | |
312 | ||
313 | ;; | |
314 | ||
315 | *) | |
316 | echo "Invalid argument to mainloop.in: $1" >&2 | |
317 | exit 1 | |
318 | ;; | |
319 | ||
320 | esac |